Structure and function of the processor

The CPU
 The processor
 Has components such as:
o Control unit
o Buses
o ALU
o Dedicated Registers

The Arithmetic and Logic Unit: ALU

 Perform Arithmetic and Logical operations on the data

 On fixed or floating point numbers
 Perform shift operations
 Boolean logic operations, comparing two values
 Using things such as: AND, OR, NOT, XOR, ADD, SUBTRACT, MULTIPLY, DIVIDE.

Control Unit
 Directs the flow of data between the CPU and other devices
 Controls and Coordinates the activities of the CPU
 Accepts the next instruction, decodes it into several sequential steps like fetching the data and
then manages the execution and stores the result in the memory registers.

Registers

Accumulator: ACC
 Stores the results of the ALU

Program Counter: PC
 Holds the next instruction to be processed from the CIR
 Sends it to the MAR

Current Instruction Register: CIR

 Holds current instructions, taken from the MDR
 Divided in opcode (instruction) and operand (data)
o Opcode is the part of the instruction that tells the CPU what should be done
o Operand is the part that contains the data

Memory Address Register: MAR

 Holds the address from where data or instruction will be fetched or where it will be
written.
  Takes it from the CIR or PC

Memory Data Register: MDR

 Store data being used
 Being read from or written
 Also known as Memory Buffer Register

BUSES:
 A bus is a set of parallel wires connecting 2 or more components of a computer.
 Usually 8, 16, 32 or 64 lines
 Each bus is a shared transmission medium
 Only one device can transmit along a bus at any one time

Data bus:
 Usually 8, 16, 32 or 64 separate lines
 Moves both ways to transfer data and instructions
 Transmits the data held in a word of memory
 The largest operand is related to the size of the data bus
 If size is 16 size cannot be greater than 2^16 -1 or more than 2 characters
 Larger data busses can transmit larger values, or more characters or more bits per
instruction

Address bus:
 Only goes one way
 Memory is divided in words
 Word = fixed size group of digits
 Usually 16, 32 or 64
 Handled as a unit by the processor
 Own specific address
  Different type of processors have different word sizes
 Transmits the memory addresses of words that are used as operands (data) in
instructions
 Therefore, data can be retrieved by the Data Bus and sent to the processor
 The width of the address bus determines the maximum possible memory capacity of the
system
 8 lines = max in binary means 11111111 = 255 which means maximum memory capacity
of 256 (including address 0)
 32 address bus means 2^32 = 4294967296 memory locations = space of 4GiB
 GiB is 1024 MB not 1000 MB
 Average pc in 2016

Control Bus:
 Both ways
 Data and address buses are shared, so control lines exist to make sure there are no
conflicts
 Purpose is to transmit between components:
 Commands
 Timing
 Specific Status Information
 Control Lines include:
 Bus Request – a device requests the use of the data bus
 Bus Grant – CPU has granted access to the data bus
 Memory Write – Makes the data on the data bus to be written on the address
given
 Memory Read – Data from the address given is loaded onto the data bus
 Interrupt Request – Indicates that a device is requesting access to the CPU
 Clock – Synchronize operations
RELATION TO ASSEMBLY LANGUAGE

 Operation code in assembly language, or opcode (instruction) is expressed as a

mnemonics
 ADD, SUB, LDA etc.
 With only 2 bits for opcode, there can not be more than 2^6 different instructions
 Operand needs to be held in only 8 bits
 Not good for general purpose computers which are likely to have word sizes of
32, 64 or 128 bits.

Fetch Decode and Execute CYCLE

Fetch Phase

1. The address of the next instruction is copied from the Program Counter (PC) to the Memory
Address Register (MAR)
2. The instructions at that address are copied to the Memory Data Register (MDR). At the same
time, the PC is incremented, holding the address of the next instruction.
3. Contents of the MDR are copied to the Current Instruction Register (CIR)

Decode Phase

4. Instructions in CIR is decoded. Instruction is split into opcode and operand.

a. Opcode determines:
i. The type of instruction
ii. Hardware that will be used to execute it
b. Operand has:
 i. The address of the data that will be used, which is then copied to the MAR
ii. The actual data, which is then copied to the MDR
iii. Data that can be passed to the ALU/accumulator

Execute Phase

5. The appropriate instruction / opcode is carried out on the operand.

Processor Performance

Clock Speed
 System Clock creates a series of signals
 Going from 0 to 1 several million timer per second
 Synchronizing CPU operations
 Each CPU operation starts when the clock changes from 0 to 1 (or 1 to 0 in some cases)
 CPU cannot perform operations faster than the clock cycle
 The amount of time needed to go from 0 to 1 and then back to 0)
 All activities begin on a clock pulse (some may take more than one clock cycle to
complete)
 One clock cycle per second = 1 Hertz (Hz)
 Clock speed is measure in Gigahertz (GHz) which is 1 billion cycles.
 Greater clock speed means the faster instructions will be executed as there are more
cycles that can be done per second.

Number of Cores
 In a traditional computer (von Neumann machine), instructions are fetched and
executed 1 by 1 in a serial manner
 Many newer computers have multiple cores
 Dual-core = 2 cores
 Quad-core = 4 cores AND SO ON
 Each core has its own fetch-execute cycle at the same time
 The software may not be able to take advantage of the multiple cores

Cache
 Small and very fast memory inside the CPU
 Instructions fetched from main memory are copied into the cache
 In case they are needed again soon after
 Unused instructions or data are replaced with more recent ones as the cache fills up
  CACHE HAS DIFFERENT LEVEL
 Level 1 – Fast but small (2-64KB)
 Level 2 – Medium fast and medium size (256KB – 2MB)
 Level 3 – Slow and big size (4MB – 50MB)
 Still faster than RAM
 If you have more fast cache than there is more data that can be quickly fetched,
reducing the time needed to fetch data therefore making processing faster

Pipelining
 Technique used by some processors to improve performance
 Without pipelining, the Fetch Decode Execute cycles are done one after the other
 Means the ALU is doing nothing while data is fetched
 Pipelining uses the processor’s architecture to allow the next instruction to be fetched
while the ALU is working
 The data is held in a buffer close to the CPU until the data can be processed by the ALU
 Sometimes split into instruction pipeline and arithmetic pipeline
 Instruction Pipeline – Stages in which instructions are moved through the processor.
 THEY OVERLAP
 Including fetched, buffered and executed
 

 Arithmetic Pipeline – Represents the parts of an arithmetic operation that can be

broken down and overlapped
 An arithmetic pipeline divides an arithmetic problem into various sub problems
for execution in various pipeline segments
 Pipelining is very common now in microprocessors in personal computers
 Intel’s Pentium can execute as many as 6 instructions simultaneously
 SAME GOD DAMN HARDWARE JUST DIFFERENT TECHNIQUE

Architectures
 Computers were first built in the 1940s and 50s
 Two early pioneers were Alan Turing and John von Neumann

Von Neuman Architecture

 Specifies in basic components of the computer and processor
 Shared memory and bus used for both data and instructions
 Stored program concept – Machine code instructions are fetched and executed serially
by a processor that performs arithmetic and logical operations
 A program needs to be in the main memory to be executed
 Machine code instructions are fetched from memory one at a time
 Virtually all computers today are built on this principle
 
 Same data bus to transfer both data and instructions
 One address bus used to transfer the addresses of data and instructions
 Same word length for all memory, even if data or instructions

Harvard architecture

 Physically separated memories for instructions and data

 Separate busses
 Used extensively with Digital Signal Processing (DSP) systems
 DSP applications include audio and speech signal processing, sonar and radar signal
processing, biomedical signal processing, seismic data processing and digital image
processing.
 The 2 different memories can have different properties
 Embedded systems instructions may be held in read-only memory and the data
will be held in a read-write memory
 Different word size can be used, there is more instruction memory than data
memory, therefore instructions will have a bigger word size
 Embedded systems include special computers built into devices often operating in real
time, like navigation systems, traffic lights, aircraft flight control systems and simulators.
 Harvard architecture can be faster than von Neuman architecture because there are
separate busses and they don’t compete
Contemporary processor architectures

 Modern high-performance CPU chips have aspects of both von Neuman and Harvard
architecture
 In one design there is one main memory for both data and instructions, but CPU
cache memory is divided into an instruction cache and data cache, using both
 Some digital signal processors such as Texas Instruments TMS320 CC55x have
multiple parallel data busses, two write and three read, and one instruction bus
 EVERYTHING COMBINED TO MAKE THE ULTIMATE