EE314:

CMOS RF Integrated Circuit Design

Practical PA Design Issues

Stanford University
Hamid Rategh

Hamid Rategh Stanford University EE314 HO#14 1

Ground inductance
VDD

„ Finite inductance in
the ground path of a Vd
Vin RL
single-ended
amplifier Ls

‰ Reduces the Gain

‰ Affects the input match Zin(ω ) ≈ g m Ls + j ( Lsω − 1 )
(input impedance) C gs C gsω
V Z ( jω )
Av = d ≈ d
Vin jLsω

Hamid Rategh Stanford University EE314 HO#14 2

Ground inductance (cont.)
„ Sharing the ground of different stages
introduces a positive feedback and can cause
instability
VDD VDD

Vd Vd

Ls

Ground shared on the

Ground shared on the package or on the radio
MMIC board

Hamid Rategh Stanford University EE314 HO#14 3

Vdd
„ Feedback through Vdd path can cause instability
„ Critical selection of Vdd bypass capacitors to ensure
unconditional stability
‰ Capacitors have parasitic series inductance (e.g. a 0402
capacitor has about 0.5nH series inductance)
‰ Different capacitor values are used to provide sufficient bypass at
a wide frequency range (e.g. a 15pF 0402 capacitor has a series
resonance frequency of around 1.8GHz)
VDD

Vd

Hamid Rategh Stanford University EE314 HO#14 4

Subharmonic Oscillation (Spur)

„ Subharmonic spurs (mostly f/2) are observed in both BJT and FET
PAs under large signal operations
„ Parametric oscillation are blamed for f/2 spurs in FETs
‰ Cgs and Cjd are voltage dependant capacitors. They can create a
negative resistance at f/2 when excited at f.
„ Memory of BJT transistors (storage of minority carriers in the base)
as well as parametric oscillation are blamed for the subharmonic
spurs
„ Usually gain peaking around f/2 is a warning for subharmonic spurs
‰ Gain peaking around subharmonic frequencies creates a tendency of
oscillation at frequencies close to the subharmonic frequency.
‰ Under large signal operation the PA can injection lock at the subharmonic
frequency.

Hamid Rategh Stanford University EE314 HO#14 5

Improving Stability
„ Minimize the feedback between different stages
‰ Separate ground connection for each stage
‰ Critical choice of Vcc/Vdd bypass capacitors
‰ Physical separation between Vdd and ground bondwires of each
stage
„ RF ballasting (distribute it on unit cells)
„ RC feedback (shunt-shunt feedback between collector-base or
drain-gate)
„ Avoid gain peaking at subharmonic frequencies
‰ Appropriate output and interstage matching network
VDD

Rf
Vd

Rb

Hamid Rategh Stanford University EE314 HO#14 6

Measuring Stability
„ Small signal
‰ Measure the small signal impedance at each node. Any negative real
impedance is a sign of instability
‰ Stability factor and stability measure technique (using small signal S-
parameter)
„ S11(dB) < 0
„ S22(dB) < 0
„ Necessary and sufficient condition (if checked for each stage):
1 − S11 − S 22 + S11.S 22 − S12 .S 21
2 2 2

stability factor: K= >1

2 S12 .S 21
b = 1 + S11 − S 22 − S11.S 22 − S12 .S 21 > 0
2 2 2
stability measure:
„ Large signal
‰ Stability factor and stability measure technique (using large signal S-
parameter. Usually, simulation convergence problem.)
‰ Transient simulation for different source and load mismatch (VSWR ≤ 6:1
and all phases) (This is the ultimate test)

Hamid Rategh Stanford University EE314 HO#14 7

 Power and Power Gain

„ Small signal power gain is „ Maximum output power

independent of the depends on both real and
imaginary part of the load imaginary part of the load
impedance impedance
‰ Gss ∝ R ‰ If ⏐X⏐ << R ⇒ Pomax∝1/R
P ‰ If ⏐X⏐ >> R ⇒ Pomax∝ R
Gss = o = Gm .R.Rin
2

Pin
R
2
Vdd .R
Po max = Rin
2( R 2 + X 2 ) Vin jX
Gm*Vin

„ Assumption: Pure sinusoidal signal even

at max pout (class A,B, and C)
Hamid Rategh Stanford University EE314 HO#14 8
Narrow-Band Matching networks
„ The load impedance should be transformed to a
different impedance (usually lower) to get the
desired power and PAE
„ High pass L-match „ High Pass L-match with
(with Vcc choke) finite Vcc inductor ( π-
match)
Vcc

RFC
Vc C
Vc
RL RL
Vin C L Vin Lvcc L
Vcc
Ls Ls

Hamid Rategh Stanford University EE314 HO#14 9

 Narrow-Band Matching networks
„ L=2nH, C=13.4pF 50

„ R=3Ω X=0Ω (@ 1GHz) 0

R=0.8 Ω X=-17Ω (@ 0.5GHz)

imag(L_HP)
real(L_HP)
„
-50

RL
C L
-100

-150
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

„ Lvcc=5.5nH L=2nH, C=13.17pF 400

freq, GHz

„ R=3Ω X=0Ω (@ 1GHz) 300

„ R=310 Ω X=0Ω (@ 0.5GHz)

imag(P_HP)
real(P_HP)
200
⇒ Negative resistance in the base 100
of the power transistor
C 0

RL -100
Lvcc L
-200
Vcc 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

freq, GHz
Hamid Rategh Stanford University EE314 HO#14 10
 Narrow-Band Matching networks
„ L=2nH, C=13.4pF 7
„ 1<R<5 for 0.7<f<1.3GHz 5
‰ Power gain and max pout 3

imag(L_HP)
real(L_HP)
variation across frequency
1
RL -1
C L -3

-5

-7
0.7 0.8 0.9 1.0 1.1 1.2 1.3
„ Lvcc=5.5nH L=2nH, C=13.17pF 7 freq, GHz
„ R changes by a very small 5
amount 3
imag(P_HP)
real(P_HP)
‰ Flat power gain across freq.
1
‰ Max pout variation across freq.
-1
C -3
RL
Lvcc L -5

-7
Vcc 0.7 0.8 0.9 1.0 1.1 1.2 1.3

freq, GHz
Hamid Rategh Stanford University EE314 HO#14 11
Narrow-Band Matching networks Vcc
RFC
RL
Vin Lvcc L
Vin C L
RL
Zin3 Vcc
Ls
20
Zin1 Ls
40

15
20
dB(S(2,1))

dB(S(4,3))
10
0 Flat power
gain
5

-20
0

-5 -40
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

freq, GHz freq, GHz

15 40

10
20
imag(Zin1)

imag(Zin3)
real(Zin1)

real(Zin3)
5
0
0

-20
-5

-10 -40
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

freq, GHz freq, GHz

Hamid Rategh Stanford University EE314 HO#14 12
Power transistor, Size
„ Size determining parameters
‰ Maximum output power
„ The power device should be big enough such that the Rce (or Rds) at
low Vce (or Vds) is much smaller than the load impedance at the
collector (or Drain) of the power device
‰ Maximum current density
„ Operating life time (reliability issue)
‰ Input power drive constrain (It is harder to drive a larger device!)
‰ Temperature
„ Heat transfer capability of substrate
„ Device layout (avoiding local Hot spots)
„ Two approaches on selecting the size of the power device
‰ Load pull
‰ Trusting the Transistor model

Hamid Rategh Stanford University EE314 HO#14 13

Power transistor Layout
„ Distributed layout
‰ The power transistor can not be considered a
lumped element
‰ Combine the power of all devices constructively
„ Improve the efficiency

„ Balance layout:
‰ Prevent thermal runaway
‰ Uniform temperature distribution
‰ Avoid hot spot

Hamid Rategh Stanford University EE314 HO#14 14

Transistor Bias Current
„ Self biasing
‰ Except for Class A amplifiers, the power device current increases by
input power
‰ Half-wave rectification of the input voltage is the source of self biasing
‰ Improves the PAE at:
„ Low powers (by the virtue of lower DC current at lower output powers)
„ High powers (By enforcing a class C operation)
‰ Effects the linearity
„ The DC current at each output power depends on:
‰ Quiescent current
‰ Ambient temperature
‰ Reference bias transistor temperature
‰ Power device temperature

Hamid Rategh Stanford University EE314 HO#14 15

 Idle current and Linearity

„ For accurate
linearity measure the
device temperature
should be
adjusted/modeled as
a function of output
power.

Hamid Rategh Stanford University EE314 HO#14 16

Idle current and Linearity 30
Gain

28

„ Adjusting the idle current 26

of the output stage affects
the ACPR across pout. 24

„ Increasing the Idle current

22
reduces PAE -10 -5 0 5 10 15 20 25 30 35

„ Select the bias conditions

which meets the linearity
spec and maximizes PAE Ico=20mA

Hamid Rategh Stanford University EE314 HO#14 17