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Coss Quiz

This document contains information about an online quiz taken by a student. It provides details about the quiz such as the date and time it was available, the number of questions, and the time limit. It then shows the student's submission details including the time taken and score received of 5 out of 5.

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0% found this document useful (0 votes)
505 views5 pages

Coss Quiz

This document contains information about an online quiz taken by a student. It provides details about the quiz such as the date and time it was available, the number of questions, and the time limit. It then shows the student's submission details including the time taken and score received of 5 out of 5.

Uploaded by

aditya20090
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

12/27/2020 Quiz 1: Computer Organization and Software Systems (S1-20_DSECFZG516)

Quiz 1
Due Dec 28 at 19:00 Points 5 Questions 10
Available Dec 27 at 19:00 - Dec 28 at 19:00 1 day Time Limit 30 Minutes

Instructions
Dear Students,

The quiz is open for 24 hours from 27th December 2020 (7.00 pm) till 28th December 2020(7.00 pm)

The duration of quiz is 30 min for 10 questions.

All the best.

Attempt History
Attempt Time Score
LATEST Attempt 1 10 minutes 5 out of 5

 Correct answers will be available on Dec 29 at 19:00.

Score for this quiz: 5 out of 5


Submitted Dec 27 at 20:17
This attempt took 10 minutes.

Question 1 0.5 / 0.5 pts

Consider a direct mapped cache having 4 lines, Block 9 will be place in

Line 0

Line 3

https://bits-pilani.instructure.com/courses/690/quizzes/1457 1/5
12/27/2020 Quiz 1: Computer Organization and Software Systems (S1-20_DSECFZG516)

Line 2

Line 1

Question 2 0.5 / 0.5 pts

The system uses Zero-address instruction method, the operands are


stored in _____ .

Cache

Stack

Registers

Accumulators

Question 3 0.5 / 0.5 pts

If cache size is 32 bytes and number of bits required to address cache


line is 5 bits. Then the size of a line in cache is

1 Byte

8 Bytes

4 Bytes

2 Bytes

https://bits-pilani.instructure.com/courses/690/quizzes/1457 2/5
12/27/2020 Quiz 1: Computer Organization and Software Systems (S1-20_DSECFZG516)

Question 4 0.5 / 0.5 pts

How many sets are there in a 4 way Set Associate Cache of size 64 bytes
and line size 2 bytes

16

Question 5 0.5 / 0.5 pts

Fewer addresses in the instruction format results in

Longer programs resulting in longer execution time

Less complex instructions

More primitive, shorter length instructions

All of the options

Question 6 0.5 / 0.5 pts

In SW instruction, data is written from ______ to ________

Memory to Memory

https://bits-pilani.instructure.com/courses/690/quizzes/1457 3/5
12/27/2020 Quiz 1: Computer Organization and Software Systems (S1-20_DSECFZG516)

Memory to Processor

Processor to Memory

Memory to Disk

Question 7 0.5 / 0.5 pts

In which instruction format 26 bit offset is specified?

I-Type

R-Type

M-Type

J-Type

Question 8 0.5 / 0.5 pts

Bootstrap program is loaded in

ROM

RAM

None of the options

Hard disk

https://bits-pilani.instructure.com/courses/690/quizzes/1457 4/5
12/27/2020 Quiz 1: Computer Organization and Software Systems (S1-20_DSECFZG516)

Question 9 0.5 / 0.5 pts

Consider a byte addressable memory where addresses 1000, 1001, 1002


and 1003 contain 25, 30, 35, and 42 respectively. What is the value of
data (assuming 4 Byte data) stored, if big endian representation is used?

42353025

50522334

25353042

25303542

Question 10 0.5 / 0.5 pts

Let a= A3H, logical shift right twice results in

3AH

A8H

28H

8BH

Quiz Score: 5 out of 5

https://bits-pilani.instructure.com/courses/690/quizzes/1457 5/5

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