AN 730: Nios II Processor Booting Methods in MAX 10 FPGA Devices

AN 730: Nios II Processor Booting
Methods in MAX 10 FPGA Devices

AN-730
2017.02.21
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Contents
Contents
1 Nios II Processor Booting Methods in MAX 10 FPGA Devices........................................... 3

1.1 Overview...............................................................................................................3
1.2 Abbreviations.........................................................................................................3
1.3 Prerequisite........................................................................................................... 4
1.4 MAX 10 FPGA On-chip Flash Overview....................................................................... 4
1.4.1 MAX 10 FPGA On-chip Flash......................................................................... 6
1.4.2 ERAM Preload Option...................................................................................6
1.5 Nios II Processor Boot Options and Guidelines............................................................ 7
1.5.1 Boot Option 1 and Option 2..........................................................................7
1.5.2 Boot Option 3: Nios II Processor Application Executes in-place from OCRAM..... 37
1.5.3 Boot Option 4 and Option 5........................................................................ 48
1.5.4 Summary of Nios II Processor Vector Configurations and BSP Settings............. 76
1.6 Appendix A: Booting Elements................................................................................ 78
1.6.1 Nios II Processor Memcpy-based Boot Copier................................................78
1.6.2 The alt_load() function.............................................................................. 79
1.6.3 Nios II SBT Makefile “mem_init_generate” Target.......................................... 79
1.6.4 The Convert Programing Files Option........................................................... 79
1.7 Appendix B: Boot Time Performance Analysis........................................................... 80
1.7.1 Boot Time Measurement Strategy............................................................... 81
1.7.2 Reducing Nios II Boot Time in MAX 10 FPGA Design.......................................82
1.7.3 Boot Time Performance and Estimation........................................................ 85
1.8 Document Revision History.....................................................................................89
AN 730: Nios II Processor Booting Methods in MAX 10 FPGA Devices

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1 Nios II Processor Booting Methods in MAX 10 FPGA Devices
1 Nios II Processor Booting Methods in MAX 10 FPGA

Devices
1.1 Overview
This document describes the various boot or software execution options available with
the Nios II processor and MAX 10 FPGAs.
You can configure the Nios® II processor to boot and execute software from different
memory locations, including the MAX10 FPGA on-chip RAM and UFM.
MAX 10 FPGA devices contain on-chip flash that is segmented into two part:
• Configuration Flash Memory (CFM)—store the hardware configuration data for MAX
10 FPGAs.
• User Flash Memory (UFM)—stores the user data or software applications.
1.2 Abbreviations
Table 1. List of Abbreviations
Abbreviation Description
App Application
CFM Configuration Flash Memory
DDR3 Double Data Rate type-3 synchronous dynamic random-access memory
EMIF External Memory Interface
ERAM Embedded Random Access Memory
HEX/.hex Hexadecimal File1
memcpy Memory copy
OCRAM On-Chip RAM
POF Programmer Object File
QSPI Quad Serial Parallel Interface
RAM Random Access Memory
SBT Software Build Tools
SOF/.sof SRAM Object File

continued...
1 An ASCII text file with the extension of .hex that stores the initial memory values for a
memory block.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2008
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
Abbreviation Description
SPI Serial Parallel Interface
UART Universal asynchronous receiver/transmitter
UFM User Flash Memory
XIP Execute In Place
1.3 Prerequisite
You are required to have the knowledge of instantiating and developing a Nios II
processor based system. Intel recommends you to go through the online tutorials and
training materials provided at http://www.altera.com/education/edu-index.html before
using this application note.
Related Links
• Nios II Gen2 Hardware Development Tutorial.
A step-by-step procedure to build a Nios II Gen2 processor system.
• Getting Started with the Graphical User Interface.
This document provides the details of the Nios II Software Build Tools using
graphical user interface.
1.4 MAX 10 FPGA On-chip Flash Overview

The Altera On-chip Flash IP core supports the following features:
• Read or write accesses to UFM and CFM sectors using the Avalon MM data and
control slave interface.
• Supports page erase, sector erase and sector write.
• Simulation model for UFM read / write accesses using various EDA simulation tool.
Table 2. On-chip Flash Regions in MAX 10 FPGA Devices

Flash Regions Functionality
Configuration Flash Memory (sectors CFM0-2) FPGA configuration file storage
User Flash Memory (sectors UFM0-1) Nios II processor application and/or user data
MAX 10 FPGA devices support several configuration modes and some of these modes
allow CFM1 and CFM2 to be used as an additional UFM region. The following table
shows the storage location of the FPGA configuration images based on the MAX 10
FPGA's configuration modes.

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Table 3. Storage Location of FPGA Configuration Images

Configuration Mode CFM22 CFM12 CFM0
Dual images Compressed Image 2 Compressed Image 1
Single uncompressed image UFM3 Uncompressed image
Single uncompressed image with Memory

Uncompressed image (with pre-initialized on-chip memory content)
Initialization
Single compressed image with Memory

Compressed image (with pre-initialized on-chip memory content)
Initialization
Single compressed image UFM3 Compressed Image
You must use the Altera On-chip Flash IP core to access to the flash memory in MAX
10 FPGAs. You can instantiate and connect the Altera On-chip Flash IP to the Nios II
processor using the Qsys system design tool in the Quartus II software. The Nios II
soft core processor uses the Avalon® Memory-Mapped (Avalon-MM) interface to
communicate with the Altera On-chip Flash IP.
Figure 1. Connection Example for The Altera On-chip Flash IP and the Nios II Processor
Related Links
• MAX 10 FPGA Configuration User Guide
• MAX 10 User Flash Memory User Guide
2 Sector is NOT supported in 10M02 device.
3 The CFM sector is configured as virtual UFM.

5
1.4.1 MAX 10 FPGA On-chip Flash

The Altera On-chip Flash IP core can provide access to five flash sectors:
• UFM0
• UFM1
• CFM0
• CFM1
• CFM2
Important facts about UFM and CFM sectors:

• CFM sectors are intended for configuration (bitstream) data (*.pof) storage.
• You can store user data in the UFM sectors.
• Certain devices do not have a UFM1 sector. You can refer to Table 4 on page 6
for available sectors in each individual MAX 10 FPGA device.
• You can configure CFM2 as a virtual UFM by selecting “Single Uncompressed
Image” configuration mode.
• You can configure CFM2 and CFM1 as a virtual UFM by selecting “Single
Compressed Image” configuration mode.
• The size of each sector varies with the selected MAX 10 FPGA devices.
Table 4. UFM and CFM Sector Size

This table lists the dimensions of the UFM and CFM arrays.
Pages per Sector Maximum Total

Page OCRAM
User Flash Configuratio
Device UFM1 UFM0 CFM2 CFM1 CFM0 Size Size
Memory n Memory
(Kbit) (Kbit)
Size (Kbit)4 Size (Kbit)
10M02 3 3 0 0 34 16 96 544 108
10M04 0 8 41 29 70 16 1248 2240 189
10M08 8 8 41 29 70 16 1376 2240 378
10M16 4 4 38 28 66 32 2368 4224 549
10M25 4 4 52 40 92 32 3200 5888 675
10M40 4 4 48 36 84 64 5888 10752 1260
10M50 4 4 48 36 84 64 5888 10752 1638
1.4.2 ERAM Preload Option

The FPGA configuration data may contain MAX 10 FPGA On-chip RAM or ERAM
initialization data. The ERAM preload occurs during FPGA configuration before the
device enters user mode. The ERAM preload option allows initialization data for the
On-chip RAM to be stored in the CFM sectors. The initialization data includes the Nios
II processor software or any type of application data.
4 The maximum possible value, which is dependent on the configuration mode you select.

6
All MAX 10 FPGA devices except for the MAX 10 10M02 supports dual FPGA
configuration images. The ERAM preload is disabled when you select the dual
configuration images mode.
When the ERAM preload feature is set to OFF, features that require initialization of on-
chip RAM will not work. The ERAM preload option is set to OFF by default.
Selecting Single Compressed Image with Memory Initialization or Single

Uncompressed Image with Memory Initialization configuration mode will enable the
ERAM Preload option but will reduce the size of UFM available.
1.5 Nios II Processor Boot Options and Guidelines

There are 5 Nios II processor boot options available.
Table 5. Nios II Processor Boot Options

Boot Option Applicati Application Boot Supported Configuration
on Code Runtime Location Method Mode
Storage
Option 1: UFM UFM (XIP) + alt_load () • Single Uncompressed

Nios II processor application executes OCRAM/ External function Image
in-place from Altera On-chip Flash RAM (for data) • Single Compressed
(UFM) Image
• Dual Compressed Images
Option 2: UFM OCRAM/ External memcpy- • Single Uncompressed

Nios II processor application copied RAM based boot Image
from UFM to RAM using boot copier copier • Single Compressed
Image
Option 3: OCRAM OCRAM No boot • Single uncompressed

Nios II processor application executes copier is image with Memory
in-place from OCRAM required Initialization
• Single compressed image
with Memory
Initialization
Option 4: QSPI flash QSPI (XIP) + alt_load() • Single Uncompressed

Nios II processor application executes OCRAM/ External function Image
in-place from QSPI flash RAM (for data) • Single Compressed
Image
Option 5: QSPI flash OCRAM/ External memcpy- • Single Uncompressed

Nios II processor application copied RAM based boot Image
from QSPI flash to RAM using boot copier • Single Compressed
copier Image
1.5.1 Boot Option 1 and Option 2

Boot Option 1: Nios II Processor Application Executes in-place from Altera
On-chip Flash (UFM)
This solution is suitable for Nios II processor applications which require limited on-chip
memory usage. The alt_load() function operates as a mini boot copier which copies
the data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM
based on the BSP settings. The code section (.text), which is a read only section,

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remains in the Altera On-chip Flash memory region. This setup minimizes the RAM
usage but may limit the code execution performance as access to the flash memory is
slower than the on-chip RAM.
The Nios II processor application is programmed into the UFM sector. The Nios II
processor's reset vector points to the UFM sector in order to execute code from the
UFM after the system resets.
If you are debugging the application using the source-level debugger, you must use a
hardware break-point to debug because the UFM does not support random memory
access. Random memory access is required for soft break-point debug.
Figure 2. Boot Option 1 Block Diagram
MAX 10 FPGA
FPGA CFM .POF
Dynamic
Memory Logic SOF FPGA Data
Memory Controllers
ALT_onchipflash IP
CFM 1/2 .SOF
Nios II
UFM Nios II Software
Dynamic .HEX
Memory User
Software
Alt_load
Table 6. RAM and ROM Size Requirement for Boot Option 1

You can manually determine the required RAM size for the Altera On-Chip Flash by referring to the initial part
of the .objdump file, created when you build your application.
RAM Size Requirement ROM Size Requirement
Equivalent to the dynamic memory space usage during run time which is Executable code must not exceed the size of
the sum of the maximum heap and stack size. the UFM.
Boot Option 2: Nios II Processor Application Copied from UFM to RAM using
Boot Copier
Intel recommends this solution for MAX 10 FPGA Nios II processor system designs
where there may be multiple iterations of application software development and when
high system performance is required. The boot copier is located within the UFM at an
offset which is the same address with the reset vector. The Nios II application is
located next to the boot copier.
For this boot option, the Nios II processor starts executing the boot copier upon
system reset to copy the application from the UFM sector to the OCRAM or external
RAM. Once copying is complete, the Nios II processor transfers the program control
over to the application.

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MAX 10 FPGA
CFM .POF
Dynamic FPGA
Memory Logic SOF FPGA Data
Memory Controllers
ALT_onchipflash IP
User CFM 1/2 .SOF
Nios II
Software
UFM Nios II Software
Dynamic .HEX
Memory User
Software
User
Software Boot
Copier

• You can manually determine the required RAM size for the Altera On-Chip Flash by referring to the initial
part of the .objdump file, created when you build your application.
• The OCRAM size is limited, you have to ensure that the size is sufficient for application execution.
Equivalent to the executable code and dynamic memory Executable code and boot copier must not exceed the size
size required by user program. of the UFM.

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Figure 4. Configuration and Booting Flow for Option 1 and Option 2
Design
• Create your Nios II Processor based project using Qsys system.
For Option 1: For Option 2:
• Add hardware breakpoint • Ensure that there is external RAM or onchip RAM in the system design.
option to the Nios II • Instantiate the Altera Dual Configuration IP into your Qsys system if you opt for
processor. Dual Images configuration mode.
MAX 10 FPGA Configuration and Compilation

• Set the same internal configuration mode in Altera On-chip Flash IP in Qsys and Quartus II software.
• Set Nios II processor reset and exception vector based on your boot option.
• Uncheck Initialize memory content option in Altera On-Chip Flash IP to include UFM data (.HEX) separately during
programming files conversion.
• Optionally, you can check Initialize memory content option to include UFM data (.HEX) into the SOF file.
• Generate your design in Qsys.
• Compile your project in Quartus II software.
BSP Editor Settings

• Create Nios II processor HAL BSP.
• Edit Nios II processor BSP settings and Linker Script in BSP Editor.
• Generate BSP project.
Application & Project Recompilation(1)

• Develop Nios II processor application code.
• Compile Nios II processor application and generate HEX file using makefile mem_init_generate target.
• Recompile your project in Quartus II software if you check Initialize memory content option in Altera On-Chip Flash IP.
Programming Files Conversion

• Generate the .pof file using Convert Programming Files feature in Quartus II software
Download
• Program the .pof file into your MAX 10 device.
Reset & Boot

• Reset your MAX 10 device using the reset button or power cycle your hardware.
(1) Project re-compilation is needed if Initialize Flash Content option was checked in Altera On-Chip Flash IP. You can ignore this step
if Intialize Flash Content option was unchecked in Altera On-Chip Flash IP.
Related Links
MAX 10 FPGA Configuration User Guide, section Remote System Upgrade in Dual
Compressed Images.

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1.5.1.1 Single Uncompressed/Compressed Image Bootable System Guideline
1.5.1.1.1 Qsys Settings

1. In the Nios II Processor parameter editor, set the reset vector memory and
exception vector memory based on the boot options below:
Boot Option Reset vector memory: Exception vector memory:
Option 1a56 Altera On-chip Flash OCRAM/ External RAM
Option 1b5 Altera On-chip Flash Altera On-chip Flash
Option 2 Altera On-chip Flash OCRAM/ External RAM
Figure 5. Nios II Parameter Editor Settings Boot Option 1a and 2
Figure 6. Nios II Parameter Editor Settings Boot Option 1b
2. In the Altera On-chip Flash IP parameter editor, set the Configuration Mode to
Single Uncompressed Image or Single Compressed Image.
5 You can set the exception vector for Boot Option 1 to OCRAM or External RAM (Option 1a) or
Altera On-chip Flash (option 1b) according to your design preference.
6 Boot option 1a which sets exception vector memory to OCRAM or External RAM is
recommended to make the interrupt processing faster.

11
Figure 7. Configuration Mode Selection in Altera On-Chip Flash Parameter Editor
3. Refer to the following table for the options to program UFM data (HEX file) and
settings required in Altera On-chip Flash IP.
Options to program Method Settings in Altera On-Chip Flash IP

UFM data
Option 1: Initialize the Quartus II includes the UFM a. Check Initialize flash content
UFM data in the SOF initialization data in the SOF during b. If default path is used, add meminit.qip generated
compilation. SOF recompilation is during “make mem_init_generate” into Quartus II
needed if there are changes in the project. Refer to Figure 9 on page 13.
UFM data.
Make sure the generated HEX naming matches the
default naming.
c. If non-default path is selected, enable the Enable
non-default initialization file and specify the path
of the HEX file.
Note: For more information about Steps 2 and 3, refer
to HEX File Generation section.
Option 2: Combine UFM UFM data is combined with the Uncheck Initialize flash content
data with a compiled SOF compiled SOF during the
during programming files programming files conversion. SOF
(POF) conversion 7 recompilation is NOT needed even
if there are changes in the UFM
data.
7 This is the recommended method for application developer. You are not required to recompile
SOF file for application changes during development.

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Figure 8. Initialize Flash Contents with Default Initialization File
Figure 9. Adding meminit.qip File in Quartus II
Figure 10. Initialize Flash Content with Non-default Initialization File

13
4. Ensure that the Altera On-chip Flash csr port is connected to the Nios II
processor data_master to enable write and erase operations.
Figure 11. CSR Connection to Nios II data_master
5. Click Generate HDL, the Generation dialog box appears.

6. Specify output file generation options, and then click Generate.
Related Links
HEX File Generation on page 19
1.5.1.1.2 Quartus II Software Settings

1. In the Quartus II software, click on Assignment -> Device -> Device and Pin
Options -> Configuration. Set Configuration mode to Single Uncompressed
Image or Single Compressed Image.8
8 The size of UFM shown will vary according to your device selection.

14
Figure 12. Configuration Mode Selection in Quartus II Software
Note: If the configuration mode setting in Quartus II software and Qsys parameter
editor is different, the Quartus II project compilation will fail with the
following error message.
2. Click OK to exit the Device and Pin Options window.

3. Click OK to exit the Device window.
4. Click Start Compilation to compile your project and generate the .sof file.
Related Links
1.5.1.1.3 BSP Editor Settings
You must edit the BSP editor settings according to the selected Nios II processor boot
options.
1. In the Nios II SBT tool, right click on your BSP project in the Project Explorer
window. Select Nios II > BSP Editor... to open the Nios II BSP Editor.
2. In Nios II BSP Editor, click on Advanced tab under Settings.
3. Click on hal to expand the list.
4. Click on linker to expand the list.

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Figure 13. BSP Editor Settings
5. Based on the boot option used, do one of the following:

— For boot option 1a, if exception vector memory is set to OCRAM or External
RAM, enable the following:
— allow_code_at_reset
— enable_alt_load
— enable_alt_load_copy_rodata
— enable_alt_load_copy_rwdata
— enable_alt_load_copy_exceptions
— For boot option 1b, if exception vector memory is set to Altera On-chip Flash,
enable the following:
— enable_alt_load
— For boot option 2, leave all the hal.linker settings unchecked.

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Figure 14. Advanced.hal.linker Settings for Boot Option 1a
Figure 15. Advanced.hal.linker Settings for Boot Option 1b

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Figure 16. Advanced.hal.linker Settings for Boot Option 2
6. Click on Linker Script tab in the Nios II BSP Editor.

— For boot option 1a and 1b, set the .text item in the Linker Section Name to
the Altera On-chip Flash in the Linker Region Name. Set the rest of the
items in the Linker Section Name list to the Altera On-chip Memory
(OCRAM) or external RAM.
— For boot option 2, set all of the items in the Linker Section Name list to
Altera On-chip Memory (OCRAM) or external RAM.
Figure 17. Linker Region Settings for Boot Option 1a and 1b

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Figure 18. Linker Region Settings for Boot Option 2
1.5.1.1.4 HEX File Generation

1. In the Nios II SBT tool, right click on your project in the Project Explorer window.
2. Click Make Targets -> Build…, the Make Targets dialog box appears. You can
also press shift + F9 to trigger the Make Target dialog box.
3. Select mem_init_generate.
4. Click Build to generate the HEX file.

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Figure 19. Selecting mem_init_generate in Make Targets
5. The “mem_init_generate” macro will create two HEX files; <on_chip_ram.hex>

and <on_chip_flash.hex>. The <on_chip_ram.hex> will be used for boot
option 3 and <on_chip_flash.hex> is used for boot option 1 and 2.
Notes: • The mem_init_generate target also generates a Quartus II IP file
(meminit.qip). Quartus II software will refer to the meminit.qip
for the location of the initialization files.
• All these files can be found under "<project_folder>/software/
<application_name>/mem_init" folder.
6. Recompile your project in Quartus II software if you check Initialize memory
content option in Altera On-Chip Flash IP. This is to include the software data
(.hex) into the SOF file.
Related Links
• Qsys Settings on page 11
• Quartus II Software Settings on page 14
1.5.1.1.5 Programmer Object File (.pof) Generation

1. In Quartus II, click on Convert Programming Files (.pof) from the File tab.
2. Choose Programmer Object File as Programming file type:.
3. Set Mode to Internal Configuration.

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Figure 20. Convert Programming File Settings
4. Click on Options/Boot info..., the MAX 10 Device Options dialog box appears.
5. Based on the Initialize flash content settings in the Altera On-chip Flash IP, do
one of the following:
— If Initialize flash content is checked, the UFM initialization data was
included in the SOF during Quartus II compilation. Select Page_0 for UFM
source: option. Click OK and proceed to next step.
— If Initialize flash content is not checked, choose Load memory file for
UFM source: option. Browse to the generated Altera On-chip Flash HEX file
(on_chip_flash.hex) in the File path: and click OK. This will add UFM data
separately to the SOF file during the programming file conversion.

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Figure 21. Setting Page_0 for UFM Source if Initialize flash content is Checked

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Figure 22. Setting Load Memory File for UFM Source if Initialize flash content is not
Checked
6. In the Convert Programming File dialog box, at the Input files to convert
section, click Add File... and point to the generated Quartus II .sof file.

23
Figure 23. Input Files to Convert in Convert Programming Files
7. Click Generate to create the .pof file.

8. Program the .pof file into your MAX 10 device.
1.5.1.2 Dual Compressed Images Bootable System Guideline

Boot Option Reset vector memory: Exception vector memory:
Option 1a910 Altera On-chip Flash OCRAM/ External RAM
Option 1b9 Altera On-chip Flash Altera On-chip Flash
Option 2 Altera On-chip Flash OCRAM/ External RAM
9 You can set the exception vector for Boot Option 1 to OCRAM or External RAM (Option 1a) or
Altera On-chip Flash (option 1b) according to your design preference.
10 Boot option 1a which sets exception vector memory to OCRAM or External RAM is
recommended to make the interrupt processing faster.

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Dual Compressed Images.
3. Refer to the following table for the options to program UFM data (HEX file) and
settings required in Altera On-chip Flash IP.
Options to program Method Settings in Altera On-Chip Flash IP

UFM data
Option 1: Initialize the Quartus II includes the UFM a. Check Initialize flash content
UFM data in the SOF initialization data in the SOF during b. If default path is used, add meminit.qip generated
compilation. SOF recompilation is during “make mem_init_generate” into Quartus II
needed if there are changes in the project. Refer to Figure 27 on page 26.
UFM data.
Make sure the generated HEX naming matches the
default naming.
c. If non-default path is selected, enable the Enable
non-default initialization file and specify the path
of the HEX file.
Note: For more information about Steps 2 and 3, refer
to HEX File Generation section.
Option 2: Combine UFM UFM data is combined with the Uncheck Initialize flash content
data with a compiled SOF compiled SOF during the
during programming files programming files conversion. SOF
(POF) conversion 11 recompilation is NOT needed even
if there are changes in the UFM
data.

25
Figure 26. Dual Compressed Images Mode with initialize flash content Turned-on
Figure 27. Adding meminit.qip File in Quartus II
11 This is the recommended method for application developer. You are not required to recompile
SOF file for application changes during development.

26
Figure 28. Dual compressed Images with Non-default Initialization File Enabled
4. Ensure that the Altera On-chip Flash csr port is connected to the Nios II
processor data_master to enable write and erase operations.
5. Ensure the Altera Dual Configuration IP is instantiated in Qsys to enable dual

images configuration.
Related Links

Options -> Configuration. Set Configuration mode to Dual Compressed
Images.12
12 The size of UFM sector will vary according to your device selection.

27
Figure 30. Dual Compressed Images Configuration Mode in Quartus II
Note: If the configuration mode setting in Quartus II software and Qsys parameter
editor is different, the Quartus II project compilation will fail with the
following error message.

Related Links
options.

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— enable_alt_load
— For boot option 1b, if exception vector memory is set to Altera On-chip Flash,
enable the following:
— enable_alt_load

29

30

the Altera On-chip Flash in the Linker Region Name. Set the rest of the
items in the Linker Section Name list to the Altera On-chip Memory
(OCRAM) or external RAM.

31


32

6. Recompile your project in Quartus II software if you check Initialize memory
content option in Altera On-Chip Flash IP. This is to include the software data
(.hex) into the SOF file.
Related Links
• Qsys Settings on page 24

1. In Quartus II, click on Convert Programming Files from the File tab.

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5. Based on the Initialize flash content settings, do one of the following:
— If Initialize flash content was checked, make sure Page_0 or Page_1 is
selected for UFM source: option. Click OK.
Note: UFM data (.HEX file) can be included in either Page_0 or Page_1 only.
The Altera On-chip flash does not support two .HEX files for Dual
Compressed images configuration mode.
— If Initialize flash content was not checked, choose Load memory file for
UFM source: option. Browse to the generated Altera On-chip Flash HEX file
(on_chip_flash.hex) in the File path: and click OK.

34
Figure 39. Setting Page_0 or Page_1 for UFM Source If Initialize flash content is
Checked

35
Figure 40. Setting Load Memory File for UFM Source if Initialize flash content is not
Checked
section, click Add File... and point to the first generated Quartus II .sof file to add
the .sof file at page_0.
7. Click on Add Sof Page to create additional page for .sof file. This creates SOF
data Page_1 automatically. Click Add File... and point to the second generated
Quartus II .sof file to add the .sof file at page_1.
Figure 41. Input Files to Convert in Convert Programming Files for Dual Images Mode

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9. Program the .pof file into your MAX 10 device.
1.5.2 Boot Option 3: Nios II Processor Application Executes in-place from

OCRAM
The on-chip memory is initialized during FPGA configuration with data from a Nios II
application image. This data is built into the FPGA configuration bitstream, the
programmer object file. This process eliminates the need for a boot copier, as the Nios
II application is already in place at system reset.
This option will not work in any of the following situations:

• When you select a configuration mode that does not support ERAM initialization.
• After a soft reset where the memory contents have been modified by the
application and the application code has been corrupted.
MAX 10 FPGA
CFM .POF
FPGA
Logic .SOF FPGA Data .SOF
ALT_onchipflash IP
Nios II User Nios II Software

Software .HEX
Dynamic
Memory CFM 1/2
UFM

37

Equivalent to the executable code and dynamic memory size required by Not applicable for this boot option.
user program.
Figure 43. Configuration and Booting Flow for Option 3
Design
• Create your Nios II Processor based project using the Qsys system.
• Ensure that there is onchip RAM in the system design.

• Set the same internal configuration mode in the Altera On-chip Flash IP in Qsys and Quartus II software.
• Set the Nios II processor reset and exception vector based on your boot option.
• Leave the Initialize memory content option unselected in Altera On-chip Flash IP. Check the Initialize memory
content option in the Altera On-chip Memory IP to include software data (.HEX) into the SOF file.
BSP Editor Settings

• Create the Nios II processor HAL BSP.
• Edit the Nios II processor BSP settings and Linker Script in BSP Editor.
• Generate the BSP project.
Application & Project Recompilation

• Develop the Nios II processor application code.
• Compile the Nios II processor application and generate the HEX file using makefile mem_init_generate target.
• Recompile your project in Quartus II software to include software data (.HEX) into the SOF file.

• Generate the .pof file using Convert Programming Files feature in Quartus II software
Download
• Program the .pof file into your MAX 10 device.
Reset & Boot

• Reset your MAX 10 device using the reset button or power cycle your hardware.

38
1.5.2.1 Single Uncompressed/Compressed Image with Memory Initialization

Guideline

1. In the Nios II Processor parameter editor, set both the Reset vector memory:
and Exception vector memory: to Altera On-Chip Memory (OCRAM).
Figure 44. Nios II Parameter Editor Settings for Boot Option 3
Single Uncompressed Image with Memory Initialization or Single
Compressed Image with Memory Initialization. Leave the Initialize flash
content unchecked. This is because the Altera On-chip flash initialization data will
not be enabled.
Figure 45. Configuration Mode with Memory Initialization Selection and Initialize Flash
Content Setting
3. In the Altera On-chip Memory (RAM or ROM) IP parameter editor, check Initialize
flash content. If default path is used, add meminit.qip generated during
“make mem_init_generate” into Quartus II project. Refer to Figure 47 on page
40. Make sure the generated HEX naming matches the default naming. If non-
default path is selected, check Enable non-default initialization file and specify
the path of the HEX file (onchip_memory2_0.hex).
Note: The meminit.qip stores the location information of the initialization files.

39
Figure 46. Enable Initialize Memory Content with Default Initialization File in On-Chip
Memory Parameter Editor Settings
Figure 47. Adding meminit.qip File into Quartus II

40
Figure 48. Enable Initialize Memory Content with Non-default Initialization File in On-
Chip Memory Parameter Editor Settings
4. Ensure that Altera On-chip Flash csr port is connected to the Nios II processor
data_master to enable write and erase operations.


Image with Memory Initialization or Single Compressed Image with
Memory Initialization.13
13 The size of UFM sector will vary according to your device selection.

41
Figure 50. Configuration Modes with Memory Initialization Selection in Quartus II
Notes: • If the configuration mode setting in Quartus II software and Qsys

parameter editor is different, the Quartus II project compilation will fail
with the following error message.
• If configuration mode without memory initialization is selected with

Initialize flash content checked in Altera On-chip Memory IP, the
Quartus II project compilation will fail with the following error
message:

options.

42
5. Enable allow_code_at_reset and leave others unchecked to make sure the

application starts at address 0x00.

43
Figure 52. Advanced.hal.linker Default Settings

7. Set all the Linker Section Regions to Altera On-chip Memory (OCRAM).
Figure 53. Linker Region Default Settings


44

6. Recompile your project in Quartus II software to include the software data (.HEX)
into the SOF file.
Note: If you are using Quartus II software version 15.0 and above, you can skip all the steps
in this section. From Quartus II 15.0 onwards, the Quartus II software will generate
both SOF and POF files. Since boot option 3 comprises single image, you may use the
generated POF file to program into the MAX 10 FPGA device directly.
1. In Quartus II, click on Convert Programming Files from the File tab.

45
5. Make sure Page_0 is set as the UFM source: option. Click OK.

46
Figure 56. Setting Page_0 for UFM Source
section, click Add File... and point to the generated Quartus II .sof file to add
the .sof file at page_0.

47
Figure 57. Input Files to Convert in Convert Programming Files

8. Program the .pof file into your MAX 10 FPGA device.
1.5.3 Boot Option 4 and Option 5

Boot Option 4: Nios II Processor Application Executes in-place from QSPI
Flash
This option is suitable for Nios II processor applications which require code space that
is larger than the UFM and/or limited on-chip memory usage. It has a similar concept
to boot option 1 where the Nios II processor application execute-in-place from UFM
but with more memory space due to use of QSPI flash (depending on QSPI chip
selection) instead of the UFM. This is an advantage for supporting larger or multiple
software applications.
The alt_load() function operates as a mini boot copier that initializes and copies the
writable memory sections only to OCRAM or external RAM. The code section (.text),
which is a read-only section, remains in the QSPI flash memory region. Retaining the
read-only section in QSPI minimizes RAM usage but may limit the code execution
performance. The Nios II processor application is programmed into the QSPI flash.
The Nios II processor reset vector points to the QSPI flash to allow code execution
after the system resets. If you are debugging the application using the source-level
debugger, you must use a hardware break-point because the QSPI cannot support
random memory access.

48
.POF MAX 10 FPGA

Nios II Software FPGA CFM .POF
.HEX Logic SOF FPGA Data
Memory Controllers
.SOF
ALT_onchipflash IP
Nios II CFM 1/2
QSPI User
Flash Software Dynamic
Memory
Dynamic UFM
Memory

Equivalent to the dynamic memory space usage during run time which is Executable code must not exceed the size of
the sum of the maximum heap and stack size. the QSPI flash.
Option 5: Nios II Processor Application Copied from QSPI Flash to RAM Using
Boot Copier
Using a boot copier to copy the Nios II application from QSPI flash to RAM is suitable
when multiple iterations of application software development and high system
performance are required. It has a similar concept to boot option 2 where Nios II
processor application copied from QSPI flash to RAM using boot copier but with larger
memory space due to QSPI flash (depending on QSPI chip selection). This is an
advantage for supporting software applications that require larger program space and
high software performance (compared to XIP).
The Nios II SBT tool automatically adds the Nios II processor memcpy-based boot
copier to the system when the executable file (.elf) is converted to the memory
initialization file (.hex). The boot copier is located at the base address of the HEX
data, followed by the application.
For this boot option, the Nios II processor starts executing the boot copier software
upon system reset that copies the application from the QSPI to the on-chip memory or
external RAM. Once this process is complete, the Nios II processor transfers the
program control over to the application.

49
.POF
Nios II Software
.HEX MAX 10 FPGA
FPGA CFM .POF
Logic SOF FPGA Data
QSPI User
Memory Controllers
ALT_onchipflash IP
CFM 1/2 .SOF
Flash Software Nios II
Boot Copier
Dynamic
Dynamic Memory
Memory User
User Software UFM
Software
Equivalent to the executable code and dynamic memory Executable code and boot copier must not exceed the size of
size required by user program. the QSPI flash.

50
Figure 60. Configuration and Booting Flow for Option 4 and Option 5
Design
• Create your Nios II Processor based project using Qsys system.
• Ensure that there is external RAM or onchip RAM and Generic Quad SPI controller IP in the system design.
• Instantiate the Altera Dual Configuration IP into your Qsys system if you opt for Dual Images configuration mode.

• Set Nios II processor reset and exception vector based on your boot option.
BSP Editor Settings

• Create Nios II processor HAL BSP based on the .sopcinfo file created from Qsys generation.
• Edit Nios II processor BSP settings and Linker Script in BSP Editor based on your boot option.
• Generate BSP project.
Application & Project Recompilation

• Develop Nios II processor application code.
• Compile Nios II processor application and generate .hex file using makefile mem_init_generate target.

• Convert the generated .hex file to .pof file using Convert Programming Files feature in Quartus II software
Download
• Using Quartus II programmer, program the parallel loader .sof into the device to enable parallel loader.
• Once the programming is completed, click on Auto Detect button. Make sure the QSPI flash is detected.
• Program the converted .pof (Nios II application) into the QSPI flash.
• Program the hardware .pof file (from Quartus II) into the MAX10 device.
Reset & Boot

• Reset your MAX 10 FPGA device using the reset button or power cycle your hardware.
Related Links
MAX 10 FPGA Configuration User Guide, section Remote System Upgrade in Dual
Compressed Images.

51
1.5.3.1 Single Uncompressed/Compressed Image Bootable System Guideline
1.5.3.1.1 Design Creation

1. Create your Nios II processor project using Quartus II and Qsys.
2. Make sure the Generic Quad SPI Controller IP is added into your Qsys system.
Refer to the diagram below for IP connection in Qsys.
Figure 61. Connection for Generic Quad SPI Controller IP
Note: The maximum input clock for Generic Quad SPI Controller IP is 25 MHz. The input
clock must not exceed this maximum value.

Boot Option Reset vector memory Exception vector memory
Option 4a 1415 QSPI flash OCRAM/ External RAM
Option 4b14 QSPI flash QSPI flash
Option 5 QSPI flash OCRAM/ External RAM
14 You can set the exception vector for Boot Option 4 to OCRAM/ External RAM (Option 4a) or
QSPI Flash (Option 4b) according to your design preference.
15 Boot option 4a which sets exception vector memory to OCRAM/External RAM is recommended
to make the interrupt processing faster.

52

Note: mem_if_ddr3_emif_0.avl is the external memory (DDR3) used in this
example.
2. Open Altera Generic Quad SPI controller parameter editor. Change the
Configuration device type to the QSPI flash selection and make sure the I/O
mode is set to QUAD.

53
Figure 64. Altera Generic Quad SPI Controller Parameter Settings

4. Specify output file generation options and then click Generate.

Image or Single Compressed Image.

4. Click Start Compilation to compile your project.

54
Note: SOF to POF file conversion is not required because there is only single
hardware image and Nios II application data will be loaded into the QSPI
flash separately. You can use the POF generated during Quartus II project
compilation to program into the MAX 10 FPGA.
Related Links
Programming Hardware Design POF File into the MAX10 FPGA on page 62
options.

— enable_alt_load

55
— For boot option 4b, if exception vector memory is set to QSPI flash, enable the
following:
— enable_alt_load

56

the QSPI flash in the Linker Region Name. Set the rest of the items in the
Linker Section Name list to the Altera On-chip Memory (OCRAM) or external
RAM.

57

1. In the Nios II SBT tool, right click on your project in the Project Explorer
window.

58
5. The “mem_init_generate” macro will create two HEX files; <OCRAM_name>.hex

and <QSPIFlash_name>.hex. Use <QSPIFlash_name>.hex for boot option 4
and 5 as you are booting from QSPI flash, not from OCRAM.
Related Links
Software Programmer Object File (.pof) Generation on page 59
1.5.3.1.6 Software Programmer Object File (.pof) Generation
Important: The quartus.ini file withPGMIO_SWAP_HEX_BYTE_DATA=ON content is required to

byteswap the programming file during the POF generation. Please create the
quartus.ini file or use the quartus.ini available in the related information and
place it under Quartus II tool directory or project directory before you proceed.
2. Choose Programmer Object File as Programming file type.
3. Set Mode to 1-bit Passive Serial.
4. Set Configuration device to CFI_512Mb.
5. Change the File name to the desired path and name.

59
6. Remove the SOF Page_0.

7. Click on Add HEX Data, choose the HEX file generated in HEX Generation
section. Select Absolute Addressing and click OK.
Figure 73. HEX to POF file Conversion Settings
Related Links
• HEX File Generation on page 58
• POF file Programming into QSPI flash on page 60
• Quartus.ini file
1.5.3.1.7 POF file Programming into QSPI flash

1. Programming Parallel Flash Loader into MAX10 Device
Note: You need to program the parallel flash loader into the MAX 10 device before
programming the QSPI flash.
a. Create Parallel Flash Loader for MAX 10 FPGA in the Quartus II. Assign QSPI
pins based on your design. Compile the project to obtain max10_qpfl.sof
file.
b. Open Quartus II programmer from the Quartus II tool (Tools ->
Programmer).
c. Make sure the Hardware Setup is set to your USB blaster.
d. Click on Auto Detect, select your MAX10 FPGA and select OK.

60
e. Right click on the MAX 10 FPGA and select Edit -> Change File. Choose the
max_qpfl.sof file.
f. Check MAX 10 device under Program/Configure and click Start to start
programming.
g. Click on Auto Detect after max10_qpfl.sof is successfully programmed.
Click Yes if you are asked to overwrite the existing settings. A new QSPI flash
device will be shown on the screen.
Figure 74. Programming Parallel Flash Loader Programmer Settings
2. Programming HEX image into QSPI Flash

a. Right click on the QSPI device and select Edit -> Change File. Choose the
generated POF file from Software POF Generation section.
b. Check the HEX file under Program/Configure column and click Start to start
programming.

61
Figure 75. HEX Image Programming into QSPI Flash
Related Links
Software Programmer Object File (.pof) Generation on page 59
1.5.3.1.8 Programming Hardware Design POF File into the MAX10 FPGA
1. After you successfully programmed HEX data into Quad SPI flash, right click on
the MAX 10 FPGA and select Edit -> Change File. Choose the downloaded POF
file generated from Quartus II project compilation.
2. Check the MAX10's CFM0 and UFM under Program/Configure column and click
Start to start programming.

62
Figure 76. POF Image Programming into QSPI Flash
Related Links
Quartus II Software Settings on page 54
1.5.3.2 Dual Compressed Images Bootable System Guideline
1.5.3.2.1 Design Creation

1. Create your Nios II processor project using Quartus II and Qsys.
2. Ensure the Generic Quad SPI Controller IP is added into your Qsys system. Refer
to the diagram below for IP connection in Qsys.
Figure 77. Connection for Generic Quad SPI Controller IP
3. Ensure Dual Configuration IP is instantiated in your Qsys system to enable dual

images configuration.
Note: The maximum input clock for Generic Quad SPI Controller IP is 25 MHz. The input
clock must not exceed this maximum value.

63

Boot Option Reset vector memory Exception vector memory
Option 4a 1617 QSPI flash OCRAM/ External RAM
Option 4b16 QSPI flash QSPI flash
Option 5 QSPI flash OCRAM/ External RAM

Note: mem_if_ddr3_emif_0.avl is the external memory (DDR3) used in this
example.
16 ) You can set the exception vector for Boot Option 4 to OCRAM/ External RAM (Option 4a) or
QSPI Flash (Option 4b) according to your design preference.
17 Boot option 4a which sets exception vector memory to OCRAM/External RAM is recommended
to make the interrupt processing faster.

64
2. There are two Nios II application data (HEX file) stored into the QSPI for
supporting dual configuration images. Reset vector memory offset has to set
correctly for the configuration images to call up the correct HEX data.
3. Set Reset vector memory offset of the Nios II Processor in first Qsys design to
address 0x00000000.
4. Set Reset vector memory offset of the Nios II Processor in second Qsys design to
another address to avoid overlapping. For example: Address 0x02000000 which is
half of the QSPI memory size (512Mb).
Figure 80. Reset Vector Offset Setting for First Qsys design
Figure 81. Reset Vector Offset Setting for Second Qsys design

65
5. Open Altera Generic Quad SPI controller parameter editor. Change the
Configuration device type to the QSPI flash selection and make sure the I/O
mode is set to QUAD.
Figure 82. Altera Generic Quad SPI Controller Parameter Settings

7. Specify output file generation options and then click Generate.

Options -> Configuration. Set Configuration mode to Dual Compressed
Images.

66

4. Click Start Compilation to compile your project.
Related Links
options.

67

— enable_alt_load
— For boot option 4b, if exception vector memory is set to QSPI flash, enable the
following:
— enable_alt_load

68

69

the QSPI flash in the Linker Region Name. Set the rest of the items in the
Linker Section Name list to the Altera On-chip Memory (OCRAM) or external
RAM.

70
Note: The following steps apply to both first and second Nios II applications.
1. In the Nios II SBT tool, right click on your project in the Project Explorer
window.

71
5. The “mem_init_generate” macro will create two HEX files; <OCRAM_name>.hex

and <QSPIFlash_name>.hex. Use <QSPIFlash_name>.hex for boot option 4
and 5 as you are booting from QSPI flash, not from OCRAM.
1.5.3.2.6 Hardware Programmer Object File (.pof) Generation

5. Under Input files to convert, select Page_0 and click on Add File button on the
right.
6. Browse to the first .sof file and click OK.
7. Click on Add Sof Page to create additional page for .sof file. This creates SOF
data Page_1 automatically.
8. Click Add File… and point to the second .sof file to add into Page_1.

72
Figure 91. SOF to POF Files Conversion Settings
Related Links
1.5.3.2.7 Software Programmer Object File (.pof) Generation
Important: The quartus.ini file with PGMIO_SWAP_HEX_BYTE_DATA=ON content is required to

byteswap the programming file during the POF generation. Please create the
quartus.ini file or use the quartus.ini available in the related information and
place it under Quartus II tool directory or project directory before you proceed.
3. Set Mode to 1-bit Passive Serial.
4. Set Configuration device to CFI_512Mb.
6. Remove the SOF Page_0.
7. Click on Add HEX Data, choose the HEX file generated in HEX Generation
section. Select Absolute Addressing and click OK.
8. Repeat Step 7 to add second HEX file.

73
Figure 92. HEX to POF file Conversion Settings
Related Links
Quartus.ini file
1.5.3.2.8 POF file Programming into QSPI flash

1. Programming Parallel Flash Loader into MAX10 Device
Note: You need to program the parallel flash loader into the MAX 10 device before
programming the QSPI flash.
a. Create Parallel Flash Loader for MAX 10 FPGA in the Quartus II. Assign QSPI
pins based on your design. Compile the project to obtain max10_qpfl.sof
file.
b. Open Quartus II programmer from the Quartus II tool (Tools ->
Programmer).
c. Make sure the Hardware Setup is set to USB blaster.
d. Click on Auto Detect, select your MAX10 FPGA and select OK.
e. Right click on the MAX 10 FPGA and select Edit -> Change File. Choose the
max_qpfl.sof file.
f. Check MAX 10 device under Program/Configure and click Start to start
programming.
g. Click on Auto Detect after max10_qpfl.sof is successfully programmed.
Click Yes if you are asked to overwrite the existing settings. A new QSPI flash
device will be shown on the screen.

74
Figure 93. Programming Parallel Flash Loader Programmer Settings
2. Programming HEX image into QSPI Flash

a. Right click on the QSPI device and select Edit -> Change File. Choose the
generated POF file from Software POF Generation section.
b. Check the HEX file under Program/Configure column and click Start to start
programming.
Figure 94. HEX Image Programming into QSPI Flash

75
1.5.3.2.9 Programming Hardware Design POF File into the MAX10 FPGA
1. After you successfully programmed HEX data into Quad SPI flash, right click on
the MAX 10 FPGA and select Edit -> Change File. Choose the hardware POF file
generated from Hardware POF Generation section.
2. Check the MAX10's CFM0 and UFM under Program/Configure column and click
Start to start programming.
Figure 95. POF Image Programming into QSPI Flash
Related Links
• Hardware Programmer Object File (.pof) Generation on page 72
1.5.4 Summary of Nios II Processor Vector Configurations and BSP

Settings
The following table shows a summary of Nios II processor reset and exception vector
configurations, and BSP settings.

76
Table 11. Summary of Nios II Processor Vector Configurations and BSP Settings
Boot Option Reset Exception BSP Editor Setting: BSP Editor
Vector Vector Settings.Advanced.hal.linker Setting: Linker
Configurati Configuration Script
on
Option 1: Altera On- 1. OCRAM/ If the exception vector memory is set • Set .text
Nios II processor chip Flash External to OCRAM/ External RAM, enable the Linker Section
application execute-in- RAM, OR following settings in to Altera On-
place from Altera On-chip 2. Altera On- Settings.Advanced.hal.linker: chip Flash
Flash (UFM) chip Flash • allow_code_at_reset • Set other
• enable_alt_load Linker
Sections
• enable_alt_load_copy_rodata
(.heap, .rwd
• enable_alt_load_copy_rwdata ata, .rodata,
• enable_alt_load_copy_exceptions .bss, .stack)
If the exception vector memory is set to OCRAM/
to Altera On-chip Flash, enable the External RAM
following settings in
Settings.Advanced.hal.linker:
• allow_code_at_reset
• enable_alt_load
• enable_alt_load_copy_rwdata
Option 2: Altera On- OCRAM/ Make sure all settings in Make sure all
Nios II processor chip Flash External RAM Settings.Advanced.hal.linker are Linker Sections
application copied from left unchecked are set to
UFM to RAM using boot OCRAM/ External
copier RAM
Option 3: OCRAM OCRAM Enable allow_code_at_reset in Make sure all

Nios II processor Settings.Advanced.hal.linker and Linker Sections
application execute-in- other settings are left unchecked. are set to OCRAM
place from Altera On-chip
Memory (OCRAM)
Option 4: QSPI flash 1. OCRAM/ If the exception vector memory is set • Set .text
Nios II processor External to OCRAM/ External RAM, enable the Linker Section
application executes in- RAM, or following settings in to QSPI Flash
place from QSPI flash 2. QSPI Flash Settings.Advanced.hal.linker: • Set other
• allow_code_at_reset Linker
• enable_alt_load Sections(.hea
p, .rwdata, .r
odata, .bss, .
• enable_alt_load_copy_rwdata stack) to
• enable_alt_load_copy_ exceptions OCRAM/
If the exception vector memory is set External RAM
to QSPI Flash, enable the following
settings in
Settings.Advanced.hal.linker:
• allow_code_at_reset
• enable_alt_load
• enable_alt_load_copy_rwdata
Option 5: QSPI flash OCRAM/ Make sure all settings in Make sure all
Nios II processor External RAM Settings.Advanced.hal.linker are Linker Sections
application copied from left unchecked are set to
QSPI flash to RAM using OCRAM/ External
boot copier RAM

77
1.6 Appendix A: Booting Elements

All Nios II processor boot options introduced in this application note use the following
booting elements to create the necessary boot files:
• The memcpy-based boot copier
• The alt_load function
• The Nios II SBT "make mem_init_generate" target
• The Convert Programming Files feature
1.6.1 Nios II Processor Memcpy-based Boot Copier

The Nios II processor memcpy-based boot copier has the following features:
• Supports EPCQ, CFI, QSPI and Altera On-chip Flash (UFM) flash memories
• Locates software application in the memory
• Unpacks and copies software application image to RAM
• Automatically switches to application code in RAM after copy completes
The memcpy-based boot copier is used to support boot option 2 and 5. The memcpy-
based boot copier is automatically appended into the HEX file during memory
initialization file generation ("mem_init_generate" target). When you download
your .pof file into the FPGA, the boot copier will be placed at the beginning of the
UFM or QSPI sector and the software application will be placed at the end of the boot
copier.
The function of the memcpy-based boot copier is to copy the software application
image to the RAM which is the entry point indicated by the software application (ELF
file). Depending on the system design, RAM can be either OCRAM or external RAM .
Once the copying is done, the boot copier will pass the system control to the
application in RAM.
Figure 96. Memory Map of An Example System Using Default Boot Copier
Memory Map
RAM &
FPGA RAM
Application
RAM base
UFM Flash
Application
Boot Copier
UFM base

78
1.6.2 The alt_load() function

The alt_load() function is a mini-bootcopier included in the HAL code and provides the
following capabilities:
• Optionally copies sections from the boot memory to RAM based on BSP settings.
• Able to copy data sections (.rodata, .rwdata, .exceptions) to RAM but not
the code sections (.text).
The alt_load() function can be enabled in the BSP Settings as shown in the following
table:
Table 12. BSP Settings and the alt_load() Functions

BSP Settings Functions
hal.linker.enable_alt_load enable alt_load() function
hal.linker.enable_alt_load_copy_rodata alt_load() copies .rodata section to RAM
hal.linker.enable_alt_load_copy_rwdata alt_load() copies .rwdata section to RAM
hal.linker.enable_alt_load_copy_exceptions alt_load() copies .exceptions section to RAM
1.6.3 Nios II SBT Makefile “mem_init_generate” Target

The Nios II SBT application Makefile “mem_init_generate” target is responsible for
generating memory initialization files using various file conversion tools. This includes
a HEX file for the UFM data, a HEX file for initialization of the on chip RAM in the SOF
and a DAT file for initializing the on chip flash model for simulation.
When required, the Nios II SBT tool automatically adds the Nios II processor memcpy-
based boot copier to the system when the executable file (.elf) is converted to
memory initialization file (.hex). This operation take place whenever the .text
section is located in a different memory that the reset vector points to, which indicates
a code copy is required. The file conversion happens during execution of “make
mem_init_generate” target.
The "make mem_init_generate" target generates different HEX file content based on
the specified boot options:
• For boot option 1, 3 and 4 the generated HEX file contains ELF loadable section.
• For boot option 2 and 5, the generated HEX file contains the boot copier and the
ELF payload.
The mem_init_generate target also generates a Quartus II IP file (meminit.qip).

Quartus II software will refer to the meminit.qip for the location of the initialization
files.
1.6.4 The Convert Programing Files Option

You can use the Convert Programming Files option in Quartus II software to convert
programming files from one file format to another. This tool is used for combining
a .sof and a HEX file into a single .pof file for programming into the Altera On-chip
Flash.

79
1.7 Appendix B: Boot Time Performance Analysis

Intel performed a boot time performance analysis for MAX 10 FPGA based on several
use cases. This section provides guidance on how to reduce Nios II boot time in
MAX10 design and boot time estimation based on performance analysis. You can use
the information in this section as a guideline when designing your custom design.
Figure 97. Boot Time Performance Analysis Design Block Diagram
Diagram shows the design was being used to run the MAX 10 FPGA boot time
performance analysis. The Nios II processor was configured with special settings for
some of the use cases.
MAX 10 FPGA (10M50DAF484C6GES)
CPU QSPI Flash QSPI
Data Master Controller Flash
Nios II
75 MHz Instruction DDR3 UniPHY, DDR3
Master 300 MHz
On-Chip Memory
On-Chip Flash
Boot Time
Performance
Counter Sysid JTAG UART
UART 0 Timer 10 μs
UART 1 Timer 100 ms
Avalon SPI Master LED
Avalon SPI Slave 0 Parallel I/O
Avalon SPI Slave 1
Regardless of the boot device, there are only 2 types of boot methods:
1. Nios II processor application execute-in-place.
2. Nios II processor application copied from boot device to RAM using boot copier.
For boot performance analysis, the Nios II processor application sizes varies between
10kB to 64kB.
Boot Time Performance Analysis Design Example
The design example was tested on the MAX 10 10M50 Development Kit (Rev B) on
using the Quartus II software v15.0 build 145.

80
The design example boots from the Altera On-chip Flash (UFM). If you want to boot
from other boot memory device, you have to change the reset vector and BSP settings
according to Table 11 on page 77.
Related Links
Boot Time Performance Analysis Design Example
1.7.1 Boot Time Measurement Strategy

The boot time measurement was done using a boot time performance counter. The
boot time counter starts when Nios II comes out of reset and the system will start the
boot sequence according to the selected boot options:
1. Nios II processor application execute-in-place:
• The Alt_load() function copies data sections
(.rodata, .rwdata , .exceptions) from boot memory to RAM.
• The code section (.text) remains in the boot memory.
• Automatically jump to the user generated application code in the boot memory
after copy completed.
• Run system/ driver initialization (alt_main).
2. Nios II processor application copied from boot device to RAM using boot copier:
• Bootcopier locates the software application in the boot memory and copies the
software application to RAM.
• Automatically jump to the user generated application code in the RAM after
copy completed.
• Run system/ driver initialization (alt_main).
The boot time counter is controlled through software and it will stop once the driver
initialization completes.
Figure 98. Boot Time Measurement

Nios II Reset Edge Start Boot Time Counter
Detection 0. Reset
1. Processor jumps to reset vector (boot code start)
• Bootcopier start and 2. Boot code initializes the processor

“copy data” (depending
on boot options) 3. Boot code initializes the application code/data memory space/data
Boot Time
• Drivers initialization 4. Application code may be copied to another memory location
(alt_main)
5. Boot code initializes all the system peripherals with HAL drivers (alt_main)
6. Entry to main
void main ( void )
{ 7. Stop boot time counter
IOWR (BOOT_TIME_ Stop Boot Time Counter
COUNTER_BASE, 0, 0) ;

81
1.7.2 Reducing Nios II Boot Time in MAX 10 FPGA Design

There are a few elements that you can consider to improve the Nios II boot time in
MAX10 designs. Based on the Nios II Boot Time analysis that Intel has performed, the
following subsections can be referred to for general guidance.
1.7.2.1 Boot Methods

1. Nios II application boot time for execute-in-place is faster than using a boot
copy/run from RAM based boot (due to the time taken to copy the code to RAM
being much longer than the time gained by the higher performance when running
from RAM instead of ROM).
2. The boot copier method is recommended for systems that require higher
performance. Although this configuration takes longer to boot, it delivers higher
application performance compared to an execute-in-place configuration.
1.7.2.2 Boot Device Performance

1. For Nios II application execute-in-place, different boot devices will have different
boot times based on their individual memory performance.
2. The following shows the performance for the supported boot device in MAX 10
FPGAs, when Nios II applications execute-in-place:
Figure 99. Supported Boot Device Performance

Fastest Slowest
On-chip Memory On-chip Flash
(OCRAM) (UFM) QSPI Flash
1.7.2.3 Peripheral Initialization
Nios II systems initialize all HAL peripherals before main() by default, therefore the
boot time has a dependency on the peripherals selected. Peripherals that are slow to
initialize or have external dependencies, will increase the boot time and potentially
make it less deterministic. If this occurs, you need to calibrate the external memory
such as DDR3 for it to work properly.
DDR3 is an example of a peripheral where the initialization time is significant in

comparison to the boot time. The calibration time is long particularly when compared
to boot times for execute-in-place boot configurations. The calibration time will
significantly impact Nios II application that execute-in-place.
To avoid this, in execute-in-place boot configurations, remove the external memory

from the Nios II linker region if it is not in use. If size is not an issue, you can choose
to use OCRAM. If you are confident working with Nios II software, another option is to
remove the DDR3 initialization routine from the boot code and initialize the memory
later–once the application code has started running.

82
1.7.2.4 Nios II Processor Caches

1. Enable Nios II processor caches. Caches improve the boot time because the data
and instruction caches reduce memory bandwidth limitations during the boot
sequence.
2. You can add caches to your Nios II hardware configuration for both execute-in-
place or bootcopier boot methods to improve boot time.
Figure 100. Nios II Design Block Diagram with Processor Caches Enabled

CPU QSPI Flash QSPI
Nios II
Master 300 MHz
32KB Data 32KB Instruction On-Chip Memory
Cache Cache
On-Chip Flash
Boot Time
Performance
UART 0 Timer 10 μs
UART 1 Timer 100 ms
Avalon SPI Slave 1
1.7.2.5 System Speed
Using Nios II processor with higher clock speed improves the boot time. For example,
you can increase the Nios II processor speed from 75 Mhz to 125 MHz.

83
Figure 101. Nios II Design Block Diagram with Higher System Speed

CPU QSPI Flash QSPI
Nios II
Master 300 MHz
On-Chip Memory
On-Chip Flash
Boot Time
Performance
UART 0 Timer 10 μs
UART 1 Timer 100 ms
Avalon SPI Slave 1
1.7.2.6 MAX 10 FPGA Nios II Flash Accelerator
Enable the Nios II flash accelerator when system resets from the MAX 10 FPGA on-
chip flash to improve the boot time.

84
Figure 102. Nios II Design Block Diagram with Flash Accelerator Enabled

CPU QSPI Flash QSPI
Nios II
Master 300 MHz
Flash On-Chip Memory
Accelerator
On-Chip Flash
Boot Time
Performance
UART 0 Timer 10 μs
UART 1 Timer 100 ms
Avalon SPI Slave 1
Related Links
AN-740: Nios II Flash Accelerator Using MAX 10
1.7.3 Boot Time Performance and Estimation
1.7.3.1 Boot Time Performance for Design that Boots from On Chip Flash with
Flash Accelerator
The following bar graphs show the boot time performance for designs that boot from
on-chip flash (application code stored in on-chip flash) with and without the flash
accelerator (FA) unit. Three scenarios have been evaluated:
1. Design with EMIF that runs from external memory DDR3 (using boot copier).
2. Design without EMIF that runs from on-chip memory (using boot copier)
3. Design without EMIF that runs from on-chip flash (execute in-place)
Note: None of the designs include an instruction or data cache.

85
Figure 103. Summary of Boot Times for Designs that Boot from On-Chip Flash with or
without Flash Accelerator
5.0
4.66 M
4.5 Without FA (9kB App)
4.0 With FA (9kB App)

Without FA (32kB App)
3.5
(Clock Cycle in millions) With FA (32kB App)
Boot Time Counter
3.0
2.70 M
2.68 M 2.6 M
2.5
2.14 M
2.0
1.5
1.0
0.75 M
0.63 M
0.5
0.17 M
25.8 k 5.5 k 25.8 k 5.7 k
Run from External Memory On-Chip Memory On-Chip Flash
Figure 104. Boot Time for Design with EMIF that runs from External Memory (DDR3)
5.0
4.66 M
4.5 Without FA
4.0 With FA
3.5
(Clock Cycle in millions)
Boot Time Counter
3.0
2.68 M 2.60 M
2.5
2.14 M
2.0
1.5
1.0
0.5
9kB App 32kB App

Run from External Memory
The boot time was reduced by ~20% and ~44% for 9 kB and 32 kB application sizes
respectively when the Nios II FA is enabled. Larger application sizes will result in
longer boot times because the code has to be copied from the on-chip flash to the
external memory during the boot process. Overall, the boot time for the scenario
where the boot code is running from the external memory is the slowest. This is due
to the long time taken by external memory calibration during system boot up and the
time taken to copy the application code to external memory.

86
Figure 105. Boot Time for Design without EMIF that runs from On-Chip Memory
3.0
2.70 M Without FA
With FA
2.5
2.0
(Clock Cycle in millions)

Boot Time Counter
1.5
1.0
0.75 M
0.63 M
0.5
0.17 M
9kB App 32kB App

Run from On-chip Memory
respectively when the Nios II FA is enabled. Running the boot code from the on-chip
memory is faster than running from external memory because the on-chip memory
does not need to go through memory calibration during system boot up. Additionally,
access time to the on-chip memory are faster than those for external DDR3 memory.
Figure 106. Boot Time for Design without EMIF that runs from On-Chip Flash (Execute In-
Place)
30
Without FA
25.8 k 25.8 k With FA
25
20
(Clock Cycle in thousands)
Boot Time Counter
15
10
5.5 k 5.7 k
5
9kB App 32kB App

Run from On-chip Flash

87
respectively when the Nios II FA is enabled. Running the boot code from the on-chip
flash (excute in-place) is faster than running from external memory and on-chip
memory. This is because the code executes in-place directly from the on-chip flash
and does not need to be copied into the external memory or on-chip memory for
execution which saves a lot of time.
1.7.3.2 Boot Time Estimation
The tables below show estimates of boot time for different MAX 10 FPGA boot
configurations. The boot time shown will help you to gauge the boot configuration
required for your system design.
Notes: • Instruction or data cache and flash accelerator are not enabled in the design.
• Boot time values are based on design with 75 MHz Nios II processor speed.
Table 13. Boot Time Estimation on Execute-in-place test cases

Test Case Boot From Boot Time Counter (Approximate Nios Boot Time
II Clock cycles)18 (millisecond)
On Chip Flash 41,000 0.55

Design without External
On Chip Memory 18,000 0.24
Memory
QSPI Flash 410,000 5.5
On Chip Flash 2,000,000 27

Design with External
On Chip Memory 2,000,000 27
Memory
QSPI Flash 2,300,000 31
Table 14. Boot Time Estimation on Boot Copier test cases

Test Case Boot from Run From Boot Time Counter Boot Time
(Clock cycle)19 (millisecond)
Design without External On Chip Flash On Chip Memory 2,800,000 37

Memory
Quad SPI Flash On Chip Memory 28,000,000 370
On Chip Flash External Memory 4,700,000 63

Design with External
Memory
Quad SPI Flash External Memory 30,000,000 400
18 Boot time counter is applicable to all software application (.elf) sizes.
19 Boot time counter is for every 32kB .elf size.

88
1.8 Document Revision History

Table 15. Document Revision History
Date Version Changes
February 2017 2017.02.21 Rebranded as Intel.
May 2016 2016.05.24 • Updated Configuration and Booting Flow figures for all boot options.
• Updated BSP Editor Settings for Boot option 3.
• Updated Summary of Nios II Processor Vector Configurations and BSP
Settings table.
• Updated Programming Hardware Design POF File into the MAX10 FPGA
step for Boot option 4 and 5 dual compressed images.
• Added note in Programmer Object File (.pof) Generation for Boot option 3.
November 2015 2015.11.19 • Added Boot Time Performance for Design that Boots from On Chip Flash
with Flash Accelerator subsection.
September 2015 2015.09.15 • Replaced MAX 10 FPGA Nios II Design Boot Time Estimation and Guidance
with Boot Time Performance Analysis and Estimation section.
• Restructure boot options and flow by combining boot options and
guidelines.
• Added Boot option 4 and boot option 5 supporting QSPI.
• Added Boot Time Performance Analysis design example information and
link.
June 2015 2015.06.15 • Added MAX 10 FPGA Nios II Design Boot Time Estimation and Guidance
section containing boot time performance analysis.
• Added The alt_load() function table.
• Added ROM Size Requirement to RAM and ROM Size Requirement For Each
Boot Option table.
• Added block diagrams for all boot options in Nios II Processor Booting
Options Using On-chip Flash.
• Added OCRAM size in UFM and CFM Array Size table.
• Added Boot Option: 3 Nios II processor application execute in-place from
Altera On-chip Memory.
• Updated 'Configuration and Booting Flow' to include Boot Option: 3.
• Updated Steps to Build a Bootable System to Guidelines to Build a
Bootable System.
• Updated Single Uncompressed/Compressed Image Bootable System
Guideline to support Single Compressed Image Mode.
• Added the third guideline; 'Single Uncompressed/Compressed Image with
Memory Initialization Bootable System Guideline'.
• Editorial changes.
January 2015 2015.01.23 Initial release.

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