2013 Computer Architecture: CS/B.Tech/CSE/NEW/SEM-4/CS-403/2013

Name : ……………………………………………………………
Roll No. : ……………………………………………..…………..

Invigilator’s Signature : ………………………………………..
CS/B.Tech/CSE/NEW/SEM-4/CS-403/2013
2013
COMPUTER ARCHITECTURE
Time Allotted : 3 Hours Full Marks : 70
The figures in the margin indicate full marks.
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Candidates are required to give their answers in their own words
as far as practicable
GROUP – A
t.c
( Multiple Choice Type Questions )
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1. Choose the correct alternativ s for the following : 10 × 1 = 10
i) The performance of a pipelined processor suffers if

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a) the pipeline stages have different delays
b) consecutive instructions are dependent on each

other
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c) the pipeline stages share hardware resources
d) all of these.
ii) What will be the speed up for a 4 segment linear

pipeline when the number of instruction n = 64 ?
a) 4·5 b) 3·82
c) 8·16 d) 2·95.
4402 [ Turn over

iii) In which type of memory mapping there will be conflict

miss ?
a) Direct mapping
b) Set associative mapping
c) Associative mapping
d) Both (a) & (b).
iv) Example of a recirculating network is
a) 3 cube network
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b) ring network
c) tree network
d) mess connected Illiac network.

t.c
v) Array process is present in
a) MIMD b) MISD
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c) SISD d) SIMB.
vi) Which type of data hazard is not possible ?

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a) WAR b) RAW
c) RAR d) WAW.
vii) In general 64 input Omega network requires

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.. ............... stages of 2 × 2 switches.
a) 6 b) 64
c) 8 d) 7.
viii) Virtual address space can be divided into some fixed

size
a) segments b) blocks
c) pages d) none of these.
4402 2
ix) MIPS means
a) Multiple Instruction Per Second
b) Millions of Instruction Per Second
c) Multi-Instruction Performed System
d) None of these.
x) Which is not the property of a memory module ?
a) Inclusion b) Consistency
c) Capability d) Locality
GROUP – B
om
( Short Answer Type Questions )
Answer any three of the following. 3 × 5 = 15
t.c
2. For the code segment given elow, explain how delayed
branching can help :
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I1 LOAD R1, A
I2. Dec R3 1
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I3. BrZero R3, 15
I4. Add R2, R4

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I5. Sub R5, R6
I6. Store R5, B
3. A certain program generates the following sequence of word

addresses :
4, 5, 12, 8, 10, 28, 6, 10
A page has four words; the number of page frames in main

memory is 3. How many page faults are generated if
optimum page replacement policy is used ?
4402 3 [ Turn over

4. Draw data flow graph to represent the following

computations :
1. A=P+Q
2. B=A/Q
3. C=P✳A
4. D=C–B
5. E=C✳A
6. F=D/E
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5. For the following code show how loop nrolling can help
improve instruction level parallelism ( ILP ) p rformance :
Loop1 : I1 : Load R0, A (R1 )

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; A is the starting address of
array location
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R1 holds the initial address of

the element
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I2 : Add R0, R2 ; R0 ← R0 + R2, R2 is a scalar
I3 : Store R0 A (R1 )
I4 : Add R1, – 8 ; go to next word in Array of

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doubles
; whose address is 8 bytes

earlier.
I5 : BNE R1, Loop1
6. What is a fundamental difference in interprocessor

coordination mechanism between multiprocessor &
multicomputer systems ? Explain with reference to their
architectural differences.
4402 4
GROUP – C
( Long Answer Type Questions )
Answer any three of the following. 3 × 15 = 45
7. a) What do you mean by cache coherence problem ?
Describe one method to remove this problem and
indicate its limitations. 5
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b) What do you mean by Program Flow Mechanism ?
Compare between Control-Flow Data-Flow and

t.c
Demand-Driven mechanism. 1+4
c) Explain in brief w th neat diagrams the Flynn’s

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classifications of computers. 5
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8. a) What do you mean by loosely coupled and tightly
coupled mu tiprocessors ? 5
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b) Compare & contrast between UMA & NUMA with
examples. What is Dumb memory ? 4+1
c) What are the major differences between segmentation
and Paging ? Why is the page size is usually a power
of 2 ? 3+2
4402 5 [ Turn over

9. a) An address space is specified by 28 bits and

corresponding memory space of 26 bits. If a page
consists of 4K words
i) How many pages and blocks are there in the
system ?
ii) The associative memory page-table contains the
following entries.
Page Block
0 0
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1 1
5 2
6 3
t.c
Make a list of all virtual addresses ( in decimal and in
binary ), that will cause a page fault. 2+3
b) Briefly explain the two wri e policies : write through and
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write back with advantages and disadvantages. 5

c) What are the different types of vector operations ? Give
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different fields in a vector instructions. What is pipeline

chaining ? 3+1+1
10. a) A sy tem has 48 bit virtual address, 36 bit physical
address and 128 MB main memory address. If the
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system has 4096 bytes pages, how many virtual and

physical pages can have address support ? How many
page frames of main memory are there ? 2+2+1
b) Describe the different types of interconnection networks
in computer systems. What is multistage switching
networks ? 4+1
c) What do you understand by instruction pipelining and
arithmetic pipelining ? Why pipeline scheduling is
necessary and how it is done ? 2+2+1
4402 6
11. a) Describe different access methods of the memory
system ? What will be the maximum capacity of a
memory, which uses an address bus of size 8 bit ? 1 + 4
b) What is the objective of OPT page replacement algorithm

policy of virtual memory ? Using LRU, show the page-
fault rate for the reference string
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1. 1+4
c) Define pipelining technique. Assume a 4 stage pipeline :
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Fetch : Read the instruction from the memory
Decode : Decode the instruction

t.c
Execute : Execute the ins ruction
Write : Store the result in destination location

bu
Draw the space- ime diagram for pipelining. 1+4

yw
m
4402 7 [ Turn over

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Name : ……………………………………………………………

Roll No. : ……………………………………………..…………..

The figures in the margin indicate full marks.

1. Choose the correct alternativ s for the following : 10 × 1 = 10

i) The performance of a pipelined processor suffers if

a) the pipeline stages have different delays

b) consecutive instructions are dependent on each

c) the pipeline stages share hardware resources

ii) What will be the speed up for a 4 segment linear

4402 [ Turn over

iii) In which type of memory mapping there will be conflict

b) Set associative mapping

d) Both (a) & (b).

iv) Example of a recirculating network is

d) mess connected Illiac network.

vi) Which type of data hazard is not possible ?

vii) In general 64 input Omega network requires

.. ............... stages of 2 × 2 switches.

viii) Virtual address space can be divided into some fixed

c) pages d) none of these.

ix) MIPS means

a) Multiple Instruction Per Second

b) Millions of Instruction Per Second

c) Multi-Instruction Performed System

x) Which is not the property of a memory module ?

I3. BrZero R3, 15

I4. Add R2, R4

I5. Sub R5, R6

I6. Store R5, B

3. A certain program generates the following sequence of word

4, 5, 12, 8, 10, 28, 6, 10

A page has four words; the number of page frames in main

4402 3 [ Turn over

4. Draw data flow graph to represent the following

Loop1 : I1 : Load R0, A (R1 )

R1 holds the initial address of

I2 : Add R0, R2 ; R0 ← R0 + R2, R2 is a scalar

I4 : Add R1, – 8 ; go to next word in Array of

; whose address is 8 bytes

I5 : BNE R1, Loop1

6. What is a fundamental difference in interprocessor

7. a) What do you mean by cache coherence problem ?

Describe one method to remove this problem and

indicate its limitations. 5

Compare between Control-Flow Data-Flow and

c) Explain in brief w th neat diagrams the Flynn’s

8. a) What do you mean by loosely coupled and tightly

b) Compare & contrast between UMA & NUMA with

examples. What is Dumb memory ? 4+1

c) What are the major differences between segmentation

and Paging ? Why is the page size is usually a power

4402 5 [ Turn over

9. a) An address space is specified by 28 bits and

write back with advantages and disadvantages. 5

different fields in a vector instructions. What is pipeline

system has 4096 bytes pages, how many virtual and

11. a) Describe different access methods of the memory

system ? What will be the maximum capacity of a

memory, which uses an address bus of size 8 bit ? 1 + 4