COA 2022-2023 PYQ --SS1

JISCE / UG / CSE / R18 / EVEN / SEM-4 / CSE401 / 2021-2022
COMPUTER ARCHITECTURE
CS401
TIME ALLOTTED: 3 HOURS FULL MARKS: 70
The figures in the margin indicate full marks.
Candidates are required to give their answers in their own words as far as practicable
GROUP – A
(Multiple Choice Type Questions)
1. Answer any ten from the following, choosing the correct alternative of each question: 10×1=10
Marks CO No.
(i) Difference between RISC and CISC is 1 1
a) RISC is more complex
b) CISC is more effective
c) RISC is better optimizable
d) None of these
(ii) Pipeline stages consists of 1 2

a) Sequential circuits
b) Combinational circuits
c) Consists of both combinational and sequential circuits
d) None of these
(iii) Dynamic pipeline allows 1 2

a) Multiple functions to evaluate.
b) To perform fixed connection.
c) Only streamline connection.
d) None of these.
(iv) Associative memory is a 1 3

a) Pointer addressable memory.
b) Virtual chip memory.
c) Content addressable memory.
d) Slow memory.
(v) VLIW stands for 1 3

a) Very large instruction word
b) Very long institution word
c) Very large institution word
d) Very long instruction word
(vi) The memory which is used to store the copy of data or instructions 1 4
stored in main memory is called ____
a) Register
b) Cache
c) TLB
d) HDD
Page 1 of 3
(vii) Fastest data access is provided using _____ 1 4

a) Cache
b) DRAM’s
c) SRAM’s
d) Registers
(viii) In general, 64 Input Omega Network requires ___________ stages of 1 5

(2*2) switches:
a) 6
b) 7
c) 8
d) 64
(ix) System containing only one processor is called 1 5

a) Multiprocessor
b) Single processor
c) Dual processor
d) Specific processor
(x) Which of the following is not the cause of possible data hazards? 1 5
a) RAR
b) RAW
c) WAR
d) WAW
(xi) The time to access shared memory is same in which of the following 1 2
shared memory multiprocessor models?
a) NUMA
b) UMA
c) COMA
d) ccNUMA
(xii) MIPS stands for 1 1

a) Multiple instructions per second
b) Millions Instructions per second
c) Multi instruction per second
d) None of these
GROUP – B
(Short Answer Type Questions)
Answer any three from the following: 3×5=15
Marks CO No.
2. How do you speed up memory access in case of vector processing? 5 2
3. Explain Superscalar processor with example and diagram. 5 2
4. (a) Draw and explain the Von Neumann architecture. 3 1

(b) Explain the problem of such architecture. 1 1
(c) How to solve it? 1 1
Page 2 of 3
5. (a) Classify Flynn’s classification of computer architecture. 3 2

(b) Describe SIMD architecture. 2 2
6. We have 2 designs D1 and D2 for a synchronous pipeline processor. D1 5 4

has a 5 stage pipeline with execution time of 3 ns, 2 ns, 4 ns, 2 ns and 3
ns. While the design D2 has 8 pipeline stages each with 2 ns execution
time. How much time can be saved using design D2 over design D1 for
executing 100 instructions?
GROUP – C
(Long Answer Type Questions)
Answer any three from the following: 3×15=45
Marks CO No.
7. (a) What is VLIW Architecture? Explain with proper diagram 7 3
(b) Distinguish between tightly coupled and loosely coupled multiprocessor 8 3
system.
8. (a) Explain about Vector instruction format. 5 4

(b) What are the dissimilarities between the multiprocessor system and 5 5 4
multiple computer system?
(c) What is cache memory? Explain briefly. 5 2
9. (a) Explain Vector Register Architecture with proper diagram 8 4

(b) Consider the following pipeline reservation table: 7 5
1 2 3 4 5 6 7 8
S1 X X X
S2 X X
S3 X X X
A. Find out the Forbidden latencies.

B. Find out the initial collision vector.
C. Draw the state transition diagram
10. (a) What is instruction level parallelism? 5 3

(b) What is the difference between array processor and vector processor? 5 3
(c) Briefly describe the VLIW processor architecture. Explain the 5 3

instruction set format of VLIW.
11. (a) Design a butterfly network with diagram 5 5

(b) Compare Omega vs. Baseline network 5 5
(c) What are the different types of multi-stage ICN ? 5 5
Page 3 of 3

COA 2022-2023 PYQ --SS1

Uploaded by

Copyright:

Available Formats

COA 2022-2023 PYQ --SS1

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

COA 2022-2023 PYQ --SS1

Uploaded by

Copyright:

Available Formats

JISCE / UG / CSE / R18 / EVEN / SEM-4 / CSE401 / 2021-2022

(ii) Pipeline stages consists of 1 2

(iii) Dynamic pipeline allows 1 2

(iv) Associative memory is a 1 3

(v) VLIW stands for 1 3

(vii) Fastest data access is provided using _____ 1 4

(viii) In general, 64 Input Omega Network requires ___________ stages of 1 5

(ix) System containing only one processor is called 1 5

(xii) MIPS stands for 1 1

3. Explain Superscalar processor with example and diagram. 5 2

4. (a) Draw and explain the Von Neumann architecture. 3 1

5. (a) Classify Flynn’s classification of computer architecture. 3 2

6. We have 2 designs D1 and D2 for a synchronous pipeline processor. D1 5 4

8. (a) Explain about Vector instruction format. 5 4

9. (a) Explain Vector Register Architecture with proper diagram 8 4

A. Find out the Forbidden latencies.

10. (a) What is instruction level parallelism? 5 3

(c) Briefly describe the VLIW processor architecture. Explain the 5 3

11. (a) Design a butterfly network with diagram 5 5

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.