CHAPTER 1.

INTRODUCTION

1.1 Introduction

Electronic devices have gradually substituted or supplemented many mechanical

systems in vehicles and other systems over the last ten years. This is mostly due to
environmental considerations that necessitate better operating conditions. Various sensors
and electronic control units (ECUs) track various criterion to aid in the monitoring of
device conditions. ECUs must exchange knowledge in order to manage machine
performance effectively. Electronic devices today include hundreds of circuits and other
electrical entities, to put it simply. The Controller Area Network (CAN) is a broadcast and
differential serial bus standard that was designed with automotive applications in mind.
This protocol provides powerful distributed real-time control while maintaining a high
degree of security. A single wire links all of the vehicle's electronic devices, actuators,
and sensors into a single circuit, allowing for high-speed data transfer between all
components. CAN is also used in a variety of other applications, including home
automation, medical equipment, and industrial control.

The high-speed data transfer along with lower circuit complexity has made CAN
the go to technology to be used especially in automobiles. Now constructing a CAN
module in Verilog HDL enables it to very communication systems virtually. Also during
the implementation in hardware the Verilog implementation can reduce the use of an extra
IC removing the extra space occupied and lowering circuit complexity. Synthesis of CAN
module with custom RAM could make it independent of the type of FPGA used. Thus,
the communication in multiprocessor environment can be made easier, faster and
independent of the controllers used.

1.2 Aim and Objectives of the Project

This project aims to design Controller Area Network using Verilog HDL with
custom RAM .

The core objectives which have been designated as fundamentals to the project are:

1. Understanding the Architecture of CAN Protocol.

2. Implementation of the smaller functional blocks using Verilog.
3. Designing and integrating custom RAM.
4. To synthesize and simulate the CAN module.
1.3 Motivation of the project
Sensors need to connect with the sensor network, which requires making use of
interaction components. CAN decreases wiring complexity as well as makes it easy to link
several devices with a single set of cords, allowing information to be traded at the same
time. Due to the various applications that are anticipated and the availability of CAN-
integrated tools on the market, passion in CAN is increasingly growing. In addition, new
emerging modern technologies associated with completely networked environments in
factories, in your home, and somewhere else, where control network methods, rather than
information networks, would be required, could meet a higher demand. Prioritization of
messages; assurance of latency times; configuration flexibility; multicast reception with
time synchronization; system vast data uniformity; multi-master; mistake detection as well
as signaling; automatic retransmission of damaged messages as soon as the bus is idle
again; distinction between temporary mistakes and also long-term node failures; and also
free interaction Such functions enable CAN an enticing communication protocol for both
wired and wireless sensing unit networks.

1.4 Literature Survey

The Control Area Network protocol’s needs and abilities have been studied from [5].
This has provided useful insights on the CAN protocols and how they can be used in a
multiprocessor environment and its message format, and its arbitration types, etc. A model
has been studied in [3] to decrease wiring complexity and to make it easy to connect with
several other devices by pair of wires and thereby allowing data exchange between them
inside communication modules using CAN network. The design was implemented on FPGA
and interfaced with an LM35 temperature sensor. Interfacing of CAN protocol to PIC
microcontroller because the control system has drawbacks of low data transmission
efficiency, host controller with poor flexibility and the data can’t be uploaded automatically,
to overcome this input and display module and MDM are combined through AT90CAN128
and CAN bus making it as multi-host Distributed control system [15]. Development of two
specific applications of the can, one for formula hybrid team and another as a Microprocessor
system class with the main objective to provide CAN solutions on prebuilt boards to
interface microcontroller with a CAN bus [11] has been studied. The formula hybrid’s main
objective is to wirelessly transmit sensor data and provide the basic control for the formula
car. Definition of HDL implementation of a Controller area network node such as to design,
development and implementation of the in-vehicle network which is Control Area Network
(CAN), to meet the need for centralized wiring and device interconnection methods, the
addition of all these hardwired technologies gives large volumes of wires and to overcome
that, this pattern design has been selected [8] and similar pattern has been selected to be
implemented in our project.

1.5 Statement of the Problem

The improvement of CAN has seen upward growth since its inception in the
automobile industry. It has rapidly spreading its wings into more and more industries
making it much more valuable asset. But the use of an additional IC like MCP2515
consumes more space and increases the complexity of the circuit. The aim of the
research presented in this thesis is to create a CAN network using Verilog HDL and with
custom RAM that allows multiple applications to communicate with the network, while
adding functionality and reducing wiring by interfacing this directly in the
microcontroller. The chosen network must be able to reduce the amount of point-to-
point wiring and also eliminates the need of explicit RAM on microcontrollers while
preserving or enhancing the application's existing integrity, as well as provide improved
connectivity to the entire system. 

1.6 Scope of the Project

This thesis presents a novel approach for implementing a Controller Area

Network with a custom RAM in any application wherever CAN is needed. Control Area
Network has been a revelation since its establishment in the field of automobile and
transportation. The ability of CAN protocol to transfer data at higher data rates in the
multiprocessor systems has been the major reason for this. The results of the research
show up an increased complexity while adding increased functionality to the
multiprocessor environment and demonstrating the advantages that can be gained from
the inclusion of reconfigurable logic elements and integration of a custom RAM to them.
The proposed network has been designed in Verilog HDL for hardware
implementations.
1.7 Organization of Thesis

The following is the structure of this thesis:  Chapter 1 (this introduction) presents
the introduction to the project specifying the aim and objectives to be covered. In
Chapter 2, the background material on data communications and the Controller Area
Network is covered. In Chapter 3, the suggested solution for implementing CAN is
presented. In chapter 4, the implementation's outcomes i.e, the synthesis and simulations
are presented. Chapter 5 concludes with a list of achievements and findings, as well as a
discussion of possible research direction.
CHAPTER 2. TRENDS AND ARCHITECTURE OF CAN

2.1 Introduction
The study of CAN, its architecture and its functioning is the first objective that has
to be fulfilled in order to know the CAN module from the scratch level. In this chapter
we introduced the Controller Area Network module’s current implementations and how
different layers are imbibed to it and their functionalities.

2.2 Controller Area Network (CAN)

The CAN protocol, as specified by Bosch, is based on the use of a message
identifier to identify transmitted messages. Both nodes search to see if the message is
valid based on the received message identifier [2]. As a result, messages may be
accepted by a single node, a group of nodes, or all nodes. The priority of bus access is
also determined by the message's identifier. To put it another way, CAN provides
schemes for prioritizing message access to the bus.

A master does not manage bus access in a CAN network; instead, any node can
transmit as soon as the bus is idle. In a competitive usage scheme like this, it's likely that
many nodes will want to fill the bus at the same time. In other protocols, a case like this
would result in messages being lost. The CAN protocol has developed an access
mechanism that ensures that the message with the highest priority is granted access first,
followed by subsequent messages without being destroyed. The data rate of up to 1 Mb/s
and the CAN network's robustness are perhaps the two most appealing features of the
CAN protocol. CAN defines two data lines that transmit the same information. The
network is not hampered if one line is disabled or grounded, but noise immunity is
reduced. The CAN protocol also has the ability to restrict bus access for network nodes
that are malfunctioning. Because of these metrics, CAN can be used to manage real-time
critical functions. CAN nodes are capable of both detecting and confining errors
depending on their magnitude. By restricting bus access by faulty nodes, fault
confinement effectively guarantees bandwidth for critical device details. The Controller
Area Network protocol's advantages made it an excellent candidate for automotive
networks.
 2.2.1 Current CAN Implementations
Many automobile manufacturers have been actively interested in the research and
development of Class C and Class A networks since the early 1980s. The coordinated
efforts were centered on ensuring that real-time, sensitive controls and comfort and
convenience controls communicated with one another. During this time, several different
protocols were developed, but CAN became the most popular for automotive
applications. Mercedes S-class cars were the first to use CAN for contact between the
engine controller, gearbox controller, dashboard, and distributed air conditioning control
in 1992[4]. A short time later, several other car companies followed Mercedes' example.

Many areas related to industrial controls and automotives, such as robots,

medical systems , , textile equipment, buses, trucks, passenger cars, trains and aircraft
have been equipped with CAN. Although the use of CAN in the automotive industry is
well-established, with the increasing interest in electric and hybrid vehicles, CAN is
likely to have a significant impact on the market. In an electric vehicle, the CAN
network is suitable for communication. However, as electric vehicles and drive-by-wire
applications become more common, there is a need for CAN updates for safety-critical,
real-time automotive systems. Although there are a wide range of protocols suitable for
use in automobiles, certain basic concepts are shared by all of them. The following
discussion focuses on the foundations of data communications, which serve as a
foundation for comprehending the Controller Area Network. Transfer of data takes place
between two devices that are directly connected by a point-to-point medium in its most
basic form. Many devices are also impractical to connect directly by point-to-point
wiring, as is the case in an automobile. A bus-organized structure is an alternative
topology for connecting a group of devices over a shared communication network. The
concept is illustrated in the below Figure 2.1

Figure 2.1 — Example of data transfer using (a) point-to-point transmission medium and
 device interconnections using a (b) bus-organized communications network

2.3 Data Communications Reference Model

Protocol and protocol architecture are two main principles that must be understood in
order for devices in a network to interact effectively with one another. In general, a computer
or node in a network can both send and receive data. As a result, two such devices must
"speak the same language" in order to interact properly with one another. To ensure this, all
devices must adhere to certain guidelines.

A protocol is a set of rules that includes three main elements:

1)Syntax

2)Semantics

3)Timing

Sequencing , error handling, Data format and control of the corresponding data
transmission, the appropriate form for data transmission, and timing of transmission are
all governed by these three elements.

The majority of network applications use a layered approach to system

development. The open systems interconnection (OSI) model established by the
International Standards Organization is the primary reference for most protocol
specifications (ISO).
In accordance to the Open System Interconnection model, data-communication systems can
be represented as a 7-successive layers. The 7 layers are:
1.Application layer
2.Presentation layer
3.Session layer
4.Transport layer
5.Network layer
6.Data Link layer
7.Physical layer

Figure 2.2 demonstrates the 7 layers of the OSI model and a short description of the
operations carried out at each layer.
 Figure 2.2 — The seven OSI layers.
Nonetheless, considering that the version was planned to offer a frame for any kind of sort of
interaction system, some systems do not use all the layers. In most cases, just three layers
(physical layer, information link layer, as well as application layer) matter [3] The Controller
Area Network convention applies majority of the bottom pair of layers of the OSI model.
 2.4 CAN Architecture
The CAN specification divides CAN into layers based on the ISO/OSI reference
model to achieve design clarity and execution compatibility:

1) Data Link

2) Physical

3) Application

The parts that follow explain the fundamental concepts of these three layers and go into
the overall architecture of CAN.

2.4.1 CAN Data Link Layer

In general, the data link layer serves two purposes. The first is the creation of data
frames, which contain data as well as control error detection code. The received control
information allows the receiver to decide whether or not a frame is relevant and whether or
not there was a transmission error. The frames are rejected and retransmitted if a frame is
corrupted.

The second main feature manages bus arbitration, which helps to settle disputes when
several nodes want to use the bus at the same time [7]. The principles of bus arbitration,
the format of a CAN frame, error detection, and error containment are all covered in the
following pages.

I. Bus Arbitration
The CAN convention makes use of a crash avoidance system, carrier-sense several
accessibility with collision evasion (CSMAICA). Although numerous nodes might begin.

1. To handle the raising variety of electronic components.

2. To minimize the expenses associated with complex circuitry electronic components.

To achieve these objectives, a variety of networks were executed with the very same driving
inputs, but this eventually resulted in connect with different qualities, enhancing the truth that
there is no single network procedure that can connect the various systems within a vehicle.
Because there is no global method, the option of one is based upon the particular
application, component availability, and expense, along with meeting the specifications
outlined in the previous area. Table demonstrates the choice of networks gone over in
the previous areas. Among these networks there is a series of useful as well as economic
benefits and also disadvantages. Networks of high data transfer are used for car
multimedia applications, where cost is less important.

Table 2.1 - Selection of automotive networks.

As a result, the node with the lowest concern is removed from bus adjudication and
becomes a receiver of the message. As a result, the bus is given to the node with the
highest priority. Once the bus is no longer expensive, the subordinate node(s) participate in
mediation once more to complete their remaining message (s).

The popular method Ethernet [26] uses the CSMA/CD gain access to technology for
contrast functions. When an Ethernet node wants to start transmitting, it scans the network
to see if any other nodes are transmitting at the same time.When there are no messages
occupying a channel after 96bit times, it is deemed cost-free. If the channel is busy
when the node wants to transmit, the node will absolutely retain track of the
channel until it becomes available. The node continues to monitor the channel for
crashes while sending. If an error occurs during transmission, the transmission is
instantly terminated and a jam signal is broadcast across the network. The jam
signal ensures that all other nodes are alerted to the fact that there has been a crash.
After a collision, the sending node waits for a certain amount of time before
attempting to re-transmit from the beginning.

II.Frame Formats

There are 4 sorts of frames specified by the CAN module:

1) Data frame

2) Remote frame

3) Error frame

4) Overload frame

The CAN requirements details two various, compatible frame formats. There is a
"base format" with an 11-bit structure identifier, as well as an "extended format"
with a 29-bit structure identifier.

1. DataFrame
The begin of frame (SOF), settlement, power, data, CRC, acknowledgement, and
end-of-frame bit fields make up a CAN data structure (Number 2.3). (EOF). It
deserves keeping in mind that the data field can be zero duration [6] The SOF little
bit is a single
leading little bit that
suggests the begin of
data frameworks
and remote
frames. In a CAN
network, a node can
only start arbitration if
the bus is idle or

complimentary. To start bus settlement, all nodes integrate to the cutting edge of
the SOF created by the first node.
Fig 2.3 Standard CAN Data frame
 The identifier area and also the remote transmission request bit (RTR), which is
sent as a leading (0) little bit in an information structure, comprise the settlement field. The
framework identifier determines a structure and determines its concern. The framework
identifier in the base format is 11 bits long, permitting a total amount of 2048 (211) unique
messages. 512 million (229) messages can be distinguished making use of the extended
layout. These bits are transferred in ID order, with ID 10 being the most considerable little
bit.

The control area is described as a six-bit field in the CAN module specification.
The identifier extension bit (IDE) is the first little bit that distinguishes between base and
also expanded styles. The IDE little bit is transferred as a leading degree in the base layout.
The second bit, rO, is scheduled for future Controller Area Network protocol development
as well as is transmitted dominantly until defined. The information length code refers to
the last four littles the control area figure out the variety of bytes transmitted in the doing
well data field [8] As an example, a value of 0 represents 0 information bytes as well as a
value of 8 corresponds to 8 information bytes. The straight binary coding of the number of
data bytes by the data size code is illustrated in Table 2.2.

Table 2.2 — Coding of the number of data bytes by the data length code.
2. Remote Frame
By utilizing the remote frame, any node might initiate transmission of a certain frame
from another node. The identifier transferred with the remote frame defines the structure
asked for by a node. The RTR little bit degree is the difference in between the remote
framework and also information frame design. For the remote structure, RTR is sent at
reasoning high; for the information structure, RTR is sent out at logic reduced [8] If a
remote structure arbitrates simultaneously with a data frame with the same identifier, the
information frame wins arbitration as a result of the variation in transmission speeds.
Another difference in between an information frame as well as a remote framework is
that a remote frame's information field is typically no. Rather than utilizing the
information length as a requirement,the data length code of the remote frame
corresponds to the data size code of the asked for frame, as opposed to defining the
number of data bytes in the information field of the remote structure.

3. Error Frame
In Controller Area Network , an error frame is referred to as a sequence of more
than 5 successive bits of the exact same value within a frame. The error flag as well as
the error delimiter are the two areas that comprise an error frame. Any type of error
discovered during the transmission of an information frame or a remote frame is
suggested by the error frame.
The superposition of error flags sent by one or more nodes is stored in the initial market.
Active and also easy mistake flags are both sorts of error flags. 6 successive logic 0 little
bits comprises the active error flags, while six consecutive reasoning 1 little bits make up
the passive error flag. When an active error node discovers an error state, it elevates an
active flag. Because the flag's type damages the bit-stuffing law, all various other nodes
spot an error and also begin sending their own error flag. As a consequence, the
reasoning 0 little bit sequence managed on the bus is the result of the superimposition of
various node error flags. This sequence has a least of six bits and highest of twelve bits.

When a transmitting node sets a passive error flag within a bit stuffed frame, the
flag will cause errors at receiving nodes. The end result is a bit of a blunder. A mistake
will not be remembered whether the flag is set during arbitration or less than six bits
before the termination of the CRC series that ends in receding bits. The receiver will not
notice an error if the flag is set during arbitration or less than 6 bits before the end of the
CRC series that ends in recessive bits. Any current operation on the bus prevents a
 receiver from sending a passive error flag. As a consequence, after detecting an error state,
error inactive receivers must wait six equal bits to complete their error flag. Each node
sends recessive bits after sending an error flag and tracks the bus level until it detects a
receding bit. After detecting a recessive bit, the node begins transmitting 7 more receding
bits. The error delimiter field determines whether the node was the first to detect an
error.

4. Overload Frame

An overload frame can be thought of as a more advanced version of an error frame.

An overload flag area and an overload delimiter make up the overload picture. The
overload frame is used to ask for a pause in the receiver's next data or remote frame, as
well as to signal such intermission field error conditions [11]. The intermission field is a
three-bit recessive bit field that represents a three-bit interval between frames.

5.Error Detection and Handling

The overall high standards for data transmission protection and integrity necessitate
an average of less than one error per 1000 messages (10^3). Inorder to achieve this,
CAN includes a number of detection mechanisms for errors, including:

1) Bit check (monitoring)

2) Frame check

3) CRC check

4) Acknowledgement check

5) Bit stuff rule check

An error flag is produced if any one of these systems are breached. Any kind of
node that sends a signal checks the equivalent bus degree throughout the tracking process.
A bit mistake is observed when the bus level does not match the transmitted level.

Therefore, bit checking is great at finding both international as well as neighbourhood

errors at the transferring node. Establish bit fields, SOF, RTR, IDE, DLC, EOF, and
delimiters exist in all CAN frames. These fixed fields need to be protocol-compliant; a
non-compliant layout field causes a design error, as well as the frame is declined by the
recipient. To enable a receiving node to verify the honesty of a received frame, CAN
utilizes the cyclic redundancy checking (CRC) concept. A CRC error occurs when the
CRC series acquired from the transferring node varies from the CRC sequence determined
by the getting node.

A transferring node anticipates a minimum of one receiver to recognize receipt of a

legitimate frame after transmission is finished. The transmitting node, on the other hand,
produces a recognition mistake if no getting nodes recognize forcibly reasoning 0 in the
recognition slot. The last error-handling procedure reinforces errors that have been found.
Any node that spots an offense of the bit-stuffing rule or simply a mistake flag produces a
mistake structure immediately. For either of the above errors, the resulting mistake
structure will be sent out to all nodes; upon receipt, all nodes will certainly remove the
received bits of the corrupted packet. As soon as informed of the error, the corrupted
message's transmitter will certainly retransmit the original message when the bus becomes
available. Although that these systems have a high degree of error detection, some errors
can constantly go unseen. According to the CAN meaning, the chance of undetected
mistakes at obtaining nodes is less .This implies that for every 20 trillion sent out
messages, just one corrupted message is most likely to go unnoticed. Nevertheless, more
investigation exposes that the residual error for a 10-node network.

2.4.2 CAN Physical Layer

The physical layer of the CAN protocol specifies exactly how the information connect
layer's frameworks or signals are really transferred. Little bit representation, bit timing,
little bit coding and also decoding, and also the physical tool spec are all specified by the
physical layer. The ISO 11898 requirement, parts 1 as well as 2, in addition to the CAN
features, specify the popular CAN physical layer interpretation.

I. Bit Timing

The bit time, tb, in CAN is the moment duration of one bit, which is the reciprocatory of the
bit rate. This bit time is segmented right into 4 segments (Fig. 2.4):
 synchronization sector, breeding hold-up segment, phase barrier segment 1, and also stage
buffer segment 2. Each sector includes a particular quantity of time quantum (tq). Time
quantum is defined as the item of the value of the baud rate prescaler (BRP), which can
include integer values from 1 to 32, and the reciprocal of the system clock (I _(sys)):

The synchronization section is the little bit time portion where signal edges occur, as
well as it is made use of to synchronize Controller Area Network bus nodes. The breeding
hold-up section solves physical hold-up times within the network. Any node integrated to the
bus would certainly run out stage with the transmitting node of the little bit stream seen on
the bus given that a Controller Area Network node is needed to obtain data from another
node throughout its own transmission. Because of this, the proliferation hold-up area should
be twice as long as the number of the two nodes' optimum signal breeding delays.

Edge phase errors, referred to as the distance in between an edge occurring outside the
synchronization segment as well as the synchronization sector, are made up for utilizing
stage buffer sections 1 and 2. The sampling point, which is the time when the bus degree
reads and interpreted as a bit worth, divides the barrier segments. The phase barrier
sectors can be changed depending on the side stage mistake to successfully change the
 sample point as well as therefore recover the tasting point about the present bit location.
As an example, the signal side would certainly get here after the synchronization segment
if the transmitter operates at a slower clock rate than the receiver.

By changing the sampling point, the receiver compensates. As shown in Number 2.5, this
is achieved by prolonging phase buffer sector 1 by an amount equal to the error. In the
case where the transmitter is quicker than the receiver, the very same method uses.

Figure 2.5 — Principle of resynchronization on a late edge.

The changes made to the phase buffer sections are only short-lived. At the next bit time,
the segments will certainly return to their original states as long as there are no phase
errors discovered in that bit time [9].

II. Physical Signaling

In the CAN method, The Non-Return-to-Zero (NRZ) code is utilized to physically

represent the bits of a framework. Considering that a communication medium can not
usually approve symbols in their "natural" kind, signs are instead sent utilizing line
codes.
 Figure 2.6 — NRZ bit representation.

Signs in CAN are transmitted utilizing the baseband line coding

technique NRZ. NRZ defines two bit degrees, leading (0) and recessive (1).
Throughout the bit time interval, the generated bit level remains consistent. Therefore,
there could be no sides available for synchronization, causing a relatively long stream
of data little bits of equal worth. To get rid of synchronization issues and also error
structure conflicts, Can controller carries out a bit stream coding technique referred to
as bit stuffing.
Generally, a transmitter applying little bit stuffing inserts an extra bit (stuff bit)
of complementary worth after a suggested amount of successive bits (things width) of
the same degree (Figure 2.7). On the receiver side, the procedure is turned around as
well as the inserted bits are eliminated. Controller Area Network utilizes a stuff width
of 5 bits; this makes certain that a sequence of six bits of equivalent polarity is an
infraction of the little bit padding guideline and also will certainly be:

Fig 2.7 Principle of bit stuffing with a stuff width of 5 bits, where S is the stuff bit.
2.4.3 CAN Application Layer

The Controller Area Network requirement just defines layers 1 and also 2 of the
OSI model. Software generally executes higher layers, such as the application layer (layer
7). Enabling application-specific layout by leaving this higher layer undefined. To carry
out network management, node tracking, as well as various other features, extra
performance not provided by the physical layer is normally needed. This is done by
making use of standardized upper layer procedures to bridge the gap in between the
application and the CAN requirement.

Because of the prevalent use of CAN and also the varying goals of each
implementation, a number of higher layer methods have been standardized. The 3
predominant procedures include:

1) CAN Application Layer (CAL)

2) CAN open.

3) DeviceNet

The development of these higher layer methods has led to interoperability of

devices from varying manufacturers.

Interoperability of gadgets from numerous makers has been made possible thanks
to the improvement of these greater layer protocols. The extent of this procedure does not
consist of all of the needs for the greater layer protocols. In summary, all 3 procedures
have attributes that produces much better interaction. For instance, CAN open enables a
master node or an outside configuration tool to set up each node. The communication
actions of a system is controlled by the parameters established by the setup. This identifies
that goes where, what enters into which message or address, and when the message is sent.
Essentially, the higher layer procedures support the intelligence of a given application.

2.5 Conclusion

In this phase, a review of the Controller Area Network protocol with it's current
applications has actually been presented. The method was explained in regards to the
ISO/OSI layers 1 as well as 2 and develops the CAN message framework, bus arbitration
process, mistake detection, and also timing specs. With an understanding of the method,
the complying with chapter defines the technique for the HDL application of the method.
CHAPTER 3. HDL IMPLEMENTATION OF CAN

3.1 Introduction
There are two methods to carrying out the Controller Area Network design. A CAN
controller node can be constructed making use of off-the-shelf parts or by using an Hardware
description language to develop the node. VHDL as well as Verilog, are 2 preferred sorts of
hardware description languages that can be utilized to design an electronic tool from the
algorithmic degree to gate level. These languages enable a system to be stood for in a
hierarchical way; that is, the system can be designed as an affiliation of elements, with each
part modeled as a collection of interconnected subcomponents.

3.2 Design Flow

Figure 3.1 shows the HDL design process. The specification step of the design
process establishes the system's functional requirements. Regardless of the system's
intricacy, mixing and communications between simpler pieces must be specified.

Figure 3.1 — Overall HDL design process

 When the requirements are identified, private modules and their routines are
defined on a system level. After that, the hardware layout flow describes characteristics at
the reasoning level as well as during synthesis; the system's Boolean functions are obtained
and also mapped to elements of an Application Details Integrated Circuit (ASIC) or Field
Programmable Gate Array (FPGA). Creating a Controller Area Network node with an
HDL allows the CAN controller subsystem to be integrated with many other logic
elements in an FPGA. A microprocessor, for example, might be made up of a suitably big
FPGA [8]. In a context where reconfigurability is required, using an FPGA provides
flexibility. Furthermore, HDL provides a simple technique of converting the system layout
to full-custom silicon or another destination.

3.3 CAN Module Specification

In general, a CAN component, or node, can be broken down into functional blocks,
as shown in Figure 3.2. The Controller Area Network bus lines, CAN high and CAN low,
are connected to the module using a CAN transceiver at the most cost-effective level. The
transceiver is in charge of message transmission and function to and from the Controller
Area Network bus.

Fig 3.2 - Typical CAN module configuration

3.4 CAN Protocol Controller
The selected solution focuses on the style of a CAN controller with user interface
to attach to an explicit trans-receiver as well as microcontroller. The primary step in the
HDL design procedure is to define all of the CAN controller's specs.

The CAN controller is accountable for a range of activities, consisting of:

1. Bus arbitration

2. Cyclic Redundancy check

3. Frame generation

4. Insertion as well as deletion of stuff bits

5. Synchronization.

6. Detection of errors.

To relieve the microcontroller of time-critical tasks, the CAN controller must carry out all
protocol-related operations in a structure other than the microcontroller.

As received Figure 3.3, the CAN controller module can also be recognized by useful
blocks. Consequently, each task can be designed utilizing a practical block in the CAN
module [12] The benefit of creating the system as a collection of fundamental blocks is
that it soothes the designer of the responsibility of attempting to create the system at one
time. Rather, each block is created independently and after that put together up until every
one of the blocks have been completed.

Fi
gure 3.3 — Structure of the CAN protocol controller
 Additionally, each block can be validated independently, staying clear of the demand
to troubleshoot a whole, complex tool, as is the case with sound software application design
principles. The transformation from design interpretation to usable code is simplified by
specifying the specifications as a collection of demands or pseudo code. If the CAN
controller core is being developed from scratch, the adhering to parts describe the
requirements for transferring to HDL. Nevertheless, because the Controller Area Network
core has actually already been developed, the adhering to specs describe just how it was
built.

3.4.1 Bit Timing Logic

The preliminary block that a bus message experiences is the bit timing Reasoning
(BTL). This block consistently watches on the bus line input and also deals with the linked
little timing according to the CAN protocol. When the BTL spots an adjustment from
receding to leading, it integrates on that particular side and also feature of a new frame can
begin. Nonetheless, as was discussed in Phase 2, there are spreading delays along with stage
shifts that affect sampling factor.

The BTL provides programmable time sectors to offset delays. Bit timing
configuration is embedded in two different set of registers. The BTL is the first block that a
bus message comes across. It continuously tracks the bus input line as well as likewise deals
with the CAN protocol-related bit timing.

When the BTL discovers a recessive to leading transformation, it synchronizes on

that edge, allowing new structure function to start. Nevertheless, as specified in Phase 2, the
sampling factor is affected by propagation delays and stage modifications. To make up for
hold-ups, the BTL supplies programmable time segments. 2 signs up are made use of to
configure the bit timing arrangement.

The proliferation hold-up area as well as stage buffer section 1 (time segment 1) are
merged in one register, as is stage barrier section 2 (time section 2) [14] The synchronization
dive size (SJW), which establishes exactly how far a resynchronization will certainly pass the
sample factor, as well as BRP are incorporated in an additional register.
The range of programmability for each segment are shown in Table 3.1

Table 3.1 CAN bit time parameters

Synchronization takes place on the edges of a Controller Area network as it

progresses from recessive to dominant phases. The objective is to maintain the distance in
between the example points and the edges under control. Edges are spotted by taking a
sample of the bus level in each time quantum and contrasting it to the previous example
point's bus degree. The stage error, e, will be negative, positive, or zero relying on where
the edge is in connection to the synchronization section.
1. e = 0, when the edge is located within the synchronized section
2. e > 0, when the edge occurs after synchronized segment.
3. e < 0, when the edge occurs before synchronized segment.
Hard synchronization and resynchronization are both types of synchronization that can
take place. Hard synchronization happens at the beginning of a framework; just
resynchronization might take place inside a frame. With the end of the synchronization
section, the bit time is reset after a hard synchronization. The edge that triggered the
difficult synchronization is forced to be situated inside the synchronization segment of the
rebooted little bit time by the tough synchronization.
Bit resynchronization includes shifting the sample factor's area about the edge by
reducing or lengthening the bit time. Phase buffer section 1 is expanded when the phase
error is positive (Figure 2.7). Phase barrier section 1 is extended by the amount of the
mistake if the magnitude of the mistake is less than SJW; or else, it is extended by SJW.
When it comes to an adverse phase mistake, stage buffer area 2 is reduced. Phase barrier
section 2 is reduced by the size of the stage error if the size of the mistake is less than
SJW; or else, it is shortened by SJW.
The list below regulations get hardsynchronization and re-synchronization:

1. Just one synchronization is allowed in between instance factors within one bit time.

2. A side will just be taken advantage of for synchronization if the worth detected at the
previous instance element varies from the signal level promptly after the signal side.

3. A challenging synchronization is done whenever there is a recessive to leading side

throughout bus idle issue.

The attributes of the bit timing reasoning make it feasible to put the example variable at
the right placement within a little bit relying on the top-notch of the signal gotten from the
bus [8]

3.4.2 Transmit and Receive Registers

The transmitting as well as receiving register serialize the message bits thar are to
be sent out and also parallelize those message bits that are obtained. The register holds the
data bits to enable the data to be accessed by BSP. Bit Stream Processor manages the load
and shift operations of the registers.

3.4.3 Bit Stream Processor

The BSP carries out numerous conventional tasks. The BSP converts messages
right into frameworks as well as frames into messages. Messages are packed as well as
destuffed in the BSP and also go through CRC check while they are in the Bit Stream
Processor.

Fig 3.4 State Diagram of Bus Arbitration Process

 Throughout the still state of the bus, it remains in the receding state. Adjudication is
introduced with an adjustment from declining to leading via the begin of frame bit. Each
being successful little bit relayed is contrasted to the bus degree as highlighted in the state
design in Fig 3.4. If the broadcasted degree matches the bus degree, after that the complying
with bit is sent. If the bus level does not match the transmitted degree, then the node either
becomes a receiver or there is a mistake. As soon as the node has really completed the
arbitration process, the remainder of the message is transmitted.
3.4.3.1 Frame Generator

The indexing of the information structure is understood depending on the CAN

format (requirement or expanded). When an outcome, as the obtained message is
acknowledged, the indexing may be utilized to evaluate the structures that describe it. The
arbitration field, for instance, is comprised of the first 12 bits in the information frame.
The SOF is the initial bit in that area, adhered to by 11 little bits that specify the identifier
field. With this format specified, the frame generator merely reads the message stream as well
as starts indexing the message once the SOF is received. Consequently, the very first little bit
is saved in a register identified SOF, while the remaining 11 little bits are saved in a register
identified identifier. The very same applies for the staying message and the matching fields
associated with the information structure.

3.4.3.2 Bit Stuffing and De-stuffing

Bit padding is the process of placing non-information little bits right into data to break
up little bit patterns to affect the synchronous transmission of information. The controlled
deletion of the stuffed bits from a stuffed signal inorder to recover the original signal that
existed before padding of the data bits is the process associated with de-stuffing. The bit
padding technique is utilized on the SOF, adjudication field, control area, and also CRC
sequence frame sectors. After finding 5 consecutive little bits of the very same worth, the
transmitter inserts a complementary bit right into the message stream. When getting a
message, the stuff little bits are drawn out and the message is broken down into structures.
3.4.3.3 Cyclic Redundancy Check

The CRC code to be sent in the Information Framework and to check the CRC code
of inbound messages are created in one area of the BSP. As defined fig 3.5 illustrates how
the CRC sequence may be generated using HDL with a corresponding 15bit CRC REG
(14:0) shift register using the pseudo code implementation. The generated CRC series are
retained in the 15-bit register in accordance with the completeness of the data frame[8].

Fig 3.5 CRC 15-bit shift register algorithm flowchart

3.4.3.4 Message Filtering

The theory of message broadcasting governs data transmission in a CAN
network. All messages sent over the bus can be read by all nodes and are received
by the controller. Each node, on the other hand, is only interested in the messages
that are sent to it. As a result, each CAN node's protocol controller implements a
message filtering mechanism to ensure that the host microcontroller only receives
messages that are important to it.

Building an accepting filter with an eight-bit acceptance mask is a simple

procedure. The acceptance mask register holds the 8 most substantial data-bits of
the message identifier ID, that should be present for a message to pass through the
filter. The acceptance mask's bits can be adjusted to 0 or 1 or unknown (X). If the
mask bit is adjusted to 0, the mask will only permit identifier bits having a value
of 0 to travel through, and also if the value of mask is adjusted to 1,only bits
having value of 1 will be allowed by the mask.

Figure 3.6 — Basic principle of message filtering.

If the mask is ready, either 1 or 0 may penetrate following the bit value. A mask to
allow values 0-15 will be displayed in Figure 3.6. To do this, all mask bits are set to zero,
except for ID 3, which is configured to be unbinding. A two-register acceptance filter is
implemented by the Controller Area Network. There is an identification for both registers,
approval code and approval mask. The registry of approvals includes the littles the
message identification a message must have. The approval mask register then decides
which of the little bits are important to filter. That's why the range of filtered messages
with identifier values between 0 and 7 is ready for both registers. If you are fully willing to
join up, all messages with ID starting from 0 to 2048 are received afterwards.
The messages can then be transmitted to the host microcontroller when they have been
filtered into the system. Ultimately, the host microcontroller will translate and do the
associated messaging.

3.4.4 Message Buffer

The sending and also receiving buffer together form the message buffer. The
sending buffer is an interface between the host and the BSP which allows a whole message
to be saved, which will be sent via the network without any problems. The host
microcontroller will write the frame information to the barrier to load the barrier and
afterwards the BSP will validate the information and send input.

Table 3.2 — Transmit and receive buffer layout of the CAN controller
 On the other hand the buffer stores receive messages that filter the message. The
buffer is a FIFO which initially only permits a single message to be processed by the host
microcontroller. Once a FIFO message is read, it will be published and the message will also
be sent. In the article standard for the Philips SJA1000 stand alone controller the design of
reception and transmission obstacles are detailed. Table 3.2 gives the provision for
addressing and designing these impediments.

3.4.5 Error Management Logic

As it processes the information stream, the BSP is frequently looking for errors.
When the BSP detects a violation in any of the devices, it generates an error and also
informs the error management reasoning (EML). In feedback, depending upon the
circumstance, the EML increments either a get error counter (REC) or a transfer error
counter (TEC). Whether or not the mistake took place throughout transmission or
reception is unknown. The worth of the error counter figure out whether the controller
remains in an error-active, error-passive, or bus-off setting, according to the CAN
method. The numerous error states specifies allow error arrest, which makes sure that a
defective node does not obstruct communications by itself.

Error confinement, which makes certain that a defective node does not block
communications along the bus, is feasible thanks to the different error states. When errors
are observed, a node in the error-active state joins regular communications while
additionally sending out an active error flag. An error-passive node with a high error
matter can still take part in communications, but it can just send easy error flags if there
are any more mistakes located. The bus interactions are not disrupted by the passive error
flag. Lastly, a node in the bus-off state is not allowed to connect with various other nodes
on the bus. A CAN node's error state layout is displayed in Figure 3.7.
 Figure 3.7 — Error state diagram of a CAN node.

If reset, a Controller Area node is quickly placed in an error-active state. As soon

as either one of the error counters surpasses 127, the node then gets in the error-passive
state.

If both counters are listed below 128, a node might revert to the error-active state. When the
counter surpasses 255 the number of transfer errors is split from bus[8]. A node can be
returned to the error-action state from this state only when the counters are reset to certainly
no when 128 sequences of 11 consecutive littles of a recessive value have really been
discovered.

The number of errors is increased by decreasing with the adherence to the policy collection
indicated in the CAN procedure:

1. When a receiver spots an error, the REC is enhanced by one, except when the
spotted mistake is a bit error throughout the transmission of an active-error flag or an
overload flag.

2. When a receiver discovers a dominant bit as the first bit after sending an error
flag, the REC is incremented by 8.

3. When a transmitter sends out an error flag the TEC is enhanced by 8.

i.If the transmitter is error passive and detects an acknowledgement error, but does
not find a leading little bit while sending its passive error flag, the TEC is not
incremented.

ii.If the transmitter transmits an error flag as a result of a stuff error during
adjudication, when right stuff little bit must have been recessive and was transmitted
as recessive, but is checked as leading the TEC remains unchanged.

4. If a transmitter finds a bit mistake while sending an active-error flag or an

overload flag, the TEC is boosted by 8.

5. If a receiver discovers a little bit mistake while sending out an active-error flag or
an overload flag, the REC is boosted by eight.

6. Any kind of node endures as much as seven successive leading bits after sending
an active-error, passive-error, or an overload flag. After discovering the fourteenth
 consecutive leading bit complying with an active-error flag or the eighth complying
with a passive-error flag, and also after each additional sequence of 8 consecutive
leading little bits, every transmitter boosts its TEC by eight. Simultaneously, every
receiver. enhances its REC by 8.

7. After the effective transmission of a framework, the TEC is decremented if it

currently has a non-zero worth.

8. After the successful reception of a frame, the REC is decremented if it is between

1 as well as 127. If the matter is absolutely no, it remains unchanged; if it was higher
than 127, it is set to a value in between 119 and also 127. The policies for mistake
confinement state that the TEC of a node is increased by 8 when a node spots a
mistake throughout transmission and is only decreased by one for a successful
transmission. As a result, a Controller Area network continues to be operational
when less than every 16 frames is flawed.

3.5 Design of custom RAM

The custom RAM used in this project is a two port 64x8 RAM which has separate
read and write clocks along with read and write signals.Since it is a 64x8 RAM this can
store 64 words of size 8 bits.Vector array named memory is used to store all these
words.The RAM has 8 bit data input and 8 bit data output signals.Since it has 64 different
locations 6 bit address lines are required to access the data from the RAM or to write data to
the RAM.On the positive edges of the respective clocks(read clock ,write clock) the
corresponding operations will be performed if the read signal / write signal is enabled.This
custom RAM is integrated to FIFO as well as BSP modules.

3.6 Testing and integration of submodules

Individual submodules are tested separately by forcing inputs through testbenches.A

wide range of values have been given and the respective outputs of each block are verified
with the theoretical values. Upon successful verification all the submodules are integrated
together in the top-level module. The corresponding inputs and outputs of each submodule
are matched and connected in this top level module and the final design of CAN module is
obtained. Along with the integration some of the necessary functions like generating
acknowledgement signal are performed in this top-level module.

3.7 Conclusion
 Chapter 3 has actually provided an overall technique for specifying
requirements essential to define the CAN protocol in an equipment description language.
Likewise, a particular strategy for designing as well as carrying out the CAN protocol. The
following phase offers the collection of outcomes i.e, the synthesis as well as the simulation
gotten by applying the techniques proposed in this thesis.

CHAPTER 4. RESULTS AND DISCUSSIONS

4.1 Introduction
The project deals with designing Can module with a custom RAM by integrating the
sub modules of CAN which are designed in Verilog HDL. So, the outputs are considered and
simulated such that required operations of each sub-module are verified. To obtain the
synthesis and simulation reports of the project a simulating tool name XILINX ISE SUITE
14.7 is used. Once all the required building blocks are designed and verified, these blocks are
integrated to design the CAN module.

4.2 Synthesis
Synthesis is a process of transforming HDL to a gate level netlist as well as the code
is enhanced for the target gadget. The first step of synthesis is to compile the HDL resource
code as well as check it for possible syntax errors. If syntax mistakes do occur they are dealt
with as well as the code is recompiled. Although it might look like a direct step there are
some constructs that are not conveniently approved by the synthesis device, Xilinx ISE
Layout Suite 14.7.
Some of the usual restrictions that took place when assembling the code were: initialization
of signals as well as variables, restricted used of delay statement, as well as designating hold-
ups. After a successful phrase structure examine the netlist is after that produced. The netlist
is then verified for the necessary input and output signals. The connections inside the netlist
show the flow of data and connections between the modules. This synthesized module is then
tested in the next stage using test bench by varying the input values and simulations are
verified to ensure the proper functioning of the design.

4.2.1 Synthesis of Registers

 Register is one of the most basic elements in the CAN module. Registers represent
data storage elements. Registers retain value until another value is placed onto them. The
term registers in Verilog with hardware registers built from edge-triggered flipflops in real
circuits. To hold 8-bit values vectors are used both on the input as well as the output
side.Non- blocking procedural assignment of values is done in registers.

The schematic in the fig 4.1 represents an 8-bit register.

Fig 4.1 Schematic of 8-bit register

The register is analogous to the general register as it takes 8-bit data input signal, write
enable signal and a clock signal. On the positive edge of the clock. If the write enable signal
is high; then the input data is written on to the register and presented as 8-bit data output
signal.

4.2.2 Synthesis of Inverse Bit Order module

IBO module is an integral part of the bit stream processor which performs the bit
stuffing and de-stuffing of bits while transmission and reception. IBO module switches the
order of the bits that is MSB to LSB and vice-versa.

Fig 4.2

Schematic of IBO module

The schematic depicts an 8bit IBO module, which takes 8-bit input signal and
inverts the bit order of the input and generates the inverted 8-bit output signal. The
simulations will be discussed later in this chapter.

4.2.3 Synthesis of First in First Out module (FIFO)

FIFO is an acronym for First In First Out, this describes how data is managed
relative to time or priority. In this case, the data that arrives first will also be the data to leave
first from a group of data. A FIFO Buffer is a read/write memory which automatically keep
track of the order in which data enters into the buffer and reads out the data in the same
order.
 Fig 4.3 Schematic of FIFO

This FIFO Buffer can store sixty-four 8bit values. This FIFO Buffer consists of a 8-
bit data input line, data input signal and a 8-bit data output line signal, data output signal. The
module is clocked using the 1-bit input clock line Clk. The module also has and a 1-bit active
high reset line, Rst.
 It has 1bit write signal and a custom RAM interfaced to it. The overrun signal gets
enabled when the FIFO is full and extra bits have to be accommodated in overrun FIFO.

4.2.4 Synthesis of Bit Timing Logic (BTL)

The initial block that a bus message comes across is the bit timing logic(BTL). This

block consistently monitors the bus line input and manages the related bit timing in

accordance to the Controller Area Network conventions. If the Bit Timing Logic discovers a

change from receding to dominant, it integrates on that edge.. Bit timing configuration is

programmed in registers.

Fig 4.4 Schematic of BTL

The above BTL schematic is pescribed with both transmitter and receiver
signal inputs. Depending upon the enabling and disabling of the signals it provides
synchronization of the signals and samples the bits accordingly. The Bit Timing Logic
monitors the serial CAN-bus line. It also provides programmable time segments and phase
shifts. It provides readjustment to the bit stream on the Can bus.

4.2.5 Synthesis of Cyclic Redundancy Check Module

Cyclic Redundancy module is 15bit module. It is an error detecting code commonly

used to detect accidental changes to raw data. It is based on the remainder of polynomial
division on contents. Which is implemented through repetitive xor operations in the Verilog
HDL code.

Fig 4.5 Schematic of CRC

The initialize signal when set to high resets the output crc[14:0]. The enable signal
should be high and the data signal should send bits in a stream line manner to generate the
corresponding crc for the transmitted or the received signal to check the error presence in the
signal.
4.2.6 Synthesis of Acceptance Check Filter Module

The Acceptance Check Filter consists of mask registers and filter registers. The CAN
Acceptance Mask set of registers are used to indicate which of the bits in the received CAN
frame ID will be used by the CAN filter set of registers. The CAN filter set of registers
compare the received CAN ID bits with the corresponding bits in the CAN filter register set.
 Fig 4.6 Schematic of ACF module

These two sets of registers that handle the selective receive of a CAN message by
the CAN engine. If there is a match between the filter and CAN ID – then the CAN frame is
then accepted by the ACF and transferred into the CAN Rx buffer. If there is no match, then
the corresponding frame is dropped.

4.2.7 Synthesis of Bit Stream Processor Module

The bit stream processor (BSP) performs several protocol tasks. The BSP translates
frames into messages and vice-versa. Messages are stuffed and destuffed within the BSP and
undergo CRC checking for error detection while in the BSP module. The buffer which is of
its memory, written to by the CPU and read out by the BSP.
 Fig 4.7 Schematic representation of BSP module.

This dissertation represents the schematic diagram of Bit Stream Processor module.

Bit Stream Processor (BSP) that is able to store a complete message for transmission over

the CAN module.

4.2.8 Synthesis of CAN module

Nodes in CAN communicate when there are no nodes communicating on the bus.

CAN is a message-based network not a address based protocol. Message priority system,

which is based on an 11-bit packet identifier in a CAN module. CAN architecture can be
many masters, as it involves peer-to-peer communications or multicast transmissions

simultaneously.

Fig 4.8 Schematic representation of CAN module

CAN Controller features a programmable bit rate to support applications that require
a high-speed (up to 1 Mbit/s) or a low-speed CAN interface. CAN module is equipped with
all sub blocks by integrating to it. Each and every sub block play a key role in the glib
transmission of the data. The simulated CAN controller is synthesized with custom RAM
memory.

4.3 Simulation

The Controller Area Network core is simulated following the synthesis . A testbench is used

to design the arrangement of the CAN controller. A testbench is a hierarchic high level

design that instantiates an appropriate model, the system under test, and various other

variables. This model is driven by a collection of test vectors, and also the design's
feedbacks are created. The testbench developed a Controller Area Network core and then

built a CAN message with one information byte for the objectives of this thesis. The

messages were after that sent out, and also the CAN controller obtained them, which were

after that positioned in the obtain line. FIFO has actually been disputed.

The following preliminary recommendations were gotten making use of the ISE design

Suite 14.7 environment. A Controller Area Network node sends a message in its

configuration with the receiver line linked to the transmitter line to enable self-reception of

the transmitted message. This simulation will gauge the feature of the CAN node.

4.3.1 Simulation of Registers

A register is implemented implicitly with a register interference. During logic

synthesis, the compiler automatically inserts an instance of register and connects it as
specified in the procedural program code. We can also implement register explicitly with
module instantiations.

Fig 4.9 Simulation of Register module

The waveform of CAN register module is shown in Fig.4.9 and the corresponding
console was obtained. From the simulation result, we can see the output of Register module
for given 8-bit inputs. Hence, the obtained output matches expected output. Register data are
used as variables in procedural blocks. They store logic values only. Here it is disguised as
the given input data and the obtained output data are same. For every 5 seconds the input
signals data has been changed and the corresponding output data signals have been achieved
accordingly. The register elements cannot be connected to the output port of a module
instantiation.

4.3.2 Simulation of Inverse Bit Order (IBO) module

Inverse Bit Order has been obtained for the given input data bit order. Thus, the bit

inversion using Inverse Bit Order module inverses the input bit order which leads to a

inverted bit order for the given input data.

Fig 4.10 Simulation of Inverse Bit Order (IBO) module

The waveforms of the Inverse Bit order module is shown in Fig. 4.10 and the

corresponding console has been verified. From the simulation result, we can see that the

output of the Inverse Bit order module for the given input 01010000 and obtained

corresponding output is 00001010.

4.3.3 Simulation of FIFO module

This cites to a FIFO layout where information values are remitted to a FIFO buffer from one

clock domain name and also the information values are read from the same FIFO buffer

from one more clock domain, where both clock domain names are asynchronous to the

other.
 Fig 4.11 Simulation of FIFO module.

The waveforms of the Simulation of FIFO module is shown in Fig. 4.11 and the
corresponding console has been verified. From the simulation result, we can see that the
output of the Simulation of FIFO module for the given input 00001010 and obtained
corresponding output is 00001010.

4.3.4 Simulation of Bit Timing Logic (BTL)

Fig 4.12 Simulation of Bit Timing Logic (BTL)

The waveforms of the Simulation of Bit Timing Logic (BTL) module is

shown in Fig. 4.12 and the corresponding console has been verified. From the simulation
result, we can see that the output of the Simulation of Bit Timing Logic (BTL) module for

the given input rst = 1 rx = 0 tx = 1 baud_rate_prescale = 56 sync_jump_width = 1

time_segment_1 = 3 time_segment_2 = 1 triple_sampling = 1 rx_idle = 0 rx_inter = 0

transmitting = 1 transmitter = 1 go_rx_inter = 0 tx_next = 1 go_overload_frame = 0

go_error_frame = 0 go_tx = 1 send_ack = 1 node_error_passive =0 and the obtained

corresponding outputs are sampled_point=0 sample_bit=1 sample_bit_q=1 tx_point=0 .

4.3.5 Simulation of Cyclic Redundancy Check Module

The test bench has been designed with data input that presents a stream of data which varies
with time pulse. Whenever the CRC has to be reset the initialize signal is made high. The
stream of data in test bench is passed by keeping the enabling signal high.

Fig 4.13 Simulation of Cyclic Redundancy Check module

The waveforms of the Simulation of Cyclic Redundancy Check module is shown in

Fig. 4.13 and the corresponding console has been verified. From the simulation result, we
can see that the output of the Simulation of Cyclic Redundancy Check module for the given
input stream of data the CRC module has performed the necessary mathematical
calculations and generated the corresponding CRC for the message signal.

4.3.6 Simulation of Acceptance Check Filter module

Fig 4.14 Simulation of Acceptance Check Filter module

The waveforms of the Simulation of of Acceptance Check Filter module is shown in

Fig. 4.14 and the corresponding console has been verified. From the simulation result, we
can see that the output of the Simulation of of Acceptance Check Filter module for the given
input20clk=0 rst =0 id = 6974 reset_mode = 0 acceptance_filter_mode = 0 extended_mode
=0acceptance_code_0=39,acceptance_code_1=69,acceptance_code_2=57,acceptance_code_
3=63, acceptance_mask0=42,acceptance_mask1=15 acceptance_mask2 = 29
acceptance_mask3 = 28 go_rx_crc_lim = 0 go_rx_inter = 0 go_error_frame = 0 data0 = 89
data1 = 52 rtr1 = 0 rtr2 = 0 ide = 0 no_byte0 = 0 no_byte1 = 0 and the obtained
corresponding output id_ok=1.
4.4 Conclusion

In this chapter the different modules needed for the designing of CAN module have
been designed, simulated and verified. They are designed and simulated using Xilinx ISE
Design Suite 14.7. The Console is generated in this Suite. In the coming chapter, we shall
see the conclusions and future scope of the project.
 CHAPTER 5. CONCLUSIONS AND FUTURE SCOPE

5.1 Conclusions
Addition of custom RAM to the design made the CAN module more invincible, as it
can be implemented on any FPGA or microcontroller without the need of any explicit RAM.
The proposed architecture of the design has been studied from various sources. This design
implementation works in count of three steps. In the first step the can module has been
disintegrated into functioning sub blocks: Bit Stream Processor, Bit Timing Logic, Cyclic
Redundancy Check module, Acceptance Check Filter, First In First Out module, Inverse Bit
Order and registers. In the second step a custom RAM of size 64x8 is designed with separate
signals for read and write using Verilog HDL which is integrated in FIFO and BSP. In the final
step of the design all the Verilog implementations of the sub-blocks are first synthesized and
simulated and then integrated together in the top-level module that forms the CAN module.
The significant reduction in the proposed architecture offers a great advantage in the reduction
of area and therefore the complexity. Thus, the proposed design of CAN is more-handy in
virtual simulations. The potential applications of this CAN equipped with custom RAM fall
mainly in areas where there is strict requirement on accuracy and low space consumption. The
Verilog implementation of CAN module helps in implementing CAN through FPGAs thereby
reducing the cost of an extra IC and the chance of failure of the system due to the IC.The
approach and outcomes shown in this report gives a reliable way for the design of CAN and
integrating custom RAM to it.

5.2 Future scope

Future scope of the work includes improving the transmission speed and security of
CAN design by using enhanced methods and interfacing with indigenous processors like
Shakti, which rely on RISC-V architecture can be a competitive model for other processors.