A Dual-Polarized Dual-Beam 28 GHZ Beamformer Chip Demonstrating A 24 Gbps 64-Qam 2X2 Mimo Link
A Dual-Polarized Dual-Beam 28 GHZ Beamformer Chip Demonstrating A 24 Gbps 64-Qam 2X2 Mimo Link
A Dual-Polarized Dual-Beam 28 GHZ Beamformer Chip Demonstrating A 24 Gbps 64-Qam 2X2 Mimo Link
Wilkinson network into two common ports for the vertical (V) V2 V4
and horizontal (H) polarizations. Each channel contains 6-bit ∑
978-1-5386-4545-1/18/$31.00 © 2018 IEEE 64 2018 IEEE Radio Frequency Integrated Circuits Symposium
OUT+ OUT-
2:1 4-bit
IN+ C-DAC
VDD1 = 1.2 V 3-bit 3-bit 260 pH
C-DAC
C-DAC
VDD2 = 2.2 V
IN- C-DAC
4-bit
9 dB attenuator 14 mA
switch
Gain Sim.
16 8 TX OP1dB
chosen to result in a low off-state capacitance. The LNA
is designed to have an IP1dB of −15 dBm and an NF of 8 2 RX IP1dB
10 1 VGA cont.
biased in class-AB with some gain peaking for improved 4
LNA cont.
Attn. on 0
Attn. on
65
10 10
V-Pol. H-Pol.
Pout (dBm)
V-Pol.
180 22
Fig. 5. Top and bottom views of the 2x2 dual-polarized Ideal IP1dB = 1 dBm
dual-beam array PCB with flipped die. Chip photograph is also 120
66
Keysight 6
E8267D V-Pol.
Keysight 5 H-Pol.
LO = 25 GHz DSO-S804A
RF = 29 GHz
EVM (%)
1m 4
Path loss 800 Mbaud
~62 dB 3 64-QAM
Keysight
M8195A AWG 2x2 Dual-Beam 2x2 Dual-Beam IF = 4 GHz 2
TRX Array TRX Array 100 Mbaud 64-QAM
(a) 1
8 10 12 14 16 18 20 22
EIRP (dBm)
TX Array (a)
DSO RX Array
12
V-Pol. 1 m Link
10 H-Pol.
EVM (%)
AWG 8
16-QAM
6.6 dB Backoff
(b) 6
4 64-QAM
H-Pol.
8 dB Backoff
2
0 2 4 6 8 10 12
Data Rate (Gbps)
EVM = 5.0% 2 Gbaud
(b)
67
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