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    Cse (B)

    Uploaded by

    Sankhadeep Chakrabarti
    This document contains VHDL code to design and simulate a half subtractor and full subtractor using structural modeling. For the half subtractor, the design entity defines ports for two 1-bit inputs and two 1-bit outputs for the difference and borrow. The architecture computes the outputs as the XOR of the inputs for the difference and the AND of the inverted first input and second input for the borrow. The testbench simulates the design by applying different input combinations and checking the outputs. For the full subtractor, the design and testbench follow the same structure but with three 1-bit inputs and outputs for the difference and borrow.

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    © All Rights Reserved
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    Cse (B)

    Uploaded by

    Sankhadeep Chakrabarti
    19 views10 pages
    This document contains VHDL code to design and simulate a half subtractor and full subtractor using structural modeling. For the half subtractor, the design entity defines ports for two 1-bit inputs and two 1-bit outputs for the difference and borrow. The architecture computes the outputs as the XOR of the inputs for the difference and the AND of the inverted first input and second input for the borrow. The testbench simulates the design by applying different input combinations and checking the outputs. For the full subtractor, the design and testbench follow the same structure but with three 1-bit inputs and outputs for the difference and borrow.

    Original Title

    121000119111_CSE(B)

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    This document contains VHDL code to design and simulate a half subtractor and full subtractor using structural modeling. For the half subtractor, the design entity defines ports for two 1-bit inputs and two 1-bit outputs for the difference and borrow. The architecture computes the outputs as the XOR of the inputs for the difference and the AND of the inverted first input and second input for the borrow. The testbench simulates the design by applying different input combinations and checking the outputs. For the full subtractor, the design and testbench follow the same structure but with three 1-bit inputs and outputs for the difference and borrow.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    19 views10 pages

    Cse (B)

    Uploaded by

    Sankhadeep Chakrabarti
    This document contains VHDL code to design and simulate a half subtractor and full subtractor using structural modeling. For the half subtractor, the design entity defines ports for two 1-bit inputs and two 1-bit outputs for the difference and borrow. The architecture computes the outputs as the XOR of the inputs for the difference and the AND of the inverted first input and second input for the borrow. The testbench simulates the design by applying different input combinations and checking the outputs. For the full subtractor, the design and testbench follow the same structure but with three 1-bit inputs and outputs for the difference and borrow.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 10

    Date – 28/07/2021

    Name -sankhadeep Chakrabarti


    UnIversity roll - 12100119111
    University Registration no- 018324.
    Stream-Computer science
    engineerin(B).
    Year – 2019-2023
    Semester – 4th
    Paper name- Computer architecture lab.
    Paper code – pcc-cs492.

    Q 4. A) Write a program to design and simulate Half


    Subtractor.
    VHDL CODE:
    DESIGN:
    -- Code your design here
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity half_sub is
    port( a,b : IN std_logic;
    diff,borrow : OUT std_logic);
    end half_sub;

    architecture dataflow of half_sub is


    begin

    diff <= a xor b;


    borrow <= (not a) and b;

    end dataflow;

    TEST BENCH:
    -- Code your testbench here
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity half_sub_tb is
    end entity;

    architecture tb of half_sub_tb is
    component half_sub is
    port(a,b : IN std_logic;
    diff,borrow : OUT std_logic);
    end component;

    signal a,b,diff,borrow : std_logic;

    begin

    uut: half_sub port map(


    a => a, b => b,
    diff => diff,
    borrow => borrow);

    stim: process
    begin

    a <= '0';
    b <= '0';
    wait for 20 ns;

    a <= '0';
    b <= '1';
    wait for 20 ns;

    a <= '1';
    b <= '0';
    wait for 20 ns;

    a <= '1';
    b <= '1';
    wait for 20 ns;
    wait;

    end process;

    end tb;

    OUTPUT :

    …………………………………………………………………………………………………
    …………………………………………………………………………………………………
    ……………………

    Q 4.B) Write a program to design and simulate Full


    Subtractor using structural type of coding.
    VHDL CODE:
    DESIGN :
    -- Code your design here
    library IEEE;
    use IEEE.std_logic_1164.all;
    entity full_sub is
    port( a,b,c : IN std_logic;
    diff,borrow : OUT std_logic);
    end full_sub;

    architecture dataflow of full_sub is


    begin

    diff <= (a xor b) xor c;


    borrow <=((not a) and (b or c)) or (b and c);

    end dataflow;

    TEST BENCH:
    -- Code your testbench here
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity full_sub_tb is
    end entity;

    architecture tb of full_sub_tb is
    component full_sub is
    port(a,b,c : IN std_logic;
    diff,borrow : OUT std_logic);
    end component;

    signal a,b,c,diff,borrow : std_logic;

    begin

    uut: full_sub port map(


    a => a, b => b,
    c => c,
    diff => diff,
    borrow => borrow);

    stim: process
    begin

    a <= '0';
    b <= '0';
    c <= '0';
    wait for 20 ns;

    a <= '0';
    b <= '0';
    c <= '1';
    wait for 20 ns;

    a <= '0';
    b <= '1';
    c <= '0';
    wait for 20 ns;

    a <= '0';
    b <= '1';
    c <= '1';
    wait for 20 ns;
    wait;

    end process;

    end tb;

    OUTPUT:
    …………………………………………………………
    …………………………………………………………
    …………….

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