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TPS259240, TPS259241
SLVSCU9B – AUGUST 2015 – REVISED SEPTEMBER 2016

TPS25924x 12-V eFuse with Over Voltage Protection and Blocking FET Control
1 Features 3 Description
•
1 VOPERATING = 4.5 V to 13.8 V, VABSMAX = 20 V The TPS25924x family of eFuses is a highly
integrated circuit protection and power management
• Integrated 28-mΩ Pass MOSFET solution in a tiny package. The devices use few
• Fixed 15-V Over Voltage Clamp external components and provide multiple protection
• 1-A to 5-A Adjustable ILIMIT modes. They are a robust defense against overloads,
• ±8% ILIMIT Accuracy at 3.7 A shorts circuits, voltage surges, excessive inrush
current, and reverse current.
• Reverse Current Blocking Support
Current limit level can be set with a single external
• Programmable OUT Slew Rate, UVLO
resistor. Over voltage events are limited by internal
• Built-in Thermal Shutdown clamping circuits to a safe fixed maximum, with no
• UL 2367 Recognized – File No. E339631* external components required.
– *RILIM ≤ 130 kΩ (5 A maximum) Applications with particular voltage ramp
• Safe During Single Point Failure Test (UL60950) requirements can set dV/dT with a single capacitor to
• Small Foot Print – 10L (3 mm x 3 mm) VSON ensure proper output ramp rates. Many systems,
such as SSDs, must not allow holdup capacitance
energy to dump back through the FET body diode
2 Applications onto a drooping or shorted input bus. The BFET pin
• Adapter Powered Devices is for such systems. An external NFET can be
• HDD and SSD Drives connected “Back to Back (B2B)” with the TPS25924x
output and the gate driven by BFET to prevent
• Set Top Boxes current flow from load to source (see Figure 43).
• Servers / AUX Supplies
• Fan Control Device Information(1)
• PCI/PCIe Cards PART NUMBER PACKAGE BODY SIZE (NOM)
TPS259241
VSON (10) 3.00 mm × 3.00 mm
TPS259240
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Application Schematic Transient: Output Short Circuit

VIN VIN OUT OUT

R1 28m:
COUT
EN/UVLO BFET
R2
dV/dT ILIM
RLIM
CdVdT GND TPS25924x

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS259240, TPS259241
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Table of Contents
1 Features .................................................................. 1 9 Application and Implementation ........................ 17
2 Applications ........................................................... 1 9.1 Application Information............................................ 17
3 Description ............................................................. 1 9.2 Typical Applications ............................................... 17
4 Revision History..................................................... 2 10 Power Supply Recommendations ..................... 23
5 Device Comparison Table..................................... 3 10.1 Transient Protection .............................................. 23
10.2 Output Short-Circuit Measurements ..................... 24
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4 11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
7.1 Absolute Maximum Ratings ..................................... 4
11.2 Layout Example .................................................... 25
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions...................... 4 12 Device and Documentation Support ................. 26
7.4 Thermal Information .................................................. 5 12.1 Device Support .................................................... 26
7.5 Electrical Characteristics.......................................... 5 12.2 Documentation Support ....................................... 26
7.6 Timing Requirements ............................................... 6 12.3 Related Links ........................................................ 26
7.7 Typical Characteristics .............................................. 7 12.4 Receiving Notification of Documentation Updates 26
12.5 Community Resources.......................................... 26
8 Detailed Description ............................................ 13
12.6 Trademarks ........................................................... 26
8.1 Overview ................................................................. 13
12.7 Electrostatic Discharge Caution ............................ 26
8.2 Functional Block Diagram ....................................... 13
12.8 Glossary ................................................................ 27
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 16 13 Mechanical, Packaging, and Orderable
Information ........................................................... 27

4 Revision History
Changes from Revision A (August 2015) to Revision B Page

• Added section: Controlled Power Down using TPS25924x ................................................................................................. 22

Changes from Original (August 2015) to Revision A Page

• Changed from Product Preview to Production Data .............................................................................................................. 1

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5 Device Comparison Table

PART NUMBER UV OV CLAMP FAULT RESPONSE STATUS

TPS259241 4.3 V 15 V Auto Retry Active
TPS259240 4.3 V 15 V Latched Active

6 Pin Configuration and Functions

DRC Package
10-Pin VSON
Top View

dV/dT 1 10 ILIM
EN/UVLO BFET
GND OUT
VIN
VIN OUT
VIN 5 6 OUT

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
O Connect this pin to the gate of a blocking NFET. See the Feature Description
BFET 9
section. This pin can be left floating if it is not used
dV/dT O Tie a capacitor from this pin to GND to control the ramp rate of OUT at device
1
turnon
This is a dual function control pin. When used as an ENABLE pin and pulled
down, it shuts off the internal pass MOSFET and pulls BFET to GND. When
EN/UVLO 2 I pulled high, it enables the device and BFET.
As an UVLO pin, it can be used to program different UVLO trip point via
external resistor divider
GND Thermal Pad — GND
ILIM 10 O A resistor from this pin to GND sets the overload and short circuit limit
OUT 6-8 O Output of the device
VIN 3-5 I Input supply voltage

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7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
over operating temperature range (unless otherwise noted)
MIN MAX UNIT
VIN –0.3 20
Supply voltage (1) V
VIN (10-ms transient) 22
OUT –0.3 VIN + 0.3 V
Output voltage
OUT (transient < 1 µs) –1.2 V
ILIM –0.3 7
EN/UVLO –0.3 7
Voltage V
dV/dT –0.3 7
BFET –0.3 30
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VIN 4.5 12 13.8
BFET 0 VIN+6
Input voltage V
dV/dT, EN/UVLO 0 6
ILIM 0 3
IOUT Continuous output current 0 5 A
ILIM Resistance 10 100 162 kΩ
OUT 0.1 1 1000 µF
External capacitance
dV/dT 1 1000 nF
TJ Operating junction temperature –40 25 125 °C
TA Operating Ambient temperature –40 25 85 °C

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7.4 Thermal Information

over operating free-air temperature range (unless otherwise noted) (1)
TPS25924x
THERMAL METRIC DRC (VSON) UNIT
10 PINS
RθJA Junction-to-ambient thermal resistance 45.9 °C/W
RθJCtop Junction-to-case (top) thermal resistance 53 °C/W
RθJB Junction-to-board thermal resistance 21.2 °C/W
ψJT Junction-to-top characterization parameter 1.2 °C/W
ψJB Junction-to-board characterization parameter 21.4 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 5.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ +125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN (INPUT SUPPLY)
VUVR UVLO threshold, rising 4.15 4.3 4.45 V
VUVhyst UVLO hysteresis (1) 5%
IQON Enabled: EN/UVLO = 2 V 0.3 0.42 0.55 mA
Supply current
IQOFF EN/UVLO = 0 V 0.13 0.225 mA
VOVC Over-voltage clamp VIN > 16.5 V, IOUT = 10 mA 13.8 15 16.5 V
EN/UVLO (ENABLE/UVLO INPUT)
VENR EN threshold voltage, rising 1.37 1.4 1.44 V
VENF EN threshold voltage, falling 1.32 1.35 1.39 V
IEN EN Input leakage current 0 V ≤ VEN ≤ 5 V –100 0 100 nA
dV/dT (OUTPUT RAMP CONTROL)
IdVdT dV/dT charging current (1) VdVdT = 0 V 220 nA
RdVdT_disch dV/dT discharging resistance EN/UVLO = 0 V, IdVdT = 10 mA sinking 50 73 100 Ω
VdVdTmax dV/dT max capacitor voltage (1) 5.5 V
GAINdVdT dV/dT to OUT gain (1) ΔVdVdT 4.85 V/V
ILIM (CURRENT LIMIT PROGRAMMING)
IILIM ILIM bias current (1) 10 µA
RILIM = 10 kΩ, VVIN-OUT = 1 V 1.02
RILIM = 45.3 kΩ, VVIN-OUT = 1 V 1.79 2.10 2.42
IOL A
RILIM = 100 kΩ, VVIN-OUT = 1 V 3.46 3.75 4.03

Overload current limit (2) RILIM = 150 kΩ, VVIN-OUT = 1 V 4.5 5.1 5.7
RILIM = 0 Ω, shorted resistor current limit (single point failure
IOL-R-Short 0.84 A
test: UL60950) (1)
RILIM = OPEN, open resistor current limit (single point failure
IOL-R-Open 0.73 A
test: UL60950) (1)
RILIM = 10 kΩ, VVIN-OUT = 12 V 1
RILIM = 45.3 kΩ, VVIN-OUT = 12 V 1.66 1.98 2.37
ISCL Short-circuit current limit (2) A
RILIM = 100 kΩ, VVIN-OUT = 12 V 2.90 3.32 3.85
RILIM = 150 kΩ, VVIN-OUT = 12 V 3.7 4.5 5.5
Fast-trip comparator level w.r.t.
RATIOFASTRIP IFASTRIP : IOL 160%
overload current limit (1)
ILIM open resistor detect
VOpenILIM VILIM rising, RILIM = OPEN 3.1 V
threshold (1)

(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
(2) Pulsed testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.

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Electrical Characteristics (continued)

–40°C ≤ TJ ≤ +125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT (PASS FET OUTPUT)
TJ = 25°C 21 28 37
RDS(on) FET ON resistance mΩ
TJ = 125°C 39 48
IOUT-OFF-LKG VEN/UVLO = 0 V, VOUT = 0 V (sourcing) –5 0 1.2
OUT bias current in off state µA
IOUT-OFF-SINK VEN/UVLO = 0 V, VOUT = 300 mV (sinking) 10 15 20
BFET (BLOCKING FET GATE DRIVER)
IBFET BFET charging current (1) VBFET = VOUT 2 µA
VVIN +
VBFETmax BFET clamp voltage (1) V
6.4
BFET discharging resistance to
RBFETdisch VEN/UVLO = 0 V, IBFET = 100 mA 15 26 36 Ω
GND
TSD (THERMAL SHUT DOWN)
TSHDN TSD threshold, rising (1) 150 °C
TSHDNhyst TSD hysteresis (1) 10 °C
TPS259240 Latched
Thermal fault: latched or auto-retry
TPS259241 Auto-retry

7.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN/UVLO → H to IVIN = 100 mA, 1-A resistive load
TON Turnon delay (1) 220 µs
at OUT
(1)
tOFFdly Turnoff delay EN/UVLO↓ to BFET↓, CBFET = 0 0.4 µs
dV/dT (OUTPUT RAMP CONTROL)
EN/UVLO → H to OUT = 11.7 V, CdVdT = 0 0.7 1 1.3
tdVdT Output ramp time ms
EN/UVLO → H to OUT = 11.7 V, CdVdT = 1 nF (1) 12
ILIM (CURRENT LIMIT PROGRAMMING)
tFastOffDly Fast-Trip comparator delay (1) IOUT > IFASTRIP to IOUT= 0 (Switch off) 300 ns
BFET (BLOCKING FET GATE DRIVER)
EN/UVLO → H to VBFET = 12 V, CBFET = 1 nF 4.2
tBFET-ON BFET Turnon duration (1) ms
EN/UVLO → H to VBFET = 12 V, CBFET = 10 nF 42
EN/UVLO → L to VBFET = 1 V, CBFET = 1 nF 0.4
tBFET-OFF BFET Turnoff duration (1) µs
EN/UVLO → L to VBFET = 1 V, CBFET = 10 nF 1.4
THERMAL SHUTDOWN (TSD)
Retry delay after TSD recovery,
tTSDdly TPS259241 only 100 µs
TJ < [TSHDN - 10°C] (1)

(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.

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7.7 Typical Characteristics

TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)

4.35 0.25

4.3
0.2
Input UVLO (Rising, Falling) (V)

4.25

IQ-OFF (mA)
0.15
4.2

4.15
0.1

4.1
0.05 125 ƒC
4.05 85 ƒC
25 ƒC
-40 ƒC
4 0
-50 0 50 100 150 0 5 10 15 20
Temperature (ƒC) C001 VIN (V) C002

Figure 1. Input UVLO vs Temperature Figure 2. IQ-OFF vs VIN

0.6 16
10 mA
100 mA
0.5
500 mA

0.4 15.5
IVIN-ON (mA)

VOVC (V)

0.3

0.2 15

125 °C
0.1 85 °C
25 °C
-40 °C
0 14.5
0 5 10 15 20 -50 0 50 100 150
VIN (V) C003 Temperature (ƒC) C005

Figure 3. IVIN-ON vs VIN Figure 4. VOVC vs Temperature Across IOUT

45 250

40 230
RDSON (m:)

210
TON (Ps)

35

30 190

25 170

20 150
-50 0 50 100 150 -50 0 50 100 150

Temperature (oC) Temperature (oC)

Figure 5. RDSON vs Temperature Figure 6. TON vs Temperature

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Typical Characteristics (continued)

TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
230 150

225

100

TdVdT (ms)
220
IdVdT (nA)

215
50

210 125 ƒC
85 ƒC
25 ƒC
-40 ƒC
205 0
-50 0 50 100 150 0 2 4 6 8 10
Temperature (ƒC) C010 CdVdT (nF) C013

Figure 7. IdVdT vs Temperature Figure 8. TdVdT vs CdVdT

1.41 100

1.4
VEN-VIH VEN-VIL (V)

1.39
10
Rising
1.38
IEN (nA)

Falling 125qC
85qC
1.37
25qC
1 -40qC
1.36

1.35

1.34 0.1
-50 0 50 100 150 0 1 2 3 4 5
o
Temperature ( C) VEN (V) D016

Figure 9. VEN-VIH, VEN-VIL vs Temperature Figure 10. IEN (Leakage Current) vs VEN
0.95 0.8

0.9
0.75
IOL-R-SHORT (A)

IOL-R-OPEN (A)

0.85

0.7
0.8

0.75 0.65
-50 0 50 100 150 -50 0 50 100 150
Temperature (oC) D001
Temperature (oC) D001
RILIM = 0 Ω RILIM = OPEN

Figure 11. IOL-R-Short vs Temperature Figure 12. IOL-R-Open vs Temperature

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Typical Characteristics (continued)

TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
4 2.2

3.5 2

3 1.8
IVOUT (A)

IVOUT (A)
2.5 1.6

2 1.4
125qC 125qC
85qC 85qC
1.5 25qC 1.2 25qC
-40qC -40qC

1 1
0 0.5 1 1.5 2 0 0.5 1 1.5 2
VVIN-OUT (V) D028
VVIN-OUT (V) D029
RILIM = 100 kΩ RILIM = 45.3 kΩ

Figure 13. IVOUT vs VVIN-OUT Figure 14. IVOUT vs VVIN-OUT

6 2

0
5
IOL, ISC (% Normalized)

-2

-4
4
IVOUT (A)

-6

-8 IOL-150k
3 ISC-150k
-10
125qC
85qC -12
2
25qC
-14
-40qC

1 -16
0 0.5 1 1.5 2 -50 0 50 100 150
VVIN-OUT (V) D027 Temperature (oC)
RILIM = 150 kΩ RILIM = 150 kΩ

Figure 15. IVOUT vs VVIN-OUT Figure 16. IOL, ISC vs Temperature

2 1

0 0
IOL, ISC (% Normalized)

IOL, ISC (% Normalized)

-2 -1

-4 -2 IOL-45.3k
ISC-45.3k
-6 IOL-100k -3
ISC-100k
-8 -4

-10 -5

-12 -6
-50 0 50 100 150 -50 0 50 100 150
Temperature (oC) Temperature (oC)
RILIM = 100 kΩ RILIM = 45.3 kΩ

Figure 17. IOL, ISC vs Temperature Figure 18. IOL, ISC vs Temperature

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Typical Characteristics (continued)

TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)

Accuracy (Process, Voltage, Temperature) (%)

3.1 35
ILIM Open Detect Threshold (V)

30
3.09
25
3.08
20

3.07 15

10
3.06
5

3.05
0
-50 0 50 100 150
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Temperature (oC) Overload Current Limit (A) D001

Figure 19. VOpenILIM vs Temperature Figure 20. Accuracy vs Overload Current Limit
4 10000

3.5
Thermal Shutdown Time (ms)

1000
Overload Current Limit (A)

2.5
100
2

1.5 10

1 TA = -40oC
1 TA = 25oC
0.5 TA = 85oC
TA = 125oC
0 0.1
0 20 40 60 80 100 120 0.1 1 10 100
RILIM Resistor (k:) D001
Power Dissipation (W) D001

Figure 21. Overload Current Limit vs RILIM Resistor Figure 22. Thermal Shutdown Time vs Power Dissipation

VIN EN
C1
C2 VIN

VOUT

C2
C2

VOUT
C2
C2 C3

C3
I_IN
C4

CdVdT = OPEN, COUT = 4.7 µF

Figure 23. Transient: Over-Voltage Clamp Figure 24. Transient: Output Ramp

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Typical Characteristics (continued)

TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
EN

VIN EN
C1 C1
C2

VOUT

VOUT
C2

C3 C3
I_OUT

I-IN

C4 C4

CdVdT = 1nF, COUT = 10 µF, ROUT = 5.7Ω EN ↓

Figure 25. Transient: Output Ramp Figure 26. Transient: Turnoff Delay
EN VIN

C1
C2

VOUT VOUT

C1
C2
BFET
BFET

C3 C3

C2
C2

EN ↓ VIN↓

Figure 27. Turnoff Delay to BFET Figure 28. Turnoff Delay to BFET
EN EN

C1
C2 VIN C1
C2 VIN

VOUT

C2 C2
VOUT
C3 C3

I_IN I_IN
C4 C4

TPS259241 TPS259241

Figure 29. Transient: Recovery From Short Circuit / Over Figure 30. Transient: Wake Up to Short Circuit
Current

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Typical Characteristics (continued)

TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
EN

C1
C2 VIN

VOUT

C2
C3
I_IN

C4

ILOAD Stepped From 50% to 120%, back to 50% RILIM = 150 kΩ

Figure 31. Transient: Overload Current Limit Figure 32. Transient: Output Short Circuit

RILIM = 150 kΩ TPS259241

Figure 33. Short Circuit (Zoom): Fast-Trip Comparator Figure 34. Transient: Thermal Fault Auto-Retry

TPS259240

Figure 35. Transient: Thermal Fault Latched

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8 Detailed Description

8.1 Overview
The TPS25924x is an e-fuse with integrated power switch that is used to manage current, voltage and start-up
voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds
the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables
the internal MOSFET. As VIN rises, the internal MOSFET of the device starts conducting and allow current to
flow from VIN to OUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off. User also has
the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.
After a successful start-up sequence, the device now actively monitors its load current and input voltage,
ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safely
clamped to VOVC level at the output. This keeps the output device safe from harmful voltage and current
transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds TSHDN,
typically 150°C, the thermal shutdown circuitry shuts down the internal MOSFET thereby disconnecting the load
from the supply. In TPS259240, the output remains disconnected (MOSFET open) until power to device is
recycled or EN/UVLO is toggled (pulled low and then high). The TPS259241 device remains off during a cooling
period until device temperature falls below TSHDN – 10°C, after which it attempts to restart. This ON and OFF
cycle continues until fault is cleared.

8.2 Functional Block Diagram

VIN OUT
3, 6,
4, 7,
5 8
Current 28mW
+ UVLO Sense
4.3V
4.08V Charge
EN/ Pump 2mA
UVLO 2 +
EN BFET
1.4V
Over 9
1.35V Voltage
SWEN
SWEN GATE
22W
Thermal CONTROL
6V Shutdown TSD
VIN 6V
220nA 10mA
+
dV/dT ILIMIT
ILIM
1 4.8x 10
+
70pF +
GND SWEN Fast Trip
EP 80W
Comp
1.6*ILIMIT

8.3 Feature Description

8.3.1 GND
This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless
otherwise specified.

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Feature Description (continued)

8.3.2 VIN
Input voltage to the TPS25924x. A ceramic bypass capacitor close to the device from VIN to GND is
recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V to 13.8 V for
TPS25924x. The device can continuously sustain a voltage of 20 V on VIN pin. However, above the
recommended maximum bus voltage, the device will be in over-voltage protection (OVP) mode, limiting the
output voltage to VOVC. The power dissipation in OVP mode is PD_OVP = (VVIN – VOVC) x IOUT, which can
potentially heat up the device and cause thermal shutdown.

8.3.3 dV/dT
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate (minimum TdVdT) on the output. Equation governing slew rate
at start-up is shown in Equation 1:
dVOUT IdVdT ´ GAINdVdT
  =      
dt CdVdT + CINT
where
• IdVdT = 220 nA (Typical)
• CINT = 70 pF (Typical)
• GAINdVdT = 4.85
dVOUT
= Desired output slew rate
dT (1)
The total ramp time (TdVdT) for 0 to VIN can be calculated using Equation 2:
TdVdT   =  106 ´ VIN ´ (CdVdT   +   70  pF ) (2)
For details on how to select an appropriate charging time/rate, refer to the applications section Setting Output
Voltage Ramp Time (TdVdT).

8.3.4 BFET
Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the
event of power failure at VIN. The BFET pin is controlled by either input UVLO (VUVR) event or EN/UVLO (see
Table 1). BFET can source charging current of 2 µA (TYP) and sink (discharge) current from the gate of the
external FET via a 26-Ω internal discharge resistor to initiate fast turnoff, typically <1 µs. Due to 2 µA charging
current, it is recommended to use >10 MΩ impedance when probing the BFET node.

Table 1. BFET
EN/UVLO > VENR VIN>VUVR BFET MODE
H H Charge
X L Discharge
L X Discharge

8.3.5 EN/UVLO
As an input pin, it controls both the ON and OFF state of the internal MOSFET and that of the external blocking
FET. In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low
on this pin turns off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge
resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also
used to clear a thermal shutdown latch in the TPS259240 by toggling this pin (H→L).
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 us typical) for quick detection of
power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on
EN/UVLO helps in quick turnoff of the BFET driver, thereby stopping the flow of reverse current (see typical
application diagram, Figure 43). For applications where a higher de-glitch delay on EN/UVLO is desired, or when
the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND.

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8.3.6 ILIM
The device continuously monitors the load current and keeps it limited to the value programmed by RILIM. After
start-up event and during normal operation, current limit is set to IOL (over-load current limit) as shown in
Equation 3.

(
IOL = 0.7 + 3 ´ 10-5 ´ RILIM ) (3)
When power dissipation in the internal MOSFET [PD = (VVIN – VOUT) × IOUT] exceeds 10 W, there is a 2% – 12%
thermal foldback in the current limit value so that IOL drops to ISC. In each of the two modes, MOSFET gate
voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts
down due to over temperature. See Figure 36.
0

-2
Foldback (ISC - IOL)/IOL (%)

-4

-6

-8

-10

-12

-14
0 10 20 30 40 50 60
Power (W)

Figure 36. Thermal Foldback in Current Limit

During a transient short circuit event, the current through the device increases very rapidly. The current-limit
amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS25924x
incorporates a fast-trip comparator, which shuts down the pass device very quickly when IOUT > IFASTRIP, and
terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed over-
load current limit (IFASTRIP = 1.6 x IOL). After the transient short-circuit peak current has been terminated by the
fast-trip comparator, the current limit amplifier smoothly regulates the output current to IOL (see Figure 37 and
Figure 38).

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Figure 37. Fast-Trip Current Figure 38. Fast-Trip and Current Limit Amplifier Response
for Short Circuit

8.4 Device Functional Modes

The TPS25924x is a hot-swap controller with integrated power switch that is used to manage
current/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN
bus. When VVIN exceeds the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high
level on this pin enables the internal MOSFET and also start charging the gate of external blocking FET (if
connected) via the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected)
starts conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (that is, below VENF),
the internal MOSFET is turned off and BFET pin is discharged, thereby, blocking the flow of current from VIN to
OUT. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT
pin and GND.
Having successfully completed its start-up sequence, the device now actively monitors its load current and input
voltage, ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safely
clamped to VOVC level at the output. This keeps the output device safe from harmful voltage and current
transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds TSHDN,
typically 150°C, the thermal shutdown circuitry shuts down the internal MOSFET thereby disconnecting the load
from the supply. In the TPS259240, the output remains disconnected (MOSFET open) until power to device is
recycled or EN/UVLO is toggled (pulled low and then high). The TPS259241 device remains off during a cooling
period until device temperature falls below TSHDN – 10°C, after which it attempts to restart. This ON and OFF
cycle continues until fault is cleared.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS25924x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in
controlling the in-rush current and provides precise current limiting during overload conditions for systems such
as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust
protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device. Alternatively, the
WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design.
Additionally, a spreadsheet design tool TPS2592xx Design Calculator (SLUC570) is available on web folder. This
section presents a simplified discussion of the design process.

9.2 Typical Applications

9.2.1 Simple 3.7-A eFuse Protection for Set Top Boxes

VIN = 4.5 to 18 V VOUT, IOUT < 3.4A

IN OUT
*
CVIN
R1 28mO COUT
1MO 0.1µF 1µF
EN/UVLO

**
R2 BFET

dVdT
ILIM
GND
TPS25924x RILIM
**Optional & only needed for external UVLO 100kO
*Optional & only for noise suppression

Figure 39. Typical Application Schematic: Simple 3.7-A e-Fuse for STBs

9.2.1.1 Design Requirements

Table 2 shows the design parameters for this application.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VIN Input voltage 12 V
V(UV) Undervoltage lockout set point Default: VUVR = 4.3 V
V(OV) Overvoltage protection set point Default: VOVC = 15 V
RL(SU) Load at start-up 4Ω
IOL = IILIM Current limit 3.7 A
COUT Load capacitance 1 µF
TA Maximum ambient temperature 85°C

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9.2.1.2 Detailed Design Procedure

The following design procedure can be used to select component values for the TPS25924x.

9.2.1.2.1 Step by Step Design Procedure

This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.

9.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection

The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
I - 0.7
RILIM = ILIM
3 x 10-5 (4)
For IOL= IILIM = 3.7 A, from Equation 4, RILIM = 100 kΩ, choose closest standard value resistor with 1% tolerance.

9.2.1.2.3 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving Equation 5.
R + R2
V(UV) = 1 ´ VENR
R2 (5)

Where VENR = 1.4 V is enable voltage rising threshold.

Since R1 and R2 leak the current from input supply (VIN), these resistors must be selected based on the
acceptable leakage current from input power supply (VIN). The current drawnby R1 and R2 from the power
supply {IR12 = VIN/(R1 + R2)}.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, IR12 must be chosen to be 20x greater than the leakage current
expected.
For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it
cannot be connected directly to VIN= 12 V. It has to be connected through R1 = 1 MΩ only, so that the pull-up
current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, VUVR. This is calculated using Equation 6.
V(PFAIL) = 0.96 x VUVR (6)
Where VUVR is 4.3 V, Power fail threshold set is 4.1 V.

9.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)

For a successful design, the junction temperature of device must be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor CdVdT needed is calculated considering the two possible cases:

9.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across
the internal FET decreases. The average power dissipated in the device during start-up is calculated using
Equation 8.
For TPS25924x, the inrush current is determined as shown in Equation 7:
V(IN)
I(INRUSH) = C(OUT) x
TdVdT (7)

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Power dissipation during start-up is given by Equation 8:

PD(INRUSH) = 0.5 x V(IN) x I(INRUSH) (8)
Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.

9.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
When load draws current during the turnon sequence, there is additional power dissipated. Considering a
resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during
TdVdT time. The average power dissipation in the internal FET during charging time due to resistive load is given
by Equation 9:
æ 1ö V 2(IN)
PD(LOAD) = çç ÷÷÷ x
çè 6 ø R
L(SU) (9)
Total power dissipated in the device during startup is given by Equation 10:
PD(STARTUP) = PD(INRUSH) + PD(LOAD) (10)
Total current during startup is given by Equation 11:
I(STARTUP) = I(INRUSH) + IL (t) (11)
If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by
Equation 12:
é æ öù
ê ç ÷÷÷ú
ê çç I
ç ÷ ú
ê IOL (INRUSH) ÷÷ú
TdVdT(Current-Limited) = COUT x RL(SU) x ê - 1 + LNççç ÷÷ú
êI ç
ç V ÷
(IN) ÷÷ú
ê (INRUSH) çççIOL - R ÷÷ú
ê è L(SU) ÷øú
ë û (12)
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as
shown in Figure 40:
10000
Thermal Shutdown Time (ms)

1000

100

10

TA = -40oC
1 TA = 25oC
TA = 85oC
TA = 125oC
0.1
0.1 1 10 100
Power Dissipation (W) D001

Figure 40. Thermal Shutdown Limit Plot

For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2, we
get Equation 13:
TdVdT = 106 x 12 x (0 + 70 pF ) = 840 ms (13)
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7 is given by
Equation 14:
12
I(INRUSH) = 1 mF x = 15 mA
840 ms (14)
The inrush Power dissipation is calculated, using Equation 8 as shown in Equation 15:

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PD(INRUSH) = 0.5 x 12 x 15 m = 90 mW (15)

For 90 mW of power loss, the thermal shut down time of the device must not be less than the ramp-up time TdVdT
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 40 at TA =
85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up time without any
load on output.
Considering the start-up with load 4 Ω, the additional power dissipation, when load is present during start up is
calculated by Equation 16, using Equation 9:
12 x 12
PD(LOAD) = =6W
6 ´ 4 (16)
The total device power dissipation during start up, using Equation 10 is given by Equation 17:
PD(STARTUP) = 6 + 90 m = 6.09 W (17)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 6.09 W is more than 10 ms. So it
is well within acceptable limits to not use an external capacitor (CdV/dT) with start-up load of 4 Ω.
If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of
CdVdT capacitor.

9.2.1.2.5 Support Component Selection—CVIN

CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN.

9.2.1.3 Application Curves

Figure 41. Output Ramp without Load on Output Figure 42. Output Ramp with 4-Ω Load at Start Up

9.2.2 Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)
Blocking FET
VIN VIN OUT VOUT, IOUT < 2.7A
*
R1 CVIN CHOLD-UP
1M: 0.1PF 28m: CSD16411 4700PF

EN/UVLO BFET FLTb

R2
150k: dVdT ILIM ZXM61P03F

CdVdT RILIM
22nF GND TPS25924x 76.8k:

*Optional & only for noise suppression

Figure 43. Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)
(TPS25924x UVLO is used as power fail comparator)
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9.2.2.1 Design Requirements

The design parameters for this design example are shown in Table 3.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VIN Input voltage 12 V
V(UV) Undervoltage lockout set point 10.8 V
V(OV) Overvoltage protection set point Default: VOVC = 15 V
RL(SU) Load at start-up 1000 Ω
IOL= IILIM Current limit 3A
COUT Load capacitance 4700 µF
TA Maximum ambient temperature 85°C

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Programming the Current-Limit Threshold: RILIM Selection

The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
For IOL = IILIM = 3 A, from Equation 4, RILIM = 76.8 kΩ. Choose closest standard value resistor with 1% tolerance.

9.2.2.2.2 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving Equation 5.

For UVLO of V(UV) = 10.8 V, select R2 = 150 kΩ, and R1 = 1 MΩ.

The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, V(UV). This is calculated using Equation 6.
Where V(UV) = 10.73 V, Power fail threshold set is V(PFAIL) = 10.35 V.

9.2.2.2.3 Setting Output Voltage Ramp Time (TdVdT)

For a successful design, the junction temperature of device must be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
For the design example under discussion, select ramp-up capacitor CdVdT = 22 nF. Then, using Equation 2 we
get Equation 18:
TdVdT = 106 x 12 x (22 nF + 70 pF ) = 265 ms (18)
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7 is given by
Equation 19:
12
I(INRUSH) = 4700 mF x = 213 mA
265 ms (19)
The inrush Power dissipation is calculated, using Equation 8 is given by Equation 20:
PD(INRUSH) = 0.5 x 12 x 213 m = 1278 mW (20)
Considering the start-up with load 1000 Ω, the additional power dissipation, when load is present during start up
is calculated, using Equation 9 is given by Equation 21:
12 x 12
PD(LOAD) = = 24 mW
6 ´ 1000 (21)
The total device power dissipation during start up is given by Equation 22:
PD(STARTUP) = 1278 + 24 = 1302 mW (22)

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From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 1.3 W is more than 300 ms. So
the device starts safely.
If CdVdT = 4.7 nF was used, the device must have tried to charge the 4700-µF output cap with inrush current of
986 mA in 57.24 ms, dissipating power of 5.94 W. This is outside the safe starting condition of the device, and
must have led the device to enter thermal shutdown during start-up.

9.2.2.3 Application Curves

COUT = CHOLD-UP = CdVdT = 22 nF COUT = CHOLD-UP = V(PFAIL) = 10.35 V RLOAD = 12 Ω

4700 µF 4700 µF

Figure 44. Output Ramp Up Figure 45. Hold-up Power When VIN Fails

9.2.3 Controlled Power Down using TPS25924x

When the device is disabled, the output voltage is left floating and power down profile is entirely dictated by the
load. In some applications, this can lead to undesired activity as the load is not powered down to a defined state.
Controlled output discharge can ensure the load is turned off completely and not in an undefined operational
state. The BFET pin in TPS25924x family of eFuses facilitates Quick Output Discharge (QOD) function as
illustrated in Figure 46. When the device is/gets disabled, the BFET pin pulls low which enables the external P-
MOSFET Q1 for discharge feature to function. The output voltage discharge rate is dictated by the output
capacitor COUT, the discharge resistance RDCHG and the load.

VIN VIN OUT VOUT

C*IN
28m:
R1
RDCHG

EN/UVLO
BFET Q1 COUT
dVdT ZXM61P03F

R2 ILIM
GND TPS25924x
CdVdT RILIM

*Optional & only for noise suppression

Figure 46. Circuit Implementation with Quick Output Discharge Function

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10 Power Supply Recommendations

The device is designed for supply voltage range of 4.5 V ≤ VIN ≤ 18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply
must be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.

10.1 Transient Protection

In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 23:
L(IN)
VSPIKE(Absolute) = V(IN) + I(LOAD) x
C(IN)

where
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input (23)
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 47.

VIN VOUT
IN OUT
*
CVIN
R1 28mO COUT
0.1µF
EN/UVLO

* *
dVdT BFET
R2
CdVdT
ILIM
GND
TPS25924x
*Optional components for
RILIM
transient suppression

Figure 47. Circuit Implementation with Optional Protection Components

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10.2 Output Short-Circuit Measurements

It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.

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11 Layout

11.1 Layout Guidelines

• For all applications, a 0.01-µF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
• The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 48 for a PCB layout example.
• High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
• The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a
copper plane or island on the board.
• Locate all support components: RILIM, CdVdT and resistors for EN/UVLO, close to their connection pin. Connect
the other end of the component to the GND pin of the device with shortest trace length. The trace routing for
the RILIM and CdVdT components to the device must be as short as possible to reduce parasitic effects on the
current limit and soft start timing. These traces must not have any coupling to switching signals on the board.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT pins.
• Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.

11.2 Layout Example

Top layer
Bottom layer signal ground plane
Via to signal ground plane

dV/dT 1 10 ILIM Ground -

Bottom
layer
EN/UVLO 2 9 BFET

VIN 3 8 OUT

VIN 4 7 OUT
6 OUT
VIN 5

VIN VOUT
* VIN
*
High Frequency
Bypass Capacitor

Power Ground
* Optional: Needed only to suppress the transients caused by inductive load switching

Figure 48. Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation
For related documentation see the following:
• TPS2592xx Design Calculator
• TPS259230-41EVM User's Guide

12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 4. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TPS259241 Click here Click here Click here Click here Click here
TPS259240 Click here Click here Click here Click here Click here

12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.6 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

26 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated

Product Folder Links: TPS259240 TPS259241

 TPS259240, TPS259241
www.ti.com SLVSCU9B – AUGUST 2015 – REVISED SEPTEMBER 2016

12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: TPS259240 TPS259241
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS259240DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 259240

TPS259240DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 259240

TPS259241DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 259241

TPS259241DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 259241

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259240DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS259240DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS259241DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS259241DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS259240DRCR VSON DRC 10 3000 367.0 367.0 35.0
TPS259240DRCT VSON DRC 10 250 210.0 185.0 35.0
TPS259241DRCR VSON DRC 10 3000 367.0 367.0 35.0
TPS259241DRCT VSON DRC 10 250 210.0 185.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DRC 10 VSON - 1 mm max height
3 x 3, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4226193/A

www.ti.com
 PACKAGE OUTLINE
DRC0010J SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

1.0 C
0.8

SEATING PLANE
0.05
0.00 0.08 C

1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED 4X (0.25)
THERMAL PAD

5 6

2X 11 SYMM
2
2.4 0.1

10
1
8X 0.5 0.30
10X
0.18
PIN 1 ID SYMM
0.1 C A B
(OPTIONAL)
0.5 0.05 C
10X
0.3

4218878/B 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.65)
(0.5)

10X (0.6)

1
10

10X (0.24)
11
SYMM (2.4)
(3.4)

(0.95)
8X (0.5)

5 6

(R0.05) TYP

( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218878/B 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)
(0.5)
SYMM
EXPOSED METAL
11 TYP

10X (0.6)
1
10
(1.53)
10X (0.24) 2X
(1.06)

SYMM

(0.63)

8X (0.5)

6
5

(R0.05) TYP
4X (0.34)

4X (0.25)
(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4218878/B 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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