TPS7A2033PDBVR

TPS7A20
SBVS338H – MARCH 2020 – REVISED JULY 2024
TPS7A20 300mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO

1 Features 3 Description
• Low output voltage noise: 7μVRMS The TPS7A20 is an ultra-small, low-dropout (LDO)
– No noise-bypass capacitor required linear regulator that can source 300mA of output
• High PSRR: 95dB at 1kHz current. The TPS7A20 is designed to provide low
• Very low IQ: 6.5μA noise, high PSRR, and excellent load and line
• Input voltage range: 1.6V to 6.0V transient performance that can meet the requirements
• Output voltage range: 0.8V to 5.5V of RF and other sensitive analog circuits. Using
• Output voltage tolerance: ±1.5% (max) innovative design techniques, the TPS7A20 offers an
• Very low dropout: ultra-low noise performance without the addition of a
– 140mV (max) at 300mA (VOUT = 3.3V) noise bypass capacitor. The TPS7A20 also provides
– 145mV (max) at 300mA (VOUT = 3.3V, DBV) the advantage of low quiescent current, which can be
• Low inrush current ideal for battery-powered applications. With an input
• Smart enable pulldown voltage range of 1.6V to 6.0V and an output range of
• Stable with 1µF minimum ceramic output capacitor 0.8V to 5.5V, the TPS7A20 can be used for a wide
• Packages: variety of applications. The device uses a precision
– 1mm × 1mm X2SON (DQN) reference circuit to provide a maximum accuracy of
– 0.616mm × 0.616mm DSBGA (YCK) 1.5% over load, line, and temperature variations.
– 0.612mm × 0.612mm DSBGA (YCJ) The TPS7A20 features an internal soft-start to lower
– 2.9mm × 2.8mm SOT23-5 (DBV) the inrush current, thus minimizing the input voltage
drop during start up. The device is stable with
2 Applications small ceramic capacitors, allowing for a small overall
• Smartphones and tablets solution size.
• IP network cameras
The TPS7A20 has a smart enable input circuit with an
• Portable medical equipment
internally controlled pulldown resistor that keeps the
• Smart meters and field transmitters
LDO disabled even when the EN pin is left floating
• Motor drives
and helps eliminate the external components used to
• Wearables
pulldown the EN pin.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
DQN (X2SON, 4) 1mm × 1mm
YCJ (DSBGA, 4) 0.612mm × 0.612mm
TPS7A20
YCK (DSBGA, 4) 0.616mm × 0.616mm
DBV (SOT-23, 5) 2.9mm × 2.8mm
(1) For more information, see the Mechanical, Packaging, and

Orderable Information.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A20
SBVS338H – MARCH 2020 – REVISED JULY 2024 www.ti.com
Table of Contents
1 Features............................................................................1 7 Application and Implementation.................................. 27
2 Applications..................................................................... 1 7.1 Application Information............................................. 27
3 Description.......................................................................1 7.2 Typical Application.................................................... 30
4 Pin Configuration and Functions...................................3 7.3 Power Supply Recommendations.............................31
5 Specifications.................................................................. 5 7.4 Layout....................................................................... 31
5.1 Absolute Maximum Ratings........................................ 5 8 Device and Documentation Support............................33
5.2 ESD Ratings............................................................... 5 8.1 Device Support......................................................... 33
5.3 Recommended Operating Conditions.........................5 8.2 Receiving Notification of Documentation Updates....33
5.4 Thermal Information....................................................6 8.3 Support Resources................................................... 33
5.5 Electrical Characteristics.............................................6 8.4 Trademarks............................................................... 33
5.6 Switching Characteristics............................................7 8.5 Electrostatic Discharge Caution................................33
5.7 Typical Characteristics................................................ 8 8.6 Glossary....................................................................33
6 Detailed Description......................................................23 9 Revision History............................................................ 34
6.1 Overview................................................................... 23 10 Mechanical, Packaging, and Orderable
6.2 Functional Block Diagram......................................... 23 Information.................................................................... 34
6.3 Feature Description...................................................24 10.1 Mechanical Data..................................................... 35
6.4 Device Functional Modes..........................................26
2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TPS7A20

TPS7A20
www.ti.com SBVS338H – MARCH 2020 – REVISED JULY 2024
4 Pin Configuration and Functions

1 2 1 2
A IN OUT B EN GND
B EN GND A IN OUT
Not to scale Not to scale
Figure 4-1. YCJ and YCK Packages, Figure 4-2. YCJ and YCK Packages,
4-Pin DSBGA (Top View) 4-Pin DSBGA (Bottom View)
Pin Functions: DSBGA

PIN
I/O DESCRIPTION
NO. NAME
Input voltage supply. For best transient response and to minimize input impedance, use
the nominal value or larger capacitor from IN to ground as listed in the Recommended
A1 IN I
Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the
device as possible.
Regulated output voltage. A low equivalent series resistance (ESR) capacitor is required
from OUT to ground for stability. For best transient response, use the nominal
A2 OUT O recommended value or larger capacitor listed in the Recommended Operating Conditions
table. Place the output capacitor as close to the OUT and GND pins of the device as
possible.
Enable input. A low voltage (< VEN(LOW)) on this input turns the regulator off and discharges
the output pin to GND. A high voltage (> VEN(HI)) on this pin enables the regulator output.
B1 EN I
This pin has an internal 500kΩ pulldown resistor to hold the regulator off by default. When
VEN > VEN(HI), the 500kΩ pulldown is disconnected to reduce input current.
B2 GND — Common ground.
Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

TPS7A20
OUT 1 4 IN
IN 1 5 OUT
GND 2
5
Thermal Pad EN 3 4 N/C

GND 2 3 EN
Not to scale
Not to scale
Figure 4-3. DQN Package, 4-Pin X2SON (Top View) Figure 4-4. DBV Package, 5-Pin SOT-23 (Top View)
Pin Functions: X2SON, SOT-23

PIN
I/O DESCRIPTION
NAME X2SON SOT-23
Input voltage supply. For best transient response and to minimize input
impedance, use the nominal value or larger capacitor from IN to ground as listed
IN 4 1 I
in the Recommended Operating Conditions table. Place the input capacitor as
close to the IN and GND pins of the device as possible.
Regulated output voltage. A low equivalent series resistance (ESR) capacitor
is required from OUT to ground for stability. For best transient response, use
the nominal recommended value or larger capacitor listed in the Recommended
OUT 1 5 O Operating Conditions table. Place the output capacitor as close to the OUT and
GND pins of the device as possible. An internal 150Ω (typical) pulldown resistor
prevents a charge from remaining on VOUT when the regulator is in shutdown
mode (VEN< VEN(LOW)).
Enable input. A low voltage (< VEN(LOW)) on this pin turns the regulator off and
discharges the output pin to GND. A high voltage (> VEN(HI)) on this pin enables
EN 3 3 I the regulator output. This pin has an internal 500kΩ pulldown resistor to hold the
regulator off by default. When VEN > VEN(HI), the 500kΩ pulldown is disconnected
to reduce input current.
GND 2 2 — Common ground.
N/C — 4 — No internal electrical connection.
Thermal pad for the X2SON package. Connect this pad to GND or leave floating.
Thermal Pad 5 — — Do not connect to any potential other than GND. Connect the thermal pad to a
large-area ground plane for best thermal performance.

TPS7A20
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (3)
MIN MAX UNIT
VIN –0.3 6.5
Voltage VOUT –0.3 6.5 or VIN + 0.3 (2) V
VEN –0.3 6.5
Current Maximum output(4) Internally limited A
Operating junction, TJ –40 150 °C
Temperature
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum value of VOUT is the lesser of 6.5 V or (VIN + 0.3 V).
(3) All voltages are with respect to the GND pin.
(4) Internal thermal shutdown circuitry protects the device from permanent damage.
5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VIN Input supply voltage 1.6 6.0 V
VEN Enable input voltage 0 6.0 V
VOUT Nominal output voltage range 0.8 5.5 V
IOUT Output current 0 300 mA
CIN Input capacitor(2) 1 µF
COUT Output capacitor(3) 1 200 µF
ESR Output capacitor effective series resistance 100 mΩ
TJ Operating junction temperature –40 125 °C
(1) All voltages are with respect to GND.

(2) An input capacitor is not required for LDO stability. However, an input capacitor with an effective value of 0.47 μF minimum is
recommended to counteract the effect of source resistance and inductance, which may in some cases cause symptoms of system-
level instability such as ringing or oscillation, especially in the presence of load transients.
(3) Effective output capacitance of 0.47 μF minimum and 200 μF maximum is required for stability.

TPS7A20
5.4 Thermal Information

TPS7A20
DBV DQN YCJ YCK
THERMAL METRIC(1) UNIT
(SOT-23) (X2SON) (DSBGA) (DSBGA)
5 PINS 4 PINS 4 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 187.1 166.1 199.6 201.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 85.5 103.6 2.8 2.8 °C/W
RθJB Junction-to-board thermal resistance 54.4 110.6 67.5 69.3 °C/W
ψJT Junction-to-top characterization parameter 27.1 3.0 1.4 1.4 °C/W
ψJB Junction-to-board characterization parameter 54.1 103.3 67.4 69.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 98.8 N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.5 Electrical Characteristics

at operating temperature range (TJ = –40℃ to +125℃), VIN = VOUT(NOM) + 0.3 V or 1.6V, whichever is greater, VEN = 1.0 V,
IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN = (VOUT(NOM) + 0.3 V) to 6.0 V,
IOUT = 1 mA to 300 mA, –1.5 1.5
VOUT ≥ 1.85 V (DQN, YCJ, YCK packages)
%
IOUT = 1 mA to 300 mA, -1.5 1.5
VOUT ≥ 2.8 V (DBV package)
ΔVOUT Output voltage tolerance
IOUT = 1 mA to 300 mA –30 30
VOUT < 1.85 V (DQN, YCJ, YCK packages)
mV
IOUT = 1 mA to 300 mA, -40 40
VOUT < 2.8 V (DBV package)
ΔVOUT Line regulation 0.03 %/V
IOUT = 1 mA
IOUT = 1 mA to 300 mA (DQN, YCJ, YCK packages) 13
ΔVOUT Load regulation mV
IOUT = 1 mA to 300 mA (DBV package) 19
TJ = 25°C 6.5 8.5
VEN = VIN = 6 V,
TJ = –40°C to 85°C 10
IGND Quiescent ground current IOUT = 0 mA µA
TJ = –40°C to 125°C 15
VEN = VIN = 6 V, IOUT = 300 mA 2000
ISHDN Shutdown ground current VEN = 0 V (disabled), VIN = 6.0 V, TJ = 25°C 0.07 0.2 µA
IGND(DO) IGND in dropout VIN ≤ VOUT(NOM) , IOUT = 0 mA, VEN = VIN 6.5 15 µA
0.8 V ≤ VOUT < 1.0 V(1) 690
1.0 V ≤ VOUT < 1.2 V(1) 490
1.2 V ≤ VOUT < 1.5 V(1) 355
IOUT = 300 mA,
1.5 V ≤ VOUT < 2.5 V 200
VOUT = 95% x VOUT(NOM),
VDO Dropout voltage mV
(DQN, YCJ, YCK packages 1.5 V ≤ VOUT < 2.5 V
205
unless otherwise noted) (DBV)
2.5 V ≤ VOUT < 5.5 V 140
2.5 V ≤ VOUT < 5.5 V
145
(DBV)

TPS7A20
5.5 Electrical Characteristics (continued)

IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃
VOUT = 0.9 x VOUT(NOM), VOUT < 1.5 V (YCJ, YCK
360 520 770
VIN = VOUT(NOM) + 0.5 V packages)
VOUT = 0.9 x VOUT(NOM), VOUT < 1.5 V (DQN
360 520 730
VIN = VOUT(NOM) + 0.5 V package)
VOUT = VOUT(NOM) - 150 mV, VOUT < 1.5 V (DBV
ICL Output current limit 360 520 730 mA
VOUT = 0.9 x VOUT(NOM), VOUT ≥ 1.5 V (YCJ, YCK
360 520 770
VIN = VOUT(NOM) + 0.3 V packages)
VOUT = 0.9 x VOUT(NOM), VOUT ≥ 1.5 V (DQN
360 520 730
ISC Short-circuit current limit VOUT = 0 V 160 mA
f = 100 Hz 95
f = 1 kHz 95
IOUT = 20 mA,
f = 10 kHz 75
VIN = VOUT + 1.0 V
f = 100 kHz 75
f = 1 MHz 45
PSRR Power-supply rejection ratio dB
f = 100 Hz 65
f = 1 kHz 92
IOUT = 300 mA,
f = 10 kHz 75
VIN = VOUT + 1.0 V
f = 100 kHz 60
f = 1 MHz 40
BW = 10 Hz to 100 kHz, IOUT = 300 mA 7

VN Output noise voltage µVRMS
VOUT = 2.8 V IOUT = 1 mA 10
Output automatic discharge
RPULLDOWN VEN < VEN(LOW) (output disabled), VIN = 3.1 V 150 Ω
pulldown resistance
TJ rising 165
TSD Thermal shutdown °C
TJ falling 140
VIN = 1.6 V to 6.0 V,
VEN(LOW) Low input threshold 0.3 V
VEN falling until the output is disabled
VIN = 1.6 V to 6.0 V
VEN(HI) High input threshold 0.9 V
VEN rising until the output is enabled
VIN rising (YCJ and YCK packages) 1.11 1.35 1.59
VIN rising (DBV and DQN packages) 1.17 1.35 1.59
VUVLO UVLO threshold V
VIN falling (YCJ and YCK packages) 1.05 1.3 1.55
VIN falling (DBV and DQN packages) 1.11 1.3 1.55
VUVLO(HYST) UVLO hysteresis 50 mV
IEN EN input leakage current VEN = 6.0 V and VIN = 6.0 V 90 250 nA
REN(PULL-
Smart enable pulldown resistor VEN = 0.25 V 500 KΩ
DOWN)
(1) Design simulation data only
5.6 Switching Characteristics

IOUT = 1 mA, CIN= 1 µF, COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25℃
From VEN > VEN(HI) to VOUT = 95% of VOUT(NOM),
tSTR Start-up time 750 1150 µs

TPS7A20
5.7 Typical Characteristics

VIN = VOUT(NOM) + 0.3 V or 1.6 V (whichever is greater), VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, and TA = 25°C
(unless otherwise noted)
3 9
TJ TJ
2 -55°C 0°C 85°C 150°C 6 -55°C 0°C 85°C 150°C
Change in Output Voltage (mV)

-40°C 25°C 125°C -40°C 25°C 125°C

1 3
0
0
-1
-3
-2
-6
-3
-9
-4
-12
-5
-6 -15
3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 5.8 6 5.6 5.65 5.7 5.75 5.8 5.85 5.9 5.95 6
Input Voltage (V) Input Voltage (V)
VEN = 1 V, DQN, YCJ, and YCK packages VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages
Figure 5-1. Line Regulation vs VIN Figure 5-2. Line Regulation vs VIN
VEN = 1 V, DBV package VOUT = 5.5 V, VEN = 1 V, DBV package
Figure 5-3. Line Regulation vs VIN Figure 5-4. Line Regulation vs VIN
15 16
TJ TJ
10 -55°C 0°C 85°C 150°C -55°C 0°C 85°C 150°C
-40°C 25°C 125°C 12 -40°C 25°C 125°C

5
8
0
-5 4
-10
0
-15
-20 -4
-25 -8
0 25 50 75 100 125 150 175 200 225 250 275 300 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Output Current (mA)
Output Current (mA)
VIN = 3.1 V, VEN = 1 V, DQN, YCJ, and YCK packages VIN = 3.1 V, VEN = 1 V, DQN, YCJ, and YCK packages
Figure 5-5. Load Regulation vs IOUT Figure 5-6. Load Regulation vs IOUT

TPS7A20
5.7 Typical Characteristics (continued)

VIN = 2.8 V, VEN = 1 V, DBV package VIN = 2.8 V, VEN = 1 V, DBV package
15 15
TJ TJ
10 -55°C 0°C 85°C 150°C -55°C 0°C 85°C 150°C
10
5 -40°C 25°C 125°C -40°C 25°C 125°C
0 5
-5
0
-10
-15 -5
-20 -10
-25
-15
-30
-35 -20
0 30 60 90 120 150 180 210 240 270 300 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Output Current (mA) Output Current (mA)
VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages
VOUT = 5.5 V, VEN = 1 V, DBV package VOUT = 5.5 V, VEN = 1 V, DBV package

TPS7A20

0.6 0.6
TJ TJ
0.4 -55°C 0°C 85°C 150°C 0.5 -55°C 0°C 85°C 150°C
-40°C 25°C 125°C -40°C 25°C 125°C
Output Voltage Accuracy (%)

0.4
0.2
0.3
0
0.2
-0.2
0.1
-0.4
0
-0.6 -0.1
-0.8 -0.2
-1 -0.3
0 25 50 75 100 125 150 175 200 225 250 275 300 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
D076
VEN = 1 V, DQN, YCJ, and YCK packages VEN = 1 V, DQN, YCJ, and YCK packages
Figure 5-13. Output Voltage Accuracy vs IOUT Figure 5-14. Output Voltage Accuracy vs IOUT
VEN = 1 V, DBV package VEN = 1 V, DBV package

0.2 0.3
TJ TJ
0.1 -55°C 0°C 85°C 150°C -55°C 0°C 85°C 150°C
-40°C 25°C 125°C 0.2 -40°C 25°C 125°C
0
0.1
-0.1
-0.2 0
-0.3
-0.1
-0.4
-0.2
-0.5
-0.6 -0.3
0 30 60 90 120 150 180 210 240 270 300 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

TPS7A20

0.15 0.15
TJ TJ
0.1 -55°C 0°C 85°C 150°C 0.1 -55°C 0°C 85°C 150°C
-40°C 25°C 125°C -40°C 25°C 125°C
0.05
0.05
0
0
-0.05
-0.05
-0.1
-0.1
-0.15
-0.15
-0.2
-0.2 -0.25
-0.25 -0.3
3.1 3.6 4.1 4.6 5.1 5.6 6 5.6 5.65 5.7 5.75 5.8 5.85 5.9 5.95 6
VEN = 1 V, IOUT = 1 mA, DQN, YCJ, and YCK packages VOUT = 5.5 V, VEN = 1 V, DQN, YCJ, and YCK packages
Figure 5-21. Output Voltage Accuracy vs VIN Figure 5-22. Output Voltage Accuracy vs VIN
VEN = 1 V, IOUT = 1 mA, DBV package VOUT = 5.5 V, VEN = 1 V, DBV package
Figure 5-23. Output Voltage Accuracy vs VIN Figure 5-24. Output Voltage Accuracy vs VIN

TPS7A20

130 90
TJ TJ
120 -55°C 0°C 85°C 150°C 85 -55°C 0°C 85°C 150°C
-40°C 25°C 125°C -40°C 25°C 125°C
110
Dropout Voltage (mV)

80
100
75
90
70
80
65
70
60
60
55
50 0 1 2 3 4 5 6 7 8 9 10
0 30 60 90 120 150 180 210 240 270 300 Output Current (mA)
Output Current (mA)
VEN = 1 V, DQN, YCJ, and YCK packages
VEN = 1 V, DQN, YCJ, and YCK packages
Figure 5-26. Dropout Voltage vs IOUT
Figure 5-25. Dropout Voltage vs IOUT
VEN = 1 V, DBV package VEN = 1 V, DBV package

Figure 5-27. Dropout Voltage vs IOUT Figure 5-28. Dropout Voltage vs IOUT
160 95
TJ TJ
150 -55°C 25°C 150°C 90 -55°C 0°C 85°C 150°C
140 -40°C 85°C -40°C 25°C 125°C
0°C 125°C 85
130
120 80
110 75
100 70
90
65
80
70 60
60 55
0 30 60 90 120 150 180 210 240 270 300 0 1 2 3 4 5 6 7 8 9 10
Output Current (mA) D099

TPS7A20

180 14
TJ TJ
170 -40°C 0°C 50°C 125°C 13 -55°C 0°C 85°C 150°C
-20°C 25°C 85°C 12 -40°C 25°C 125°C
160
Quiescent Current (PA)
11
150
10
140
9
130 8
120 7
110 6
100 5
4
90 1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 6
1.5 2 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V)
Output Voltage ( V)
VEN = 1 V, IOUT = 0 mA
IOUT = 300 mA
Figure 5-34. I GND vs VIN
Figure 5-33. Dropout Voltage vs VOUT
13 12
TJ TJ
12 -55°C 0°C 85°C 150°C 11 -55°C 0°C 85°C 150°C
-40°C 25°C 125°C -40°C 25°C 125°C
11 10
10
9
9
8
8
7
7
6
6
5
5
4 4
1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 6 1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.5
VEN = VIN, IOUT = 0 mA VOUT(NOM) = 5.5 V, VEN = 1 V, IOUT = 0 mA
Figure 5-35. IGND vs VIN Figure 5-36. IGND vs VIN in the Dropout Region

TPS7A20

12 3250
TJ 3000 TJ
11 -55°C 0°C 85°C 150°C -55°C 0°C 85°C 150°C
2750 -40°C 25°C 125°C
-40°C 25°C 125°C
2500
10
Ground Current (uA)

2250
9 2000
1750
8 1500
1250
7
1000
6 750
500
5 250
0
4 0 30 60 90 120 150 180 210 240 270 300
1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.5 Output Current (mA)
Input Voltage (V)
VEN = 1 V
VOUT(NOM) = 5.5 V, VEN = VIN, IOUT = 0 mA
Figure 5-38. IGND vs IOUT
Figure 5-37. IGND vs VIN in the Dropout Region
4000 500
TJ TJ
-55°C 85°C 450 -55°C 0°C 85°C 150°C
1000 -40°C 125°C 400 -40°C 25°C 125°C
0°C 150°C
Ground Current (PA)
Ground Current (PA)
25°C 350
300
100 250
200
150
10 100
50
2 0
0.001 0.01 0.1 1 10 100 300 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VEN = 1 V VEN = 1 V
Figure 5-39. IGND vs IOUT Figure 5-40. IGND vs IOUT
45 4000
TJ TJ
40 -55°C -40°C 0°C 25°C 3500 85°C 125°C 150°C
35
3000
Shutdown Current (nA)
Shutdown Current (nA)
30
2500
25
20 2000
15 1500
10
1000
5
500
0
-5 0
1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 6 1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 6
VEN = 0 V VEN = 0 V
Figure 5-41. Shutdown Current vs VIN Figure 5-42. Shutdown Current vs VIN

TPS7A20

4500 4.5
TJ
4000 4 -55°C 0°C 85°C
Enable Pin Leakage Current (nA)
-40°C 25°C 125°C

3500 3.5
Output Voltage (V)

3000 3
2500 2.5
2000 2
1500 1.5
1000 TJ 1
-55°C 25°C 150°C
500 -40°C 85°C 0.5
0°C 125°C
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 50 100 150 200 250 300 350 400 450 500 550 600
VEN - VIN (V) Output Current (mA)
VEN = 6 V, IOUT = 0 mA VEN = 1 V
Figure 5-43. Enable Pin Leakage Current vs Figure 5-44. Current Limit
VEN – VIN
1.2 1.4
TJ VUVLO+ (VIN rising)
-55°C 0°C 85°C 150°C 1.39 VUVLO- (VIN falling)
1 -40°C 25°C 125°C 1.38
1.37
Output Voltage (V)
Input Voltage (V)
0.8
1.36
0.6 1.35
1.34
0.4 1.33
1.32
0.2
1.31
0 1.3
0 50 100 150 200 250 300 350 400 450 500 550 600 -60 -40 -20 0 20 40 60 80 100 120 140 160
Output Current (mA) Temperature (°C) D088
VOUT = 0.8 V, VEN = 1 V VEN = 1 V

Figure 5-45. Current Limit Figure 5-46. UVLO Threshold vs Temperature
1 0.9
Enable Pin Logic Low Threshold VEN(LO) (V)
Enable Pin Logic High Threshold VEN(HI) (V)
0.95 VIN VIN

0.85
1.6 V ( Vout = 0.8 V ) 1.6 V ( Vout = 0.8 V )
0.9 2.1 V ( Vout = 1.8 V ) 0.8 2.1 V ( Vout = 1.8 V )
0.85 3.1 V ( Vout = 2.8 V ) 3.1 V ( Vout = 2.8 V )
5.8 V ( Vout = 5.5 V ) 0.75 5.8 V ( Vout = 5.5 V )
0.8 6.0 V ( Vout = 0.8 V - 5.5 V ) 6.0 V ( Vout = 0.8 V - 5.5 V )
0.7
0.75
0.65
0.7
0.6
0.65
0.55
0.6
0.55 0.5
0.5 0.45
0.45 0.4
0.4 0.35
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (°C) Temperature (°C)
Figure 5-47. Enable Logic High Threshold vs Temperature Figure 5-48. Enable Logic Low Threshold Low vs Temperature

TPS7A20

400 540
VIN VIN
Smart Enable Pulldown Resistor ( K:)

1.6 V ( VOUT = 0.8 V ) 1.6 V
350 2.1 V ( VOUT = 1.8 V ) 520 2.4 V
3.1 V ( VOUT = 2.8 V ) 3.4 V
Pulldown Resistor (:)
6 V ( VOUT = 5.5 V ) 4.4 V

300 500 5.4 V
6.0 V
250 480
200 460
150 440
100 420
-60 -35 -10 15 40 65 90 115 140 160 -60 -30 0 30 60 90 120 150
Temperature (°C) Temperature (°C)
VEN = 0.25 V VEN = 0.25 V
Figure 5-49. Output Pulldown Resistor vs Temperature Figure 5-50. Smart Enable Pulldown Resistor vs Temperature
and VIN
1 20 0.9 40
IOUT
0.9 10 0.8 VOUT 30
AC-Coupled Output Voltage (mV)

0.8 0 0.7 20
0.7 -10 0.6 10
Output Current (A)
Output Current (A)
0.6 -20 0.5 0

0.5 -30 0.4 -10
0.4 -40 0.3 -20
0.3 -50 0.2 -30
0.2 -60 0.1 -40
0.1 IOUT -70 0 -50
VOUT
0 -80 -0.1 -60
0 2 4 6 8 10 12 14 16 18 20 0 4 8 12 16 20 24 28 32 36 40
Time (Ps) D030
Time (µs) D033
IOUT = 1 mA to 300 mA, tRISING = 1 µs IOUT = 300 mA to 1 mA, tFALLING = 1 µs

Figure 5-51. Load Transient Figure 5-52. Load Transient
1 20 0.9 40
IOUT
0.9 0 0.8 VOUT 30

0.8 -20 0.7 20
0.7 -40 0.6 10
Output Current (A)
Output Current (A)
0.6 -60 0.5 0

0.5 -80 0.4 -10
0.4 -100 0.3 -20
0.3 -120 0.2 -30
0.2 -140 0.1 -40
0.1 IOUT -160 0 -50
VOUT
0 -180 -0.1 -60
0 2 4 6 8 10 12 14 16 18 20 0 10 20 30 40 50 60 70 80 90 100
Time (Ps) D031
Time (µs) D032
IOUT = 1 mA to 300 mA, tRISING = 200 ns IOUT = 300 mA to 1 mA, tFALLING = 200 ns

TPS7A20

0.9 40 0.9 30
IOUT
0.8 0 0.8 VOUT 20

0.7 -40 0.7 10
0.6 -80 0.6 0
Output Current (A)

Output Current (A)
0.5 -120 0.5 -10

0.4 -160 0.4 -20
0.3 -200 0.3 -30
0.2 -240 0.2 -40
0.1 -280 0.1 -50
0 IOUT -320 0 -60
VOUT
-0.1 -360 -0.1 -70
0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 350 400 450 500
Time (µs) D035
Time (µs) D037
IOUT = 0 mA to 300 mA, tRISING = 1 µs IOUT = 300 mA to 0 mA, tFALLING = 1 µs

0.9 40 0.9 30
IOUT
0.8 0 0.8 VOUT 20

0.7 -40 0.7 10
0.6 -80 0.6 0
Output Current (A)
Output Current (A)
0.5 -120 0.5 -10

0.4 -160 0.4 -20
0.3 -200 0.3 -30
0.2 -240 0.2 -40
0.1 -280 0.1 -50
0 IOUT -320 0 -60
VOUT
-0.1 -360 -0.1 -70
0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 350 400 450 500
Time (µs) D034
Time (µs) D036
IOUT = 0 mA to 300 mA, tRISING = 200 ns IOUT = 300 mA to 0 mA, tFALLING = 200 ns
6 7 6 6
VOUT VOUT
5 VIN 6 5 VIN 5
4 5 4 4
3 4 3 3
Input Voltage (V)
Input Voltage (V)

2 3 2 2
1 2 1 1
0 1 0 0
-1 0 -1 -1
-2 -1 -2 -2
-3 -2 -3 -3
-4 -3 -4 -4
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Time (µs) D060
Time (Ps) D061
VIN = 3.1 V → 4.1 V → 3.1 V, VIN tRISING = 5 µs, IOUT = 1 mA VIN = 3.1 V → 4.1 V → 3.1 V, VIN tRISING = 5 µs,
IOUT = 300 mA
Figure 5-59. Line Transient Figure 5-60. Line Transient

TPS7A20

120 120
110 VIN 110 VIN
3.10 V 3.1 V
Power Supply Rejection Ratio (dB)

100 3.30 V 100 3.3 V
90 3.80 V 90 3.8 V
80 80
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D011
Frequency (Hz) D001
D015
IOUT = 20 mA IOUT = 300 mA

Figure 5-61. PSRR vs VIN vs Frequency and VIN Figure 5-62. PSRR vs Frequency and VIN
120 120
110 110 COUT
1 PF

100 100 10 PF
90 90 200 PF
80 80
70 70
60 60
50 50
40 40
30 30
20 IOUT 20
0.01 mA 100 mA 300 mA
10 20 mA 200 mA 10
0 0
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D012
Frequency (Hz) D001
D013
IOUT = 20 mA
Figure 5-63. PSRR vs Frequency and IOUT Figure 5-64. PSRR vs Frequency and COUT
2 2
IOUT VIN
1 1
1 mA, RMS noise = 8.63 PVRMS 3.1 V, RMS Noise = 6.66 PVRMS
Output Voltage Noise (PV —Hz)
0.5 20 mA, RMS noise = 6.66 PVRMS 0.5 3.3 V, RMS Noise = 6.71 PVRMS
100 mA, RMS noise = 6.69 PVRMS 3.8 V, RMS Noise = 6.70 PVRMS
0.2 200 mA, RMS noise = 6.73 PVRMS 0.2
300 mA, RMS noise = 7.76 PVRMS
0.1 0.1
0.05 0.05
0.02 0.02
0.01 0.01
0.005 0.005
0.002 0.002
0.001 0.001
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D002
Frequency (Hz) D003
VRMS BW = 10 Hz to 100 kHz IOUT = 20 mA, VRMS BW = 10 Hz to 100 kHz

Figure 5-65. Noise vs Frequency and IOUT Figure 5-66. Noise vs Frequency and VIN

TPS7A20

2 2
VIN COUT
1 1
3.1 V, RMS Noise = 6.76 PVRMS 1 PF, RMS noise = 6.65 PVRMS
Output voltage Noise (PV —Hz)

0.5 3.3 V, RMS Noise = 6.77 PVRMS 0.5 10 PF, RMS noise = 6.94 PVRMS
3.8 V, RMS Noise = 7.10 PVRMS 200 PF, RMS noise = 6.56 PVRMS
0.2 0.2
0.1 0.1
0.05 0.05
0.02 0.02
0.01 0.01
0.005 0.005
0.002 0.002
0.001 0.001
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D004
Frequency (Hz) D006
IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz VIN = 3.8 V, IOUT = 20 mA, VRMS BW = 10 Hz to 100 kHz
Figure 5-67. Noise vs Frequency and VIN Figure 5-68. Noise vs Frequency and COUT
2 2
COUT IOUT
1 1
1 PF, RMS noise = 7.14 PVRMS 20 mA, RMS noise = 7.11 PVRMS
0.5 10 PF, RMS noise = 7.14 PVRMS 0.5 300 mA, RMS noise = 7.04 PVRMS
200 PF, RMS noise = 6.87 PVRMS
0.2 0.2
0.1 0.1
0.05 0.05
0.02 0.02
0.01 0.01
0.005 0.005
0.002 0.002
0.001 0.001
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D007
Frequency (Hz) D010
VIN = 3.8 V, IOUT = 300 mA, VRMS BW = 10 Hz to 100 kHz VOUT = 0.8 V, VRMS BW = 10 Hz to 100 kHz
Figure 5-69. Noise vs Frequency and COUT Figure 5-70. Noise vs Frequency and IOUT
2 2
IOUT IOUT
1 1
20 mA, RMS noise = 7.09 PVRMS 20 mA, RMS noise = 7.21 PVRMS
0.5 300 mA, RMS noise = 7.19 PVRMS 0.5 300 mA, RMS noise = 7.69 PVRMS
0.2 0.2
0.1 0.1
0.05 0.05
0.02 0.02
0.01 0.01
0.005 0.005
0.002 0.002
0.001 0.001
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D009
Frequency (Hz) D008
VOUT = 0.8 V, VIN = 1.8 V, VRMS BW = 10 Hz to 100 kHz VOUT = 5.5 V, VIN = 6 V, VRMS BW = 10 Hz to 100 kHz
Figure 5-71. Noise vs Frequency and IOUT Figure 5-72. Noise vs Frequency and IOUT

TPS7A20

900 2
1.8
850 1.6
1.4
800
Turnon Time (Ps)
1.2
Voltage (V)
750 1
0.8
700 0.6
0.4
650 VIN
0.2 VEN
0 VOUT ( IOUT = 0 mA)
600 VOUT ( IOUT = 1 mA)
-0.2 VOUT ( IOUT = 300 mA)
550 -0.4
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Temperature (°C) Time (Ps) D048
From VEN = VEN(HI) to VOUT = 95% of VOUT(NOM), IOUT = 0 mA VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = 0 V to 1.8 V, VEN rises
500 µs behind VIN, VIN and VEN slew rate = 1 V/µs
Figure 5-73. Start-Up Turn-On Time Figure 5-74. Start-Up
2 2
1.8 1.8
1.6 1.6
1.4 1.4
1.2 1.2
Voltage (V)
Voltage (V)
1 1
0.8 0.8
0.6 0.6
0.4 0.4
VIN
0.2 VEN 0.2 VIN / VEN
0 VOUT ( IOUT = 0 mA) 0 VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA) VOUT ( IOUT = 1 mA)
-0.2 VOUT ( IOUT = 300 mA) -0.2 VOUT ( IOUT = 300 mA)
-0.4 -0.4
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Time (Ps) D049
Time (Ps) D050
VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = 0 V to 1.8 V, VEN rises VOUT = 0.8 V, VIN = 0 V to 1.8 V, VEN = VIN,
500 µs ahead of VIN, VIN and VEN slew rate = 1 V/µs VIN slew rate = 1 V/µs
Figure 5-75. Start-Up Figure 5-76. Start-Up
4.5 4.5
4 4
3.5 3.5
3 3
Voltage (V)
Voltage (V)
2.5 2.5
2 2
1.5 1.5
1 VIN 1 VIN
VEN VEN
0.5 VOUT ( IOUT = 0 mA) 0.5 VOUT ( IOUT = 0 mA)
-0.5 -0.5
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (Ps) D051
Time (Ps) D052
VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN rises 500 µs behind VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN rises 500 µs ahead
VIN, VIN and VEN slew rate = 1 V/µs of VIN, VIN and VEN slew rate = 1 V/µs

TPS7A20

4.5 6.5
6
4
5.5
3.5 5
3 4.5
4
Voltage (V)
Voltage (V)
2.5
3.5
2 3
2.5
1.5
2
1 1.5 VIN
VIN / VEN 1 VEN
0.5 VOUT ( IOUT = 0 mA) VOUT ( IOUT = 0 mA)
VOUT ( IOUT = 1 mA) 0.5 VOUT ( IOUT = 1 mA)
0
VOUT ( IOUT = 300 mA) 0 VOUT ( IOUT = 300 mA)
-0.5 -0.5
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (Ps) D053
Time (us) D054
VIN = 0 V to 3.8 V, VEN = 0 V to 3.8 V, VEN = VIN, VIN and slew VOUT = 5.5 V, VIN = 0 V to 6.0 V, VEN = 0 V to 6.0 V, VEN rises
rate = 1 V/µs 500 µs behind VIN, VIN and VEN slew rate = 1 V/µs
6.5 6.5
6 6
5.5 5.5
5 5
4.5 4.5
4 4
Voltage (V)
Voltage (V)
3.5 3.5
3 3
2.5 2.5
2 2
1.5 VIN 1.5
1 VEN 1 VIN / VEN
0.5 VOUT ( IOUT = 1 mA) 0.5 VOUT ( IOUT = 1 mA)
-0.5 -0.5
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Time (Ps) D055
Time (Ps) D056
VOUT = 5.5 V, VIN = 0 V to 6.0 V, VEN = 0 V to 6.0 V, VEN rises VOUT = 5.5 V, VIN = 0 V to 6 V, VEN = VIN, VIN slew rate =
500 µs ahead of VIN, VIN and VEN slew rate = 1 V/µs 1 V/µs
20 2.5 300 5
IIN VIN VEN VOUT IIN VIN VEN VOUT
18 2.25 270 4.5
16 2 240 4
14 1.75 210 3.5
Input CUrrent (mA)
Input Current (mA)
Voltage (V)
Voltage (V)
12 1.5 180 3
10 1.25 150 2.5
8 1 120 2
6 0.75 90 1.5
4 0.5 60 1
2 0.25 30 0.5
0 0 0 0
0 120 240 360 480 600 720 840 960 1080 1200 0 150 300 450 600 750 900 1050 1200 1350 1500
Time (µs) D047
Time (µs) D043
VOUT = 0.8 V, VIN = 1.8 V, VEN = 0 V to 1.8 V, VIN = 3.8 V, VEN = 0 V to 3.8 V, VEN slew rate = 1 V/µs,
VEN slew rate = 1 V/µs, COUT = 10 µF COUT = 10 µF
Figure 5-83. Inrush Current Figure 5-84. Inrush Current

TPS7A20

800 8
IIN VIN VEN VOUT
720 7.2
640 6.4
560 5.6
Input Current (mA)
Voltage (V)
480 4.8
400 4
320 3.2
240 2.4
160 1.6
80 0.8
0 0
0 150 300 450 600 750 900 1050 1200 1350 1500
Time (µs) D044
VOUT = 5.5 V, VIN = 6.0 V, VEN = 0 V to 6.0 V,

VEN slew rate = 1 V/µs, COUT = 10 µF
Figure 5-85. Inrush Current

TPS7A20
6 Detailed Description
6.1 Overview
Designed to meet the needs of sensitive RF and analog circuits, the TPS7A20 provides low noise, high
PSRR, low quiescent current, as well as low line and load transient response figures. Using innovative design
techniques, the TPS7A20 offers class-leading noise performance without the need for a separate noise filter
capacitor.
The TPS7A20 is designed to operate with a single 1-µF input capacitor and a single 1-µF ceramic output
capacitor.
6.2 Functional Block Diagram
Current
IN OUT
Limit
Bandgap +
Active Discharge
± P-Version Only
±
Error
+ Amp
+
UVLO
Internal
Thermal Controller
Shutdown
EN
500NŸ
GND

TPS7A20
6.3 Feature Description

6.3.1 Low Output Noise
Any internal noise at the TPS7A20 reference voltage is reduced by a first-order, low-pass RC filter before being
passed to the output buffer stage. The low-pass RC filter has a –3dB cut-off frequency of approximately 0.1Hz.
During start-up, the filter resistor is bypassed to reduce output rise time; the filter begins normal operation after
the output voltage reaches the correct value.
6.3.2 Smart Enable
The enable (EN) input polarity is active high. The output voltage is enabled when the voltage of the enable input
is greater than VEN(HI) and disabled when the enable input voltage is less than VEN(LOW). If independent control
of the output voltage is not needed, connect EN to IN.
This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is
driven above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable
internal pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is
connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical
Characteristics table.
6.3.3 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the value required to maintain output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
VDO
RDS(ON) =
IRATED (1)
6.3.4 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brick-wall-foldback scheme. The current limit transitions from a
brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with
the output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current
limit, the pass transistor dissipates power [(VIN – V OUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application note.

TPS7A20
Figure 6-1 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0V IOUT
0 mA ISC IRATED ICL
Figure 6-1. Foldback Current Limit
6.3.5 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
6.3.6 Thermal Shutdown
A thermal shutdown protection circuit disables the LDO when the junction temperature (TJ) of the pass transistor
rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the
temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

TPS7A20
6.3.7 Active Discharge (P Version Only)

An internal pulldown MOSFET connects a resistor from OUT to ground when the device is disabled to actively
discharge the output capacitance. The active discharge circuit is activated by driving EN low or by the voltage on
IN falling below the undervoltage lockout (UVLO) threshold.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
6.4 Device Functional Modes
6.4.1 Device Functional Mode Comparison
Table 6-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics
table for parameter values.
Table 6-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN VEN IOUT TJ
Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown)
Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < IOUT(max) TJ < TSD(shutdown)
Disabled
(any true condition VIN < VUVLO VEN < VEN(LOW) Not applicable TJ > TSD(shutdown)
disables the device)
6.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
6.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
6.4.4 Disabled
The output of the LDO can be shut down by driving EN to less than VEN(LOW) (see the Electrical Characteristics
table). When disabled, the pass transistor is turned off, internal circuits are shut down, and the output voltage is
actively discharged to ground by an internal discharge circuit between OUT and ground.

TPS7A20
7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
7.1 Application Information

7.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
7.1.2 Input and Output Capacitor Requirements
Although the LDO itself is stable without an input capacitor, good analog design practice is to connect a
capacitor from IN to GND, with a value at least equal to the nominal value specified in the Recommended
Operating Conditions table. The input capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR, and is recommended if the source impedance is greater than 0.5 Ω. When the
source resistance and inductance are sufficiently high, especially in the presence of load transients, the overall
system may be susceptible to instability (including ringing and sustained oscillation) and other performance
degradation if there is insufficient capacitance between IN and GND. A capacitor with a value greater than
the minimum may be necessary if large, fast-rise-time load or line transients are anticipated or if the device is
located more than a few centimeters from the input power source.
An output capacitor of an appropriate value helps ensure stability and improve dynamic performance. Use an
output capacitor within the range specified in the Recommended Operating Conditions table.
7.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure
7-1 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.
tAt tCt tDt tEt tGt tHt
B F
Figure 7-1. Load Transient Waveform
During transitions from a light load to a heavy load, the:

• Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)

TPS7A20
• Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load, the:
• Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
• Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
7.1.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum
operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure
7-2 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the
following parts:
• Region A: The device does not start until the input reaches the UVLO rising threshold.
• Region B: Normal operation, regulating device.
• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device remains enabled.
• Region D: Normal operation, regulating device.
• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is re-enabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
• Region F: Normal operation followed by the input falling to the UVLO falling threshold.
• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold

UVLO Hysteresis
VIN
VOUT C
tAt tBt tDt tEt tFt tGt
Figure 7-2. Typical UVLO Operation
7.1.5 Power Dissipation (PD)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT (2)

TPS7A20
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A20 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 4 rearranges Equation 3 for output current.
TJ = TA + (RθJA × PD) (3)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)] (4)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of
the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a
well-designed thermal layout, RθJA is actually the sum of the X2SON package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
7.1.5.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD (5)
where:
• PD is the power dissipated as explained in Equation 2
• TT is the temperature at the center-top of the device package
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
7.1.5.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 7-3 and can be
separated into the following parts:
• Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Operation section for more details.
• The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
• The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum-rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN –
VOUT increases the output current must decrease.
• The rated input voltage range governs both the minimum and maximum of VIN – VOUT.

TPS7A20
Figure 7-3 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA as given in the Thermal Information table.
Output current limited by Rated output

Output current limited by thermals
dropout current
Output Current (A)
Limited by Limited by
minimum VIN maximum VIN
VIN ± VOUT (V)
Figure 7-3. Region Description of Continuous Operation Regime
7.2 Typical Application

Figure 7-4 shows the typical application circuit for the TPS7A20. Input and output capacitances may need to be
increased above the 1 µF minimum for some applications.
INPUT VIN VOUT OUTPUT
1.0 µF 1.0 µF
TPS7A20
ENABLE VEN
GND
GND
SVA-30180501
Figure 7-4. TPS7A20 Typical Application
7.2.1 Design Requirements

Table 7-1 summarizes the design requirements for Figure 7-4.
Table 7-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 3.1 V to 3.6 V
Output voltage 2.8 V
Output current 200 mA
Maximum ambient temperature 85°C

TPS7A20
7.2.2 Detailed Design Procedure

For this design example, the 2.8V output version (TPS7A2028) is selected. A nominal 3.3V input supply is
assumed. A minimum 1.0μF input capacitor is recommended to minimize the effect of resistance and inductance
between the 3.3V source and the LDO input. A minimum 1.0μF output capacitor is also recommended for
stability and good load transient response. The dropout voltage (VDO) is less than 140mV maximum at a 2.8V
output voltage and 300mA output current, so there are no dropout issues with a minimum input voltage of 3.0V
and a maximum output current of 200mA.
7.2.3 Application Curves
4.5 100
IOUT
4 90 200 mA
3.5 80
3 70
Voltage (V)
PSRR (dB)
2.5 60
2 50
1.5 40
1 30
0.5 20
0 VIN / VEN 10
VOUT
-0.5 0
0 200 400 600 800 1000 1200 1400 1600 1800 2000 10 20 100 1000 10000 100000 1000000 1E+7
Time (us) D064
Frequency (Hz) D065
Figure 7-5. Start-Up Figure 7-6. PSRR
7.3 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.6V to 6.0V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 0.3V or 1.6V, whichever is greater.
TI highly recommends using a 1µF or greater input capacitor to reduce the impedance of the input supply,
especially during transients.
7.4 Layout
7.4.1 Layout Guidelines
• Place input and output capacitors as close to the device as possible.
• Use copper planes for device connections to optimize thermal performance.
• Place thermal vias around the device to distribute the heat.
• Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
7.4.2 Layout Examples
VIN VOUT
CIN 1 IN OUT 5 COUT
GND GND
2 GND
Enable
3 EN N/C 4
Figure 7-7. DBV Package (SOT-23) Typical Layout

TPS7A20
VOUT TPS7A20 VIN
1 4
COUT CIN
2 3
Power Ground
VEN
Figure 7-8. DQN Package (X2SON) Typical Layout
VIN VOUT
TPS7A20
A1 A2
CIN COUT
B1 B2
Power Ground
VEN
Figure 7-9. YCJ and YCK Package (DSBGA) Typical Layout

TPS7A20
8 Device and Documentation Support

8.1 Device Support
8.1.1 Device Nomenclature
Table 8-1. Device Nomenclature
PRODUCT (1) (2) VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8V; 125 = 1.25V).
TPS7A20xx(x)Pyyyz P indicates an active output discharge feature.
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces for DQN and DBV; 12000 pieces for YCJ and YCK).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 0.8V to 5.5V in 25mV increments are available. Contact the factory for details and availability.
8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

TPS7A20
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (May 2022) to Revision H (July 2024) Page
• Changed Packages bullet in Features for clarification....................................................................................... 1
• Changed title of Application Schematic figure.................................................................................................... 1
• Deleted discussion of pulldown resistor from OUT pin description in YCJ and YCK package Pin Functions
table.................................................................................................................................................................... 3
• Added clarification to Active Discharge (P Version Only) section that this feature only applies to the P
device version...................................................................................................................................................26
• Changed active output discharge feature discussion in Device Nomenclature table....................................... 33
Changes from Revision F (April 2022) to Revision G (May 2022) Page

• Changed UVLO condition from rising to falling for YCJ and YCK packages......................................................6
10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

TPS7A20
10.1 Mechanical Data

PACKAGE OUTLINE
YCJ0004-C02 SCALE 15.000
DSBGA - 0.35 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
D
C
0.35 MAX
SEATING PLANE
0.13 BALL TYP 0.05 C
0.07
0.35
TYP
B
D: Max = 0.636 mm, Min = 0.596 mm
0.35 SYMM
E: Max = 0.636 mm, Min = 0.596 mm
TYP
1 2
0.20 SYMM
4X
0.16
0.015 C A B
4226216/A 09/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com

TPS7A20
EXAMPLE BOARD LAYOUT
YCJ0004-C02 DSBGA - 0.35 mm max height
(0.35) TYP
4X ( 0.18)
1 2
A
SYMM
(0.35) TYP
SYMM
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 50X
0.0375 MAX 0.0375 MIN METAL UNDER

( 0.18) SOLDER MASK
METAL
SOLDER MASK EXPOSED EXPOSED ( 0.18)

OPENING METAL METAL SOLDER MASK
OPENING
SOLDER MASK
NON-SOLDER MASK DEFINED
DEFINED (PREFERRED)
SOLDER MASK DETAILS

NOT TO SCALE
4226216/A 09/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com

TPS7A20
EXAMPLE STENCIL DESIGN

YCJ0004-C02 DSBGA - 0.35 mm max height
(0.39) TYP
4X ( 0.21) (R0.05) TYP
1 2
A
SYMM
(0.39) TYP
METAL
TYP SYMM
SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL
SCALE: 50X
4226216/A 09/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com

TPS7A20
PACKAGE OUTLINE
YCK0004-C01 SCALE 15.000
DSBGA - 0.33mm MAX HEIGHT
A
B E
BUMP A1 CORNER
D
0.33 MAX C
SEATING PLANE
0.13
0.07 0.05 C
BUMP
0.175
D: Max = 0.636 mm, Min = 0.596 mm

B
E: Max = 0.636 mm, Min = 0.596 mm
0.175
0.35
0.20 1 2
4X
0.16
0.015 C A B 0.35
4228575/A 03/2022
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per
ASME Y14.5M.
www.ti.com

TPS7A20

YCK0004-C01 DSBGA - 0.33mm MAX HEIGHT
SYMM
4X ( 0.18)
1 2
(0.175)
A
SYMM
(0.35)
(0.175)
(0.35)

EXPOSED METAL SHOWN
SCALE:60X
0.0375 MIN ( 0.18)

0.0375 MAX ( 0.18) SOLDERMASK
METAL OPENING
EXPOSED
METAL SOLDERMASK EXPOSED METAL UNDER
OPENING METAL SOLDER MASK
NON SOLDERMASK SOLDERMASK

DEFINED DEFINED
(PREFERRED)
SOLDERMASK DETAILS
NOT TO SCALE
4228575/A 03/2022
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com

TPS7A20
YCK0004-C01 DSBGA - 0.33mm MAX HEIGHT
(R0.05)
METAL SYMM TYP
TYP
1 2
A 4X
( 0.21)
(0.195)
SYMM
(0.39)
(0.195)
(0.39)
SOLDERPASTE EXAMPLE
SCALE:80X
4228575/A 03/2022
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com

PACKAGE OPTION ADDENDUM
www.ti.com 27-Sep-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
PTPS7A2025PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 Samples
PTPS7A2045PDQNR ACTIVE X2SON DQN 4 3000 TBD Call TI Call TI -40 to 125 Samples
TPS7A2009PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GBF Samples
TPS7A2009PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KT Samples
TPS7A20105PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KS Samples
TPS7A2011PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 Q Samples
TPS7A2012PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2ATF Samples
TPS7A2012PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JC Samples
TPS7A2012PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 M Samples
TPS7A2015PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2DTF Samples
TPS7A2015PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JD Samples
TPS7A2016YCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 Z Samples
TPS7A201825PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 IQ Samples
TPS7A201825PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 IQ Samples
TPS7A20185PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2CBF Samples
TPS7A20185PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JE Samples
TPS7A20185PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JE Samples
TPS7A20185PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 T Samples
TPS7A2018PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AUF Samples
TPS7A2018PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JF Samples
Addendum-Page 1
(6)
TPS7A2018PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JF Samples
TPS7A2018PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 D Samples
TPS7A2018YCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 Y Samples
TPS7A2020PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 S Samples
TPS7A20225PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PX Samples
TPS7A2022PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 K Samples
TPS7A2024PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2CCF Samples
TPS7A2025PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AVF Samples
TPS7A2025PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JG Samples
TPS7A2025PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 L Samples
TPS7A2027PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KO Samples
TPS7A2027PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 N Samples
TPS7A20285PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GCF Samples
TPS7A20285PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KN Samples
TPS7A20285PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 P Samples
TPS7A2028PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AWF Samples
TPS7A2028PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JH Samples
TPS7A2028PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JH Samples
TPS7A2028PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 E Samples
TPS7A2028PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 E Samples
TPS7A2029PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JI Samples
Addendum-Page 2
(6)
TPS7A2030PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AXF Samples
TPS7A2030PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JJ Samples
TPS7A2030YCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 X Samples
TPS7A2031PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GDF Samples
TPS7A2032PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GEF Samples
TPS7A2033PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2AZF Samples
TPS7A2033PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 JA Samples
TPS7A2033PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JA Samples
TPS7A2033PYCJR ACTIVE DSBGA YCJ 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 O Samples
TPS7A2033YCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 V Samples
TPS7A2036PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GIF Samples
TPS7A2036PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KP Samples
TPS7A2040PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KQ Samples
TPS7A2042PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GFF Samples
TPS7A2042PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KV Samples
TPS7A2045PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GGF Samples
TPS7A2045PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 JB Samples
TPS7A2050PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2B1F Samples
TPS7A2050PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KR Samples
TPS7A2050PDQNRM3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KR Samples
TPS7A2050PYCKR ACTIVE DSBGA YCK 4 12000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 H Samples
Addendum-Page 3
(6)
TPS7A2055PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2GHF Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Oct-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A2009PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS7A2009PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2
TPS7A2011PYCKR DSBGA YCK 4 12000 180.0 8.4 0.71 0.71 0.42 2.0 8.0 Q1
TPS7A2012PYCJR DSBGA YCJ 4 12000 180.0 8.4 0.71 0.71 0.42 2.0 8.0 Q1
TPS7A2016YCKR DSBGA YCK 4 12000 180.0 8.4 0.71 0.71 0.42 2.0 8.0 Q1
Pack Materials-Page 1

(mm) W1 (mm)
TPS7A201825PDQNRM3 X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.5 4.0 8.0 Q2

(mm) W1 (mm)
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A2009PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS7A2009PDQNR X2SON DQN 4 3000 210.0 185.0 35.0
TPS7A2011PYCKR DSBGA YCK 4 12000 182.0 182.0 20.0
TPS7A2012PYCJR DSBGA YCJ 4 12000 182.0 182.0 20.0
TPS7A2016YCKR DSBGA YCK 4 12000 182.0 182.0 20.0
TPS7A201825PDQNRM3 X2SON DQN 4 3000 210.0 185.0 35.0
PACKAGE OUTLINE
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
B 1.05 A
0.95
1.05
PIN 1 0.95
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
0.48+0.12
-0.1
0.05
(0.05) TYP 0.00
2 NOTE 6
3
EXPOSED
5 THERMAL PAD
2X 0.65
(0.07) TYP
NOTE 5
1 4
PIN 1 ID 4X 0.28
0.15
(OPTIONAL) (0.11)
NOTE 4 0.3 0.1 C A B
0.2
0.05 C
3X 0.30
0.15
4215302/E 12/2016
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
(0.86)
SYMM
4X (0.36) 4X SEE DETAIL

(0.03)
4
4X (0.21) 1
SYMM 5 (0.65)
4X (0.18)
( 0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE

SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
EXPOSED METAL OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL

4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
4X (0.21) 1
5
SYMM
(0.65)
SOLDER MASK
EDGE 4X (0.22)
2
3
( 0.45)
4X (0.235)

BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA
1 5
2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)
4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/K 08/2024
NOTES:
per ASME Y14.5M.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/K 08/2024
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)

SCALE:15X
4214839/K 08/2024
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated

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TPS7A20

SBVS338H – MARCH 2020 – REVISED JULY 2024

TPS7A20 300mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO

(1) For more information, see the Mechanical, Packaging, and

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS7A20

4 Pin Configuration and Functions

Not to scale Not to scale

Pin Functions: DSBGA

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

Thermal Pad EN 3 4 N/C

Pin Functions: X2SON, SOT-23

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS7A20

5.2 ESD Ratings

5.3 Recommended Operating Conditions

(1) All voltages are with respect to GND.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

5.4 Thermal Information

5.5 Electrical Characteristics

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS7A20

5.5 Electrical Characteristics (continued)

BW = 10 Hz to 100 kHz, IOUT = 300 mA 7

(1) Design simulation data only

5.6 Switching Characteristics

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

5.7 Typical Characteristics

Change in Output Voltage (mV)

-40°C 25°C 125°C -40°C 25°C 125°C

VEN = 1 V, DBV package VOUT = 5.5 V, VEN = 1 V, DBV package

Change in Output Voltage (mV)

-40°C 25°C 125°C 12 -40°C 25°C 125°C

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS7A20

5.7 Typical Characteristics (continued)

Change in Output Voltage (mV)

5 -40°C 25°C 125°C -40°C 25°C 125°C

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

5.7 Typical Characteristics (continued)

Output Voltage Accuracy (%)

VEN = 1 V, DBV package VEN = 1 V, DBV package

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS7A20

5.7 Typical Characteristics (continued)

Output Voltage Accuracy (%)

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

5.7 Typical Characteristics (continued)

Dropout Voltage (mV)

VEN = 1 V, DBV package VEN = 1 V, DBV package

Dropout Voltage (mV)

12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TPS7A20

5.7 Typical Characteristics (continued)

VEN = VIN, IOUT = 0 mA VOUT(NOM) = 5.5 V, VEN = 1 V, IOUT = 0 mA

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

5.7 Typical Characteristics (continued)

Ground Current (uA)

Ground Current (PA)

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated