EC6703 -Embedded Real Time Systems

Dr.D.Rukmanidevi
Professor
R.M.D. Engineering College

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 Today’s Lecture

 What is the embedded system?

An embedded system is one that has
computer-hardware with software
embedded in it as one of its most important
component.
An embedded system has three main components
Hardware ,Application software and RTOS

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Block diagram of Embedded System

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COMPLEX SYSTEMS AND
MICROPROCESSORS

 Embedding Computers
 Characteristics of Embedded
Computing Applications
 Why use microprocessors?
 Challenges in Embedded Computing
System Design
 Performance in Embedded Computing

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 Embedding Computers
Medical
Automotive

 Embedded Systems are

Communications
Military
everywhere
 Ubiquitous, invisible
 Hidden (computer inside)
 Dedicated purpose
 MicroProcessor
Industrial
Comsumer
 Intel: 4004, ..8080,.. x86
 Freescale: 6800, .. 9S12,..
PowerPC
Embedded system  ARM, DEC, SPARC, MIPS,
PowerPC, Natl. Semi.,…
Microcontroller LM3S or TM4C Electrical,
Processor
mechanical,  MicroController
chemical,
I/O Ports or  Processor+Memory+
RAM optical I/O Ports (Interfaces)
devices
ROM DAC Analog
Bus ADC signals

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Early History
 Late 1940’s: MIT Whirlwind computer was designed for real-
time operations.
 Originally designed to control an aircraft simulator.
 First microprocessor was Intel 4004 in early 1970’s.
 HP-35 calculator used several chips to implement a
microprocessor in 1972.
 Automobiles used microprocessor-based engine controllers
starting in 1970’s.
 Control fuel/air mixture, engine timing, etc.
 Provides lower emissions, better fuel efficiency.

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A Short List of Embedded Systems

Anti-lock brakes Modems

Auto-focus cameras MPEG decoders
Automatic teller machines Network cards
Automatic toll systems Network switches/routers
Automatic transmission On-board navigation
Avionic systems Pagers
Battery chargers Photocopiers
Camcorders Point-of-sale systems
Cell phones Portable video games
Cell-phone base stations Printers
Cordless phones Satellite phones
Cruise control Scanners
Curbside check-in systems Smart ovens/dishwashers
Digital cameras Speech recognizers
Disk drives Stereo systems
Electronic card readers Teleconferencing systems
Electronic instruments Televisions
Electronic toys/games Temperature controllers
Factory control Theft tracking systems
Fax machines TV set-top boxes
Fingerprint identifiers VCR’s, DVD players
Home security systems Video game consoles
Life-support systems Video phones
Medical testing systems Washers and dryers

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An Application Example: Digital Camera

Digital Camera Block Diagram

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 Components of Embedded Systems
Memory Controllers Interface

Software
(Application Programs)

Processor
Coprocessors

ASIC

Converters

Analog Digital Analog

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Components of Embedded Systems
 Analog Components
 Sensors, Actuators, Controllers, …
 Digital Components
 Processor, Coprocessors
 Memories
 Controllers, Buses
 Application Specific Integrated Circuits (ASIC)
 Converters – A2D, D2A, …
 Software
 Application Programs
 Exception Handlers

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Automotive Embedded Systems
 Today’s high-end automobile may have 100
microprocessors:
 4-bit microcontroller checks seat belt;
 microcontrollers run dashboard devices;
 16/32-bit microprocessor controls engine.
 Customer’s requirements
 Reduced cost
 Increased functionality
 Improved performance
 Increased overall dependability

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An Engineering View

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BMW 850i Brake and Stability Control
System
 An antilock brake system (ABS) reduces skidding by
pumping the brakes.
 An automatic stability control Plus Traction (ASC + T)
system intervenes with the engine during drive to
improve the car’s stability
 the ASC + T is integrated with the ABS functions.
There is a single electronic control unit (with more
processing power than an ABS-only unit), and the
same four spinning toothed rings with magnetic
pickups to determine individual wheel speeds.

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 BMW 850i Brake and Stability Control
System
 The purpose of an ABS is to temporarily release the brake on a wheel when it
rotates too slowly—when a wheel stops turning, the car starts skidding and
becomes hard to control. It sits between the hydraulic pump, which provides
power to the brakes, and the brakes themselves as seen in the diagram. This
hookup allows the ABS system to modulate the brakes in order to keep the
wheels from locking. The ABS system uses sensors on each wheel to measure
the speed of the wheel. The wheel speeds are used by the ABS system to
determine how to vary the hydraulic fluid pressure to prevent the wheels from
skidding.
 The hydraulic control unit has four channels. The ABS-only unit has three
channels, only one for both rear wheels. Separate rear channels are required
for individual control of rear wheel spin. (ASC + T system has even better
braking performance).
 ABS has to control the braking force at all four wheels. ASC + T has to control
the power delivery of the engine, and the way the rear differential distributes
torque between the two back wheels.

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BMW 850i Brake and Stability Control
System
 The ASC + T control unit has a high-speed (CAN) data link to the main
engine control unit, and has control of a throttle actuator motor. This
allows it to reduce engine power.
 There is a dashboard switch that allows the ASC + T to be disabled (but
the ABS functions remain active).
 The ASC + T system determines that a wheel is spinning by comparing
the rear wheels' speed to the front. Also, there is probably a maximum
wheel acceleration threshold built into the system.
 The ASC + T system intervenes in two stages: When it detects one rear
wheel near the threshold of adhesion, it starts to rapid pulse the brake to
that wheel (just like ABS). When the second rear wheel nears the limit of
adhesion, engine power is reduced.
 The first stage (single wheel braking) actually improves vehicle
performance. The second stage is reducing engine power.

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BMW 850i, cont’d.

sensor sensor

brake brake

hydraulic
ABS
pump

brake brake

sensor sensor

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Characteristics of Embedded Systems
 Very high performance, sophisticated functionality
 Vision + compression + speech + networking all on the same
platform.
 Complex Algorithms
 User Interfaces
 Multiple task, heterogeneous.
 Real-time.
 Often low power.
 Low manufacturing cost..
 Highly reliable.
 I reboot my piano every 4 months, my PC every day.
 Designed to tight deadlines by small teams.
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Why Use Microprocessors?
 Alternatives: field-programmable gate arrays
(FPGAs), custom logic, application specific
integrated circuit (ASIC), etc.
 Microprocessors are often very efficient: can use
same logic to perform many different functions.
 Microprocessors simplify the design of families of
products.

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Why Use Microprocessors?
 Two factors that work together to make
microprocessor-based designs fast
 First, microprocessors execute programs very
efficiently. While there is overhead that must
be paid for interpreting instructions, it can often
be hidden by clever utilization of parallelism
within the CPU
 Second, microprocessor manufacturers spend
a great deal of money to make their CPUs run
very fast.

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Why Use Microprocessors?
 Performance
 Microprocessors use much more logic to implement a
function than does custom logic.
 But microprocessors are often at least as fast:
 heavily pipelined;
 large design teams;
 aggressive VLSI technology.
 Power consumption
 Custom logic is a clear winner for low power devices.
 Modern microprocessors offer features to help control power
consumption.
 Software design techniques can help reduce power
consumption.
 Heterogeneous systems: some custom logic for well-defined
functions, CPUs+ software for everything else.

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Microprocessor Varieties
 Microcontroller: includes I/O devices, on-board
memory.
 Digital signal processor (DSP): microprocessor
optimized for digital signal processing.
 Typical embedded word sizes: 8-bit, 16-bit, 32-bit.

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Microprocessor Varieties
 4-bit, 8-bit, 16-bit, 32-bit :
 8-bit processor : more than 3 billion new chips per year
 32-bit microprocessors : PowerPC, 68k, MIPS, and
ARM chips.
 ARM-based chips alone do about triple the volume that
Intel and AMD peddle to PC makers.
 Most (98% or so) 32-bit processors are used in
embedded systems, not PCs.
 RISC-type processor owns most of the overall
embedded market [MPF: 2002].

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Platforms
 Embedded computing platform: hardware
architecture + associated software.
 Many platforms are multiprocessors.
 Examples:
 Single-chip multiprocessors for cell phone baseband.
 Automotive network + processors.

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The physics of software
 Computing is a physical act.
 Software doesn’t do anything without hardware.
 Executing software consumes energy, requires
time.
 To understand the dynamics of software (time,
energy), we need to characterize the platform on
which the software runs.

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Challenges in Embedded Computing System Design

 How much hardware do we need?

How big is the CPU? Memory?
more hardware - capabilities -more money

 How do we meet deadlines?

Faster hardware or cleverer software

 How do we minimize power consumption?

Turn off unnecessary logic
Reduce memory accesses
Run at slower clock rate

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Challenges in Embedded Computing
System Design
 Does it really work?
Is the specification correct?
Does the implementation meet the specification?
How do we test for real-time characteristics?
How do we test on real data?

 How do we work on the system?

Observability and controllability
What is our development platform?

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What does “Performance” mean?
 In general-purpose computing, performance often
means average-case, may not be well-defined.
 In real-time systems, performance means
meeting deadlines.
 Missing the deadline by even a little is bad.
 Finishing ahead of the deadline may not help.

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Characterizing performance
 We need to analyze the system at several levels
of abstraction to understand performance:
 CPU: microprocessor architecture.
 Platform: bus, I/O devices.
 Program: implementation, structure.
 Task: multitasking, interaction between tasks.
 Multiprocessor: interaction between processors.

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Design methodologies
 A procedure for designing a system.
 Understanding your methodology helps you
ensure you didn’t skip anything.
 Compilers, software engineering tools, computer-
aided design (CAD) tools, etc., can be used to:
 help automate methodology steps;
 keep track of the methodology itself.

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Design goals

 Performance.
 Overall speed, deadlines.
 Functionality and user interface.
 Manufacturing cost.
 Power consumption.
 Other requirements (physical size, etc.)

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Levels of abstraction

requirements

specification

architecture

component
design
system
integration
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Top-down vs. bottom-up
 Top-down design:
 start from most abstract description;
 work to most detailed.
 Bottom-up design:
 work from small components to big system.
 Real design uses both techniques.

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Stepwise refinement

 At each level of abstraction, we must:

 analyze the design to determine characteristics
of the current state of the design;
 refine the design to add detail.

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Requirements

 Plain language description of what the user

wants and expects to get.
 May be developed in several ways:
 talking directly to customers;
 talking to marketing representatives;
 providing prototypes to users for comment.

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Functional vs. non-functional requirements

 Functional requirements:
 output as a function of input.
 Non-functional requirements:
 time required to compute output;
 size, weight, etc.;
 power consumption;
 reliability;
 Performance -Speed
 Cost – Manufacturing Cost and Nonrecurring
Engineering Cost
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Our requirements form
name
purpose
inputs
outputs
functions
performance
manufacturing cost
power
physical size/weight

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Example: GPS moving map requirements

 Moving map
obtains position
from GPS, paints I-78
map from local

Scotch Road
database.

lat: 40 13 lon: 32 19
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GPS moving map needs
 Functionality: For automotive use. Show major
roads and landmarks.
 User interface: At least 400 x 600 pixel screen.
Three buttons max. Pop-up menu.
 Performance: Map should scroll smoothly. No
more than 1 sec power-up. Lock onto GPS within
15 seconds.
 Cost: $120 street price = approx. $30 cost of
goods sold.

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GPS moving map needs, cont’d.

 Physical size/weight: Should fit in hand.

 Power consumption: Should run for 8 hours
on four AA batteries.

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GPS moving map requirements form

name GPS moving map

purpose consumer-grade
moving map for driving
inputs power button, two
control buttons
outputs back-lit LCD 400 X 600
functions 5-receiver GPS; three
resolutions; displays
current lat/lon
performance updates screen within
0.25 sec of movement
manufacturing cost $100 cost-of-goods-
sold
power 100 mW
physical size/weight no more than 2: X 6:,
12 oz.

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Specification

 A more precise description of the system:

 should not imply a particular architecture;
 provides input to the architecture design
process.
 May include functional and non-functional
elements.
 May be executable or may be in
mathematical form for proofs.

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GPS specification

 Should include:
 What is received from GPS;
 map data;
 user interface;
 operations required to satisfy user requests;
 background operations needed to keep the
system running.

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Architecture design

 What major components go satisfying the

specification?
 Hardware components:
 CPUs, peripherals, etc.
 Software components:
 major programs and their operations.
 Must take into account functional and non-
functional specifications.

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GPS moving map block diagram

GPS search display

renderer
receiver engine

user
database interface

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GPS moving map hardware
architecture

display frame CPU

buffer
GPS
receiver

memory
panel I/O

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GPS moving map software architecture

position database pixels

renderer
search

user
timer
interface

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Designing hardware and software components

 Must spend time architecting the system before

you start coding.
 Some components are ready-made, some can
be modified from existing designs, others must be
designed from scratch.

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System integration
 Put together the components.
 Many bugs appear only at this stage.
 Have a plan for integrating components to
uncover bugs quickly, test as much functionality
as early as possible.

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Summary

 Embedded computers are all around us.

 Many systems have complex embedded
hardware and software.
 Embedded systems pose many design
challenges: design time, deadlines, power,
etc.
 Design methodologies help us manage the
design process.

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EC6703 -Embedded Real Time Systems

Dr.D.Rukmanidevi
Professor
R.M.D. Engineering College

8/6/2019
 ARM 7 PROCESSOR
 Processor and Memory Organization
 ARM processor was designed by Advanced RISC Machine (ARM) Limited Company.
ARM processors are used for low-power and low cost applications like Mobile
phones, Communication modems, Automotive engine management systems and
Hand-held digital systems. There are different versions of the ARM architecture are
identified by different numbers. ARM7 is a von Neumann architecture machine, while
ARM9 uses Harvard architecture.
 The ARM architecture supports
 Memory is byte addressable
 32-bit addresses
 32-bit processor registers
 Two operand lengths are used in moving data between the memory and the
processor registers
 Bytes (8 bits) and words (32 bits)
 Word addresses must be aligned, i.e., they must be multiple of 4
 Both little-endian and big-endian memory addressing
 When a byte is loaded from memory into a processor register or stored from a
register into the memory always located in the low-order byte position of the register

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ARM Features
 Capable of executing Thumb instruction set
 Featuring with IEEE Std. 1149.1 JTAG boundary-scan debugging
interface.
 Featuring with a Multiplier-And-Accumulate (MAC) unit for DSP
applications.
 Featuring with the support of embedded In-Circuit Emulator.
 Three Pipe Stages: Instruction fetch, decode, and Execution.
 7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
 Simple structure -> reasonably good speed / Low power consumption
 High density Code and Smaller die Size

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ARM Pins
ALE –Address Latch Enable DBGACK -Debug acknowledge
ABORT –Memory Abort
DBGEN -Debug enable
APE-Address pipeline enable
ABE-Address bus enable DBGRQ-Debug request
BIGEND -Big endian configuration DBGRQI -Internal debug request
BL[3:0] -Byte latch control
BREAKPT Breakpoint ECLK -External clock output
HIGHZ-High impedance
BUSDIS Bus disable
ISYNC -Synchronous interrupts
BUSEN Data bus configuration MCLK-Memory clock input
CPA -Coprocessor absent MAS –Memory Access size
CPB -Coprocessor busy
DBE -Data bus enable

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Byte organizations within
an ARM word

Bit 31 Bit 0

Word 4

Byte 3 Byte 2 Byte 1 Byte 0 Word 0

Little-endian

Bit 31 Bit 0

Word 4

Byte 0 Byte 1 Byte 2 Byte 3 Word 0

Big-endian
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ARM Registers

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ARM Encoding Format

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ARM assembly language

Fairly standard assembly language:

LDR r0,[r8] ; a comment

label ADD r4,r0,r1

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ARM data instructions

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Example
 ADD R0,R1,R2 ---- add [R1]+[R2] and store results into R0.
 ADD R0,R1,#2 ----- immediate operands, add [ R1]+ 2 and store
results into R0.
 RSB R0, R1,R2 ----- subtract[ R2]-[R1] and store results into R0.
 ADD R0, R1, R5, LSL #4 ---- R5 is shifted left 4-bit positions (equivalent to
[R5]x16), and it is then added to the contents of R1; the sum is placed in
R0

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ARM comparison
instructions

CMP : compare
CMN : negated compare
TST : bit-wise test
TEQ : bit-wise negated test
These instructions set only the NZCV bits
of CPSR.

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Example

CMP R0, R1 --- computes R0 – R1, sets

the status bits
CMN R0,R1 ----- computes R0+R1 set the
status bits.(reverse process of CMP)
TST performs a bit-wise AND on the
operands
TEQ performs an exclusive-or.

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ARM move instructions

Example

 MOV R0, R1 ------ move the content of R0 into the R1

(R0 -- R1)
 MVN instruction complements the operand bits (one’s
complement) during the move.
 MVN R0,R1 -----move one’s complement of R0 content
into the R1 (one’s complement of R0 -- R1)

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ARM load/store
instructions

LDR, LDRH, LDRB : load (half-word, byte)

STR, STRH, STRB : store (half-word,
byte)
Examples:
register indirect : LDR r0,[r1] r1 contains 0x100 , the
content of 0x100 is loaded into the register r0
with second register : LDR r0,[r1,-r2]
with constant : LDR r0,[r1,#4]

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ARM ADR pseudo-op

Cannot refer to an address directly in an

instruction.
Generate value by performing arithmetic
on PC.
ADR pseudo-op generates instruction
required to calculate address:
ADR r1,FOO

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Example: C assignments

C:
x = (a + b) - c;

Assembler:
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
ADR r4,b ; get address for b, reusing r4
LDR r1,[r4] ; get value of b
ADD r3,r0,r1 ; compute a+b
ADR r4,c ; get address for c
LDR r2[r4] ; get value of c

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C assignment, cont’d.
SUB r3,r3,r2 ; complete computation of x
ADR r4,x ; get address for x
STR r3[r4] ; store value of x

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Example: C assignment

C:
y = a*(b+c);

Assembler:
ADR r4,b ; get address for b
LDR r0,[r4] ; get value of b
ADR r4,c ; get address for c
LDR r1,[r4] ; get value of c
ADD r2,r0,r1 ; compute partial result
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a

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C assignment, cont’d.
MUL r2,r2,r0 ; compute final value for y
ADR r4,y ; get address for y
STR r2,[r4] ; store y

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Example: C assignment

C:
z = (a << 2) | (b & 15);

Assembler:
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
MOV r0,r0,LSL 2 ; perform shift
ADR r4,b ; get address for b
LDR r1,[r4] ; get value of b
AND r1,r1,#15 ; perform AND
ORR r1,r0,r1 ; perform OR

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C assignment, cont’d.
ADR r4,z ; get address for z
STR r1,[r4] ; store value for z

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Additional addressing
modes

Base-plus-offset addressing:
LDR r0,[r1,#16]
Loads from location r1+16
Auto-indexing increments base register:
LDR r0,[r1,#16]!
Post-indexing fetches, then does offset:
LDR r0,[r1],#16
Loads r0 from r1, then adds 16 to r1.
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ARM flow of control

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ARM flow of control

All operations can be performed

conditionally, testing CPSR:
EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE,
LT, GT, LE
Branch operation:
B #100
Can be performed conditionally.

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Example: if statement

C:
if (a > b) { x = 5; y = c + d; } else x = c - d;

Assembler:
; compute and test condition
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
ADR r4,b ; get address for b
LDR r1,[r4] ; get value for b
CMP r0,r1 ; compare a < b
BGE fblock ; if a >= b, branch to false block

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If statement, cont’d.
; true block
MOV r0,#5 ; generate value for x
ADR r4,x ; get address for x
STR r0,[r4] ; store x
ADR r4,c ; get address for c
LDR r0,[r4] ; get value of c
ADR r4,d ; get address for d
LDR r1,[r4] ; get value of d
ADD r0,r0,r1 ; compute y
ADR r4,y ; get address for y
STR r0,[r4] ; store y
B after ; branch around false block
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If statement, cont’d.
; false block
fblock ADR r4,c ; get address for c
LDR r0,[r4] ; get value of c
ADR r4,d ; get address for d
LDR r1,[r4] ; get value for d
SUB r0,r0,r1 ; compute a-b
ADR r4,x ; get address for x
STR r0,[r4] ; store value of x
after ...

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Example: Conditional
instruction implementation
; true block
MOVLT r0,#5 ; generate value for x
ADRLT r4,x ; get address for x
STRLT r0,[r4] ; store x
ADRLT r4,c ; get address for c
LDRLT r0,[r4] ; get value of c
ADRLT r4,d ; get address for d
LDRLT r1,[r4] ; get value of d
ADDLT r0,r0,r1 ; compute y
ADRLT r4,y ; get address for y
STRLT r0,[r4] ; store y

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Example: switch
statement

C:
switch (test) { case 0: … break; case 1: … }

Assembler:
ADR r2,test ; get address for test
LDR r0,[r2] ; load value for test
ADR r1,switchtab ; load address for switch table
LDR r1,[r1,r0,LSL #2] ; index switch table
switchtab DCD case0
DCD case1
...

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Example: FIR filter

C:
for (i=0, f=0; i<N; i++)
f = f + c[i]*x[i];

Assembler
; loop initiation code
MOV r0,#0 ; use r0 for I
MOV r8,#0 ; use separate index for arrays
ADR r2,N ; get address for N
LDR r1,[r2] ; get value of N
MOV r2,#0 ; use r2 for f

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FIR filter, cont’.d
ADR r3,c ; load r3 with base of c
ADR r5,x ; load r5 with base of x
; loop body
loop LDR r4,[r3,r8] ; get c[i]
LDR r6,[r5,r8] ; get x[i]
MUL r4,r4,r6 ; compute c[i]*x[i]
ADD r2,r2,r4 ; add into running sum
ADD r8,r8,#4 ; add one word offset to array index
ADD r0,r0,#1 ; add 1 to i
CMP r0,r1 ; exit?
BLT loop ; if i < N, continue

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ARM subroutine linkage

Branch and link instruction:

BL foo
Copies current PC to r14.
To return from subroutine:
MOV r15,r14

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Nested subroutine calls

Nesting/recursion requires coding

convention:
f1 LDR r0,[r13] ; load arg into r0 from stack
; call f2()
STR r13!,[r14] ; store f1’s return adrs
STR r13!,[r0] ; store arg to f2 on stack
BL f2 ; branch and link to f2
; return from f1()
SUB r13,#4 ; pop f2’s arg off stack
LDR r13!,r15 ; restore register and return

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Summary

Load/store architecture
Most instructions are RISCy, operate in
single cycle.
Some multi-register operations take longer.
All instructions can be executed
conditionally.

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