APL1581

DUAL INPUT LOW DROPOUT REGULATOR

Features General Description

• Adjustable or Fixed Output The APL1581 series of high performance positive volt-
• 520mV typ. Dropout at 5A in Dual Power age regulators are designed for use in applications re-
Voltage Mode quiring very low dropout voltage at 5Amp.
• Remote Sense Pin Available
The APL1581 can provide a output voltage at the range of
• 2% Accuracy Over Temperature Range
1.25V to 2.55V where both 5V and 3.3V voltage supplies
• Build-in Over Temperature Protection
are available.
• Build-in Current Limit
The superior dropout characteristics result in reducing
• 5 Pin TO-220 and TO-263, TO-252, SOP-8-P
heat dissipation compared to regular LDOs. The APL1581
Packages
also provides excellent regulation over line, load, and tem-
• Lead Free and Green Devices Available
perature variations.
(RoHS Compliant)
Current limit is trimmed to ensure specified output cur-
rent and controlled short-circuit current. On-chip thermal
Applications limiting provides protection against any combina-
tion of overload that would create excessive junction
• Microprocessor Supplies temperature.
• Chip Set Supplies The APL1581 is available in both the through-hole and
• VGA Card Power surface mount versions of the industry standard 5-Pin
• LCD Monitor Power TO-220 and TO-263, TO-252, SOP-8P power packages.

Ordering and Marking Information

APL1581 Package Code
F : TO-220-5 G : TO-263-5 U :TO-252-5
KA : SOP-8P
Assembly Material Temperature Range
C : 0 to 70° C
Handling Code
Handling Code
TR : Tape & Reel
Temperature Range
Voltage Code :
Package Code 15 : 1.5V 18 : 1.8V
25 : 2.5V Blank : Adjustable Version
Voltage Code Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device

15
APL1581-15 F/G/U : APL1581 XXXXX - Date Code APL1581 KA : APL1581 XXXXX - Date Code
XXXXX XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. B.5 - Mar., 2008
APL1581

Pin Configuration

5 VIN
5 VIN
4 VCNTL
4 VCNTL
TAB is VOUT 3 VOUT
TAB is VOUT 3 VOUT
2 ADJ (or GND) 2 ADJ(or GND)
1 VSENSE 1 VSENSE

Front View of TO-220-5 Front View of TO-252-5

5 VIN
VSENSE 1 8 VOUT

4
ADJ (or GND) 2 7 VOUT
VCNTL
TAB is VOUT
VCNTL 3 6 VOUT
3 VOUT
VIN 4 5 VOUT
2 ADJ (or GND)

1 VSENSE SOP-8-P (Top View)

NC = No internal connection
Front View of TO-263-5 = Thermal Pad
(connected to VOUT plane for better heat
dissipation)
Pin 5~8 must be connected together by a shortest
wide track or plane.

Pin Description

PIN
Description
Name I/O

Positive side of the reference voltage, which allows remote sensing to

VSENSE I
obtain excellent load regulation.

Negative side of the reference voltage, which allows to use resistor divider
ADJ O to set an expect output voltage. A small bypass capacitor can be connected
from this pin to ground to improve PSRR performance.

For fixed voltage devices this is the bottom of the resistor divider that sets
GND O
the output voltage.

Output pin of the regulator, which connects to the TAB. A minimum of 10µF
VOUT O
capacitor must be connected from this pin to ground to ensure the stability.

Supply pin of the control circuitry, which must be always higher than VOUT
VCNTL I
for the device to regulate. (See electrical characteristics)

Power input pin of the regulator, which must be always higher than VOUT for
VIN I
the device to regulate. (See electrical characteristics)

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Rev. B.5 - Mar., 2008
APL1581

Block Diagram
VIN VOUT

VCNTL

Current
VSENSE
Limit

Thermal Voltage
Protection Regulation ADJ/GND

Absolute Maximum Ratings (Note 1, 2)

Symbol Parameter Rating Unit
VIN Input Voltage 7 V
VCNTL Control Voltage 7 V

PD Power Dissipation Internally Limited W

TJ Junction Temperature 150 °C

TSTG Storage Temperature Range -65 to +150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: The maximum allowable power dissipation at any TA (ambient temperature) is calculated using: PD
(max) = (TJ – TA) / θJA; TJ = 125°C. Exceeding the maximum allowable power dissipation will result in
excessive die temperature.

Thermal Characteristics
Symbol Parameter Typical Value Unit

(Note 3)
Junction-to-Ambient Resistance in free air
TO-263-5 (Toplayer plane size : 15mm x 15 mm) 28 o
θJA C/W
TO-252-5 (Toplayer plane size : 10mm x 10 mm) 42
SOP-8-P (Toplayer plane size : 10mm x 10 mm) 68
(Note 4)
Junction-to-Case Resistance
TO-220-5 3 o
θJC C/W
TO-263-5 4
TO-252-5 5
Note 3: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The sizes of the
rectangular plane, where the devices are mounted, are shown in the table.
Note 4: The case temperature is measured on the TAB of the device mounted on the test board described in Note 3 except the
package TO-220-5. The case temperature of the TO-220-5 is measured on the bottom of the case directly below the die.

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Rev. B.5 - Mar., 2008
APL1581

Electrical Characteristics
Unless otherwise noted , these specifications apply over CIN = 10µF, CCNTL = 1µF, COUT = 10µF, and TA = 0 to 70°C.
Typical values refer to TA = 25°C. VOUT = VSENSE.
APL1581
Symbol Parameter Test Conditions UNIT
MIN TYP MAX
Reference Voltage VCNTL=2.75~5.5V, VIN=2.05~5.5V,
VREF 1.225 1.250 1.275 V
APL1581 IO =10mA~5A, VADJ=0V
Output Voltage (IO =0~5A for fixed versions)
1.470 1.500 1.530
APL1581-15 VCNTL=3~5.5V , VIN=2.3~5.5V
VOUT 1.764 1.800 1.836 V
APL1581-18 VCNTL=3.3~5.5V , VIN=2.6~5.5V 2.450 2.500 2.550
APL1581-25 VCNTL=4~5.5V , VIN=3.3~5.5V
Line Regulation (IO =0A for fixed versions)
APL1581 VCNTL=2.75~5.5V, VIN=1.75~5.5V,
IO =10mA, VADJ=0V
REGLINE 3 mV
APL1581-15 VCNTL=3~5.5V, VIN=2.3~5.5V
APL1581-18 VCNTL=3.3~5.5V, VIN=2.6~5.5V
APL1581-25 VCNTL=4~5.5V, VIN=3~5.5V
Load Regulation (Note 5) (IO =0~5A for fixed versions)
APL1581 VCNTL=2.75V, VIN=2.1V, VADJ =0V,
IO =10mA~5A
REGLOAD 5 mV
APL1581-15 VCNTL=3V, VIN=2.35V
APL1581-18 VCNTL=3.3V, VIN=2.65V
APL1581-25 VCNTL=4V, VIN=3.35V
Dropout Voltage (Note 6) IO =5A for all versions
APL1581 VIN=2.05V, VADJ =0V
VCNTL-VOUT APL1581-15 VIN=2.3V 1.20 1.35 V
APL1581-18 VIN=2.6V
APL1581-25 VIN=3.3V
Dropout Voltage (Note 6) IO =5A for all versions
APL1581 VCNTL=2.75V, VADJ =0V
VIN-VOUT APL1581-15 VCNTL=3V 0.52 0.75 V
APL1581-18 VCNTL=3.3V
APL1581-25 VCNTL=4V
ILIMIT Current Limit VCNTL-VOUT=1.5V, VIN-VOUT=0.6V 5 A
Minimum Load Current
(Note7)
ILMIN VCNTL=5V, VIN=3.3V, VADJ =0V 0.8 10 mA
APL1581
REGTHERMAL Thermal Regulation 30ms Pulse 0.01 %/W
Power Supply Ripple VRIPPLE=1VPP at 120Hz, IO=5A
Rejection
APL1581 VCNTL=5V, VIN=5V, VADJ =0V
PSRR 60 70 dB
APL1581-15 VCNTL=5.25V, VIN=5.25V
APL1581-18 VCNTL=5.55V, VIN=5.55V
APL1581-25 VCNTL=6.25V, VIN=6.25V
VCNTL-VOUT=1.5V, VIN-VOUT=0.8V,
ICNTL CNTL Pin Current 45 120 mA
IO =5A
Ground Pin Current
APL1581-15 VCNTL =3V, VIN =2.3V
IGND 8 13 mA
APL1581-18 VCNTL =3.3V, VIN =2.6V
APL1581-25 VCNTL =4V, VIN =3.3V
Adjust Pin Current
IADJ 50 120 µA
APL1581 VCNTL=2.75V, VIN=2.05V , VADJ =0V
Note 5 : Low duty cycle pulse test with Kelvin connections are required to maintain data accuracy .
Note 6 : Dropout voltage is defined as the minimum difference between VIN and VOUT required to maintain 1% VOUT
regulation.
Note 7 : Minimum load current is defined as the minimum current required at the output to maintain VOUT regulation.

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Rev. B.5 - Mar., 2008
APL1581

Application Circuit

(1) Adjustable Output Voltage Device

VIN VIN VOUT VOUT
+3.3V APL1581 +2.5V/5A
(Adj.)
VCNT L VCNTL VSENSE
+5V ADJ R1
V REF 120
CCNTL CIN COUT
10uF 100uF 470uF
R2
120

GND GND
* VOUT = VREF ( 1+ R2 / R1 ) + IADJ * R2
where VREF =1.25V (typical)
IADJ=50µA (typical)
* R1 is typically in range of 100Ω to 125Ω to satisfy the minimum load current requirement.

(2) Fixed Output Voltage Device

V IN VIN VOUT V OUT

+3.3V +2.5V/5A
APL1581-25

V CNT L VCNTL VSENSE

+5V GND

CCNTL CIN COUT

10uF 100uF 470uF

GND GND

(3) With Enable Control Application

VIN VIN VOUT VOUT

+3.3V APL1581 +2.5V/5A
(Adj.)
Q1
VCNT L VCNTL VSENSE
10k R1
+5V ADJ
V REF 120
CCNTL CIN COUT
Q2
Enable 10uF 100uF 470uF
R2
10k 120

GND GND
Q1 : APM2301A
Q2 : APM2300A

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Rev. B.5 - Mar., 2008
APL1581

Typical Characteristics

Reference Voltage vs. Junction Temperature Adjust Pin Current vs. Junction Temperature
1.275 80

1.270 70

Adjust Pin Current (uA)

1.265
Reference Voltage (V)

60
1.260
50
1.255

1.250 40
1.245 30
1.240
20
1.235
10
1.230

1.225 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150

Junction Temperature (°C) Junction Temperature (°C)

Minimum Load Current vs. Junction Temperature VIN-VOUT Dropout Voltage vs. Output Current
1.2 700
VIN-VOUT Dropout Voltage (mV)

TJ=125°C
Minimum Load Current (mA)

600
1.0
VCNTL-VOUT=10.75V
500
0.8
TJ=25°C
VCNTL-VOUT=1.45V 400
0.6
300
TJ=-50°C
0.4
200

0.2
100

0.0 0
-50 -25 0 25 50 75 100 125 150 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Junction Temperature (°C) Output Current (A)

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Rev. B.5 - Mar., 2008
APL1581

Typical Characteristics

Short-Circuit Current vs. Junction Temperature VCONTROL-VOUT Dropout Voltage vs. Output Current
14 1.4

VCNTL-VOUT Dropout Voltaage (V)

TJ=-50°C
VIN=5.0V
12 1.3 TJ=0°C
Short-Circuit Current (A)

10 1.2

VIN=3.3V
8 1.1

6 1.0 TJ=25°C

4 0.9
TJ=125°C
2 0.8

0 0.7
-50 -25 0 25 50 75 100 125 150 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Junction Temperature (°C) Output Current (A)

Control Pin Current vs. Output Current Control Pin Current vs. Output Current
VIN-VOUT=0.6V VIN-VOUT=0.8V
160 80

TJ=125°C TJ=-50°C
140 70
VCNTL Pin Current (mA)
VCNTL Pin Current (mA)

120 60
TJ=0°C

TJ=25°C
100 50
TJ=25°C
80 TJ=75°C
40

60 30
TJ=0°C
40 TJ=-50°C 20 TJ=125°C

20 TJ=75°C 10

0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Output Current (A) Output Current (A)

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Rev. B.5 - Mar., 2008
APL1581

Typical Characteristics

Control Pin Current vs. Output Current Control Pin Current vs. Output Current
VIN-VOUT=1.0V VIN-VOUT=4.25V
80 70

70
TJ=-50°C
60 TJ=-50°C

VCNTL Pin Current (mA)

VCNTL Pin Current (mA)

60 TJ=0°C
50 TJ=0°C
TJ=25°C
50 TJ=25°C
40
40 TJ=75°C TJ=75°C
30
30

20
20
TJ=125°C TJ=125°C
10 10

0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Output Current (A) Output Current (A)

Application Information

General APL1581 is available in SOP-8P, TO-252-5,

The APL1581 (adjustable or fixed) regulator is a 5 ter- TO-263-5, and TO-220-5 packages to meet different
minal device designed specifically to provide extremely power dissipation applications.
low dropout voltages comparable to the PNP type with-
Output Voltage Setting
out the disadvantage of the extra power dissipation
See Figure 1 Adjustable APL1581 develops a 1.25V
due to the base current associated with PNP regulators.
reference voltage between the VSENSE pin and the
This is done by bringing out the control pin of the regu-
ADJ pin. Placing a resistor between these two termi-
lator that provides the base current to the power NPN
nals causes a constant current to flow through R1 and
and connecting it to a voltage that is greater than the
down through R2 to set the overall output voltage. In
voltage present at the VIN pin. This flexibility makes
general, R1 is chosen so that this current is the speci-
APL1581 ideal for applications where dual inputs are
fied minimum load current of 10mA.The current out of
available, such as a computer motherboard with an
the ADJ pin is small, typically 50µA and itadds to the
ATX power supply that provides 5V and 3.3V to the
current from R1. Because IADJ is very small, it needs
board.
to be considered only when very precise output volt-
APL1581 is equipped with a 1.25V reference, preci- age setting is required. For best regulation, the top of
sion and fast voltage regulations, on-chip current and the resistor divider should be connected directly to
thermal limits, and remote sensing capability to re- the SENSE pin. The adjustable APL1581 can be pro-
duce system total cost.

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Rev. B.5 - Mar., 2008
APL1581

Application Information (Cont.)

Output Voltage Setting (Cont.) regardless of whether they are inside or outside the
grammable to any voltages in the range of 1.25V to 5.5V regulation loop.
according to the following formula:
VOUT
VIN VIN VOU T
R2 APL1581
VOUT = VREF x (1+ ) + IADJ x R2
R1 VCNTL VCN TL VSENSE
AD J Load
R1

where VREF = 1.25V (typical)

Adjustable R2
IADJ = 50µA (typical) Device

The recommended R1 is in range of 100Ω to125Ω to

RP
satisfy the minimum load current requirement. Proper
VOUT
sizes of R2 and R1 are also concerned for power VIN VIN VOU T

dissipation. APL1581
VCNTL VCN TL VSENSE
GN D Load

VIN VIN VOU T VOUT

APL1581
VCNT L VCNTL VSENSE Fixed Voltage
AD J R1
Device
VRE F RP

Figure 2 Remote Voltage Sensing

IA DJ=50uA R2

Stability and Output Capacitors

Figure 1 Setting Output Voltage The circuit design of using the APL1581 series re-
quires an output capacitor as part of the device fre-
Grounding and Output Sensing
quency compensation. The following chart shows a
The APL1581 allows true Kelvin sensing for both the stable region to select output capacitor for APL1581.
high and low side of the load. Figure 2 shows the de- This region above the curve indicates minimum re-
vice connected to take advantage of the remote sense quired ESR and capacitance to maintain stability.
feature. The SENSE pin and the top of the resistor However, the output capacitor should have an ESR
divider are connected to the top of the load; the bot- less than1Ω.
tom of the resistor divider is connected to the bottom
of the load. Typically the load is a microprocessor 100
and parasitic resistance RP is made up of the PC traces 80
ESR (mΩ)

and /or connector resistance between the regulator 60 Stable Region

and the processor. RP is now connectedinside the 40
regulation loop of the APL1581 and for reasonable val- 20
ues of RP the load regulation at the load will be 0
negligible. Voltage drops due to RP are not eliminated; 1 10 100 1000
Capacitance(µF)
they will add to the dropout voltage of the regulator

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Rev. B.5 - Mar., 2008
APL1581

Application Information (Cont.)

Stability and Output Capacitors (Cont.) exceeded under continuous normal load conditions.
A low-ESR solid tantalum and aluminum electrolytic Careful consideration must be given to all sources of
capacitor (ESR<1Ω) works extremely well and provides thermal resistance from junction to ambient, includ-
good transient response and stability over temperature. ing junction-to-case, case-to-heat sink interface, and
Ultra-low-ESR capacitors, such as ceramic chip heat sink resistance itself.
capacitors, may promote unstable or under-damped See Figure 3 The SOP-8P is a cost-effective package
transient response, but proper ceramic chip capaci- featuring a small size as a standard SOP-8 and a
tors placed near loads can be used as decoupling bottom thermal pad to minimize the thermal resistance
capacitors. of the package, being applicable to high current
The output capacitors are also used to reduce the slew applications. The thermal pad is soldered to the top
rate of load current and help the APL1581 to minimize VOUT plane which may be connected to internal or
variations of the output voltage, improving transient bottom VOUT plane by vias to reduce the heat sink
response. For this purpose, the low-ESR capacitors thermal resistance. Therefore, the printed circuit board
are recommended. (PCB) forms a heat sink and dissipates heat into am-
bient air.
Input Capacitors

The input capacitors of VCNTL and VIN pins are not

Top layer
required for stability but for supplying surge currents VOUT plane
for Heat Dissi p a t i o n
during large load transients, and this will prevent the (L a rg e r a re a i s better)

input rail from drooping and improve the performance C OUT

of the APL1581. Because parasitic inductors from volt-

age sources or other bulk capacitors to the VCNTL
and VIN pins will limit the slew rate of the surge cur-
8 7 6 5
rents during large load transients, resulting in voltage
Load
drop at VIN and VCNTL pins. Vias
Vias
A capacitor of 1µF (ceramic chip capacitor) or greater
(aluminum electrolytic capacitor) is recommended and 1 2 3 4

connected near VCNTL pin. For VIN pin, an aluminum S o l d e ri n g a re a

(1 4 0 m i l x
electrolytic capacitor (>33µF) is recommended. It is 110mil) C IN
CCNTL
for bottom p a d
not necessary to use low-ESR capacitors. More ca-
pacitance reduces the variations of the input voltage Figure 3 Recommended SOP-8P Layout
at VIN pin.

Layout and Thermal Consideration

The APL1581 series have internal power and thermal

limiting (TJ=150oC typical) circuitry designed to pro-
tect the device under overload conditions. However,
maximum junction temperature ratings should not be

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Rev. B.5 - Mar., 2008
APL1581

Package Information
TO-220-5

D
Q

R
b e
e1
E

L
H1

A c J1
F

Millimeters Inches
Dim
Min. Max. Min. Max.
A 3.55 4.83 0.140 0.190
b 0.63 1.02 0.025 0.040
c 0.35 0.56 0.014 0.022
D 14.22 16.51 0.560 0.650
e 1.57 1.83 0.062 0.072
e1 6.68 6.94 0.263 0.273
E 9.65 10.67 0.380 0.420
F 1.14 1.40 0.045 0.055
H1 5.84 6.60 0.230 0.260
J1 2.03 3.05 0.080 0.120
L 13.72 14.22 0.540 0.560
R 3.53 4.09 0.139 0.161
Q 2.54 3.43 0.100 0.135

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Rev. B.5 - Mar., 2008
APL1581

Package Information
TO-263-5
A

E c2 E1

L1

D1
D

b e c

SEE VIEW A
0

GAUGE PLANE SEATING PLANE

L
A1
0.25

VIEW A

S TO-263-5
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190

A1 0.00 0.25 0.000 0.010

b 0.51 0.99 0.020 0.039

c 0.38 0.74 0.015 0.029

c2 1.14 1.65 0.045 0.065

D 8.38 9.65 0.330 0.380

D1 6.00 9.00 0.236 0.354

E 9.65 11.43 0.380 0.450

E1 6.22 9.00 0.245 0.354

e 1.70 BSC 0.067 BSC

H 14.61 15.88 0.575 0.625

L 1.78 2.79 0.070 0.110

L1 1.68 0.066

0 0o 8o 0o 8o

Note : Follow from JEDEC TO-263 BB.

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Rev. B.5 - Mar., 2008
APL1581

Packaging Information
TO-252-5

E A
b3 c2 E1

L3

D1
D

c
b e
SEE VIEW A
0

GAUGE PLANE SEATING PLANE

L
A1
0.25

VIEW A

S TO-252-5
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 2.18 2.39 0.086 0.094
A1 0.13 0.005
b 0.50 0.89 0.020 0.035
b3 4.32 5.46 0.170 0.215
c 0.46 0.61 0.018 0.024
c2 0.46 0.89 0.018 0.035
D 5.33 6.22 0.210 0.245
D1 4.57 6.00 0.180 0.236
E 6.35 6.73 0.250 0.265
E1 3.81 6.00 0.150 0.236
e 1.27 BSC 0.050 BSC
H 9.40 10.41 0.370 0.410
L 1.40 1.78 0.055 0.070
L3 0.89 2.03 0.035 0.080
0 0° 8° 0° 8°

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Rev. B.5 - Mar., 2008
APL1581

Packaging Information
SOP-8-P
D

SEE VIEW
A
D1

E1
E2

THERMAL
PAD E

°
h X 45

e b c

0.25
A2

GAUGE PLANE
SEATING PLANE
A1

L
0
VIEW A
S SOP-8P
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.60 0.063

A1 0.00 0.15 0.000 0.006

A2 1.25 0.049
b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
D1 2.25 3.50 0.098 0.138

E 5.80 6.20 0.228 0.244

E1 3.80 4.00 0.150 0.157
E2 2.00 3.00 0.079 0.118
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050

0 0o 8o 0o 8o
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

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Rev. B.5 - Mar., 2008
APL1581

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 B A
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
381.0±2.00 60 MIN. 24.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 24.0±0.30 1.75±0.10 11.5±0.10
-0.00 -0.20
TO-263-5 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 16.0±0.10 2.0±0.10 -0.00 1.5 MIN. -0.40 10.8±0.20 16.1±0.20 5.2±0.20
Application A H T1 C d D W E1 F
330.0±2.00 50 MIN. 16.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.05
-0.00 -0.20
TO-252-5 P0 P1 P2 D0 D1 T A0 B0 K0
4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 1.5 MIN. 0.6+0.00 6.80±0.20 10.40± 2.50±0.20
-0.00 -0.40 0.20
Application A H T1 C d D W E1 F
330.0±2.00 50 MIN. 12.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
SOP-8-P P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 -0.00 1.5 MIN. -0.40 6.40±0.20 5.20±0.20 2.10±0.20

(mm)

Copyright  ANPEC Electronics Corp. 15 www.anpec.com.tw

Rev. B.5 - Mar., 2008
APL1581

Devices Per Unit

Package Type Unit Quantity

TO-252-5 Tape & Reel 2500
TO-263-5 Tape & Reel 1000
SOP-8-P Tape & Reel 2500

Reflow Condition (IR/Convection or VPR Reflow)

TP tp
Critical Zone
TL to TP
Ramp-up

TL
tL
Temperature

Tsmax

Tsmin
Ramp-down
ts
Preheat

25
t 25°C to Peak

Time

Reliability Test Program

Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw

Rev. B.5 - Mar., 2008
APL1581

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
3°C/second max. 3°C/second max.
(TL to TP)
Preheat
100°C 150°C
- Temperature Min (Tsmin)
150°C 200°C
- Temperature Max (Tsmax)
60-120 seconds 60-180 seconds
- Time (min to max) (ts)
Time maintained above:
183°C 217°C
- Temperature (TL)
60-150 seconds 60-150 seconds
- Time (tL)
Peak/Classification Temperature (Tp) See table 1 See table 2
Time within 5°C of actual
10-30 seconds 20-40 seconds
Peak Temperature (tp)
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.

Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures

3 3
Volume mm Volume mm
Package Thickness
<350 ≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C

Table 2. Pb-free Process – Package Classification Reflow Temperatures

3 3 3
Volume mm Volume mm Volume mm
Package Thickness
<350 350-2000 >2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.

Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw

Rev. B.5 - Mar., 2008