RT9173B

2A Bus Termination Regulator

General Description Features
The RT9173B regulator is designed to convert voltage z Support Both DDR I (1.25VTT) and DDR II (0.9VTT)
supplies ranging from 1.7V to 6V into a desired output Requirements
voltage of which adjusted by two external voltage divider z SOP-8 and TO-252-5 Packages
resistors. The regulator is capable of sourcing or sinking z Capable of Sourcing and Sinking Current
up to 2A of current while regulating an output voltage to z Current-limiting Protection
within 40mV. z Thermal Protection
The RT9173B, used in conjunction with series termination z Integrated Power MOSFETs
resistors, provides an excellent voltage source for active z Generates Termination Voltages for SSTL-2
termination schemes of high speed transmission lines as z High Accuracy Output Voltage at Full-Load
those seen in high speed memory buses and distributed z Adjustable VOUT by External Resistors
backplane designs. The voltage output of the regulator can z Minimum External Components
be used as a termination voltage for DDR SDRAM. z Shutdown for Standby or Suspend Mode Operation
with High-impedance Output
Current limits in both sourcing and sinking mode, plus on-
z RoHS Compliant and 100% Lead (Pb)-Free
chip thermal shutdown make the circuit tolerant of the
output fault conditions.
Applications
The RT9173B are available in the popular 5-lead TO-252
z DDR Memory Termination Supply
and fused SOP-8 (the multiple VCNTL pins on the SOP-8
z Active Termination Buses
package are internally connected but lowest thermal
z Desktop PC/AGP Graphics
resistance) surface mount packages.
z Set Top Box/IPC
z Supply Splitter
Ordering Information
RT9173B Pin Configurations
Package Type (TOP VIEW)
S : SOP-8
L5 : TO-252-5 VIN 8 VCNTL
Operating Temperature Range GND 2 7 VCNTL
P : Pb Free with Commercial Standard REFEN 3 6 VCNTL
G : Green (Halogen Free with Commer- VOUT 4 5 VCNTL
cial Standard)

Note : SOP-8
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require- 5 VOUT
4 REFEN
ments of IPC/JEDEC J-STD-020.
3 VCNTL (TAB)
`Suitable for use in SnPb or Pb-free soldering processes. 2 GND
`100%matte tin (Sn) plating. 1 VIN

TO-252-5

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RT9173B
Typical Application Circuit
VCNTL = 3.3V
VIN = 2.5V
CCNTL RTT

R1 VCNTL CIN
VIN
RT9173B
REFEN VOUT
2N7002
EN R2 GND
COUT
RDUMMY

R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω

COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing condition
RDUMMY = 1kΩ as for VOUT discharge when VIN is not present but VCNTL is present
CIN = 470μF (Low ESR), CCNTL = 47μF

Test Circuit

3.3V 2.5V

VCNTL VIN
RT9173B VOUT
1.25V REFEN VOUT

GND COUT V
IL

Figure 1. Output Voltage Tolerance, ΔVOUT

3.3V A 2.5V

VCNTL VIN
RT9173B 1.25V
VOUT
1.25V REFEN VOUT
0V
GND COUT
RL V
0.2V

RL and COUT
Time deleay

Figure 2. Current in Shutdown Mode, ΙSHDN

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 RT9173B
3.3V 2.5V

VCNTL VIN
RT9173B VOUT
1.25V REFEN VOUT

GND A COUT V
IL

Figure 3. Current Limit for High Side, ΙCLHIGH

Power Supply
3.3V with Current Limit
2.5V

VCNTL VIN A
IL
RT9173B VOUT
1.25V REFEN VOUT

GND COUT V

Figure 4. Current Limit for Low Side, ΙCLLOW

3.3V 2.5V

VCNTL VIN
RT9173B VOUT
1.25V REFEN VOUT
VREFEN
0.2V GND RL COUT V
1.25V

VOUT
0V
VOUT would be low if VREFEN < 0.2V
VOUT would be high if VREFEN > 0.6V

RL and COUT
Time deleay

Figure 5. REFEN Pin Shutdown Threshold, VTRIGGER

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RT9173B
Functional Pin Description
Pin Name Pin Function
VIN Power Input
GND Ground
VCNTL Gate Drive Voltage
REFEN Reference Voltage Input and Chip Enable
VOUT Output Voltage

Function Block Diagram

VCNTL VIN

Current
Limiting Sensor

REFEN CNTL VOUT

Thermal

GND

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 RT9173B
Absolute Maximum Ratings (Note 1)
z Input Voltage ------------------------------------------------------------------------------------------------------------ 7V
z Power Dissipation, PD @ TA = 25°C
SOP-8 -------------------------------------------------------------------------------------------------------------------- 0.625W
TO-252 ------------------------------------------------------------------------------------------------------------------- 1.471W
z Package Thermal Resistance (Note 5)
SOP-8, θJA -------------------------------------------------------------------------------------------------------------- 160°C/W
SOP-8, θJC -------------------------------------------------------------------------------------------------------------- 23°C/W
TO-252, θJA ------------------------------------------------------------------------------------------------------------- 68°C/W
TO-252, θJC ------------------------------------------------------------------------------------------------------------- 8°C/W
z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C
z Junction Temperature ------------------------------------------------------------------------------------------------ 150°C
z Storage Temperature Range ---------------------------------------------------------------------------------------- –65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 3)

z Junction Temperature Range ---------------------------------------------------------------------------------------- –40°C to 125°C

Electrical Characteristics
(VIN = 2.5V, VCNTL = 3.3V, VREFEN = 1.25V, COUT = 10μF (Ceramic), TA = 25°C unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Units

Output Offset Voltage VOS IOUT = 0A, Figure 1 (Note 4) −20 0 20 mV
IL : 0A → 2A, Figure 1
Load Regulation ΔVLOAD −20 0 20 mV
IL : 0A → -2A
VIN Keep VCNTL ≥ VIN on operation power 1.7 2.5/1.8 --
Input Voltage Range (DDR I/II) V
VCNTL on and power off sequences 3 3.3/5 6
Operating Current of VCNTL ICNTL No Load -- 1 2.5 mA
Current In Shutdown Mode ISHDN VREFEN < 0.2V, RL = 180Ω, Figure 2 -- 50 90 μA
Short Circuit Protection
Current limit ILIM Figure 3,4 2.2 2.6 -- A
Over Temperature Protection
Thermal Shutdown Temperature TSD 3.3V ≤ VCNTL ≤ 5V 125 170 -- °C
Thermal Shutdown Hysteresis ΔTSD 3.3V ≤ VCNTL ≤ 5V -- 35 -- °C
Shutdown Function
Output = High, Figure 5 0.6 -- --
Shutdown Threshold Trigger V
Output = Low, Figure 5 -- -- 0.2

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RT9173B
Note 1. Stresses beyond those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended. The human body model is a 100pF capacitor discharged
through a 1.5kΩ resistor into each pin.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Note 5. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard. The case point of θJC is on the center of VCTRL pins (Lead 6 & 7) for
SOP-8 packages.

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 RT9173B
Typical Operating Characteristics
Source Current Limit vs. Temperature Source Current Limit vs. Temperature
3.8 3.8

3.4 VIN = 1.8V, VCNTL = 5V 3.4

Source current (A)

Source current (A)

VIN = 1.8V, VCNTL = 3.3V

3 3

2.6 2.6
VIN = 2.5V, VCNTL = 5V
VIN = 2.5V, VCNTL = 3.3V
2.2 2.2

1.8 1.8
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)

Sink Current Limit vs. Temperature Sink Current Limit vs. Temperature
3.8 3.8

VIN = 1.8V, VCNTL = 5V

3.4 3.4
Sink current (A)
Sink current (A)

3 3 VIN = 1.8V, VCNTL = 3.3V

VIN = 2.5V, VCNTL = 5V

2.6 2.6 VIN = 2.5V, VCNTL = 3.3V

2.2 2.2

1.8 1.8
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)

Turn-On Threshold vs. Temperature Turn-Off Threshold vs. Temperature

0.5 0.5
Threshold Voltage (V)

Threshold Voltage (V)

0.45 VIN = 2.5V, VCNTL = 5V 0.45

0.4 0.4
VIN = 2.5V, VCNTL = 3.3V VIN = 2.5V, VCNTL = 5V

0.35 0.35 VIN = 2.5V, VCNTL = 3.3V

0.3 0.3
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)

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RT9173B

Output Voltage vs. Temperature Output Voltage vs. Temperature

0.91 1.26
VIN = 1.8V VIN = 2.5V
VCNTL = 3.3V VCNTL = 3.3V

0.905 1.255

Output Voltage (V)

Output Voltage (V)

0.9 1.25

0.895 1.245

0.89 1.24
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)

0.9VTT @ 2A Transient Response 0.9VTT @ 2A Transient Response

Output Transient
Output Transient

VREFEN = 0.9V VIN = 1.8V VREFEN = 0.9V VIN = 1.8V

Voltage (mV)
Voltage (mV)

100 Swing Frequency : 1kHz VCNTL = 3.3V 100 Swing Frequency : 1kHz VCNTL = 5V

0 0

-100 -100
Output Current (A)
Output Current (A)

2 2

0 0

-2 -2

Time (250us/Div) Time (250us/Div)

1.25VTT @ 2A Transient Response 1.25VTT @ 2A Transient Response

Output Transient

VREFEN= 1.25V VIN = 2.5V

Output Transient

VREFEN = 1.25V VIN = 2.5V

Voltage (mV)
Voltage (mV)

100 Swing Frequency : 1kHz VCNTL = 3.3V 100 Swing Frequency : 1kHz VCNTL = 5V

0 0

-100 -100
Output Current (A)
Output Current (A)

2 2

0 0

-2 -2

Time (250us/Div) Time (250us/Div)

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 RT9173B

Output Short-Circuit Protection Output Short-Circuit Protection

Source Sink VIN = 2.5V
VIN = 2.5V
6 VCNTL = 3.3V 12 VCNTL = 3.3V

10

Output Short Circuit (A)

5
Output Short Circuit (A)

4 8

3 6

2 4

1 2

0 0
Force the output shorted to ground Force the output shorted to VDDQ

Time (1ms/DIV) Time (1ms/DIV)

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RT9173B
VREFEN
Application Information

Internal parasitic diode R1 VCNTL VIN

RT9173B
Avoid forward-bias internal parasitic diode, VOUT to VCNTL, REFEN VOUT
and VOUT to VIN, the VOUT should not be forced some
R2 GND
voltage respect to ground on this pin while the VCNTL or
VIN is disappeared.
Consideration while designs the resistance of voltage Figure 6
divider
Make sure that VCNTL >= VIN in all conditions including
Make sure the sinking current capability of pull-down NMOS power on and off. As other linear regulator, dropout voltage
if the lower resistance was chosen so that the voltage on and thermal issue should be specially considered. Figure
VREFEN is below 0.2V. 6 and 7 show the RDS(ON) over temperature of RT9173B in
In addition, the capacitor and voltage divider form the low- SOP-8 and TO-252 packages respectively. The minimum
pass filter. There are two reasons doing this design; one is dropout voltage could be obtained by the product of RDS(ON)
for output voltage soft-start while another is for noise and output current. For thermal consideration, please refer
immunity. to the relative sections.

How to reduce power dissipation on Notebook PC or RDS(ON) vs. Temperature

0.45
the dual channel DDR SDRAM application? SOP-8
0.43
VCNTL = 3.3V
In notebook application, using RichTek’ s Patent 0.41
“ DistributedBus Terminator Topology” with choosing 0.39
RichTek’ s product is encouraged. 0.37
R DS(ON) (Ω)

0.35
Distributed Bus Terminating Topology
Terminator Resistor 0.33
R0
BUS(0) 0.31
R1 0.29
BUS(1)
VOUT R2 0.27
RT9173B BUS(2)
R3 0.25
BUS(3)
0.23
R4
BUS(4) -50 -25 0 25 50 75 100 125
REFEN
R5 Temperature (°C)
BUS(5)
R6
BUS(6)
VOUT R7 RDS(ON) vs. Temperature
RT9173B BUS(7)
0.48
R8 TO-252
BUS(8)
0.45 VCNTL = 3.3V
R9
BUS(9)
0.42
R DS(ON) (Ω)

0.39
RN
BUS(N)
R(N+1) 0.36
BUS(N+1)
0.33
General Regulator
The RT9173B could also serves as a general linear 0.30

regulator. The RT9173B accepts an external reference 0.27

voltage at REFEN pin and provides output voltage regulated 0.24
to this reference voltage as shown in Figure 6, where -50 -25 0 25 50 75 100 125
Temperature (°C)
VOUT = VREF x R1/(R1+R2)
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 RT9173B
Input Capacitor and Layout Consideration Since the multiple VCTRL pins of the SOP-8 package are
Place the input bypass capacitor as close as possible to internally shorted and connected to lead frame, it is efficient
the RT9173B. A low ESR capacitor larger than 470uF is to dissipate the heat by adding cooper area on VCTRL
recommended for the input capacitor. Use short and wide footprint. Figure 7 shows the relation about thermal
traces to minimize parasitic resistance and inductance. resistance θJA vs. copper area on a standard JEDEC 51-7
Inappropriate layout may result in large parasitic inductance (4 layer, 2S2P) thermal test board at TA = 25°C. The
and cause undesired oscillation between RT9173B and corresponding maximum power dissipation is shown in
the preceding power converter. Figure 8. For example, with 10mm x 10mm cooper area,
we can obtain the lower thermal resistance about 45°C/W.
Thermal Consideration The power maximum dissipation can be calculated as:
An internal thermal limiting circuitry shuts down the PD(MAX) = (125 − 25°C) / 45 = 2.22W (SOP-8)
RT9173B when junction temperature is over 170°C. This
protects the device during overload conditions. It is noted θJA vs. Copper Area
that the thermal limiting circuitry is not intended for normal 100

operation. For maximum reliability, the junction temperature 90

should not exceed absolute maximum operation
temperature 125°C during normal operation. The power 80
θ JA (°C/W)

dissipation should be well considered to keep the junction 70

temperature within the specification.
60
The power dissipation in RT9173B is calculated as:
50
PD = (VIN − VOUT) x IOUT + VIN x IQ
40
The maximum power dissipation can be calculated by
SOP-8
following formula: 30
0 10 20 30 40 50 60 70 80 90 100
PD(MAX) = ( TJ(MAX) -TA ) /θJA 2
Copper Area (mm )
Where T J(MAX) is the maximum operation junction
Figure 7
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance.
Power Dissipation vs. Copper Area
The junction to ambient thermal resistance θJA highly 100
TJ = 125°C
depends on IC package, PCB layout , the rate of 90
surroundings airflow. θJA for SOP-8 package is 160°C/W 80
Copper Area (mm 2 ))
2

and TO-252 package is 68°C/W on standard JEDEC 51-3 70

TA = 65°C
(single layer, 1S) thermal test board. The maximum power 60
TA = 55°C
dissipation at TA = 25°C can be calculated by following 50
TA = 25°C
formula: 40

PD(MAX) = (125 − 25°C) / 160 = 0.625W (SOP-8) 30

20
PD(MAX) = (125 − 25°C) / 68 = 1.471W (TO-252)
10
SOP-8
0
0 0.5 1 1.5 2 2.5 3
Power Dissipation (W)

Figure 8

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RT9173B
Outline Information
E C2
b3 R

L3
T
V
S
D
H

b P
L2

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 2.184 2.388 0.086 0.094
b 0.381 0.889 0.015 0.035
b3 4.953 5.461 0.195 0.215
C2 0.457 0.889 0.018 0.035
D 5.334 6.223 0.210 0.245
E 6.350 6.731 0.250 0.265
H 9.000 10.414 0.354 0.410
L 0.508 1.780 0.020 0.070
L2 0.508 Ref. 0.020 Ref.
L3 0.889 2.032 0.035 0.080
P 1.270 Ref. 0.050 Ref.
V 5.200 Ref. 0.205 Ref.
R 0.200 1.500 0.008 0.059
S 2.500 3.400 0.098 0.134
T 0.500 0.850 0.020 0.033

5-Lead TO-252 Surface Mount Package

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 RT9173B

H
A

J B

C
I
D

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.050 0.254 0.002 0.010
J 5.791 6.200 0.228 0.244
M 0.400 1.270 0.016 0.050

8-Lead SOP Plastic Package

Richtek Technology Corporation Richtek Technology Corporation

Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com

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