dr*ign ihcir

8*c*J‹›m fnr ***I@irrs and it is probable that suinc <•D' t ad vances w›ll rms j ,

*•4 BASIC MOS TRANSISTORS

® * >8 now established some background, let >*
and dcvic• s. In panicaisr, je us examine the »uos
b8SlC trsns isio rs as shown in Figures 1 ,d(g) and
(b)•

Scanned by CamScanner
 p-au
n-substrate

Drain

Scanned by CamScanner
 the more lightly doped p-region as shown. ’1 furs, stnnce anil tlraiii .me
ftenr one another by two diodes. Connections to tlic source and drain arc madly by
order to make a useful device, there must be the cnpabllily fi›r
a current between source and dratn, and this is commonly
achievctl g of ::two ways, giving rise to the enhancement mode and depletion mode tr ans
lSt‹irs.
Consider the enhancement mode device flrst, shown in Figure l.4(a). A polysilicon
gate p cited on a layer of insulation over the region between source and drain. Figure
1.4(a)
a basic enhancement mode device in which the channel is not established and the
is in a non-conducting condition, Pp — K = Pg, = 0. If this gate is connected to a teHe
positive voltage with respect to the source, then the electric field establlshed between
the Tele and ,the substrate gives rise to a charge inversion region in the subslrate under the
gete insulttioa and a conducting path or chiilnei is formed between source and drain.
The’channel may also be so that it is present under the conditiofl Egg
. established
. . . .. .
by implanting suitable impunties in the region between source and drain during
manufacture and prior.to’ depositing’ ihe insulation and the gate. This. arrangement is shown
in Figure l.4{b). Under these circumstances, source and drain are connected by a conducling
channel, but the, channel may now be closed by applying a suitable negative voltage to the
gate.
In both cases, variations of the gate voltage allow control of any current flow between
source attd drain.
Figure ‘1.4(c) 8hows the basic pMDS transistor structure for an enhancement mode
device. In this case „the substrate is of n-type material and the source and drain diffusions are
consequently p-type. ln the figure, the conditions shown are those for an unbiased device;
however, the application of a negative voltage of suitable magnitude (> | K, |) between gate
and coutce will give rise to the formation of a channel (p-type) between the source and drain
and current may then flow if the drain is made negative with .respect to the source. In this
case tht tnrmnf is carrie‹i by moles as oppi›sed to electrons (as is the case for nMOS devices).
In cñnsequence, pMOS transistors .are inherently slower than nMOS, since hole mobility Jim
is. less, by a :facioc of approximately 2.5, than electron mobility , q . However, bearing these
difference in miad,! the discussions of nM0S transistors which follow telate equally well to
pMOSmmasom.

1.5 Et¥HANCEMENT MODEe TRANSISTOR ACTION

To gzio mode
dwicfi, aa to Figure
lift place,:â:.rñioimum !+ O1tage’1eN0l of threshold voltage
source (and ofi. course between .gate .and .‘substrate
co*ditions ptevailing with the ’chaiinel
established

the channel by applying a voltage 'Kp between.,.drain and

u corresponding’ ffl drop = along the channel. This
 * ’e*"**/ Circuits and S sfems

= 0V

0V
Channel

OV

Pinch off
connected to 0 V.
Nole.' V’y, is the drain•to-source voltage. Substrate assumed
r V with \V vV|
FIGURE 1.s snhZgn ceme0t M oda transistor fo particular values of
•

JJ, = J g, — I (no rurreni flows when be voltage available

channel at the drain end so long as limitin g condition
’g the de ’ice is in the non-
in Figure 1.5(b). saiura
Consider now w•hat happens when J, is increased to a level greater thaa
this case, an IN drop — Kg, - V, takes place over less than the whole length Of
SO tltat over part of the channel, near the drain, there is i»*«fricient electric f e ld t
tO give rise to an inversion layer to create the channel. The channel is therefor e ‘pin
as indicated in Fig•ure l.5(c}. Diffusion current completes the path from SO>*C* °
 wdbehavr aa a c‹›n»taiit vtJr£ '»/

saasa’ or

1.6 DEPLETI ON MODE TRANSISTOR ACTION

Ofi I l0tlOfl mtide devices the channel is
P#, 0. and to cause the ch«flflel to cease established. because ‹if the irilplant, even when
ie cxi.st a negative v‹›ltagc F„t U›ffsl he app)icJ
^°*•*•° Bate and scurce.
< —0.ñ DD. depending on the implant and suhstrnlc bias, btil, thrcs hull I
'voltage differences asidt. the action is similar to that of ihe enhancement nio‹Je traitor.sttir
b“ommonly used symbols for nMOS and pMOS transistors arc stt out in Figure 1 I›.

nMOS nMO5
enhancement depletbn
FIGURE 1.6 Transistor circuit symbols.

1.7 nMOS FABRICATION

A brief introduction to the general aspects of the polysilicon gate self-aligning nMOS fabrication
process will now be given. As well as being relevant in their own right, the tahrtcatioIl
prt›cesses used for nMOS are relevant to CMOS and BiCMOS which may be viewed as
involving additional fabrication steps. Also, it is clear that an appreciation of the fabricati‹›n
pi‹›cessos will give an insight into the way in whith design information must be presented
anti into the reasons for certain performance characteristics and limitations. An nMOh pr‹iccss
is illustrated in Figure 1.7 and may be outlined as follows:
I . Processing is carried out on a thin wafer cut from a single crystal of silicon of high
purity into which the required p-impurities are introduced as the crystal is grown.
Such wafers are t lC8lly 75 to 150 mm in diameter and 0.4 mm thick and ate doped
3
with, say, boron to impurity concentrations of l0 " /cm to 10 /Cm'. b • ing resistivity
jp t]jq 2ppyoximatc range 25 ohm cm to 2 ohm ciii.
 1.

z.

Mask

4.

5. Window in oxide

6.
On thin OXid0

FIGURE 1.7 Continued

 7.

Patterned metallizatlon
(aluminum 1 ym)

F!GURE #•? fi OS fabrication •‹rocess.

2. A layer of silicon dioxide (SiO2), typically km thick, is grown all over the surface
l
of the wafer to protest the surface, act as a barrier to dopants during processing, and
provide a generally insulating substrate Ollto which other layers may be deposited
and patterned.
3. The surface Is now covered with a photoresist which is deposited onto the wafer and
spun to achieve an even distribution of the required thickness.
4. The photoresist layer is then exposed to ultraviolet light through a mask which
defines those regions into which diffusion is to take place together with transistor
channels. Assume, for example, that those areas exposed to ultraviolet radiation are
polymerized (hardened), but that the areas required for dlffusion are shielded by the
mask and remain unaffected.
5. ‘these atcas are subsequently readily etched away together with the underlying
silicon dioxide so that the wafer surface is exposed in the window defined by lhe
mask.
6. The remaining photoresist is removed and a thin layer of SiO2 (0.1 km typical) is
grown over the entire chip surface and then polysilicon is deposited on top of this
to fonn the gate structure. The polysilicon layer consists of heavily doped polysilicon
deposited by chemical vapor deposition (CVD). In the fabrication of fine pattern
devices, precise control of thickness, impurity concentration, and resistivity is necessary.
allows the polysilicon to be patterned
Further pholoresist coating and masking
(as shown in Step 6), and then the thin oxide is removed to expose areas into whiCh
n-type impurities are to be to form the source and drain as shown. Diffusion
diffused
 e containing
is achieved by heating the wafer to a high temperatur and passing a gas
 yr {pentcvclent) gaa

FIGURE 1.s Diffusion proce e-

fi will be seen that the process revolves around the formation or deposition and patlcM,'
of three layers. separatcd by silicon dioxide insulation. The layers are diffused witLiii i'
substrate, polysilicon on oxide on the substrate, snd metal ••••• • •+ again by oxide.
To fomi depletion mode devices it is only necessary to introduce a »•b«3 ion implaiiiiiil
step between Steps 5 and 6 in Figure 1.7. Again, the thick oxide acts as a mask anal 1! process
stage is also self-aligning.
Consideration of the processing steps will
and the self-aligning aspects of the
registration. In practice, some the oven il•°'
of the whol water, except here contac required. Howe
proCDSs is basically straightforward to comes d‹» "
the business of delineating the masks for
prc›cess may be reiterated as follows.

1.7.1 5ummnry of on
 ‹›xi‹lc n cr «II. i'nr this rcasun, his n1 nk is nflcti knnwn as the ’/fi/n‹› mv‹¿ f›ut
*t* › lxx\.t rcI?r It› \t as lits ili|)trsti›n mu,sk.
• \ftf' P«ltcm the inn ittiylax‹ati‹›n wiihin tht ihif nx rcginn where ‹IcpIcIi‹›n nxxlr
are to be pmduced—set/-efigtiiny.
{tm thick typically), Ihcn pattern ti.z‹ng
oxide layer where it is not covcretJ hy

oJoo there thin oxide hue been removed. J’ransiiior drains

>f« ihtis self-elignins wiik xsPcct ao the gaac stn‹cturcs.
—Grow thick osid› oYgF BII and thcn etch for contact cuts.
• ^*•'* 3—D*posii metal nd pattern with Mask 5.
° MOSk 6—Would be required
** th o erglassing process step.

1.8 CMOS FABRICATION

There are a number of approaches to CMOS
including the p-well, the n-well, the
fabrication,
tWin-tub, and the ordcr to introduce the reader to CMOS
destgn we will be concerned mainly well-based clrCUlis. The p-well process is widely
with
used in practice and the n-well process is olso
popular, particularly as il wns an essy
retrofit to existing nMOS lines.
For the lambda-based niles set out later, we will assume a p-well process.

J.8.1 The P-well Process

A brief overview of the
fabrication steps may be obtained with iofemnce to Figure
that the basic processing steps are of the same nature as those used for nMOS.
In primitive terms, the structure consists of nn n-type substrate in which p-devices may
be formed by suitable masking and diffusion and, in order to accommodate n-type devices,
a deep p-well is diffused into the n-type substrate as shown.
This diffusion must be carried out with special care since the p-well doping
concentration and depth will affect the threshold voltages as well as the breakdown voltages
of the n-transistors. To achieve low threshold voltages (0.6 to 1.0 V), wC need either deep
well diirusion or high well resistivity. However, deep wells require larger spacing
between the n- and p-type transistors and wires because of lateral diffusion and therefore a
larger chip area.
The p-wells act as substrates for the n-devices within the parent n-substrate, and,
provided that voltage polarity restrictions are observed, the two areas are electrically isolated.
However, since there are now in effect two substrates, two substrate connections (Kpp and
Kp) are required, as shown in Figure 1.10.
In all other respects—masking, patterning, and diffusion—the process is similar to
nMOS fabrication. In summary, typical processing steps are:
• Mask /—defines the areas in which the deep p-well diffusions are to take place.
 p mask (negativej

Figure J-9 CMOS p-well process sleps

FIGURE 1.10 CMOS p-well Inverter showing U' and VSS sUbstrato connocti<>S
 to Al Ctd S Technolo
A Review O MiCroelecf is

• Whisk 2—defines the lhinox regions, namely those

areas where the thick oxl€C IS IO
be stripped and thin oxide groWn to accommodate p-
and n-t ransislors alld difb IJi>>

- In.ik 3—used to pattern the polysilicon layer which

thin oxide.
• Musk 4—A p-plus mask is now used (to be in effect is deposited after the
all areas where p-diffusion is to take place. 'Anded’ with Mask 2) to defnG
° MW. k 5—This is usually performed using the negative form Of the p-plus fl2ftSk nftd,
with Mask 2, defines those areas where n-type diffusion is to lake place.
* Wfisk 6—Contact cuts are now defined.
• Muck 7 c metal layer pattern is derincd by this mask.
• M‹iSk 8 An overall passivation (overglass) layer is now applied and Mask 8 is
needed to derine the openings for access to bonding pads.

I .8.2 The N-well Process

As indicated earlier, although
the p-well process is widely used, n-well fabrication has also
goincd wide acceptan ce,
initially as a retrofit to nMOS lines.
N-wCll CMOS circuits are also superior to p-well because of the lower substrate bias
cft”ccts on transiSto£ threshold voltage and inherently lower parasitic capacitances assocsated

"typical n-well fabrication steps are illustrated in Frame 1.11. The first mask defines the n-
xvcll regions. This is followed by a low dose phosphorus implant driven in by a high

Formation of n-well regions

Osllno nMOS and pMO5 active areas

Field and gate oxidations (thioox)

Form and pattern potysilicon

F›GURE 1.11 uai n steps In a typical «- !! P+^<^S*

› c»os p-«'ell process, f«› •••n›i›i•, i›« ° i'iai› i•»r•›•'•'• r-•*"'*f• '•n••••
tq I d3{)°C), the nMOS process }}pyjp@ jlO SllC}l pC•£jtljfClTlCllL lJCCOtl5C Ci (llf siiiiFlicity,

it is likely thai
nMOS and CMOS system designs will continue to coexist for some lien to <<*

1.10 BiCMOS TECHNO LOGY

The deficiency of MOS technology lies in the limited load driving capabilities of MOS
transistors. This is due to the limited current sourcing and current sinking abilities n.ssociated
Wfth both p- alld n-transistors and although it is possible, for example, to design so-called
super buffers using MOs transisto rs alone, such arrangements do not always compare well
with the capabilities Of blpolar transistors. Bipolar transistors also provide higher gain and
have generally better noise and high frequency characteristirs than MOS transistors. Using
BiCMOS gales may he an effective way of speeding up VLSI circuits. However, the application
of BiCMOS in subsystems such as ALU, ROM, a register-rlle, or, for that matter. a barrel
shifler i S IlOt always an effective way of improving speed. This is because most gates in
such structures do not have to drive large capacitive loads so that the BiCMOS arrangements
give no speed advantage. To take advantage of BiCMOS, the whole functional entity, not
just the logic gates, must be considered. A comparison between the characteristics of
CMOS and bipolar circuits is set out in Table 1.2 and the differences are self-evident.
BiCMOS technology goes some way toward combining the virtues of both technologies.

T+»re 1.2 COMPARISON BETWEEN CMOS xnD BIPOLAR TECHNOLOGY US

CMOS technology Bipolar l#chnalogy

• Low static power dissipation • High power dissipation
High input impedance • Low input impedance
(low drive current) (high drive current)
• Scalable threshold voltage
• High noise margin » Low voltage swing logic
• High packing density • Low packing density
• High delay sensitivity to load • Low delay sensitivity to load
(fan-out limitations)
• Low output drive current • High output drive current
« Low gp Qp a V; ) • High gp Qg a eY;y)
• High at low currents
• Bidirectional capability • Essentially unidirectional
(drain rind source are interchangeabl e)
• A near ideal switching device
theoretically there
When considering CMOS technology, it becomes apparent that
should

be little difficulty in the fabrication processes to include bipolar well as MGM

extending as
 !’^‹*°=*! .* l'›‹'t'I‹ii ‹›i' j› »-rl1 ‹i»•l ii '‹‹II ‹ 1I‹›x I'*"""’“" *’ t'l
" i‹

n- i cl1 a url thy* atltlitit›iia! pli;isc i'ucion is 1‹›c:ileal

stich :i b1 OliltP
chord to Fieurc 1.16. Bipolar t ransistor
rcle ”ant design rules are dealt u'itli in Chapter
see e to further illustrate the actual kCOFtJGtfT BiCMOS bipu far traiisixlor in ft-‹i „
technclopy. Since extra design and r O Ce S l >8 e P S
ar e in volved, the IC lS ilfl I nc V t t9b',
t

illCftRSO in CO5t,

Pro«ess
1.to.1 BiCMOS Fobricafion in on N-well
The basic process steps used are those already outlined for CMOS but Wlth additional prom.
steps and additional masks defining (i) the p+ base region; (ii) n’ collector area; and (iii) 1r:
buried subcollector (BCCD).
Table 1.3 sets out the process steps for a single poly, single metal CMOS n- i!
process, showing the additional process steps for the bipolar devices.

1.J 0.2 Some Aspects of Bipolar and CMOS Devices

Clearly there are relative advantages and disadvantages when comparing bipolar tec6no1‹.
with CMOS technology. A readily assimilated comparison of some key features was
set o. in Table 12.
It will be seen that there are several advantages if the properties of CMOS and bite.
technologies could be combined. This is achieved to a significant extent in the BiC› '
technology. As in all things, there is a penalty which, in this case, arises from the
addlll0fi! process steps, some loss of packing density nd thll5 higher cost.
A further advantage which arises from BiCMOS technology is that analog amP
design 's facilitated and improved. High impedance CMOS transistors may be used 0f '
'H Ut C if6uit ry while the remaining stages and output drivers are realized using b P°' '
transisto rs.
To take maximum advantage of available si
licon tec hnologies one might gfiVlSfl§
following mix of technologies in a silicon system:
CMos for logic
BiCMos for I/O and driver circuits
ECL for critical high speed parts
t S MX Wi2
' › 1 not be
of the systcnl
Owever, in dealing
w‹ th the ECL technology.