3A, 28V, 925Khz Step-Down Converter: The Future of Analog Ic Technology
3A, 28V, 925Khz Step-Down Converter: The Future of Analog Ic Technology
3A, 28V, 925Khz Step-Down Converter: The Future of Analog Ic Technology
DESCRIPTION FEATURES
The MP2372 is a 925KHz step-down regulator • 3A Continuous Output Current, 4A Peak
with a built-in power MOSFET. It achieves 3A Output Current
continuous output current over a wide input • Programmable Soft-Start
supply range with excellent load and line • 100mΩ Internal Power MOSFET Switch
regulation. • Stable with Low ESR Output Ceramic
Current mode operation provides fast transient Capacitors
response and eases loop stabilization. • Up to 91% Efficiency
• 20μA Shutdown Mode
Fault condition protection includes cycle-by-
• Fixed 925KHz Frequency
cycle current limiting and thermal shutdown.
• Thermal Shutdown
Adjustable soft-start reduces the stress on the
input source at turn-on. In shutdown mode, the • Cycle-by-Cycle Over Current Protection
regulator draws 20μA of supply current. • Wide 4.5V to 28V Operating Input Range
• Output is Adjustable From 0.92V to 21V
The MP2372 is available in an 8-pin SOIC • Under Voltage Lockout
package with an exposed pad, and requires a
minimum number of readily available external APPLICATIONS
components to complete a 3A step-down DC to • Distributed Power Systems
DC converter solution. • Battery Chargers
• Pre-Regulator for Linear Regulators
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
C5
10nF Efficiency Curve
INPUT 100
2 1
IN BS VOUT=5V
OPEN = 7 3
EN SW OUTPUT 90
EFFICIENCY (%)
AUTOMATIC 3.3V
STARTUP MP2372
8 5
SS FB VOUT=3.3V
C1 80
COMP R1
CERAMIC
4 6
A
50v D1
70
C4 R2 C2
C6 CERAMIC VIN=12V
OPEN
60
6.3V 0 0.5 1.0 1.5 2.0 2.5 3.0
LOAD CURRENT (A)
ORDERING INFORMATION
Part Number* Package Top Marking Free Air Temperature (TA)
MP2372DN SOIC8N MP2372DN –40°C to +85°C
* For Tape & Reel, add suffix –Z (eg. MP2372DN–Z).
For RoHS compliant packaging, add suffix –LF (eg. MP2372DN–LF–Z)
PACKAGE REFERENCE
TOP VIEW
BS 1 8 SS
IN 2 7 EN
SW 3 6 COMP
GND 4 5 FB
EXPOSED PAD
CONNECT TO PIN 4
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Shutdown Supply Current Isupply VEN = 0V 20 30 μA
Quiesent Supply Current Iq VEN = 3V, VFB =1.4V 1.3 1.5 mA
4.5V ≤ VIN ≤ 28V,
Feedback Voltage VFB 0.892 0.920 0.948 V
VCOMP < 2V
Error Amplifier Voltage Gain AVEA 400 V/V
Error Amplifier Transconductance GEA ΔICOMP = ±10μA 690 μA/V
High-Side Switch-On Resistance RDS(ON)1 100 mΩ
Low-Side Switch-On Resistance RDS(ON)2 10 Ω
High-Side Switch Leakage Current VEN = 0V, VSW = 0V 0.1 10 μA
Short Circuit Current Limit 6.5 A
Current Sense to COMP Transconductance GCS 6.0 A/V
Oscillation Frequency fS 925 KHz
Short Circuit Oscillation Frequency VFB = 0V 110 KHz
Maximum Duty Cycle DMAX VFB = 0.8V 76 80 99 %
Minimum On Time TON 130 ns
EN Threshold Voltage 0.9 1.2 1.5 V
Enable Pull Up Current VEN = 0V 0.9 1.6 2.3 μA
Under Voltage Lockout Threshold Rising 2.3 2.6 2.9 V
Under Voltage Lockout Threshold Hysteresis 210 mV
CSS = 0.1μF L=10μH
Soft-Start Period 10 ms
CO=47μF IO=3A(CC)
Thermal Shutdown 160 °C
PIN FUNCTIONS
Pin # Name Description
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET
1 BS
switch. Connect a 10nF or greater capacitor from SW to BS to power the high side switch.
Power Input. IN supplies the power to the IC, as well as the step-down converter switches.
2 IN Drive IN with a 4.5V to 28V power source. Bypass IN to GND with a suitably large capacitor to
eliminate noise on the input to the IC. See Input Capacitor
Power Switching Output. SW is the switching node that supplies power to the output. Connect
3 SW the output LC filter from SW to the output load. Note that a capacitor is required from SW to BS
to power the high-side switch.
4 GND Ground. Connect the exposed pad on backside to Pin 4.
Feedback Input. FB senses the output voltage to regulate said voltage. Drive FB with a
5 FB resistive voltage divider from the output voltage. The feedback threshold is 0.92V. See Setting
the Output Voltage
Compensation Node. COMP is used to compensate the regulation control loop. Connect a
6 COMP series RC network from COMP to GND to compensate the regulation control loop. In some
cases, an additional capacitor from COMP to GND is required. See Compensation
Enable/UVLO. A voltage greater than 2.9V enables operation. For complete low current
shutdown the EN pin voltage needs to be at less than 900mV. When the voltage on EN
7 EN
exceeds 1.2V, the internal regulator will be enabled and the soft-start capacitor will begin to
charge. The MP2372 will start switching after the EN pin voltage reaches 2.9V.
Soft-Start Control Input. SS controls the soft start period. Connect a capacitor from SS to GND
8 SS
to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 10ms.
ELECTRICAL CHARACTERISTICS
VIN = 12V, C1 = 10µF, C2 = 47µF, L = 10µH and TA = +25°C, unless otherwise
noted.
Operating Range
100.00
1.00
0.10
1.0 10.0 100.0
Input Voltage (V)
VOUT VOUT
VOUT
2V/div. 2V/div.
10mV/div.
VIN
5V/div. VEN
VEN
5V/div.
5V/div.
VSW VSW
VSW
10V/div. 10V/div.
10V/div.
IINDUCTOR IINDUCTOR
IINDUCTOR 2A/div. 1A/div.
2A/div.
4ms/div. 4ms/div.
1s/div.
OPERATION
The MP2372 is a current-mode step-down The converter uses an internal N-Channel
regulator. It regulates input voltages from 4.5V to MOSFET switch to step-down the input voltage
28V down to an output voltage as low as 0.92V, to the regulated output voltage. Since the
and is able to supply up to 3A of load current. MOSFET requires a gate voltage greater than
the input voltage, a boost capacitor connected
The MP2372 uses current-mode control to
between SW and BS drives the gate. The
regulate the output voltage. The output voltage
capacitor is internally charged while SW is low.
is measured at FB through a resistive voltage
divider and amplified through the internal error An internal 10Ω switch from SW to GND is used
amplifier. The output current of the to insure that SW is pulled to GND when SW is
transconductance error amplifier is presented at low to fully charge the BS.capacitor.
COMP where a network compensates the
regulation control system. The voltage at COMP
is compared to the switch current measured
internally to control the output voltage.
IN 2
INTERNAL CURRENT
REGULATORS SENSE
AMPLIFIER + 5V
OSCILLATOR
SLOPE
925KHz COMP --
1 BS
CLK
+ + S Q
R Q
3 SW
1.2V -- SHUTDOWN -- CURRENT
COMPARATOR COMPARATOR
EN 7
LOCKOUT
-- COMPARATOR
2.60V + + -- 4 GND
1.8V
5 6 8
FB COMP SS
VOUT ⎛ V ⎞
APPLICATION INFORMATION ILP = ILOAD + × ⎜1 − OUT ⎟⎟
2 × fS × L ⎜⎝ VIN ⎠
COMPONENT SELECTION
(Refer to Figure 5) Where ILOAD is the load current.
Setting the Output Voltage Table 1 lists a number of suitable inductors
The output voltage is set using a resistive from various manufacturers. The choice of
voltage divider from the output voltage to FB pin. which style inductor to use mainly depends on
The voltage divider divides the output voltage the price vs. size requirements and any EMI
down to the feedback voltage by the ratio: requirement.
R2 Table 1—Inductor Selection Guide
VFB = VOUT
R1 + R2
Package
Where VFB is the feedback voltage and VOUT is Dimensions
the output voltage. Vendor/ Core Core (mm)
Model Type Material W L H
Thus the output voltage is:
Sumida
R1 + R2
VOUT = 0.92 × CR75 Open Ferrite 7.0 7.8 5.5
R2
CDH74 Open Ferrite 7.3 8.0 5.2
A typical value for R2 can be as high as 100kΩ,
CDRH5D28 Shielded Ferrite 5.5 5.7 5.5
but a typical value is 10kΩ. Using that value, R1
is determined by: CDRH5D28 Shielded Ferrite 5.5 5.7 5.5
CDRH6D28 Shielded Ferrite 6.7 6.7 3.0
R1 = 10.87 × ( VOUT − 0.92)(kΩ )
CDRH104R Shielded Ferrite 10.1 10.0 3.0
Inductor Toko
The inductor is required to supply constant
D53LC
current to the output load while being driven by Shielded Ferrite 5.0 5.0 3.0
Type A
the switched input voltage. A larger value
D75C Shielded Ferrite 7.6 7.6 5.1
inductor will result in less ripple current that will
result in lower output ripple voltage. However, D104C Shielded Ferrite 10.0 10.0 4.3
the larger value inductor will have a larger D10FL Open Ferrite 9.7 1.5 4.0
physical size, higher series resistance, and/or Coilcraft
lower saturation current. A good rule for DO3308 Open Ferrite 9.4 13.0 3.0
determining the inductance to use is to allow
DO3316 Open Ferrite 9.4 13.0 5.1
the peak-to-peak ripple current in the inductor
to be approximately 30% of the maximum Output Rectifier Diode
switch current limit. Also, make sure that the The output rectifier diode supplies the current to
peak inductor current is below the maximum the inductor when the high-side switch is off. To
switch current limit. The inductance value can reduce losses due to the diode forward voltage
be calculated by: and recovery times, use a Schottky diode.
VOUT ⎛ V ⎞ Choose a diode whose maximum reverse
L1 = × ⎜⎜1 − OUT ⎟⎟
fS × ΔIL ⎝ VIN ⎠ voltage rating is greater than the maximum
input voltage, and whose current rating is
Where VIN is the input voltage, fS is the 925KHz greater than the maximum load current. Table 2
switching frequency and ΔIL is the peak-to-peak lists example Schottky diodes and
inductor ripple current. manufacturers.
Choose an inductor that will not saturate under Input Capacitor
the maximum inductor peak current. The peak The input current to the step-down converter is
inductor current can be calculated by: discontinuous, therefore a capacitor is required
Table 2—Diode Selection Guide preferred to keep the output voltage ripple low.
Voltage/Current Manufacture The output voltage ripple can be estimated by:
Diode
Rating VOUT ⎛ V ⎞ ⎛ ⎞
1
ΔVOUT = × ⎜1 − OUT ⎟⎟ × ⎜ R ESR + ⎟
SK33 30V, 3A Diodes Inc. f S × L ⎜⎝ VIN ⎠ ⎝
⎜ 8 × f S × C2 ⎟
⎠
SK34 40V, 3A Diodes Inc.
B330 30V, 3A Diodes Inc. Where L is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
B340 40V, 3A Diodes Inc.
output capacitor.
MBRS330 30V, 3A On Semiconductor
MBRS340 40V, 3A On Semiconductor In the case of ceramic capacitors, the
impedance at the switching frequency is
to supply the AC current to the step-down
dominated by the capacitance. The output
converter while maintaining the DC input
voltage ripple is mainly caused by the
voltage. Use low ESR capacitors for the best
capacitance. For simplification, the output
performance. Ceramic capacitors are preferred,
voltage ripple can be estimated by:
but tantalum or low-ESR electrolytic capacitors
may also suffice. VOUT ⎛ V ⎞
ΔVOUT = 2
× ⎜⎜1 − OUT ⎟⎟
Since the input capacitor (C1) absorbs the input 8 × fS × L × C2 ⎝ VIN ⎠
switching current, it requires an adequate ripple
current rating. The RMS current in the input In the case of tantalum or electrolytic capacitors,
capacitor can be estimated by: the ESR dominates the impedance at the
switching frequency. For simplification, the
VOUT ⎛⎜ VOUT ⎞ output ripple can be approximated to:
I C1 = ILOAD × × 1− ⎟
VIN ⎜⎝ VIN ⎟
⎠
VOUT ⎛ V ⎞
ΔVOUT = × ⎜⎜1 − OUT ⎟⎟ × R ESR
The worst-case condition occurs at VIN = 2VOUT, fS × L ⎝ VIN ⎠
where:
The characteristics of the output capacitor also
I affect the stability of the regulation system. The
IC1 = LOAD
2 MP2372 can be optimized for a wide range of
capacitance and ESR values.
For simplification, choose the input capacitor
whose RMS current rating greater than half of Compensation Components
the maximum load current. MP2372 employs current mode control for easy
compensation and fast transient response. The
The input capacitor can be electrolytic, tantalum
system stability and transient response are
or ceramic. When using electrolytic or tantalum
controlled through the COMP pin. COMP pin is
capacitors, a small, high quality ceramic the output of the internal transconductance
capacitor, i.e. 0.1μF, should be placed as close
error amplifier. A series capacitor-resistor
to the IC as possible. When using ceramic
combination sets a pole-zero combination to
capacitors, make sure that they have enough
control the characteristics of the control system.
capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The The DC gain of the voltage feedback loop is
input voltage ripple caused by capacitance can given by:
be estimated by: VFB
A VDC = R LOAD × G CS × A VEA × Where AVEA is
ILOAD V ⎛ V ⎞ VOUT
ΔVIN = × OUT × ⎜1 − OUT ⎟⎟
fS × C1 VIN ⎜⎝ VIN ⎠ the error amplifier voltage gain, GCS is the current
sense transconductance and RLOAD is the load
Output Capacitor resistor value.
The output capacitor (C2) is required to
maintain the DC output voltage. Ceramic, The system has two poles of importance. One is
tantalum, or low ESR electrolytic capacitors are due to the compensation capacitor (C3) and the
recommended. Low ESR capacitors are output resistor of error amplifier, and the other is
due to the output capacitor and the load resistor. have been optimized for fast transient
These poles are located at: responses and good stability at given conditions.
GEA Table 3—Compensation Values for Typical
fP1 = Output Voltage/Capacitor Combinations
2π × C3 × A VEA
VOUT C2 (µF, R3 C3
1 L (µH) C6
fP2 = (V) Ceramic) (kΩ) (nF)
2π × C2 × R LOAD 1 1 47 3 10 None
Where GEA is the error amplifier transconductance, 1.2 1 47 5.1 6.8 None
530μA/V. 1.8 2.2 47 7.5 3.3 None
2.5 2.2 - 4.7 47 10 4.7 None
The system has one zero of importance, due to
3.3 2.2 - 4.7 47 15 5.6 None
the compensation capacitor (C3) and the
5 4.7 – 6.8 2 x 22 20 4.7 None
compensation resistor (R3). This zero is located
at: 12 6.8 - 10 2 x 22 44.2 2.2 None
To optimize the compensation components for
1 conditions not listed in Table 3, the following
f Z1 =
2π × C3 × R3 procedure can be used.
The system may have another zero of importance,
1. Choose the compensation resistor (R3) to set
if the output capacitor has a large capacitance
the desired crossover frequency. Determine the
and/or a high ESR value. The zero, due to the R3 value by the following equation:
ESR and capacitance of the output capacitor, is
located at: 2π × C2 × f C VOUT
R3 = ×
G EA × G CS VFB
1
fESR =
2π × C2 × R ESR Where fC is the desired crossover frequency.
In this case, a third pole set by the compensation 2. Choose the compensation capacitor (C3) to
capacitor (C6) and the compensation resistor (R3) achieve the desired phase margin. For
is used to compensate the effect of the ESR zero applications with typical inductor values, setting
on the loop gain. This pole is located at: the compensation zero, fZ1, below one forth of the
1 crossover frequency provides sufficient phase
f P3 = margin. Determine the C3 value by the following
2π × C6 × R3
equation:
The goal of compensation design is to shape
the converter transfer function to get a desired 4
C3 >
loop gain. The system crossover frequency 2π × R3 × f C
where the feedback loop has the unity gain is
3. Determine if the second compensation
important.
capacitor (C6) is required. It is required if the ESR
Lower crossover frequencies result in slower zero of the output capacitor is located at less than
line and load transient responses, while higher half of the 925KHz switching frequency, or the
crossover frequencies could cause system following relationship is valid:
unstable. A good rule of thumb is to set the
1 f
crossover frequency to approximately one-tenth < S
of the switching frequency or lower. The 2π × C2 × R ESR 2
switching frequency for the MP2372 is 925KHz, If this is the case, then add the second
so the desired crossover frequency is equal to compensation capacitor (C6) to set the pole fP3 at
or less than 92.5KHz. the location of the ESR zero. Determine the C6
value by the equation:
Table 3 lists the typical values of compensation
components for some standard output voltages C2 × R ESR
C6 =
with various output capacitors and inductors. R3
The values of the compensation components
COMP SGND
C3 R3
4 GND
1 BST
SW
IN
C5
2
3
L1
C1 D1
PGND C2
C3 R3
R4
C6
R1
C4 SGND
SS/REF 8
EN 7
6
FB 5
SGND
R2
COMP
Vout
4 GND
BST
Feeback
SW
IN
1
2
3
C5
L1
C1 D1
PGND C2
INPUT
4.5V to 28V
2 1
7 IN BS 3 OUTPUT
OPEN = AUTOMATIC EN SW 2.5V
STARTUP 3A
MP2372
8 5
SS FB
GND COMP
4 6
C6 D1
OPEN B330A
C5
10nF
INPUT
4.5V to 28V
2 1
7 IN BS OUTPUT
3
OPEN = AUTOMATIC EN SW 3.3V
STARTUP 3A
MP2372
8 5
SS FB
GND COMP
4 6
C3
C6 5.6nF D1
OPEN B330A
PACKAGE INFORMATION
SOIC8N (EXPOSED PAD)
0.189(4.80) 0.124(3.15)
0.197(5.00) 0.136(3.45)
8 5
1 4
0.051(1.30)
0.067(1.70)
0.0075(0.19)
SEATING PLANE
0.0098(0.25)
0.000(0.00)
0.013(0.33) 0.006(0.15)
0.020(0.51) SIDE VIEW
0.050(1.27)
BSC
GAUGE PLANE
0.010(0.25) BSC
0.024(0.61) 0.050(1.27)
0.016(0.41)
0o-8o 0.050(1.27)
0.063(1.60)
DETAIL "A"
0.103(2.62) 0.213(5.40)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH ,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
0.138(3.51) OR PROTRUSIONS.
4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
RECOMMENDED LAND PATTERN 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.