Scribd
Upload
46 views7 pages

Introduction To Design With Verilog 3.4 Exercises: Dr. Paul D. Franzon

Uploaded by

kimjim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
46 views7 pages

Introduction To Design With Verilog 3.4 Exercises: Dr. Paul D. Franzon

Uploaded by

kimjim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

Digital ASIC Design

3. Introduction to Design With Verilog


3.4 Exercises
Dr. Paul D. Franzon

©2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 1


Digital ASIC Design

Exercise: Three Timing Examples (from Timing Notes)


 What do these look like in Verilog?
A E
B Compare
C
Compare F

D Compare G

always@(A or B or C)
begin Why not move E, F assignments
if (A>B) then E = A; else E = B; down to here?
if (C>E) then F = C; else F = E;
end
always@(posedge clock) E, F would now be outputs
if (D>F) then G <= D; else G <=F; of flip-flops.

©2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 2


Digital ASIC Design

… Three timing examples


 Produce a Verilog code fragment for …
 Use continuous assignment
A E
B Compare
C
Compare G

D Compare F

assign E = (A>B) ? A : B;
assign F = (C>D) ? C : D;

always@(posedge clock)
if (E>F) then G <= E; else G <=F;

©2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 3


Digital ASIC Design

… Three Timing Examples


 And for this…
A
E
B Compare
F
C
C1
Compare
D
D1
Compare G
D2

Note: Outputs of all flip-flops have to be named


always@(posedge clock)
begin
if (A>B) then E <= A; else E <=B;
C1 <= C;
D1 <= D;
if (E>C1) then F <= E; else F <= C1;
D2 <= D1;
if (F>D2) then G <= F; else G <= D2;
end

©2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 4


Digital ASIC Design

Sample Problem
 Accumulator:
 Design an 8-bit adder accumulator with the following properties:
 While ‘accumulate’ is high, adds the input, ‘in1’ to the current accumulated total and
add the result to the contents of register with output ‘accum_out’.
 use absolute (not 2’s complement) numbers

 When ‘clear’ is high (‘accumulate’ will be low) clear the contents of the register with
output ‘accum_out’
 The ‘overflow’ flag is high is the adder overflows

Hint:
8-bit adder produces a 9-bit result:
{carry_out, sum} = A+B;

©2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 5


Digital ASIC Design

Sketch Design
1. Determine and name registers.
2. Determine combinational logic
3. Hand generate a timing diagram to verify
Clear

accumulate
0
accum_out
accum_in

in1 +

overflow

©2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 6


Digital ASIC Design

Code Verilog
module accum (clock, accumulate, clear, in1, accum_out, overflow);

input clock, accumulate, clear;


input [7:0] in1;
output [7:0] accum_out;
output overflow;

reg [7:0] accum_out;


wire [7:0] accum_in;
wire overflow;

always@(posedge clock)
begin
if (clear) accum_out <= 8'b0;
else if (accumulate) accum_out <= accum_in;
end

assign {overflow, accum_in} = accum_out + in1;

endmodule /* counter */

©2013, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 7

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy