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BRAC University: Lab Assignment 3 On CSE460

This document contains Lab Assignment 3 submitted by Sameha Kamrul for the course CSE460. It includes answers to 3 questions. The first question involves analyzing a K-map and deriving a logical expression. A circuit is designed and its timing diagram matches the expected values. The second question implements the logical expression using a 16-1 multiplexer. The timing diagram shows each clock cycle is doubled from the previous. The third question designs a 4-bit down counter with reset using D flip-flops, showing the count value on a 7-segment display. The counter value decrements on the positive clock edge and reset is triggered by a switch.

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72 views7 pages

BRAC University: Lab Assignment 3 On CSE460

This document contains Lab Assignment 3 submitted by Sameha Kamrul for the course CSE460. It includes answers to 3 questions. The first question involves analyzing a K-map and deriving a logical expression. A circuit is designed and its timing diagram matches the expected values. The second question implements the logical expression using a 16-1 multiplexer. The timing diagram shows each clock cycle is doubled from the previous. The third question designs a 4-bit down counter with reset using D flip-flops, showing the count value on a 7-segment display. The counter value decrements on the positive clock edge and reset is triggered by a switch.

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Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BRAC University

Lab Assignment 3
on CSE460

Submitted By
Sameha Kamrul,
ID: 18101523,
Sec: 4

Date of Submission
9th December 2021
Ans to the question 1

The given KMAP is :


00 01 11 10

00 1 0 1 1

01 1 d d 0

11 d d 1 0

10 1 1 0 1
Timing Diagram:

From the Kamp, we can group them to have a equation, by selecting the boxes. Then we get the
equation:
A’B’+A’C+BD+B’D’+AC’D’
After getting this, we can simply design the circuit and simulate it to find out the timing diagram
whether it matches with our work or not. We have set the clock value like this so that the output
must have complete one full cycle and we can get a clear idea about that the input and output
combination. For the 1st clock we have set 80 after that for the 2nd one we have assigned 40, soon
after that for the 3rd one we have assigned 20 and for the last clock we have given the value of
10. When A = 0, B= 1, C = 0, D = 0 we get Y =0 in this case, on the other hand, if A = 0, B = 0,
C = 0, D = 0 then we get Y =1. Which resembles, same value as we get form the theories. So, we
can tell that the time diagram also matches with our expected values.
Ans. to the question no 2
Here, we were asked to implement a logical expression using 16 to 1 multiplexer.
Circuit:

Timing Diagram:
For this diagram, firstly we need to make 4:1 multiplexer so that after making this, we can use it
as block diagram to make 16:1 multiplexer. In order to ensure that this diagram fit perfect or not,
the timing diagram is the proof that all the clock cycle is correct. And to get the time diagram we
need to set the clock cycle in a way that each one of the values is doubled then the previous one.
This is how we can get the desired multiplexer to find he logical expression.
Ans. to the question no: 3
Timing diagram:

Here, we need to design a 4-bit down counter with reset functionality using D- flipflop. Also, we
need to show the count value with seven segment display. So, using flipflops we have shown the
counter value which is simultaneously decreasing time to time. And to start the process we have
used switch. Moreover, the counting value decrement is happening at the positive edge of the
clock.

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