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Ade Simp Questions 22

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9 views

Ade Simp Questions 22

Uploaded by

kaluukaluu412
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ADE SIMP QUESTIONS 22

Prepared by: The TIE review team- RNSIT, SJBIT, JSSATE and KSSEM

Module-1

1. Explain with a neat diagram and characteristics and applications


(i)Photodiode (ii)LED (iii)Photo Coupler
2. With the Circuit diagram derive the expression for
(i)Fixed bias BJT (ii)Collector-to-Base bias (iii)Voltage Divider bias
3. Draw and explain
(i)Monostable/astable multivibrator (ii)Schmitt trigger (iii)Relaxation oscillator
4. Explain the working of R-2R ladder D to A converter
5. With a neat waveform and circuit diagram, explain the working of the monostable
multivibrator.

Module-2

1. Find the minimum SOP and minimum POS expression for the following using Kmap
f(A,B,C,D)= Σm(1,3,4,11)+ Σd(2,7,8,12,14,15)
2.What are the disadvantages of KMAP,Explain how QM method overcomes these
disadvantages? Simplify using QM method
f(A,B,C,D)= Σm(0,1,2,3,4,5,6,7,8,9,10,11)
3.What is Map Entered variable? Using MEV simplify.
f(A,B,C,D)= Σm(2,3,4,5,13,15)+ Σd(8,9,10,11)
4.Design the function EX-OR using (i) NAND gates only (ii) NOR gates only
5.Plot the following function on a K-map (Do not expand to minterm before plotting):
F(A, B, C, D) = A′B′ + CD′ + ABC + A′B′CD′ + ABCD′ , find the minimum sum of
products.

Module-3

1. What are the hazards of Digital Circuits? Explain different types of hazards?
2. Draw and explain Full Adder using 3 to 8 decoder?
3. Differentiate between PAL and PLA. Realize the following using PLA. Give PLA table and
Internal connection diagram for PLA
f(A,B,C,D)= Σm(1,2,4,5,6,8,10,12,14)
f(A,B,C,D)= Σm(2,4,6,8,10,11,12,14,15)
4. What is a multiplexer? Implement the following using 8:1 Mux
f(A,B,C,D)= Σm(1,2,4,6,9,12)
5. Explain simulation and testing of digital circuits
6. Design Hexadecimal (Binary) to ASCII Code Converter using suitable ROM. Give the
connection diagram of the ROM

Module-4

1. Explain the structure of the VHDL program. Write VHDL Code for 4-bit parallel adder
using full adder as a component.
2. Explain the working of the SR latch using NOR gates and show how the SR latch can
be used for switch debouncing.
3. Derive the characteristics of D, T, SR and JK FFs
4. Difference between Latch and Flipflop, show how SR ff can be converted to DFF
5. Construct SR gates latch using NAND gates and derive the characteristics equation for
the same
6. Write the syntax of the Conditional signal assignment statement in VHDL

Module-5

1. What is a shift register? Explain the working of an N-bit parallel adder with an
accumulator with a neat diagram
2. Design a 3bit Synchronous counter using T-FFs where n=8
3. Design a synchronous up counter for the given set of values
0➯4➯7➯2➯3➯0 using (i)T-ff (ii)D-ff (iii)SR-ff (iv) JK-ff

4. Explain the sequential parity checker.


5. Write a note on (i) ring counter (ii) Johnson tail counter

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