GPIO

GPIO pins and alternate functions

Run Clock Gate Control Register for GPIO (RCGCGPIO) (address is 0x400FE608)

Base addresses for GPIO ports

Port A: 0x40004000
Port B: 0x40005000
Port C: 0x40006000
Port D: 0x40007000
Port E: 0x40024000
Port F: 0x40025000

Data Register: GPIODATA, offset 0x000

Data direction register: GPIODIR, offset 0x400

GPIO Alternate Function Select: GPIOAFSEL, offset 0x420

GPIO Port Control: GPIOPCTL, offset 0x52C

GPIO Interrupt Sense (GPIOIS), offset 0x404

GPIO Interrupt Both Edges:GPIOIBE, offset 0x408

GPIO Interrupt Event : GPIOIEV, offset 0x40C

GPIO Interrupt Mask: GPIOIM, offset 0x410

GPIO Raw Interrupt Status: GPIORIS, offset 0x414 (read only)

GPIO Masked Interrupt Status: GPIOMIS, offset 0x418 (read only)

GPIO Interrupt Clear: GPIOICR, offset 0x41C

GPIO Pull-Up Select: GPIOPUR, offset 0x510

GPIO Pull-Down Select (GPIOPDR), offset 0x514

GPIO Analog Mode Select: GPIOAMSEL, offset 0x528

GPIO Digital Enable: GPIODEN, offset 0x51C

GPIO ADC Control: GPIOADCCTL, offset 0x530

 TIMER

SysTick

SysTick Control and Status Register(STCTRL)

Enable: 0 timer disabled, 1 timer enabled

INTEN: 0 interrupt disabled, 1 interrupt is generated to the NVIC when SysTick counts to 0.
CLK_SRC: 0 (POSC) divided by 4, 1 system clock
COUNT: 0 SysTick timer has not counted to 0 yet, 1 SysTick timer has counted to 0. This bit is cleared
by a read of the register or if the STCURRENT register is written with any value.

SysTick Reload Value Register (STRELOAD)

This register specifies the start value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
Start value can be between 0x1 and 0x00FFFFFF (only 24 bit value an be written)

SysTick Current Value Register (STCURRENT)

This register is write-clear. Writing to it with any value clears the register. Clearing this register also
clears the COUNT bit of the STCTRL register.
 General Purpose Timers

Base addresses of six 16/32 bit Timers and six 32/64 bit Timers:
■ 16/32-bit Timer 0: 0x4003.0000
■ 16/32-bit Timer 1: 0x4003.1000
■ 16/32-bit Timer 2: 0x4003.2000
■ 16/32-bit Timer 3: 0x4003.3000
■ 16/32-bit Timer 4: 0x4003.4000
■ 16/32-bit Timer 5: 0x4003.5000
■ 32/64-bit Wide Timer 0: 0x4003.6000
■ 32/64-bit Wide Timer 1: 0x4003.7000
■ 32/64-bit Wide Timer 2: 0x4004.C000
■ 32/64-bit Wide Timer 3: 0x4004.D000
■ 32/64-bit Wide Timer 4: 0x4004.E000
■ 32/64-bit Wide Timer 5: 0x4004.F000

Timer Configuration : CFG, offset 0x000

Value of Bit field 2:0 Description

0x0 For a 16/32-bit timer, this value selects the 32-bit timer configuration.
For a 32/64-bit wide timer, this value selects the 64-bit timer configuration.
For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter
0x1 configuration.
For a 32/64-bit wide timer, this value selects the 64-bit real-time clock (RTC)
counter configuration.
0x4 For a 16/32-bit timer, this value selects the 16-bit timer configuration.
For a 32/64-bit wide timer, this value selects the 32-bit timer configuration.

Timer A/B Mode : TAMR/ TBMR, offset 0x004/0x008

Bit field Value Description

1:0 0x1 One shot timer mode
0x2 Periodic timer mode
0x3 Capture mode
2 0 Edge count mode
1 Edge time mode
3 0 Capture or compare mode
1 PWM
4 0 Timer counts down
 1 Timer counts up
5 0 The match interrupt is disabled for match events.
1 An interrupt is generated when the match value in the TAMATCHR
register is reached in the one-shot and periodic modes.
6 0 Timer A begins counting as soon as it is enabled
1 If Timer A is enabled (TAEN is set in the CTL register), Timer A
does not begin counting until it receives a trigger from the timer in the
previous position in the daisy chain
7 0 Snap shot mode is disabled
1 If Timer A is configured in the periodic mode, the actual free-running,
capture or snapshot value of Timer A is loaded at the time-out
event/capture or snapshot event into the Timer A ( TAR) register.
If the timer prescaler is used, the prescaler snapshot is loaded into
the Timer A ( TAPR).
8 0 Update the TAR and TAV registers with the value in the TAILR
register on the next cycle. Also update the TAPS and TAPV
registers with the value in the TAPR register on the next cycle.
1 Update the TAR and TAV registers with the value in the TAILR
register on the next timeout. Also update the TAPS and TAPV
registers with the value in the TAPR register on the next timeout.
9 0 Capture event interrupt is disabled.
1 Capture event interrupt is enabled.
10 0 Update the TAMATCHR register and the TAPR register, if used,
on the next cycle.
1 Update the TAMATCHR register and the TAPR register, if used,
on the next time out.
11 0 Legacy operation with CCP pin driven Low when the TAILR is
reloaded after the timer reaches 0.
1 CCP is driven High when the TAILR is reloaded after the timer
reaches 0.

Timer Control : CTL, offset 0x00C

Bit field Value Description

14 0 Output is unaffected.
1 Output is inverted.
13 0 The output Timer B ADC trigger is disabled.
1 The output Timer B ADC trigger is enabled.
11:10 0x0 Timer B Event Mode, Positive edge
0x1 Timer B Event Mode, Negative edge
0x3 Timer B Event Mode, both edges
9 0 Timer B continues counting while the processor is halted by the debugger.
1 Timer B freezes counting while the processor is halted by the debugger.
8 0 Timer B is disabled.
1 Timer B is enabled and begins counting or the capture logic is enabled
based on the CFG register.
6 0 Timer A PWM Output Level is unaffected.
1 Timer A PWM Output Level is inverted.
5 0 The output Timer A ADC trigger is disabled.
1 The output Timer A ADC trigger is enabled.
4 0 RTC counting freezes while the processor is halted by the debugger.
1 RTC counting continues while the processor is halted by the debugger.
3:2 0x0 Timer A Event Mode, Positive edge
0x1 Timer A Event Mode, Negative edge
0x3 Timer A Event Mode, both edges
1 0 Timer A continues counting while the processor is halted by the debugger.
1 Timer A freezes counting while the processor is halted by the debugger.
0 0 Timer A is disabled.
1 Timer A is enabled and begins counting or the capture logic is enabled
based on the CFG register.

Timer Interrupt Mask: IMR, offset 0x018

bit function
16 32/64-Bit Wide Write Update (WUE) Error Interrupt Mask
11 Timer B Match (TBM) Interrupt Mask
10 Timer B Capture Mode Event (CBE) Interrupt Mask
9 Timer B Capture Mode Match (CBM) Interrupt Mask
8 Timer B Time-Out (TBTO) Interrupt Mask
4 Timer A Match (TAM) Interrupt Mask
3 RTC Interrupt Mask
2 Timer A Capture Mode Event (CAE) Interrupt Mask
1 Timer A Capture Mode Match (CAM) Interrupt Mask
0 Timer A Time-Out (TATO) Interrupt Mask
0: Interrupt is disabled, 1: Interrupt is enabled
Timer Raw Interrupt Status : RIS, offset 0x01C

0: Match/capture/time-out etc. events not occurred.

1: Match/capture/time-out etc. events occurred.
(TBM, CBE, etc. corresponds to the same abbreviations as the above table)

Timer Masked Interrupt Status : MIS, offset 0x020

0: Match/capture/time-out etc. interrupts has not occurred or masked.

1: Unmasked Match/capture/time-out etc. interrupt has occurred.
(TBM, CBE, etc. corresponds to the same abbreviations as the above table)

Timer Interrupt Clear: ICR, offset 0x024

Writing a 1 to this a bit clears the respective bit in RIS and MRIS registers.

Timer A/B Interval Load: TAILR/ TBILR, offset 0x028/0x02C

(Same for Timer B)

Timer A/B Match: TAMATCHR/ TBMATCHR, offset 0x030/0x034

(Same for Timer B)

Timer A/B Prescale: TAPR/ TBPR, offset 0x038/0x03C

TAPSRH: GPTM Timer A Prescale High Byte. For the 16/32-bit GPTM, this field is reserved. For the
32/64-bit Wide GPTM, this field contains the upper 8-bits of the 16-bit prescaler.

TAPSRL: GPTM Timer A Prescale Low Byte. For the 16/32-bit GPTM, this field contains the entire 8-
bit prescaler. For the 32/64-bit Wide GPTM, this field contains the lower 8-bits of the 16-bit prescaler.

(Same for Timer B)

Timer A/B Prescale Match: TAPMR/TBPMR, offset 0x040/0x044

TAPSRH: GPTM Timer A Match Prescale High Byte. For the 16/32-bit GPTM, this field is reserved.
For the 32/64-bit Wide GPTM, this field contains the upper 8-bits of the 16-bit match prescaler.

TAPSRL: GPTM Timer A Match Prescale Low Byte. For the 16/32-bit GPTM, this field contains the
entire 8-bit match prescaler. For the 32/64-bit Wide GPTM, this field contains the lower 8-bits of the
16-bit match prescaler.

(Same for Timer B)

Timer A/B: TAR/ TBR, offset 0x048/0x04C

PB4: Timer1:
rcgc -> orr 0x02: timer1
rcgc -> orr 0x02 ctl -> bic 0x01: disable clock
dır -> bic 0x10 : input cfg -> mov 0x04: 16 bit
afsel -> orr 0x10 tamr -> mov 0x07 : capture/edge time
pctl -> orr 0x70000: timer1 tailr -> 0xffffffff
amsel -> 0 imr -> orr 0x04: capture event interrupt
den -> orr 0x10 : digital enable ctl -> orr 0x0f : both edges/enable/stall

(Same for Timer B)

Timer A/B Value : TAV/ TBV, offset 0x050/0x054

Check RIS:
loop ldr r1, =RIS
ldr r2, [r1]
cmp r2, #0x04 ; wait for captue
bne loop ; if no capture, loop
ldr r1, =TAR
r2, [r1]
ldr r1, =ICR
mov r0, #0x04 ; clear caeris
str r0, [r1]

(Same for Timer B)

 Analog-to-Digital Converter

Base addresses of the ADC modules are:

ADC0: 0x4003.8000
ADC1: 0x4003.9000

Analog-to-Digital Converter Run Mode Clock Gating Control: RCGCADC, 0x400FE638

Rn=0 ADC module n is disabled.

Rn=1 Enable and provide a clock to ADC module n in Run mode.

ADC Sample Sequence Input Multiplexer Select 0: ADCSSMUX0, offset 0x040

ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060

ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080

ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0

ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044

ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064

ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084.
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4

ADC Active Sample Sequencer (ADCACTSS), offset 0x000

ASENn=0, sample sequencer n is disabled,

ASENn=1, sample sequencer n is enabled.

BUSY=0, ADC is idle,

BUSY=1, ADC is busy.
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028

GSYNC bit is cleared once sampling has been initiated.

GSYNC=1 This bit initiates sampling in multiple ADC modules at the same time. Any ADC module that
has been initialized by setting an SSn bit and the SYNCWAIT bit starts sampling once this bit is
written.

SYNCWAIT=0 Sampling begins when a sample sequence has been initiated.

SYNCWAIT=1 This bit allows the sample sequences to be initiated, but delays sampling until the
GSYNC bit is set.

SSn=0 No effect.
SSn=1 Begin sampling on Sample Sequencer n, if the sequencer is enabled in the ADCACTSS
register.

ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048

ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8

ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C

ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC

FULL=0 The FIFO is not currently full.

FULL=1 The FIFO is currently full.

EMPTY=0 The FIFO is not currently empty.

EMPTY=1 The FIFO is currently empty.

HPTR / TPTR: the current "head" / "tail" pointer index for the FIFO, that is, the next entry to be written.
ADC Underflow Status (ADCUSTAT), offset 0x018

UVn=0 The FIFO has not underflowed.

UVn=1 The FIFO for the Sample Sequencer has hit an underflow condition, meaning that the FIFO is
empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are
returned.
This bit is cleared by writing a 1.

ADC Overflow Status (ADCOSTAT), offset 0x010

OVn=0 The FIFO has not overflowed.

OVn=1 The FIFO for Sample Sequencer n has hit an overflow condition, meaning that the FIFO is full
and a write was requested. When an overflow is detected, the most recent write is dropped.
This bit is cleared by writing a 1.

ADC Event Multiplexer Select (ADCEMUX), offset 0x014

ADC0: sub r3, r5,r3;z

PE3: sampling: convert analog:
rcgc -> orr 0x01 udıv r4, r2, r1
rcgc -> orr 0x10: port e pssı -> orr 0x08: ss3 select r1, #1220
actss -> bic 0x08: disable seq. 3 mul r4, r4, r1;y
dir -> bix 0x08 : input loop RIS->ands 0x08 -> beq loop mul r5, r0, r1
emux -> bic 0xf000: sw trig sub r4, r2, r4
afsel -> orr 0x08 : enable ssfıfo3 -> get value r1, #10000
ssmux3 -> bic 0x000f: ain0 udıv r2, r1 ; x
amsel -> orr 0x08: analog ısc -> clear flag(write any value) udıv r5, r1
ssctl3 -> orr 0x06: interrupt/end lsl r2, #8
den -> bic 0x08: no digital r1, #10
pc -> orr 0x01 : 125ksps lsl r4, #4
udov r2, r5, r1
actss -> orr 0x08: enable seq3. add r2, r2, r4
mul r3, r2, r1
add r3, r3, r2 :xyz
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020

SSn: This field contains a binary-encoded value that specifies the priority encoding of Sample
Sequencer n. A priority encoding of 0x0 is highest and 0x3 is lowest.
ADC Sample Phase Control: ADCSPC

ADC Interrupt Mask (ADCIM), offset 0x008

DCONSSn=0 The status of the digital comparators does not affect the SSn interrupt status.
DCONSSn=1 The raw interrupt signal from the digital comparators (INRDC bit in the ADCRIS register)
is sent to the interrupt controller on the SSn interrupt line.
MASKn=0 The status of Sample Sequencer n does not affect the SSn interrupt status.
MASKn=1 The raw interrupt signal from Sample Sequencer 3 (ADCRIS register INRn bit) is sent to the
interrupt controller.
ADC Interrupt Status and Clear (ADCISC), offset 0x00C

DCINSSn=0 No interrupt has occurred or the interrupt is masked. Both the INRDC bit in the ADCRIS
register and the DCONSSn bit in the ADCIM register are set, providing a level-based interrupt to the
interrupt controller.
DCINSSn=1 This bit is cleared by writing a 1 to it. Clearing this bit also clears the INRDC bit in the
ADCRIS register.
INn=0 No interrupt has occurred or the interrupt is masked.
INn=1 Both the INRn bit in the ADCRIS register and the MASKn bit in the ADCIM register are set,
providing a level-based interrupt to the interrupt controller.
This bit is cleared by writing a 1. Clearing this bit also clears the INRn bit in the ADCRIS register.

ADC Raw Interrupt Status (ADCRIS), offset 0x004

INRn = 0 An interrupt has not occurred.

INRn = 1 A sample has completed conversion and if the respective ADCSSCTLn IEx bit is set,
enabling a raw interrupt.

This bit is cleared by writing a 1 to the INn bit in the ADCISC register.

ADC Peripheral Configuration (ADCPC), offset 0xFC4

 Serial I/O

Run Clock Gate Control Register for UART (RCGCUART) (address is 0x400FE618)

UART Data (UARTDR), offset 0x000

UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004

UART Control (UARTCTL), offset 0x030
UART Line Control (UARTLCRH), offset 0x02C
UART Flag (UARTFR), offset 0x018
 transmit: ands r0, #0x20; check txff =1
r4,=dr bne waitr : uart full, wait
loop ldrb r2,[r5],#1 str r2, [r4] : otherwise, send
cmp r2, #0x04 waitd
beq done
ldr r0,[r1]
waitr
ands r0,#0x08: check if busyy
r1,=fr
bne waitd
r0,[r1]
b loop

PA1: uart:
rcgc -> orr 0x01 ctl -> bic 0x01:disable
den -> orr 0x02 ibrd -> #104
amsel -> bic 0x02: disable fbrd -> #11
afsel -> orr 0x02: lcrh -> #0x74: 8bit/fifo/one start
pctl -> orr 0x10 : tx one stop/ even
ctl -> 0x00000101 : enable tx
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034

UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024

UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028

UART Interrupt Mask (UARTIM), offset 0x038

pa0: uart0:
rcgc-> orr 0x01 rcgc-> orr 0x01
den -> orr 0x01 ctl -> bic 0x01
amsel -> bic 0x01 ibrd -> #104
afsel -> orr 0x01 fbrd -> #11
pctl -> orr 0x01: rx10 lcrh ->#74
ctl -> #201: receiver enable

receiver:
r4, =dr
check
r1, =fr
r0, [r1]
ands r0, #0x10: rxfe=0 check
bne check: if no char. check
r5, [r4]: receive
bx lr
UART Raw Interrupt Status (UARTRIS), offset 0x03C

UART Interrupt Clear (UARTICR), offset 0x044