MSP432 ARM Timer

Programming

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An 8-bit up-counter stages

2
An 8-bit down-counter stages

3
Counter Mode of Operation of Timer

4
Compare Mode of Operation of Timer

5
Capture Mode of Operation of Timer

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 System Tick Timer

• 24 Bit Down Counter

• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz)
and invokes a SysTick routine.
• A high-speed alarm timer using the system clock.
• A simple counter used to measure time to completion and time used.

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 System Tick Timer Internal Structure

MCLK

24 Bit Down Counter

8
System Tick Counting

9
STRVR (STReload Value Register)
STCVR (STCurrent Value Register)

10
STCTRL (System Tick Control)

In MSP432P401R, External Clk is not implemented

MCLK only

SysTick->CTRL = 5 = 0101 11
if (SysTick->CTRL & 0x10000) // If COUNTFLAG is Set
 Delay Calculation using SysTick Timer

Delay = Reload Value (N) x Time taken by 1 Clk

= N x 1/MCLK
Example : For Generating 1Hz or 1Sec Delay, Reload Value (N) = ?
Delay = N x 1/MCLK
N = Delay x MCLK
= 1Sec x 30,00,000 Hz
= 30,00,000

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 Timer32 Timer

• Features of Timer32:
• Two independent counters (T1 & T2) each configurable as 32-bit or 16-bit Down
Counter
• Three different timer modes supported for each counter
• Prescale unit to divide the input clock by 1, 16 or 256
• Independent Interrupts from each of the counter, as well as, a combined interrupt
from both the counters
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 Mode of Operation

• For each of the timers, the following modes of operation are available:
• Free-running mode: The counter wraps after reaching its zero value, and
continues to count down from the maximum value. This is the default mode.
• Periodic/Wrapping timer mode: The counter generates an interrupt at a
constant interval, reloading the value from T32LOADx register.
• One-shot timer mode: The counter generates an interrupt once. When the
counter reaches zero, it halts until reprogrammed by the user.

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Counting in Free-Running Mode vs. Periodic/Wrapping Mode

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 Timer32 Timer Internal Structure

MCLK

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 Timer32 Registers
Offset Acronym Register Name Type Reset Value
00H T32LOAD1 Timer 1 Load Register RW 0
04H T32VALUE1 Timer 1 Current Value Register R FFFFFFFFH
08H T32CONTROL1 Timer 1 Timer Control Register RW 20H
0CH T32INTCLR1 Timer 1 Interrupt Clear Register W -
10H T32RIS1 Timer 1 Raw Interrupt Status Register R 0
14H T32MIS1 Timer 1 Interrupt Status Register R 0
18H T32BGLOAD1 Timer 1 Background Load Register RW 0
20H T32LOAD2 Timer 2 Load Register RW 0
24H T32VALUE2 Timer 2 Current Value Register R FFFFFFFFH
28H T32CONTROL2 Timer 2 Timer Control Register RW 20H
2CH T32INTCLR2 Timer 2 Interrupt Clear Register W -
30H T32RIS2 Timer 2 Raw Interrupt Status Register R 0
34H T32MIS2 Timer 2 Interrupt Status Register R 0
38H T32BGLOAD2 Timer 2 Background Load Register RW 0H
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 T32CONTROLx Register

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TIMER32_1->CONTROL = 0xC2 = 0x1100 0010;
T32RISx (T32 Raw Interrupt Status) Register

while((TIMER32_1->RIS & 1) == 0);

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T32LOADx & T32VALUEx Register

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T32INTCLRx Register

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 Delay Calculation using Timer32

Delay = Prescalar x Load Value (N) x Time taken by 1 Clk

= P x N x 1/MCLK
Example : For Generating 1Hz or 1Sec Delay (Assume P = 1), Load Value (N) = ?
Delay = P x N x 1/MCLK
N = (Delay x MCLK)/P
= (1Sec x 30,00,000 Hz)/1
= 30,00,000

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 Timer A Timer

• Timer A features :
• Asynchronous 16-bit timer/counter with four operating modes
• Selectable and configurable clock source
• Up to seven configurable capture/compare registers
• Configurable outputs with pulse width modulation (PWM) capability
• Asynchronous input and output latching
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TimerA Modes of Operation

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Counting in Up Mode

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Counting in Continuous Mode

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Counting in Up/Down Mode

Used for PWM Generation

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Timer_A Simplified Diagram
Four 16 Bit Timer A

TAxCTL.ID (Input Divider)

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A more detailed diagram of Timer_A

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TAxR register

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TAxCTL register

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bit Name Description
TAxCTL register
Timer_A Interrupt Flag
0 TAIFG 0: Timer did not overflow
1: Timer overflowed (TAIFG will be cleared on writing one to this bit)
1 TAIE Timer_A Interrupt Enable (0: Disabled, 1: Enabled)
2 TACLR 0: Timer_A Not Clear, 1: Timer_A Clear
Mode Control:
00: Stop mode: timer is halted
4-5 MC 01: Up mode: Timer counts up to TAxCCR0
10: Continuous mode: Timer counts up to 0xFFFF
11: Up/down mode: Timer counts up to TAxCCR0 then down to 0.
Input divider: These bits select the divider for the input clock:
00: divide by 1
6-7 ID 01: divide by 2
10: divide by 4
11: divide by 8
Timer_A clock Source Select: These bits select the Timer_A clock source:
00: TAxCLK (external clock): The timer uses external clock which is fed to the
PM_TAxCLK pin. (Counter Mode)
8-9 TASSEL
01: ACLK (internal clock)
10: SMCLK (internal clock)
11: INCLK (Counter Mode)
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TIMER_A1->CTL = 0x02D1 = 0000 0010 1101 0001
 TAxEXn Register

TIMER_A1->EX0 = 7; // Divider 2 = TAIDEX+1 = 7+1 = 8 33

TAxCCRn Registers and TAxCCTLn Flags

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TAxCCRn Register

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 Delay Calculation using Timer A

Delay = TAxCCR0 x 2ID x (TAIDEX + 1) x Time taken by 1 Timer A Clk

= TAxCCR0 x 2ID x (TAIDEX + 1) x (1/SMCLK)
Example : For Generating 1Hz or 1Sec Delay (Assume 2ID = 8, TAIDEX = 7),
TAxCCR0 = ?
Delay = TAxCCR0 x 2ID x (TAIDEX + 1) x (1/SMCLK)
TAxCCR0 = (Delay x SMCLK) / (2ID x (TAIDEX + 1))
= (1Sec x 30,00,000 Hz)/(8 x (7+1))
= 46,875
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TAxCCTLn Capture/Compare Control Register

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 TAxCCTLn Register
bit Name Description
Capture mode
00: No capture
15-14 CM 01: Capture on rising edge
10: Capture on falling edge
11: Capture on both rising and falling edges
Capture/compare input select. These its select the TAxCCR0 input signal:
00: CCIxA
13-12 CCIS 01: CCIxB
10: GND
11: VCC
Synchronize capture source. This bit is used to synchronize the capture input signal with the
timer clock.
11 SCS
0: Asynchronous capture
1: Synchronous capture

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 TAxCCTLn Register
bit Name Description
Synchronized capture/compare input. The selected CCI input signal is latched
10 SCCI
with the EQUx signal and can be read via this bit.
Capture mode
8 CAP 0: Compare mode
1: Capture mode
Output mode. Modes 2, 3, 6, and 7 are not useful for TAxCCR0 because
EQUx = EQU0
000: OUT bit value
001: Set
OUTM 010: Toggle/reset
7-5
OD 011: Set/reset
100: Toggle
101: Reset
110: Toggle/set
111: Reset/set

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 TAxCCTLn Register
bit Name Description
Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding
CCIFG flag.
4 CCIE
0: Interrupt disabled
1: Interrupt enabled
3 CCI Capture/compare input. The selected input signal can be read by this bit.
Output. For output mode 0, this bit directly controls the state of the output.
2 OUT 0: Output low
1: Output high
Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with
software.
1 COV
0: No capture overflow occurred
1: Capture overflow occurred
Capture/compare interrupt flag
CCIF
0 0: No interrupt pending
G
1: interrupt pending

while((TIMER_A1->CCTL[0] & 1) == 0); 40