St.

Thomas' College of Engineering and Technology

DEPARTMENT OF
INFORMATION TECHNOLOGY
Laboratory Manual
Computer Architecture
PCC-CS492

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 General Information

Computer Architecture
Course Name Semester IV
Lab
Course Code PCC-CS492 Year with stream 2ndyear IT
Course Credit 2 Session 2020-2021
Faculty Class hours and
4 hrs.
Instructor/s total class load
Technical
Laboratory
assistant/s

1. To provide knowledge of hardware simulation for both structural and behavioral

approach.
2. To provide knowledge of combinational systems composed of standard combinational
Course
modules, such as multiplexers, decoders etc.
objectives
3. To provide knowledge of sequential systems composed of standard sequential modules,
such as counters and registers.

Course Outcomes Bloom’s Level

CO 1 Apply the knowledge of hardware simulation for both structural and Apply
behavioral approach.
CO 2 Choose proper combinational modules, such as multiplexers, Apply
decoders etc. to develop a complex combinational system
CO 3 Build sequential systems composed of standard sequential modules, Apply
such as counters and registers.
CO 4 Analyze complex circuit and break them into smaller module and Analyzing
implement.
CO 5 Understand interfacing of peripheral devices with controller. Understanding

CO 6 Design & Develop any digital design interface using HDL Create

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CO-PO-PSO matrix of the course:

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
CO1
CO2
CO3
CO4
CO5
CO6

Recommended 1. J.Bhasker, B.S.Publications, “A Verilog HDL Primer”.

books 2. Samir Palnitkar, “Verilog HDL A guide to Digital Design and Synthesis”,
Prentice Hall; 2 edition (March 3, 2003).

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List of Experiments

Expt. Name of Experiment Page Date of Grade Signature

No. Number Expt. awarded
1 Familiarization with Data types
and basic gates
2 Tristate Buffer

3 Boolean Logic Equations

4 Combinatorial circuit I

5 Combinatorial circuit II

6 Code converter and familiarization

with behavioral approach.
7 Arithmetic operations I

8 Arithmetic operations II

9 Sequential logic circuits

10 Counters

11 Shift Register& GPR

12 Main Memory Design

13 Design of ALU

14 Moore FSM Sequence Detector

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LAB SESSION 01

Title:Familiarization with Data types

Objective: Familiarization with different data types.
Theory:

Net Data Type

Net data types are used to model connections in structural descriptions. They do not store values
(except trireg). The net data types have the value of their drivers.

The Verilog defines the following net types:

wire or tri simple interconnecting wire

wor or trior wired outputs OR together
wand or triand wired outputs AND together
tri0 pulls down when tri-stated
tri1 pulls up when tri-stated
supply0 constant logic 0 (supply strength)
supply1 constant logic 1 (supply strength)
trireg stores last value when tri-stated (capacitance strength)

A net data type must be used when:

• A signal is driven by the output of some device.
• A signal is also declared as an input or inout port.
• A signal is on the left-hand side of a continuous assignment.

Example:
wire [7:0] Data; // Array declaration
wire [7:0] data [0:7] // Two dimensional array
wire [7:0] Array [0:255][0:255][0:255]; // Multidimensional array

Notes:
• supply1 and supply0 are used to declare power and ground nets only.

Register Data Type

• Register data types store values.

Syntax:
• register_type [ size ]variable_name, variable_name, ...;
• register_type [ size ]variable_name = initial_value;
• register_type [ size ]memory_name [ array_size ];
• register_type [ size ]memory_name [ array_size ] [ array_size ] ...; //
Multi-dimensional array

Description:

• Register data types are used as variables in procedural blocks. They store logic values only (no
logic strength).
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The Verilog defines the following register types:

Reg unsigned variable of any bit size

Integer signed 32-bit variable
Time unsigned 64-bit variable
real or realtime double-precision floating point variable

• A register data type must be used when the signal is on the left-hand side of a procedural
assignment.
• Verilog-2001 adds the ability to initialize variables at the time they are declared. The initial value
assigned to the variable takes effect at simulation time zero, just as if the value had been assigned
within an initial block.

Example:
• reg [7:0] Data;
• integer Int;
• time Now;
• reg [15:0] Memory [0:1023];
• reg [7:0] A = 8'h3C;
• reg [7:0] Array [0:255][0:255][0:255];

Use reg for describing logic, integer for loop variables and calculations, real in system modules,
and time and realtime for storing simulation times in testbenches.

Verilog Operators:

Continuous Assignment
A continuous assignment drives a value into a net.

Syntax:
net_data_type [ strength ] [ delay ] [ size ] net_name = expression; // implicit
assign [ strength ] [ #( delay ) ] net_name = expression; // explicit

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Description:
Continuous assignments model combinational logic. Each time the expression changes on the right-hand side, the
right-hand side is re-evaluated, and the result is assigned to the net on the left-hand side.

The implicit continuous assignment combines the net declaration (see Net data type) and continuous assignment into
one statement. The explicit assignment require two statements: one to declare the net (see Net data type), and one to
continuously assign a value to it.

Continuous assignments are not the same as procedural continuous assignments. Continuous assignments are
declared outside of procedural blocks. They automatically become active at time zero, and are evaluated concurrently
with procedural blocks, module instances, and primitive instances.

Example:
wire Q = A || B; // continuous assignment
wire Out;
assign Out = A & B;
assign {COut, Sum} = A + B + CIn;
wire #50 Out = A & B;

Problem statement:
Write verilog programs to design, simulate and test the following circuits:
a) Basic gates
b) Universal gates
c) Exclusive gates

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Questionnaires:
1.1. What is the difference between wire and reg?
1.2. Which of the following statements is true for Verilog modules?
a. A module can contain definitions of other modules.
b. When a module X is called multiple numbers of times from some other module, only one copy
of module X is included in the hardware after synthesis.
c. More than one module can be instantiated within another module.
d. If a module X is instantiated 4 times within another module, 4 copies of X are created.
1.3. For the following Verilog code segment, what will be the number of bits in C as deduced during
synthesis?
wire [9:0] A, B;
integer C;
C = A + B + 1;

The assignment covers COs _________________________________________________

Teacher’s signature with date :

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LAB SESSION 02
Title: TERNARY OPERATOR
Objective: Introduction to ternary operator
Theory:
Procedural Assignment
A procedural assignment updates the value of register data types.
Syntax:
[ delay ]register_name = [ delay ] expression; // blocking
[ delay ]register_name<= [ delay ] expression; // non-blocking
Description:
Procedural assignments are used for updating register data types and memory data types.
The expression in a blocking procedural assignment is evaluated and assigned when the statement is encountered. In
a begin-end sequential statement group, execution of the next statement is blocked until the assignment is complete.
In a non-blocking procedural assignment, the expression is evaluated when the statement is encountered, and
assignment is postponed until the end of the time-step. In a begin-end sequential statement group, execution of the
next statement is not blocked and may be evaluated before the assignment is complete. A group of statements with a
non-blocking assignment has similar functionality as a group of statements within a fork-join block.
The left-hand side of a procedural assignment should be one of the following:

• Register data type: reg, integer, time, real or realtime.

• Bit-select of reg, integer or time.
• Part-select of reg, integer or time.
• Memory word.
• Concatenation of any of the above.

When the right-hand side evaluates to a fewer bits than the left-hand side, the assignment to a reg does not
sign-extend.
The evaluation of the assignment is delayed by the delay when the delay is specified before the register name. When
the delay is specified before the expression, the expression is evaluated when the statement is encountered, and
assigned in the time-step specified by the delay.
Example:
begin
a = 0;
#10 a = 1;
#5 a = 2;
end // time 0: a=0; time 10: a=1; time 15 (#10+#5): a=2;
begin
a <= 0;
#10 a <= 1;
#5 a <= 2;
end // time 0: a=0; time 5: a=2; time 10: a=1;
begin
a <= b;
b <= a;
end // both assignments are evaluated before a or b changes
Useful statement: assign out = sel ? 0:1;assigns the value of out as 0 if selis 1 and the value of out as 1 when selis 0.

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2.1 A Tristate Buffer

Statement: Write a Verilog program to design, simulate and test a circuit ofa tri-state buffer having following
properties:
• Take 1-bit Input as I
• Control Input (CNT’)
• Output is Z
------------------------------------------------------------------------------------------------------------------------------
2.24-bit Unidirectional Bus

Statement: Write a Verilog program to design, simulate and test a circuit ofa 4-bit unidirectional bus circuithaving
following properties: [Hint: use 2.1 module initiation in the coding]
• Take 4-bit Input as I
• Control Input (CNT’)
• Output is Z (4-bit)
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Questionnaires:

1.1. What are the differences between blocking and non-blocking assignments?
1.2. Write averilogcode to swap contents of two registers with and without atemporary register?
1.3. What is the difference between === and == ?
 

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 03
Title: MINIMIZATION TECHNIQUES
Objective: Implementation of Boolean function and Logic Equations

Problem statement:
3.1 Majority Circuit

A majority circuit is a combinatorial circuit whose output is equal to 1 if the input variables have more
1’s than 0’s. Design a 3-input majority circuit.

Statement: Write a Verilog program to design, simulate and test a circuit of3-input majority circuit
having following properties:
• Take 3-bit Input as A2A1A0
• Output as Z
---------------------------------------------------------------------------------------------------------------------------
3.2 Two’s complementer

Design a 4-bit combinational circuit for implementing 2’s complement. Show that the circuit can be
constructed using exclusive-OR gates.

Statement: Write a Verilog program to design, simulate and test a circuit of4-bit 2’s complement circuit
having following properties:
• Consider 4-bit input as (A3A2A1A0) and 4-bit output as (B3B2B1B0).
• Form the truth table for 4-bit 2’s complementer circuit.
• Use the minimal sum-of-products(SOP) method to derive the logic for the 4-bit output
(B3B2B1B0).
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3.3 Function minimization
A) Statement:Implement the Boolean function: F(A, B, C, D)= Σ (0, 1, 3, 4, 8, 9,15) using a Verilog
program and test the above circuit.

B) Statement: Write a Verilog program to design, simulate and test a combinatorial circuit with 3-bit
input as A2A1A0 and 3-bit output as B2B1B0. When the binary input is 0, 1, 2, or 3, the binary output
is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less than
the input.

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Questionnaire:

3.1. Explain difference between $monitor, $display

3.2. Given the following verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1;
$display(a);
end
3.3. For the following Verilog code segment, if the initial value of IR is ABCD3456 (in hexadecimal),
the value of “data” in decimal will be ………….. (Note that “data” is a 4-bit variable)
wire [31:0] IR;
wire [3:0] data;
wire [15:0] d1;
wire [31:16] d2;
assign d1 = IR[31:16];
assign d2 = IR[15:0];
assign data = d1[11:8] + d2[19:16] + d2[31:28];

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 04
Title: COMBINATIONAL CIRCUITS
Objective: Implementation of combinational circuits.

Problem statement:
4.1 Multiplexer (4 to 1)
Statement:Write a Verilog program that implements Multiplexer module (4x1 MUX).
---------------------------------------------------------------------------------------------------------------------------
4.2 8-to-1 multiplexer
Statement: Write a Verilog program that includes above module (4x1 MUX) to describe the functionality
of 8-1 multiplexer circuit.
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4.3 Decoder (3 to 8)
Statement: Write a verilog code to design, simulate and test a circuit of 3 to 8 decoder.

Instruction: Use the following skeleton for your module

module deco3_8(a, b, c, out, en);

Input a,b,c,en;
Output [3:0] out;
……….
endmodule
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Truth Table/ Functional Table& Circuit/Block Diagram:

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Questionnaires:

4.1. What is the difference between the following two lines of verilog code?
#5 a = b;
a = #5 b;
4.2. What do we mean by continuous assignment?
4.3. For the following Verilog code segment:
wire [7:0] A;
wire B;
assign B = ^A;

if the value of A is 16’b10110011, what will be the value of {A[4:3], 3{B}}?

a. 5’b10111 b. 5’b10000 c. 5’b01000 d. None of the above

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 05

Title: COMBINATIONAL CIRCUITS

Objective: Implementation of combinational circuits.
Problem statement:
5.1 Function implementation using Decoder
A combinational circuit is specified by following three Boolean functions:
F1 = Σ (2, 4, 7)
F2 = Σ (0, 3)
F3 = Σ (0, 2, 3, 4, 7)
Statement: Write a hardware description language to implement the circuit with a decoder constructed
with NAND and NAND or AND gates connected to the decoder outputs. Use a block diagram for the
decoder. Minimize the number of inputs in the external gates.
-------------------------------------------------------------------------------------------------------------------------
5.2 Priority Encoder
If more than two inputs are active simultaneously, the output is unpredictable or rather it is not what we
expect it to be.This is resolved if priority is established so that only one input is encoded, no matter how
many inputs are active at a given point of time. The priority encoder includes a priority function, if two or
more inputs are active at a time, the input having the highest priority will take precedence.
Statement: Write a verilog code to design, simulate and test a circuit of a 4 to 3 Priority encoder.
-------------------------------------------------------------------------------------------------------------------------
5.3 Magnitude Comparator
Statement: Write a verilog code to design, simulate and test a circuit of 4 bit magnitude comparator.

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Truth Table/ Functional Table/ Circuit/Block Diagram:

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Questionnaires:

5.1. What is meant by inferring latches and how to avoid it?

5.2. What is casex and casez statement?

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 06
Title: CODE CONVERTER
Objective: Implementation of code converter and familiarization with behavioral approach.

Problem statement:
6.1 Code conversion

A) Binary-to-BCD Converter
B) Binary to gray code converter
C) Gray code to binary converter
D) Binary to Excess-3 code converter
E) Excess-3 code to binary converter

Statement: Write a verilog code to design ,simulate and test the circuits of the above Converters (4 bit).

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Questionnaires:

6.1. For the following code segment, the final value of variable “Z” will be ……. Justify your answer.

Integer X, Y, Z;
Initial
Begin
X=33; Y=27; Z= 16;
Y <= #10 X- Z;
X<= #10 Y * 5;
Z<= #10 X + Y
End

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 07

Title: ARITHMETIC OPERATION

Objective: Implementation of Arithmetic operations.

Problem statement:
7.1Half Adder

Statement:Write a Verilog program to design, simulate and test the functionality of a half adder circuit.

---------------------------------------------------------------------------------------------------------------------------

7.2 Full Adder

Statement:Write a Verilog program to design, simulate and test the functionality of a full adder circuit.
---------------------------------------------------------------------------------------------------------------------------

7.3 4-bit Adder/subtractor

Statement:Write a hardware description to design, simulate and test the functionality of the 4-bit
adder/subtractor circuit.
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Questionnaires:

7.1. If the 8-bit variable “x” declared as “reg [7:0] x” is initialized to 8’b 10101101, what will be its value
after executing the following code segment?
always @(posedge clock)
begin
x <= x << 1;
x[0] <= x[7];
end

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 08
Title: ARITHMETIC OPERATION
Objective: Implementation of Arithmetic operations

Problem statement:
8.1 Incrementer Circuit (4-bit)

Statement:Write a verilog program to design, simulate and test the functionality of the 4-bit incrementer
circuit.
------------------------------------------------------------------------------------------------------------------------
8.2 Decrementer Circuit (4-bit)

Statement:Write a verilog program to design, simulate and test the functionality of the 4-bit decrementer
circuit.
------------------------------------------------------------------------------------------------------------------------

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Questionnaires:

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 09
Title: SEQUENTIAL LOGIC
Objective: Implementation of Sequential logic

Problem statement:
9. Flip Flops

Statement: Write a Verilog program to design, simulate and test the circuits of the following flip-flops

A) D Flip Flop
B) S-R Flip Flop
C) J-K Flip Flop
D) T Flip Flop
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Questionnaires:

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 10
Title: COUNTERS
Objective: Implementation of Counters

Problem statement:
10.Statement: Write a Verilog program to design, simulate and test the following counters.

A) 4-bit Up-Down Counter

B) Random counter
C) Mod-10 Counter
D) Ring Counter
E) Johnson Counter
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Questionnaires:

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 11
Title:Shift Register
Objective: Implementation of Shift Registers and GPR

Problem statement:
11.Statement: Write a verilog program to design, simulate and test the following registers.

A) SISO
B) SIPO
C) PISO
D) PIPO
E) GPR
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Questionnaires:

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 12
Title:Main Memory
Objective: Implementation of Main Memory

Problem statement:
12.1 RAM Realization

Statement: Write a Verilog program to model a RAM memory cell with all the following considerations.

• Read / write signal(WE’)

• Address line(A)
• Select line(EN’ active low)
• Data I/P (DI)
• Data O/P (DO)
----------------------------------------------------------------------------------------------------------------------------
12.2 RAM Cascading
Statement:Write a Verilog program to do the following expansions using 12.1 module initiations in the
coding.
A) Horizontal Expansion
B) Vertical Expansion
C) Hybrid Expansion
------------------------------------------------------------------------------------------------------------------------------
12.3 ROM Realization

Statement: Write a Verilog program to model a ROM memory cell with all the following considerations.

• Read signal(RD’)
• Address line (A)
• Select line (EN’ active low)
• Data I/P (DI)
• Data O/P (DO)

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Questionnaires:

The assignment covers COs _________________________________________________

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Teacher’s signature with date :

LAB SESSION 13
Title:Arithmetic and Logical Unit (ALU)

Objective: Implementation of ALU

Problem statement:
13.Statement:Write a verilog program to implement an 8-bit ALU which will perform the following
functional table.
Functional Table:
Sl no. Operation Remarks
0 A-B Without carry
1 A+B
2 A+B+Cin
3 A-B+(~Cin) With carry
4 A^B A xorB
5 ~B B’
6 A|B AOR B
7 A&B A AND B

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Questionnaires:

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The assignment covers COs _________________________________________________

Teacher’s signature with date :

LAB SESSION 14
Title:Moore FSM Sequence Detector

Objective: Implementation of Sequence Detector

Problem statement:
The Moore FSM keeps detecting a binary sequence from a digital input and the output of the FSM goes
high only when a "1011" sequence is detected. The state diagram of the Moore FSM for the sequence
detector is shown in the following figure.

Fig. 14.1. State diagram of FSM

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Questionnaires:

14.1 Differentiate between two types of FSMs.

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The assignment covers COs _________________________________________________

Teacher’s signature with date :

Loops in Verilog
1. While loop
A while statement executes the code within it repeatedly if the condition it is assigned to check returns true.
While loops are normally not used for models in real life, but they are used in test benches. As with other
statement blocks, they are delimited by begin and end.
always @ (posedgeclk or posedgerst)
if (rst) begin
count <= 0;
end
else begin
while (enable) begin
count <= count + 1;
end
end
---------------------------------------------------------------------------------------------------------------------------
2. For loop
For loops in Verilog are almost exactly like for loops in C or C++. The only difference is that the ++ and --
operators are not supported in Verilog. Instead of writing i++ as you would in C, you need to write out its
full operational equivalent, i = i + 1.

for (i = 0; i< 16; i = i +1) begin

$display ("Current value of i is %d", i);
End
---------------------------------------------------------------------------------------------------------------------------
3. Repeat loop
Repeat is similar to for loop. Instead of explicitly specifying a variable and incrementing it when we
declare for loop, we tell the program how many times to run through the code, and no variables are
incremented (unless we want them to be, like in this example).
repeat (16) begin
$display ("Current value of i is %d", i);
i = i + 1;
end
------------------------------------------------------------------------------------------------------------------------------
Time directive
The `timescale compiler directive is used to tell Verilog compilers how to process certain delay (#)
statements in the code.
Syntax:
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`timescale time_unit / time_precision

Example:
`timescale 10ns/1ns

Test Bench in Verilog

We need to test it to see if it works according to specifications. Let's look at the Module Under Test (MUT)
testbench.

module MUT (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);

// Testbench Code Goes here

module MUT_tb;

reg clock, reset, req0,req1;

wire gnt0,gnt1;

initial begin
$monitor ("req0=%b,req1=%b,gnt0=%b,gnt1=%b", req0,req1,gnt0,gnt1);
clock = 0;
reset = 0;
req0 = 0;
req1 = 0;
#5 reset = 1;
#15 reset = 0;
#10 req0 = 1;
#10 req0 = 0;
#10 req1 = 1;
#10 req1 = 0;
#10 {req0,req1} = 2'b11;
#10 {req0,req1} = 2'b00;
#10 $finish;
end

always begin
#5 clock = ! clock;
end

MUT U0 (
.clock (clock),
.reset (reset),
.req_0 (req0),
.req_1 (req1),

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.gnt_0 (gnt0),
.gnt_1 (gnt1)
);

endmodule

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