Exp. No.

8: MULTIPLEXERS & DEMULTIPLEXERS Logic Laboratory

MULTIPLEXERS & DEMULTIPLEXERS

Object: To study the function of multiplexer and demultiplexer circuits.

Theory:
(A) Multiplexer (Data selector):
A multiplexer (MUX) is a device that allows digital information from several sources
to be routed onto a single line for transmission over that line to a common destination. The
basic multiplexer, then, has several data input lines and a single output line. It also has
data selector inputs that permit digital data on any one of the input to be switched to the
output line.
A simple multiplexer can be represented by a switch operation that sequentially
connects each of the input lines with the output, as illustrated in Fig.(8-1).

HIGH A T1
HIGH
Inputs LOW B LOW
T2 T1 T2 T3
HIGH C
T3

Fig. (8-1) Simple Multiplexer operation

Assume that we have logic levels an indicated on the three inputs.

D0
MUX
Data D1 Y
Inputs D2 Data Output
D3
S1 S0

Data select
Fig. (8-2) Logic symbol for 4-to-1 data selector

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If a binary 0 (S1=0 and S0=0) is applied to the data-select lines, the data on input D0 appear
on the data-output line. If a binary 1 (S1=0 and S0=1) is applied to the data-select lines, the
data on the input D1 is appear on the data output. If a binary 2 (S1=1 and S0=0) is applied, the
data on D2 appear on the output. If a binary 3 (S1=1 and S0=1) is applied, the data on D3 are
switched to the output line. A summary of this operation is given in table (8-1).
DATA-SELECT INPUTS INPUT
S1 S0 SELECTED
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Table (8-1) Data selection for a 4-input Multiplexer

The data output Y is equal to the data input D0 if and only if S1=0 and S0=0;
Y  D0 S1 .S 0

The data output Y is equal to D1 if and only if S1=0 and S0=1;

The data output is equal to D2 if and only if S1=1 and S0=0;

The data output is equal to D3 if and only if S1=1 and S0=1;

These terms are (OR)ed, the total expression for the data output is:
Y= D0 S1 .S 0 + D1 S1 .S 0 + D2 S1 .S 0 + D3 S1 .S 0

The implementation of this equation is shown in Fig. (8-2).

S0 •
S1 •
• •
D0

D1 • Y

D2 •

D3
Fig. (8-2) Logic diagram for a 4-input Multiplexer

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Exp. No. 8: MULTIPLEXERS & DEMULTIPLEXERS Logic Laboratory

(B) Demultiplexer:
A demultiplexer (DMUX) basically reverses the multiplexing function. It takes data
from one line and distributes them to a given number of output lines. Fig. (8-3) shows a one-
line to four-line demultiplexer block diagram.

DMUX
Data Data Output
Input Lines
S1 S0

Data select
Fig. (8-3) Logic symbol 1-line to 4-line demultiplexer

Fig. (8-4) shows a 1-line-to-4-line demultiplexer circuit. The two select lines enable only one
gate at a time, and the data appearing on the input line will pass through the selected gate to
the associated output line.

Select S0 •
lines S1 •
• • D0
Data input •

• • D1
Data output
lines
• •
D2

D3

Fig. (8-4) A 1-to-4-line demultiplexer

Procedure:

(A) Multiplexer:
1. Connect a circuit of 2-to-1 multiplexer and observe its table.
2. Connect the circuit of Fig. (8-2) and observe its table.

(B) Demultiplexer:
1. Connect the circuit of Fig. (8-4) and observe its table.

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Discussion:
1. The data input and data select waveforms in Fig. (8-5) are applied to the multiplexer in
Fig. (8-2). Determine the output waveform in relation to the input.

D0

D1

D2

D3

S0
S1

Fig. (8-5)

2. The serial data input waveform and data selectors are shown in Fig. (8-6). Determine the
data-output waveform for the demultiplexer shown in Fig. (8-4).

Data input

S0

S1

Fig. (8-6)

3. Design 8-to-1 MUX and verify its truth table.

4. Design 1-to-8 DEMUX and verify its truth table.

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