DIGITAL ELECTRONICS

Multiplexers & Demultiplexers

Syllabus:

• Block Diagram, Truth Table, Logical Expression and Logic Diagram of Multiplexer (4:1 and
8:1), Design of 8:1 using 2 4: 1 Mux, Multiplexer ICs.
• Block Diagram, Truth Table, Logical Expression and Logic Diagram of Demultiplexer (1:4, 1:8,
1:16), Demultiplex ICs.

Questions:

1. What is multiplexer? (2)

2. Design a 16:1 Multiplexer using 4:1 MUX and OR gate. (3)
3. Design a 16:1 Multiplexer using 8:1 and 2:1 MUX. (3)
4. Design a 4:1 MUX using 2:1 MUX. (3)
5. Design 8:1 MUX using logic gates. (5)
6. Design 8:1 MUX by using 4:1 MUXs only. (5)
7. Design 8:1 MUX with enable input. (5)
8. Implement a full adder using two 4:1 MUX. (4)
9. Show that you can implement full adder circuit by using two 8:1 MUX only. (5)
10. Implement the following functions with an 8:1 MUX
𝑓(𝑊, 𝑋, 𝑌, 𝑍) = ∑ 𝑚(0,1,3,4,5,8,9,15) (5)
11. Implement the following functions with an 8:1 MUX
𝑓(𝐴, 𝐵, 𝐶) = Π𝑀(2,4,5,7) (5)
12. Realize the following expression using multiplexer: 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0,1,3,4,8,9,15) (5)

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Multiplexers & Demultiplexers

Multiplexers:

The term ‘multiplex’ means ‘many into one’. Multiplexing is the process of transmitting a large
number of information over a single line. A digital multiplexer (MUX) is a combinational circuit that
selects one digital information from several sources and transmits the selected information on a
single output line. The selection of a particular input line is controlled by a set of selection line or
control inputs.

Block diagram

Number of input lines = n

Number of select lines = m
Number of output line = 1
Condition ⇒ 𝑛 = 2𝑚

4:1 MUX:

Data select inputs outputs

𝑆1 𝑆0 Y
0 0 𝐷0
0 1 𝐷1
1 0 𝐷2
1 1 𝐷3

𝑌 = 𝐷0 𝑆1̅ 𝑆0̅ + 𝐷1 𝑆1̅ 𝑆0 + 𝐷2 𝑆1 𝑆0̅ + 𝐷3 𝑆1 𝑆0

2:1 MUX:

Data select inputs outputs

𝑆0 Y
0 𝐷0
1 𝐷1

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𝑌 = 𝐷0 𝑆0̅ + 𝐷1 𝑆0

8:1 MUX:

Data select inputs outputs

𝑆2 𝑆1 𝑆0 𝑌
0 0 0 𝐷0
0 0 1 𝐷1
0 1 0 𝐷2
0 1 1 𝐷3
1 0 0 𝐷4
1 0 1 𝐷5
1 1 0 𝐷6
1 1 1 𝐷7

𝑌 = 𝐷0 𝑆2̅ 𝑆1̅ 𝑆0̅ + 𝐷1 𝑆2̅ 𝑆1̅ 𝑆0 + 𝐷2 𝑆2̅ 𝑆1 𝑆0̅

+ 𝐷3 𝑆2̅ 𝑆1 𝑆0 + 𝐷4 𝑆2 𝑆1̅ 𝑆0̅
+ 𝐷5 𝑆2 𝑆1̅ 𝑆0 + 𝐷6 𝑆2 𝑆1 𝑆0̅
+ 𝐷7 𝑆2 𝑆1 𝑆0

2:1 MUX as an Inverter:

𝑌 = 1. 𝐴̅ + 0. 𝐴 = 𝐴̅

2:1 MUX as a 2 – input XOR gate:

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𝑌 = 𝐵. 𝐴̅ + 𝐵̅. 𝐴 = 𝐴 ⊕ 𝐵

Implementation of higher order MUX using lower order MUX:

1. Implementation of 4:1 MUX using 2:1 MUX:

2. Implementation of 8:1 MUX using 2:1 MUX:

3. Implementation of 16:1 MUX using 8:1 MUX:

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Multiplexers & Demultiplexers

Implementation of lower order MUX using higher order MUX:

1. Implementation of 2:1 MUX using 4:1 MUX:

Truth table:

𝑆1 𝑆0 𝑌 𝑆0 𝑌
0 0 𝐷0 ⇒ 0 𝐷0
1 1 𝐷3 1 𝐷1

2. Implementation of 4:1 MUX using 8:1 MUX

Truth table:

𝑆2 𝑆1 𝑆0 𝑌 𝑆1 𝑆0 𝑌
0 0 0 𝐷0 0 0 𝐷0
0 1 1 𝐷3 ⇒ 0 1 𝐷1
1 0 0 𝐷4 1 0 𝐷2
1 1 1 𝐷7 1 1 𝐷3

Implementation of Boolean expression using MUX:

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1. Convert the logical expression into canonical minterms.

2. Select appropriate MUX.
(Number of variables in Boolean expression = number of select lines or control inputs. ∴
Requirements ⇒ 2𝑉𝑎𝑟𝑖𝑎𝑏𝑙𝑒 : 1 MUX)
3. Variables are connected to the select lines.
4. Put 1 to the corresponding inputs according to the minterms present in the expression and
put 0 to the other inputs.

Example: 𝑓 = ∑ 𝑚(0,3,5,6,7,12,13)

Number of variables (i.e., bits) required to write 13

are 4.

∴ It is a 4 variable expression (A, B, C, D).

Requirements ⇒ 24 : 1 MUX i.e., 16: 1 MUX.

If 𝟐𝑽𝒂𝒓𝒊𝒂𝒃𝒍𝒆 : 𝟏 MUX is not available but 𝟐𝑽𝒂𝒓𝒊𝒂𝒃𝒍𝒆−𝟏 : 𝟏 MUX is available.

Example: 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0,1,3,4,8,9,15) ⇒ 16:1 MUX is not available; we have to implement

this expression using 8:1 MUX.

1. Connect variable A, B and C to the select lines.

2. Draw the truth table of the logical expression and write down the dependency relation of f
with D i.e., f(D).
3. Now, construct a truth table which depends on A, B, C and f(D).
4. Corresponding f(D) values are connected to the inputs of MUX.

A B C D f f(D) A B C f(D)
0 0 0 0 1 0 0 0 1
1
0 0 0 1 1 0 0 1 D
0 0 1 0 0 0 1 0 D̅
D
0 0 1 1 1 0 1 1 0
0 1 0 0 1 ̅ 1 0 0 1
D
0 1 0 1 0 1 0 1 0
0 1 1 0 0 1 1 0 0
0
0 1 1 1 0 1 1 1 D

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1 0 0 0 1
1
1 0 0 1 1
1 0 1 0 0
0
1 0 1 1 0
1 1 0 0 0
0
1 1 0 1 0
1 1 1 0 0
D
1 1 1 1 1

Implement the following function using MUX:

𝑓 = ∑ 𝑚(0,2,3,7,10,12,14) + ∑ 𝑑(11,13)

Application of MUX:

1. Data routing (several source to one destination).

2. Logic function generator.
3. Control sequencer.
4. Parallel to serial converter.

Multiplexer ICs:

1. SN 74157 – Quad 2:1 MUX

2. SN 74153 – Dual 4:1 MUX
3. SN 74151 – 8:1 MUX
4. SN 74152 – 8:1 MUX

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5. SN 74150 – 16:1 MUX

8:1 MUX

16:1 MUX

Demultiplexers (Data Distributors):

The word “demultiplex” means “one into many”. Demultiplexing is the process of taking information
from one input and transmitting the same over one of several outputs.

As the serial data is changed to parallel data in DMUX, it is also called distributor or serial to parallel
data converter.

DMUX has one input signal, ‘m’ select signals and

‘n’ output signals.
The relation between n and m is 𝑛 = 2𝑚 .

1:2 DMUX:

Data Select
Outputs
inputs lines
𝑌0 = 𝑆0̅ . 𝐷,
D 𝑆0 𝑌0 𝑌1
𝑌1 = 𝑆0 . 𝐷
D 0 0 D
D 1 D 0

1:4 DMUX:

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Data
Select lines Outputs
input
𝑌0 = 𝑆1̅ . 𝑆0̅ . 𝐷,
D 𝑆1 𝑆0 𝑌0 𝑌1 𝑌2 𝑌3
𝑌1 = 𝑆1̅ . 𝑆0 . 𝐷,
D 0 0 D 0 0 0
𝑌2 = 𝑆1 . 𝑆0̅ . 𝐷,
D 0 1 0 D 0 0
𝑌3 = 𝑆1 . 𝑆0 . 𝐷.
D 1 0 0 0 D 0
D 1 1 0 0 0 D

1:8 DMUX:

𝑌0 = 𝑆2̅ 𝑆1̅ . 𝑆0̅ . 𝐷,

𝑌1 = 𝑆2̅ 𝑆1̅ . 𝑆0 . 𝐷,
𝑌2 = 𝑆2̅ 𝑆1 . 𝑆0̅ . 𝐷,
𝑌3 = 𝑆2̅ 𝑆1 . 𝑆0 . 𝐷,
𝑌4 = 𝑆2 𝑆1̅ . 𝑆0̅ . 𝐷,
𝑌5 = 𝑆2 𝑆1̅ . 𝑆0 . 𝐷,
𝑌6 = 𝑆2 𝑆1 . 𝑆0̅ . 𝐷,
𝑌7 = 𝑆2 . 𝑆1 𝑆0 . 𝐷.

Data
Select lines Outputs
input
D 𝑆2 𝑆1 𝑆0 𝑌0 𝑌1 𝑌2 𝑌3 𝑌4 𝑌5 𝑌6 𝑌7
D 0 0 0 D 0 0 0 0 0 0 0
D 0 0 1 0 D 0 0 0 0 0 0
D 0 1 0 0 0 D 0 0 0 0 0
D 0 1 1 0 0 0 D 0 0 0 0
D 1 0 0 0 0 0 0 D 0 0 0
D 1 0 1 0 0 0 0 0 D 0 0
D 1 1 0 0 0 0 0 0 0 D 0
D 1 1 1 0 0 0 0 0 0 0 D

Demultiplexer ICs:

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Multiplexers & Demultiplexers

1. IC 74139 – Dual 1:4 DMUX (2 to 4 decoder) – Inverted output

2. IC 74155 – Dual 1:4 DMUX (2 to 4 decoder) – Inverted output
3. IC 74156 – Dual 1:4 DMUX (2 to 4 decoder) – Inverted output (Open-collector)
4. IC 74138 – 1:8 DMUX (3 to 8 decoder) – Inverted output
5. IC 74154 – 1:16 DMUX (4 to 16 decoder) – Inverted output
6. IC 74159 – 1:16 DMUX (4 to 16 decoder) – Inverted output (Open-collector)

1:16 DMUX

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