Vegas Sklkbl-U 17841-1 Rev A00

5 4 3 2 1
D D
Vegas Schematic
C
KBL-R C
2017/11/08
REV : A00
B B
DY : None Installed <Core Design>
A
UMA: UMA only installed Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
OPS: DISCRTE OPTIMUS installed Title

Taipei Hsien 221, Taiwan, R.O.C.
Cover Page
Size Document Number Rev
A4
Vegas SKL/KBL-U A00
Date: Wednesday, November 08, 2017 Sheet 1 of 105
5 4 3 2 1
5 4 3 2 1
CHARGER
ISL88739
Vegas/Turis MLK KBL-R Block Diagram
44
Project code: INPUTS OUTPUTS
PCB P/N:17841-1 AD+
DCBATOUT
Revision: X02 BT+
SYSTEM DC/DC
TPS51225RUKR-GP 45
INPUTS OUTPUTS
2GB = 256Mb x 32 x 2 PCS NEW 3D3V_PWR
NEW NEW 3D3V_S5
DCBATOUT 5V_PWR
D D
DDR4 2400
5V_S5
GPU Intel CPU
DDR4 2400MHz Channel A
S ODIMM A CPU Core Power
V RAM(GDDR5) *2 AMD
GDDR5 PCIE x 4 12 NCP81208MNTXG 46~50
2GB (256Mb x 32) R17M-M1-30 33
25W Kabylake-U 4+2 NCP81382MNTXG x 2

81, 82
DDR4 2400 NCP81382MNTXG (23e)
DDR4 2400MHz Channel A NCP81253MNTBG
DIS only 76, 77, 78, 79, 80
15W (UMA&DIS)
INPUTS OUTPUTS
S ODIMM B
DCBATOUT VCC_CORE
13
DCBATOUT +VCCGT
DCBATOUT +VCCGT (23e)
Vegas 14"/15" LCD eDP x2
Turis KBL PCH-LP VEGAS only NEW
15" Touch Panel USB2.0 x1 Fingerprint DCBATOUT+VCCSA
(TURIS only) USB2.0 x1 10 USB 2.0/1.1 ports

FM-03331
92
DDR4 SUS
55 RT8231AGQW-GP
6 USB 3.0 ports 51
APL5930KAI-TRG
High Definition Audio INPUTS OUTPUTS
3 SATA ports 1D2V_S3
Camera USB2.0 x1 6 PCIE ports
PCIE x1 NGFF WLAN Vegas
DCBATOUT 0D6V_S0
3D3V_S5 2D5V_S3
C
Digital MIC LPC I/F 802.11a/b/g/n Turis
C
ACPI 5.0 USB2.0 x1 BT V4.0 combo CPU VCCPRIM_CORE

61
LAN 10/100 TURIS only 1V
REALTEK RTL8106E
Vegas 11
Turis RJ45 Conn.
PCIE x1
INPUTS OUTPUTS
32 LAN 10/100/1000
REALTEK RTL8111H 1D0V_S5 +VCCPRIM_CORE
31 VEGAS only
Vegas CPU DCDC-V1D00A
Turis HDMI V1.4a 57
DDI1 AOZ2262QI-10-GP-U 53
INPUTS OUTPUTS
SATA (Gen3) x1 HDD DCBATOUT 1D0V_S5
VEGAS only 60
Vegas
DP/VGA Converter LDO-V1D8V
VGA Conn. REALTEK RTD2166
DDI2
APL5930KAI-TRG 54
Turis 56 56
SATA (Gen1) x1 Vegas INPUTS OUTPUTS
ODD Turis 3D3V_S5 1D8V_S5
60
Left side Kyloren 15 5V/3V S0
USB2.0 x1
Vegas TPS22966DPUR-GP 40
Turis USB1(USB3.0) eSPI BUS INPUTS OUTPUTS
B
eSPI debug port B
USB3.0 x1 68 5V_S5
3D3V_S5
5V_S0
3D3V_S0
36
Kyloren EOPIO/EDRAM (23e)

FAN Control TPS22961DNYT 40
Left side
USB2.0 x1
15 EC OUTPUTS
INPUTS
Vegas SMSC MEC1416-NU-GP 26
Turis USB2(USB3.0) 24
1D0V_S5
1D0V_S5
+V_EDRAM_VR
+V_EOPIO_VR
USB3.0 x1 3D3V VGA
36
AO3419L 86
SPI Flash ROM Vegas

INPUTS OUTPUTS
16MB Int. KB 3D3V_S0 3D3V_VGA_S0
2CH SPEAKER
25 Turis
65
Vegas (2CH 2W/4ohm) VEGAS only VGA_CORE
Audio Codec 26
ISL62771HRTZ-GP-U 85
Turis HDA
ALC3246 INPUTS OUTPUTS
27
TPM 2.0 DCBATOUT VGA_CORE
29
NPCT650/750 91 PS2
P recisionTouch pad 1D5V_VGA_S0
MIC_IN/GND Y8288RAC-GP 86
HP_R/L
I2C
Universal Jack 65 INPUTS OUTPUTS
DCBATOUT 1D5V_VGA_S0
A A
Vegas USB3(USB2.0) USB2.0 x1 <Core Design>
Turis
Wistron Corporation
2 1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
CardReader
Vegas SD Card Slot Realtek RTS5170
USB2.0 x1 T itle
Block Diagram
Turis Size Document Number Rev
IO Board C Vegas SKL/KBL-U A00
Date: Wednesday, November 08, 2017 Sheet 2 o f 105
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
#544669 CRB Rev0.52

+VCCST_CPU
+VCCSTG = 1.0 V
1
#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm
#544669 Rev0.52: R419 +VCCSTG
D Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm 1KR2J-1-GP D
+VCCSTG = 1.0 V XDP_TMS R421 1 2 51R2J-2-GP

DY
2
+VCCSTG PCH_THERMTRIP XDP_TDI R422 1 2 51R2J-2-GP
DY
XDP_TDO_CPU R423 1 2 51R2J-2-GP
DY
[PECI] and [PROCHOT#]
1
Impedance control: 50 ohm PCH_JTAG_TDI R408 1 2 51R2J-2-GP
Rb R401 CPU1D 4 OF 20 0525 Follow KY15 & SF
1KR2J-1-GP PCH_JTAG_TDO R409 1 2 51R2J-2-GP
[24] H_PECI H_CATERR#
TPAD14-OP-GP TP401 1 D63 SKYLAKE_ULT
Ra H_PECI A54 CATERR# PCH_JTAG_TMS R416 1 2 51R2J-2-GP
[24,44,46] H_PROCHOT# PECI
2
H_PROCHOT# R403 1 2 H_PROCHOT#_R C65
PROCHOT# JTAG
499R2F-2-GP PCH_THERMTRIP C63 XDP_TCK_JTAGX R417 1 2 1KR2J-1-GP
TPAD14-OP-GP TP402 1 SKTOCC# A65 THERMTRIP# B61 XDP_TCLK
DY
[24,55] TOUCH_PANEL_INTR# SKTOCC# PROC_TCK D60 XDP_TDI
CPU MISC PROC_TDI
TPAD14-OP-GP TP405 1 XDP_BPM0 C55 A61 XDP_TDO_CPU XDP_TRST# R402 1 2 51R2J-2-GP
[24,65] INT_TP#
TPAD14-OP-GP TP406 1 XDP_BPM1 D55 BPM#[0] PROC_TDO C60 XDP_TMS
DY
TPAD14-OP-GP TP407 1 XDP_BPM2 B54 BPM#[1] PROC_TMS B59 XDP_TRST# XDP_TCLK R406 1 2 51R2J-2-GP
TPAD14-OP-GP TP408 1 XDP_BPM3 C56 BPM#[2] PROC_TRST#
BPM#[3] PCH_JTAG_TCK R407 1 2 51R2J-2-GP
A6 B56 PCH_JTAG_TCK
DY
TOUCH_PANEL_INTR# A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 PCH_JTAG_TDI
INT_TP# R410 1 2 TOUCHPAD_INTR# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 PCH_JTAG_TDO
0R0402-PAD TPAD14-OP-GP TP404 1 GPP_B4/CPU_GP3 AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 PCH_JTAG_TMS
GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 XDP_TRST#
R412 1 2 49D9R2F-L1-GP CPU_POPIRCOMP AT16 PCH_TRST# A59 XDP_TCK_JTAGX
R413 1 2 49D9R2F-L1-GP PCH_POPIRCOMP AU16 PROC_POPIRCOMP JTAGX
R414 1 2 49D9R2F-L1-GP EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
C R415 1 2 49D9R2F-L1-GP EOPIO_RCOMP H65 OPCE_RCOMP C
OPC_RCOMP XDP_TRST#
SKYLAKE-U-GP
1
DY EC401
SC1KP50V2KX-L-1-GP
2
(#543016) PROCHOT# Routing Guidelines
B B
M1,2,3,4,5: <3 inches

M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
CPU_(JTAG/CPU SIDE BAND)
A3
Vegas SKL/KBL-U A00
Date: W ednesday, November 08, 2017 Sheet 4 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

DDR4 ball type: Interleaved Type
D D
PU1B PU1C
C 2 OF 20 C 3 OF 20
SKYLAKE_ULT
M _A_DQ0 AL71 AU53 M _A_DQ32 AY39 SKYLAKE_ULT AN45
[12] M _A_DQ0 M _A_DQ1 AL68 D DR0_DQ[0] D DR0_CKN[0] AT53 M _A_CLK#0 [12] [12] M _A_DQ32 M _A_DQ33 AW39 D DR0_DQ[32]/DDR1_DQ[0] D DR1_CKN[0] AN46 M _B_CLK#0 [13]
[12] M _A_DQ1 M _A_DQ2 AN68 D DR0_DQ[1] D DR0_CKP[0] AU55 M _A_CLK0 [12] [12] M _A_DQ33 M _A_DQ34 AY37 D DR0_DQ[33]/DDR1_DQ[1] D DR1_CKN[1] AP45 M _B_CLK#1 [13]
[12] M _A_DQ2 M _A_DQ3 AN69 D DR0_DQ[2] D DR0_CKN[1] AT55 M _A_CLK#1 [12] [12] M _A_DQ34 M _A_DQ35 AW37 D DR0_DQ[34]/DDR1_DQ[2] D DR1_CKP[0] AP46 M _B_CLK0 [13]
[12] M _A_DQ3 M _A_DQ4 AL70 D DR0_DQ[3] D DR0_CKP[1] M _A_CLK1 [12] [12] M _A_DQ35 M _A_DQ36 BB39 D DR0_DQ[35]/DDR1_DQ[3] D DR1_CKP[1] M _B_CLK1 [13]
M_A_DQ[0:7] [12] M _A_DQ4 M _A_DQ5 AL69 D DR0_DQ[4] BA56
M_A_DQ[32:39] [12] M _A_DQ36 M _A_DQ37 BA39 D DR0_DQ[36]/DDR1_DQ[4] AN56
[12] M _A_DQ5 M _A_DQ6 AN70 D DR0_DQ[5] D DR0_CKE[0] BB56 M _A_CKE0 [12] [12] M _A_DQ37 M _A_DQ38 BA37 D DR0_DQ[37]/DDR1_DQ[5] D DR1_CKE[0] AP55 M _B_CKE0 [13]
[12] M _A_DQ6 M _A_DQ7 AN71 D DR0_DQ[6] D DR0_CKE[1] AW56 M _A_CKE1 [12] [12] M _A_DQ38 M _A_DQ39 BB37 D DR0_DQ[38]/DDR1_DQ[6] D DR1_CKE[1] AN55 M _B_CKE1 [13]
[12] M _A_DQ7 M _A_DQ8 AR70 D DR0_DQ[7] D DR0_CKE[2] AY56 [12] M _A_DQ39 M _A_DQ40 AY35 D DR0_DQ[39]/DDR1_DQ[7] D DR1_CKE[2] AP53
[12] M _A_DQ8 M _A_DQ9 AR68 D DR0_DQ[8] D DR0_CKE[3] [12] M _A_DQ40 M _A_DQ41 AW35 D DR0_DQ[40]/DDR1_DQ[8] D DR1_CKE[3]
[12] M _A_DQ9 M _A_DQ10 AU71 D DR0_DQ[9] AU45 [12] M _A_DQ41 M _A_DQ42 AY33 D DR0_DQ[41]/DDR1_DQ[9] BB42
[12] M _A_DQ10 M _A_DQ11 AU68 D DR0_DQ[10] D DR0_CS#[0] AU43 M _A_CS#0 [12] [12] M _A_DQ42 M _A_DQ43 AW33 D DR0_DQ[42]/DDR1_DQ[10] D DR1_CS#[0] AY42 M _B_CS#0 [13]
[12] M _A_DQ11 M _A_DQ12 AR71 D DR0_DQ[11] D DR0_CS#[1] AT45 M _A_CS#1 [12] [12] M _A_DQ43 M _A_DQ44 BB35 D DR0_DQ[43]/DDR1_DQ[11] D DR1_CS#[1] BA42 M _B_CS#1 [13]
M_A_DQ[8:15] [12] M _A_DQ12 M _A_DQ13 AR69 D DR0_DQ[12] D DR0_ODT[0] AT43 M _A_DIMA_ODT0 [12] M_A_DQ[40:47] [12] M _A_DQ44 M _A_DQ45 BA35 D DR0_DQ[44]/DDR1_DQ[12] D DR1_ODT[0] AW42 M _B_DIMB_ODT0 [13]
[12] M _A_DQ13 M _A_DQ14 AU70 D DR0_DQ[13] D DR0_ODT[1] M _A_DIMA_ODT1 [12] [12] M _A_DQ45 M _A_DQ46 BA33 D DR0_DQ[45]/DDR1_DQ[13] D DR1_ODT[1] M _B_DIMB_ODT1 [13]
[12] M _A_DQ14 M _A_DQ15 AU69 D DR0_DQ[14] BA51 M _A_A5 [12] M _A_DQ46 M _A_DQ47 BB33 D DR0_DQ[46]/DDR1_DQ[14] AY48 M _B_A5
[12] M _A_DQ15 D DR0_DQ[15] D DR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M _A_A5 [12] [12] M _A_DQ47 D DR0_DQ[47]/DDR1_DQ[15] D DR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M _B_A5 [13]
[13] M _B_DQ0 M _B_DQ0 AF65 BB54 M _A_A9 M _B_DQ32 AU40 AP50 M _B_A9
D DR0_DQ[16] D DR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
D DR1_DQ[0]/DDR0_DQ[16] M _A_A9 [12] [13] M _B_DQ32 D DR1_DQ[32]/DDR1_DQ[16] D DR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M _B_A9 [13]
[13] M _B_DQ1 M _B_DQ1 AF64 BA52 M _A_A6 M _B_DQ33 AT40 BA48 M _B_A6
D DR1_DQ[1]/DDR0_DQ[17]DDR0_DQ[17] D DR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] M _A_A6 [12] [13] M _B_DQ33 D DR1_DQ[33]/DDR1_DQ[17] D DR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M _B_A6 [13]
[13] M _B_DQ2 M _B_DQ2 AK65 AY52 M _A_A8 M _B_DQ34 AT37 BB48 M _B_A8
[13] M _B_DQ3 M _B_DQ3 AK64 AW52 M _A_A7 M _B_DQ35 AU37 AP48 M _B_A7
M _B_DQ4 AF66 AY55 M _B_DQ36 AR40 AP52
M_B_DQ[0:7] [13] M _B_DQ4
M _B_DQ5 AF67 D DR1_DQ[4]/DDR0_DQ[20]DDR0_DQ[20] D DR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 M _A_A12 M _A_BG0 [12] M_B_DQ[32:39] [13] M _B_DQ36
M _B_DQ37 AP40 D DR1_DQ[36]/DDR1_DQ[20] D DR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 M _B_A12 M _B_BG0 [13]
[13] M _B_DQ5 D DR1_DQ[5]/DDR0_DQ[21]DDR0_DQ[21] D DR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M _A_A12 [12] [13] M _B_DQ37 D DR1_DQ[37]/DDR1_DQ[21] D DR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] M _B_A12 [13]
[13] M _B_DQ6 M _B_DQ6 AK67 BA54 M _A_A11 M _B_DQ38 AP37 AN48 M _B_A11
D DR1_DQ[6]/DDR0_DQ[22]DDR0_DQ[22]D DR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M _A_A11 [12] [13] M _B_DQ38 D DR1_DQ[38]/DDR1_DQ[22] D DR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M _B_A11 [13]
[13] M _B_DQ7 M _B_DQ7 AK66 BA55 [13] M _B_DQ39 M _B_DQ39 AR37 AN53 M _B_ACT_N
M _B_DQ8 AF70 D DR1_DQ[7]/DDR0_DQ[23]DDR0_DQ[23] D DR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 M _A_ACT_N [12] M _B_DQ40 AT33 D DR1_DQ[39]/DDR1_DQ[23] D DR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 M _B_ACT_N [13]
[13] M _B_DQ8 D DR1_DQ[8]/DDR0_DQ[24] D DR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M _A_BG1 [12] [13] M _B_DQ40 D DR1_DQ[40]/DDR1_DQ[24] D DR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] M _B_BG1 [13]
[13] M _B_DQ9 M _B_DQ9 AF68 [13] M _B_DQ41 M _B_DQ41 AU33
M _B_DQ10 AH71 D DR1_DQ[9]/DDR0_DQ[25] AU46 M _A_A13 M _B_DQ42 AU30 D DR1_DQ[41]/DDR1_DQ[25] BA43 M _B_A13
[13] M _B_DQ10 D DR1_DQ[10]/DDR0_DQ[26] D DR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M _A_A13 [12] [13] M _B_DQ42 D DR1_DQ[42]/DDR1_DQ[26] D DR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] M _B_A13 [13]
[13] M _B_DQ11 M _B_DQ11 AH68 AU48 M _A_A15 M _B_DQ43 AT30 AY43 M _B_A15
D DR1_DQ[11]/DDR0_DQ[27] D DR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] M _A_A15 [12] [13] M _B_DQ43 D DR1_DQ[43]/DDR1_DQ[27] D DR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] M _B_A15 [13]
M _B_DQ12 AF71 AT46 M _A_A14 M _B_DQ44 AR33 AY44 M _B_A14
M_B_DQ[8:15] [13] M _B_DQ12
M _B_DQ13 AF69 D DR1_DQ[12]/DDR0_DQ[28] D DR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 M _A_A16
M _A_A14 [12] M_B_DQ[40:47] [13] M _B_DQ44
M _B_DQ45 AP33 D DR1_DQ[44]/DDR1_DQ[28] D DR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 M _B_A16 M _B_A14 [13]
[13] M _B_DQ13 D DR1_DQ[13]/DDR0_DQ[29] D DR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M _A_A16 [12] [13] M _B_DQ45 D DR1_DQ[45]/DDR1_DQ[29] D DR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] M _B_A16 [13]
[13] M _B_DQ14 M _B_DQ14 AH70 AU52 [13] M _B_DQ46 M _B_DQ46 AR30 BB44
M _B_DQ15 AH69 D DR1_DQ[14]/DDR0_DQ[30] D DR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 M _A_A2 M _A_BA0 [12] M _B_DQ47 AP30 D DR1_DQ[46]/DDR1_DQ[30] D DR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 M _B_A2 M _B_BA0 [13]
[13] M _B_DQ15 D DR1_DQ[15]/DDR0_DQ[31] D DR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M _A_A2 [12] [13] M _B_DQ47 D DR1_DQ[47]/DDR1_DQ[31] D DR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] M _B_A2 [13]
M _A_DQ16 BB65 AT48 M _A_DQ48 AY31 BA44
[12] M _A_DQ16 M _A_DQ17 AW65 D DR0_DQ[16]/DDR0_DQ[32] D DR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 M _A_A10 M _A_BA1 [12] [12] M _A_DQ48 M _A_DQ49 AW31 D DR0_DQ[48]/DDR1_DQ[32] D DR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 M _B_A10 M _B_BA1 [13]
[12] M _A_DQ17 D DR0_DQ[17]/DDR0_DQ[33] D DR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M _A_A10 [12] [12] M _A_DQ49 D DR0_DQ[49]/DDR1_DQ[33] D DR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M _B_A10 [13]
C M _A_DQ18 AW63 BB50 M _A_A1 M _A_DQ50 AY29 AY46 M _B_A1 C
[12] M _A_DQ18 D DR0_DQ[18]/DDR0_DQ[34] D DR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] M _A_A1 [12] [12] M _A_DQ50 D DR0_DQ[50]/DDR1_DQ[34] D DR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M _B_A1 [13]
M _A_DQ19 AY63 AY50 M _A_A0 M _A_DQ51 AW29 BA46 M _B_A0
M_A_DQ[16:23] [12] M _A_DQ19 M _A_DQ20 BA65 D DR0_DQ[19]/DDR0_DQ[35] D DR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 M _A_A3 M _A_A0 [12] M_A_DQ[48:55] [12] M _A_DQ51 M _A_DQ52 BB31 D DR0_DQ[51]/DDR1_DQ[35] D DR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 M _B_A3 M _B_A0 [13]
[12] M _A_DQ20 D DR0_DQ[20]/DDR0_DQ[36] D DR0_MA[3] M _A_A3 [12] [12] M _A_DQ52 D DR0_DQ[52]/DDR1_DQ[36] D DR1_MA[3] M _B_A3 [13]
M _A_DQ21 AY65 BB52 M _A_A4 M _A_DQ53 BA31 BA47 M _B_A4
[12] M _A_DQ21 D DR0_DQ[21]/DDR0_DQ[37] D DR0_MA[4] M _A_A4 [12] [12] M _A_DQ53 D DR0_DQ[53]/DDR1_DQ[37] D DR1_MA[4] M _B_A4 [13]
M _A_DQ22 BA63 M _A_DQ54 BA29
[12] M _A_DQ22 M _A_DQ23 BB63 D DR0_DQ[22]/DDR0_DQ[38] AM70 M _A_DQS_DN0 [12] M _A_DQ54 M _A_DQ55 BB29 D DR0_DQ[54]/DDR1_DQ[38] BA38 M _A_DQS_DN4
[12] M _A_DQ23 M _A_DQ24 D DR0_DQ[23]/DDR0_DQ[39] D DR0_DQSN[0] _A_DQS_DP0 [12] M _A_DQ55 _A_DQ56 D DR0_DQ[55]/DDR1_DQ[39] D DR0_DQSN[4]/DDR1_DQSN[0] _A_DQS_DP4
[12] M _A_DQ24
BA61
D DR0_DQ[24]/DDR0_DQ[40] D DR0_DQSP[0]
AM69 M M_A_DQS0 [12] M _A_DQ56
M AY27
D DR0_DQ[56]/DDR1_DQ[40] D DR0_DQSP[4]/DDR1_DQSP[0]
AY38 M M_A_DQS4
M _A_DQ25 AW61 AT69 M _A_DQS_DN1 M _A_DQ57 AW27 AY34 M _A_DQS_DN5
[12] M _A_DQ25 M _A_DQ26 D DR0_DQ[25]/DDR0_DQ[41] D DR0_DQSN[1] _A_DQS_DP1 [12] M _A_DQ57 _A_DQ58 D DR0_DQ[57]/DDR1_DQ[41] D DR0_DQSN[5]/DDR1_DQSN[1] _A_DQS_DP5
[12] M _A_DQ26
BB59
D DR0_DQ[26]/DDR0_DQ[42] D DR0_DQSP[1]
AT70 M M_A_DQS1 [12] M _A_DQ58
M AY25
BA34 M M_A_DQS5
M _A_DQ27 AW59 AH66 M _B_DQS_DN0 M _A_DQ59 AW25 AT38 M _B_DQS_DN4
M_A_DQ[24:31] [12] M _A_DQ27 M _A_DQ28 D DR0_DQ[27]/DDR0_DQ[43] D DR1_DQSN[0]/DDR0_DQSN[2] _B_DQS_DP0 M_A_DQ[56:63] [12] M _A_DQ59 _A_DQ60 D DR0_DQ[59]/DDR1_DQ[43] D DR1_DQSN[4]/DDR1_DQSN[2] _B_DQS_DP4
[12] M _A_DQ28
BB61
AH65 M
M_B_DQS0 [12] M _A_DQ60
M BB27
AR38 M M_B_DQS4
M _A_DQ29 AY61 AG69 M _B_DQS_DN1 M _A_DQ61 BA27 AT32 M _B_DQS_DN5
[12] M _A_DQ29 M _A_DQ30 D DR0_DQ[29]/DDR0_DQ[45] D DR1_DQSN[1]/DDR0_DQSN[3] _B_DQS_DP1 [12] M _A_DQ61 _A_DQ62 D DR0_DQ[61]/DDR1_DQ[45] D DR1_DQSN[5]/DDR1_DQSN[3] _B_DQS_DP5
[12] M _A_DQ30
BA59
AG70 M
M_B_DQS1 [12] M _A_DQ62
M BA25
AR32 M M_B_DQS5
M _A_DQ31 AY59 BA64 M _A_DQS_DN2 M _A_DQ63 BB25 BA30 M _A_DQS_DN6
[12] M _A_DQ31 M _B_DQ16 D DR0_DQ[31]/DDR0_DQ[47] D DR0_DQSN[2]/DDR0_DQSN[4] _A_DQS_DP2 [12] M _A_DQ63 _B_DQ48 D DR0_DQ[63]/DDR1_DQ[47] D DR0_DQSN[6]/DDR1_DQSN[4] _A_DQS_DP6
[13] M _B_DQ16 AT66
AY64 M M_A_DQS2 [13] M _B_DQ48 M AU27
D DR1_DQ[48] D DR0_DQSP[6]/DDR1_DQSP[4]
AY30 M M_A_DQS6
[13] M _B_DQ17 M _B_DQ17 AU66 AY60 M _A_DQS_DN3
[13] M _B_DQ49 M _B_DQ49 AT27 AY26 M _A_DQS_DN7 1 D2V_S3
M _B_DQ18 AP65 D DR1_DQ[17]/DDR0_DQ[49] D DR0_DQSN[3]/DDR0_DQSN[5] BA60 M _A_DQS_DP3 M_A_DQS3 M _B_DQ50 AT25 D DR1_DQ[49] D DR0_DQSN[7]/DDR1_DQSN[5] BA26 M _A_DQS_DP7 M_A_DQS7
[13] M _B_DQ18 D DR1_DQ[18]/DDR0_DQ[50] D DR0_DQSP[3]/DDR0_DQSP[5] [13] M _B_DQ50 D DR1_DQ[50] D DR0_DQSP[7]/DDR1_DQSP[5]
M _B_DQ19 AN65 AR66 M _B_DQS_DN2 M _B_DQ51 AU25 AR25 M _B_DQS_DN6
M_B_DQ[16:23] [13] M _B_DQ19
M _B_DQ20 D DR1_DQ[19]/DDR0_DQ[51] D DR1_DQSN[2]/DDR0_DQSN[6] _B_DQS_DP2 M_B_DQ[48:55] [13] M _B_DQ51
_B_DQ52 D DR1_DQ[51] D DR1_DQSN[6] _B_DQS_DP6 M_B_DQS6
1
[13] M _B_DQ20 AN66 AR65 M M_B_DQS2 [13] M _B_DQ52 M AP27 AR27 M
M _B_DQ21 AP66 D DR1_DQ[20]/DDR0_DQ[52] D DR1_DQSP[2]/DDR0_DQSP[6] AR61 M _B_DQS_DN3 M _B_DQ53 AN27 D DR1_DQ[52] D DR1_DQSP[6] AR22 M _B_DQS_DN7 R 505
[13] M _B_DQ21 D DR1_DQ[21]/DDR0_DQ[53] D DR1_DQSN[3]/DDR0_DQSN[7] [13] M _B_DQ53 D DR1_DQ[53] D DR1_DQSN[7]
[13] M _B_DQ22 M _B_DQ22 AT65 AR60 M _B_DQS_DP3 M_B_DQS3 [13] M _B_DQ54 M _B_DQ54 AN25 AR21 M _B_DQS_DP7 M_B_DQS7 470R2F-GP
M _B_DQ23 AU65 D DR1_DQ[22]/DDR0_DQ[54] D DR1_DQSP[3]/DDR0_DQSP[7] M _B_DQ55 AP25 D DR1_DQ[54] D DR1_DQSP[7]
[13] M _B_DQ23 D DR1_DQ[23]/DDR0_DQ[55] [13] M _B_DQ55 D DR1_DQ[55]
[13] M _B_DQ24 M _B_DQ24 AT61 AW50 [13] M _B_DQ56 M _B_DQ56 AT22 AN43
D DR1_DQ[24]/DDR0_DQ[56] D DR0_ALERT# M _A_ALERT_N [12] D DR1_DQ[56] D DR1_ALERT# M _B_ALERT_N [13]
2
[13] M _B_DQ25 M _B_DQ25 AU61 AT52 [13] M _B_DQ57 M _B_DQ57 AU22 AP43
M _B_DQ26 AP60 D DR1_DQ[25]/DDR0_DQ[57] D DR0_PAR M _A_PARITY [12] M _B_DQ58 AU21 D DR1_DQ[57] D DR1_PAR AT13 S M_DRAMRST# M _B_PARITY [13]
[13] M _B_DQ26 M_B_DQ[56:63] [13] M _B_DQ58 1 R 504 2 DR4_DRAMRST# [12,13]
M _B_DQ27 AN60 D DR1_DQ[26]/DDR0_DQ[58] AY67 M _B_DQ59 AT21 D DR1_DQ[58] D RAM_RESET# AR18 S M_RCOMP_0R 5011 D
M_B_DQ[24:31] [13] M _B_DQ27 [13] M _B_DQ59 2 121R2F-GP
M _B_DQ28 AN61 D DR1_DQ[27]/DDR0_DQ[59] D DR_VREF_CA AY68 V _SM_VREF_CNTA [12] M _B_DQ60 AN22 D DR1_DQ[59] D DR_RCOMP[0] AT18 S M_RCOMP_1R 5021
[13] M _B_DQ28 [13] M _B_DQ60 2 80D6R2F-L-GP 0R0402-PAD
M _B_DQ29 AP61 D DR1_DQ[28]/DDR0_DQ[60] D DR0_VREF_DQ BA67 M _B_DQ61 AP22 D DR1_DQ[60] D DR_RCOMP[1] AU18 S M_RCOMP_2R 5031 2 100R2F-L3-GP
[13] M _B_DQ29 D DR1_DQ[29]/DDR0_DQ[61] D DR1_VREF_DQ V _SM_VREF_CNTB [13] [13] M _B_DQ61 D DR1_DQ[61] D DR_RCOMP[2]
[13] M _B_DQ30 M _B_DQ30 AT60 [13] M _B_DQ62 M _B_DQ62 AP21
M _B_DQ31 AU60 D DR1_DQ[30]/DDR0_DQ[62] AW67 S M_PGCNTL M _B_DQ63 AN21 D DR1_DQ[62]
DDR CH - B
[13] M _B_DQ31 D DR1_DQ[31]/DDR0_DQ[63] DDR CH - A D DR_VTT_CNTL [13] M _B_DQ63 D DR1_DQ[63]
1
#543016
SKYLAKE-U-GP SKYLAKE-U-GP Layout Note: DYD502
E
AZ5725-01FDR7G-GP
Design Guideline: 83.05725.0A0
SM_RCOMP keep routing length less than 500 mils.
2
close to CPU
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential
B
clock pair to clock pair swapping within a channel is not allowed. 3 D3V_S5 B
3 D3V_S0
1
R 507
1
10KR2J-L-GP
R 506
Q 502 220KR2F-L-GP
PDG: DDR/ODT
2
Q 502_G G
2
D
S M_PGCNTL_R [51]
D
S
Q 501
DMN5L06K-7-GP 2N7002K-2-GP
S M_PGCNTL G 84.05067.031 84.2N702.J31
ND = 84.2N702.031
2
3rd = 84.07002.I31
S
???
Difference with Kyloren
M _A_DQS_DN[7:0] [12] M _B_DQS_DN0 M _B_DQS_DN[7:0] [13]

M _A_DQS_DN0 M _B_DQS_DN1
A M _A_DQS_DN7 A
M _B_DQS_DP0 M _B_DQS_DP[7:0] [13]

M _B_DQS_DP1
M _B_DQS_DP2
M _A_DQS_DP0 M _A_DQS_DP[7:0] [12] M _B_DQS_DP3
M _A_DQS_DP1 M _B_DQS_DP4 <Core Design>
M _A_DQS_DP2 M _B_DQS_DP5
M _A_DQS_DP3 M _B_DQS_DP6
M
M
_A_DQS_DP4
_A_DQS_DP5
M _B_DQS_DP7 W istron Corporation
2 1F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
M _A_DQS_DP6
M _A_DQS_DP7
T Title
itle
C PU_(DDR)
A 2
V egas SKL/KBL-U A 00
Date: Wednesday, November 08, 2017 Sheet 5 o f 105
5 4 3 2 1
5 4 3 2 1
Main Func = CPU C PU1S 19 OF 20
RESERVED SIGNALS-1
0607 Delete TP
TPAD14-OP-GP T P618 1 C FG0 E68 SKYLAKE_ULT BB68
T P619 1 C FG1 CFG[0] RSVD_TP#BB68
TPAD14-OP-GP B67 BB69
T P620 1 C FG2 CFG[1] RSVD_TP#BB69
TPAD14-OP-GP D65
T P621 1 C FG3 CFG[2]
TPAD14-OP-GP D67 AK13
T P622 1 C FG4 CFG[3] RSVD_TP#AK13
TPAD14-OP-GP E70 AK12
T P623 1 C FG5 CFG[4] RSVD_TP#AK12
TPAD14-OP-GP C68
T P624 1 C FG6 CFG[5]
TPAD14-OP-GP D68 BB2
T P625 1 C FG7 CFG[6] RSVD#BB2
TPAD14-OP-GP C67 BA3
T P626 1 C FG8 CFG[7] RSVD#BA3
D TPAD14-OP-GP F71 D
T P627 1 C FG9 CFG[8]
TPAD14-OP-GP G69
T P628 1 C FG10 CFG[9]
TPAD14-OP-GP F70 AU5
T P629 1 C FG11 CFG[10] TP5
TPAD14-OP-GP G68 AT5
T P630 1 C FG12 CFG[11] TP6
TPAD14-OP-GP H70
T P631 1 C FG13 CFG[12]
TPAD14-OP-GP G71
T P632 1 C FG14 CFG[13]
TPAD14-OP-GP H69 D5
T P633 1 C FG15 CFG[14] RSVD#D5
TPAD14-OP-GP G70 D4
CFG[15] RSVD#D4
B2
1 RSVD#B2
TPAD14-OP-GP T P634 C FG16 E63
CFG[16] RSVD#C2
C2
TPAD14-OP-GP T P635 1 C FG17 F63
CFG[17]
B3
1 RSVD#B3
TPAD14-OP-GP T P636 C FG18 E66
CFG[18] RSVD#A3
A3
TPAD14-OP-GP T P637 1 C FG19 F66
CFG[19]
AW1
R 601 1 2 C FG_RCOMP E60 RSVD#AW1
CFG_RCOMP
49D9R2F-L1-GP E1
1 I TP_PMODE RSVD#E1
TPAD14-OP-GP T P638 E8
ITP_PMODE RSVD#E2
E2
AY2 BA4
RSVD#AY2 RSVD#BA4
AY1 BB4
RSVD#AY1 RSVD#BB4
D1 A4
RSVD#D1 RSVD#A4
D3 C4
RSVD#D3 RSVD#C4
K46 BB5
RSVD#K46 TP4
K45
RSVD#K45
A69
RSVD#A69
AL25 B69
RSVD#AL25 RSVD#B69
C AL27 C
RSVD#AL27
AY3
RSVD#AY3
C71
RSVD#C71
B70 D71
RSVD#B70 RSVD#D71
C70
RSVD#C70
F60
RSVD#F60
C54
RSVD#C54
A52 D54
RSVD#A52 RSVD#D54
1 R SVD_TP_BA70 BA70 AY4 T P1_AY4 1 T P610 TPAD14-OP-GP
1 R SVD_TP_BA68 RSVD_TP#BA70 TP1 T P2_BB3 1
TPAD14-OP-GP T P601 BA68
RSVD_TP#BA68 TP2
BB3 T P611 TPAD14-OP-GP
TPAD14-OP-GP T P602
J71 AY71 V SS_AY71 R 602 1 2 0R0402-PAD #54469 CRB.
J68 RSVD#J71 VSS AR56 Z VM# 1 T P616
RSVD#J68 ZVM# TPAD14-OP-GP
1 R SVD_F65 F65 AW71 R SVD_TP_AW 71 1 T P614 TPAD14-OP-GP

1 R SVD_G65 VSS RSVD_TP_AW71RSVD_TP#AW71 R SVD_TP_AW 70 1
TPAD14-OP-GP T P612 G65
VSS
AW70 T P615 TPAD14-OP-GP
TPAD14-OP-GP T P613 RSVD_TP_AW70RSVD_TP#AW70 + VCCST_CPU
F61 AP56 M SM# 1 T P617 TPAD14-OP-GP
E61 RSVD#F61 MSM# C64 P ROC_SELECT# R 603 1 DY 2 100KR2J-1-GP
RSVD#E61 PROC_SELECT#
0515 DY
SKYLAKE-U-GP
PCH strap pin:

C FG3
B
1
B
[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
R 604
DY 1KR2J-1-GP 0 : ENABLED
CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2
1 : DISABLED
(#543016)
C FG4
1
DISPLAY PORT PRESENCE STRAP

R 605
1KR2J-1-GP 0 : ENABLED
CFG[4] An external Display Port device is connected to the Embedded Display Port.
2
1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.
CFG TERMINATIONS #544669 Rev0.52 (CRB)

20140807 david
A <Core Design> A
Wistron Corporation
SKL(#543016): 2 1F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort* Title
CPU_(RESERVED)
A3
V egas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

20170427 CPU1M 13 OF 20
+VCCGT
VCC_CORE
CPU1L 12 OF 20
VCC_CORE
For U22 & U42 CPU POWER 2 OF 4
N70 +VDDQ_CPU_CLK
CPU POWER 1 OF 4 VCCGT
A48 N71
GT_CORE VCCGT VCCGT
A30 G32 A53 SKYLAKE_ULT R63
A34 VCC VCC G33 A58 VCCGT VCCGT R64
VCC VCC +VCCGT VCCGT VCCGT
1
A39 SKYLAKE_ULT G35 A62 R65 1D2V_S3
A44 VCC VCC G37 A66 VCCGT VCCGT R66
DY C722
SC1U10V2KX-1GP
AK33 VCC VCC G38 AA63 VCCGT VCCGT R67
VCC VCC VCCGT VCCGT
2
AK35 G40 AA64 R68
VCC VCC VCCGT VCCGT
1
AK37 G42 AA66 R69
C719
SC1U10V2KX-1GP
DY +VCCIO(ICCMAX.=2.73A
AK38 VCC VCC J30 AA67 VCCGT VCCGT R70 CPU1N 14 OF 20
AK40 VCC VCC J33 AA69 VCCGT VCCGT R71 +VCCIO
VCC VCC VCCGT VCCGT CPU POWER 3 OF 4
2
AL33 J37 AA70 T62
AL37 VCC VCC J40 AA71 VCCGT VCCGT U65 AU23 AK28
AL40 VCC VCC K33 AC64 VCCGT VCCGT U68 AU28 VDDQ VCCIO AK30
AM32 VCC VCC K35 AC65 VCCGT VCCGT U71 AU35 VDDQ SKYLAKE_ULT VCCIO AL30
D D
AM33 VCC VCC K37 AC66 VCCGT VCCGT W63 AU42 VDDQ VCCIO AL42
[46] VCC_SENSE VCC VCC VCCGT VCCGT 1D2V_S3 +VDDQ_CPU_CLK VDDQ VCCIO
AM35 K38 AC67 W64 BB23 AM28
[46] VSS_SENSE VCC VCC VCCGT VCCGT VDDQ VCCIO
AM37 K40 AC68 W65 BB32 AM30
AM38 VCC VCC K42 AC69 VCCGT VCCGT W66 R705 1 2 BB41 VDDQ VCCIO AM42 +VCCSA
G30 VCC VCC K43 AC70 VCCGT VCCGT W67 0R0603-PAD BB47 VDDQ VCCIO
VCC VCC AC71 VCCGT VCCGT W68 BB51 VDDQ AK23
[46] VSSSA_SENSE VCC_SENSE VCCGT VCCGT VDDQ VCCSA
K32 E32 J43 W69 2
SC10U6D3V3MX-GP DY1 C715 AK25
[46] VCCSA_SENSE RSVD#K32RSVD_K32 VCC_SENSE VSS_SENSE GT_CORE VCCGT VCCGT VCCSA
20170427 E33 J45 W70 G23
AK32 VSS_SENSE J46 VCCGT VCCGT W71 +VCCST_CPU AM40 VCCSA G25
[46] VCCGT_SENSE
FOR KBL U22 U42 RSVD#AK32
RSVD_AK32 B63 H_CPU_SVIDALRT# J48 VCCGT VCCGT Y62 VDDQC VCCSA G27
AB62 VIDALERT# A63 H_CPU_SVIDCLK J50 VCCGT VCCGT GTX_CORE SC1U10V2KX-1GP 2 VCCSA
[46] VSSGT_SENSE +V_EDRAM_VR P62 VCCOPC VIDSCK D64 H_CPU_SVIDDAT +VCCSTG J52 VCCGT DY1 C716 0.04 A A18
VCCST VCCSA
G28
J22
+VCCSTG
3A V62 VCCOPC VIDSOUT
+VCCGT
J53 VCCGT AK42 A22 VCCSA J23
VCCOPC G20 +VCCFUSEPRG R703 1 2 J55 VCCGT VCCGTX AK43 SC1U10V2KX-1GP 2 VCCSTG VCCSA
H63 VCCSTG J56 VCCGT VCCGTX AK45
DY1 C717
AL23 VCCSA
J27
K23
+V1.8S_EDRAM VCC_OPC_1P8
0R0402-PAD
J58 VCCGT VCCGTX AK46 VCCPLL_OC VCCSA K25
140mA
Symbol error for layout NC
G61
VCC_OPC_1P8
J60 VCCGT
VCCGT
VCCGTX
VCCGTX
AK48
1D2V_S3
K20
VCCPLL
VCCSA
VCCSA
K27 ???
+VCCGT
AC63
GT_CORE
K48
K50 VCCGT VCCGTX
AK50
AK52
2
SCD1U16V2KX-3GP DY1 C718 K21
VCCPLL VCCSA
K28
K30 20170508
AE63 VCCOPC_SENSE VCCGT VCCGTX VCCSA
VSSOPC_SENSE
R721 1 DY
0R2J-L-GP
2 U22_POWER_K52
+VCCGT
K52
K53 VCCGT VCCGTX
AK53
AK55 AM23 待確認
VCCGT VCCGTX VCCIO_SENSE
+V_EOPIO_VR AE62
AG62 VCCEOPIO follow INTEL suggestion
K55
K56 VCCGT VCCGTX
AK56
AK58
+V1.00U_CPU
VSSIO_SENSE
AM22
KYLOREN
3A VCCEOPIO K58 VCCGT VCCGTX AK60 GTX_CORE 0.12 A H21 VSSSA_SENSE
AL63 K60 VCCGT VCCGTX AK70 VSSSA_SENSE H20 VCCSA_SENSE
AJ62 VCCEOPIO_SENSE VCCGT VCCGTX VCCSA_SENSE
1
L62 AL43 C720 DY C721
VSSEOPIO_SENSE L63 VCCGT VCCGTX AL46
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
L64 VCCGT VCCGTX AL50 SKYLAKE-U-GP
VCCGT VCCGTX
2
SKYLAKE-U-GP L65 AL53
L66 VCCGT VCCGTX AL56 GTX_CORE
L67 VCCGT VCCGTX AL60
L68 VCCGT VCCGTX AM48
VCC_CORE L70 VCCGT VCCGTX AM52
M62 VCCGT VCCGTX AM56
N63 VCCGT VCCGTX AM58
R710 1
R711 1
2 100R2F-L3-GP
2 100R2F-L3-GP
VCC_SENSE
VSS_SENSE
N64
N66
VCCGT
VCCGT
VCCGTX
VCCGTX
AU58
AU63
For U42 only VCC_CORE GT_CORE +VCCGT
N67 VCCGT VCCGTX BB57
N69 VCCGT VCCGTX BB66
C
Layout Note: VCCGT VCCGTX U42 U22 C
R718 1 2 R719 1 2
1. Place close to CPU VCCGT_SENSEJ70 AK62 D0002R5J-GP-U D0002R5J-GP-U
VSSGT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61
2. VCC_SENSE/ VSS_SENSE VSSGT_SENSE VSSGTX_SENSE
impedance=50 ohm
3. Length match<25mil SKYLAKE-U-GP
VCC_CORE GTX_CORE
+VCCGT
U42
R720 1 2
R712 1 2 100R2F-L3-GP VCCGT_SENSE D0002R5J-GP-U
R713 1 2 100R2F-L3-GP VSSGT_SENSE
Layout Note:
1. Place close to CPU
+VCCSA
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil VCCSA_SENSE R716 1 2 100R2F-L3-GP
VSSSA_SENSE R717 1 2 100R2F-L3-GP
Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil
Layout Note:
The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).
Route the Alert signal between the Clock and the Data signals.
B B
SVID DATA
+VCCST_CPU
CLOSE TO CPU
1
R726
100R2F-L3-GP #544669
2
H_CPU_SVIDDAT R709 1 2
VR_SVID_DATA [46]
0R0402-PAD
+VCCST_CPU
SVID_543016:
SVID CLOCK #544669
1
CLOSE TO VR
DY R723
54D9R2F-L1-GP
2
H_CPU_SVIDCLK 1 R732 2
VR_SVID_CLK [46]
0R0402-PAD
A A
+VCCST_CPU
#544669
1
CLOSE TO CPU
R727 <Core Design>
56R2J-4-GP
Wistron Corporation
2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Title
H_CPU_SVIDALRT# R728 1 2
220R2J-L2-GP
VR_SVID_ALERT# [46]
CPU(VCC_CORE)
A2
Turis/Vegas KBL-R A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

CPU1A 1 OF 20
E55 SKYLAKE_ULT C47

[57] HDMI_DATA2# DDI1_TXN[0] EDP_TXN[0] eDP_TX_CPU_N0 [55]
F55 C46
[57] HDMI_DATA2 DDI1_TXP[0] EDP_TXP[0] eDP_TX_CPU_P0 [55]
E58 D46
D HDMI [57]
[57]
HDMI_DATA1#
HDMI_DATA1
F58 DDI1_TXN[1]
DDI1_TXP[1]
EDP_TXN[1]
EDP_TXP[1]
C45
eDP_TX_CPU_N1
eDP_TX_CPU_P1
[55]
[55]
D
F53 A45
[57] HDMI_DATA0# DDI1_TXN[2] EDP_TXN[2]
G53 B45
[57] HDMI_DATA0 DDI1_TXP[2] EDP_TXP[2]
F56 A47
[57] HDMI_CLK# DDI1_TXN[3] EDP_TXN[3]
G56 B47
[57] HDMI_CLK DDI1_TXP[3] EDP_TXP[3]
C50 E45
[56] PCH_DPC_N0 DDI2_TXN[0] DDI EDP_AUXN eDP_AUX_CPU_N [55]
D50 EDP F45
DP to VGA [56]
[56]
PCH_DPC_P0
PCH_DPC_N1
C52 DDI2_TXP[0]
DDI2_TXN[1]
EDP_AUXP eDP_AUX_CPU_P [55]
D52 B52 EDP_DISP_UTIL 1
[56] PCH_DPC_P1 DDI2_TXP[1] EDP_DISP_UTIL
A50 TP801 TPAD14-OP-GP
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50
C51 DDI2_TXN[3] DDI1_AUXP E48
DDI2_TXP[3] DDI2_AUXN PCH_DPC_AUXN [56]
F48
DDI2_AUXP PCH_DPC_AUXP [56]
G46
DISPLAY SIDEBANDS RSVD#G46 F46
L13 RSVD#F46
HDMI [57] CPU_DP1_CTRL_CLK
[57] CPU_DP1_CTRL_DATA
L12 GPP_E18/DDPB_CTRLCLK
GPP_E19/DDPB_CTRLDATA
Strap GPP_E13/DDPB_HPD0
L9
CPU_DP1_HPD [57]
L7
CPU_DP2_HPD [56]
C CPU_DP2_CTRL_CLK N7 SKYLAKE-U-GP GPP_E14/DDPC_HPD1 L6 SIO_EXT_SMI#_R C
CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK Strap GPP_E15/DDPD_HPD2 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10
GPP_E17/EDP_HPD EDP_HPD [55]
TPAD14-OP-GP N11
+VCCIO 1 DDPD_CTRLDATA N12 GPP_E22
TP802
GPP_E23
Strap EDP_BKLTEN
R12
L_BKLT_EN [24]
R801 R11
EDP_COMP EDP_BKLTCTL L_BKLT_CTRL [55]
1 2 E52 U13
EDP_RCOMP EDP_VDDEN EDP_VDD_EN [55]
24D9R2F-L-GP (#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.
Design Guideline:
3D3V_S0 Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.
3D3V_S0
RN801
2 3 CPU_DP1_CTRL_CLK SIO_EXT_SMI#_R R802 1 2 10KR2J-L-GP
1 4 CPU_DP1_CTRL_DATA
CPU_DP2_HPD R806 1Vegas 2 100KR2J-1-GP
SRN2K2J-1-GP
RN803
B
2 3 CPU_DP2_CTRL_DATA Strap pin: B
1 4 CPU_DP2_CTRL_CLK
Vegas Port B /
Sampled at rising edge of PCH_PWROK
SRN2K2J-1-GP
Port C Detected
(#543016) eDP_RCOMP Guideline 0 = Port B is not detected.

DDPB_CTRLDATA * 1 = Port B is detected.
Signal Trace Isolation Resistor Length
Width Spacing Value
0 = Port C is not detected.
eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% Max = 100 mils DDPC_CTRLDATA 1 = Port C is detected.
*
(#543016) DDI Disabling and Termination Guidelines These two signals have weak internal pull-down.
Port Strap Enable Port Disable Port <Core Design>
PU to 3.3 V with 2.2-k
A
Port 1 DDPB_CTRLDATA ±5% resistor NC Wistron Corporation A
PU to 3.3 V with 2.2-k Taipei Hsien 221, Taiwan, R.O.C.
Port 2 DDPC_CTRLDATA ±5% resistor NC
Title
CPU_(DISPLAY)
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

10U 0603 x 4 (#543016 PDG)
VCC_CORE
CORE U-line 23e 28W
IccMax current-10ms max = 34 A
1D2V_S3
PC1001 PC1002 PC1003 PC1004 PC1005 PC1006 PC1007 PC1008 PC1009 PC1010 PC1011 PC1012 PC1013 PC1014 PC1015 PC1055 PC1057 PC1058 PC1056 PC1059 PC1060 PC1061 PC1062 PC1063 PC1064
1
1
DY DY DY DY DY DY DY DY
2
2
D D
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC10U6D3V3MX-GP SC4D7P50V2BN-GP SC22U6D3V3MX-1-GP

22U 0603 x 22 SC4D7P50V2BN-GP
PC1016 PC1017 PC1018 PC1019 PC1020 PC1021 PC1022 PC1023 PC1024 PC1025 PC1026 PC1027 PC1028 PC1029 PC1030 +VCCSA
VCCSA
1
1
DY DY 22U 0603 x 8
2
2
PC1045 PC1046 PC1047 PC1048 PC1049 PC1050 PC1051 PC1052 PC1054 PC1098
1
DY DY
2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

PC1040 PC1066 PC1067 PC1068 PC1097 PC1099 +VCCIO 1D0V_S5 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
1
SC22U6D3V3MX-1-GP
+VCCIO(ICCMAX.=2.73A)
2
U42 U42 U42 DY U42 U42 PC1035 PC1036 PC1037 PC1038 PC1039
1
1
C
DY C
2
2
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 20170810
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP New Common Part
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-GP
+VCCGT
SLICED GT U-line 23e 28W
IccMax current-10ms max[A] = 67 A 22U 0603 x28
PC1031 PC1032 PC1033 PC1034 PC1041 PC1042 PC1043 PC1044 PC1069 PC1070 PC1071 PC1072 PC1073 PC1074 PC1075
1
1
DY DY
2

B PC1076 PC1077 PC1078 PC1079 PC1080 PC1081 PC1082 PC1083 PC1084 PC1085 PC1086 PC1087 PC1088 PC1089 PC1090 B
1
DY DY
2

PC1091 PC1092 PC1093 PC1094 PC1095 PC1096 PC1053 PC1065

1
DY DY DY DY
2
U42 U42

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
A <Core Design> A
Wistron Corporation
Title
CPU_(Power CAP1)
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

PCH DERIVED RAILS UNSLICED GT VCCIO
1D0V_S5 +VCCPRIM_CORE +VCCGT +VCCIO
D
1U 0402 x 6 +VCCIO(ICCMAX.=2.73A) D
R1101 1 2
0R1206-PAD
C1136
C1138
C1147
C1148
C1149
C1150
C1151
C1152
C1153
C1154
1
1
+V1.00A_SIP DY DY DY DY DY
2
R1117 1 2
0R0603-PAD-2-GP-U 1
C1108
SC22U6D3V3MX-1-GP
SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
2

SC1U10V2KX-1GP
+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)
3D3V_S5_PCH +V3.3A_SIP
C C
R1110 1 2 +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP
0R0603-PAD-2-GP-U
C1104
SC22U6D3V3MX-1-GP
1
C1182
SC22U6D3V3MX-1-GP
C1174
SC1U10V2KX-1GP
C1173
C1180
C1184
SC22U6D3V3MX-1-GP
C1172
SC1U10V2KX-1GP
C1176
SC10U6D3V3MX-GP
C1175
SC1U10V2KX-1GP
2
1
2
2
SC1U10V2KX-1GP
SC1U10V2KX-1GP
1D8V_S5 +V1.8A_SIP
Layout Note:
R1139 1 2
0R0603-PAD-2-GP-U
C1106
SC22U6D3V3MX-1-GP
1uF:
1
C1174 near N15

C1180 near K15
2
C1173 near AF20

B
C1172 near N18 B
C1175 near AB19
22uF :
C1182 C1184 near N15
10uF:
C1176 near N15
VCC_CORE
1U 0402 x 5 +VCCPRIM_CORE +V3.3A_SIP
U-line 23e 28W
IccMax current-10ms max = 34 A
C1101
C1102
C1103
C1116
C1117
PC1105
PC1106
C1183
SC10U6D3V3MX-GP
1
1
2
<Core Design>
A SC1U10V2KX-1GP SC1U10V2KX-1GP SC22U6D3V3MX-1-GP A

SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP SC22U6D3V3MX-1-GP Wistron Corporation
Title
CPU_(Power CAP2)
Custom
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = DDR4 SODIMM

DM1A 1 OF 4
DM1D 4 OF 4
20170502 DM1
[5]
[5]
M_A_A0
M_A_A1
144
133
132
A0
A1
DQ0
DQ1
8
7
20
M_A_DQ0 [5]
M_A_DQ1 [5]
DM1B 2 OF 4 1
2 VSS VSS
99
102
062.10011.00U1>
[5]
[5]
[5]
M_A_A2
M_A_A3
M_A_A4
131
128
126
A2
A3
A4
DQ2
DQ3
DQ4
21
4
3
M_A_DQ2 [5]
M_A_DQ3 [5]
M_A_DQ4 [5]
DQS0_C
DQS0_T
11
13
32
M_A_DQS_DN0
M_A_DQS_DP0
M_A_DQS_DN1
5
6
9
VSS
VSS
VSS
VSS
VSS
VSS
103
106
107
062.10011.01C1
[5] M_A_A5 A5 DQ5 M_A_DQ5 [5] DQS1_C M_A_DQS_DP1 VSS VSS
127 16 34 10 167
[5] M_A_A6 A6 DQ6 M_A_DQ6 [5] DQS1_T M_A_DQS_DN2 VSS VSS
122 17 53 14 168
125 28 55 15 171
121 29 74 18 172
D 146 41 76 19 175 D
[5] M_A_A10 A10/AP DQ10 M_A_DQ10 [5] DQS3_T M_A_DQS_DN4 VSS VSS
120 42 177 22 176
119 24 179 23 180
158 25 198 26 181
151 38 200 27 184
[5] M_A_A14 WE#/A14 DQ14 M_A_DQ14 [5] DQS5_T M_A_DQS_DN6 VSS VSS
156 37 219 30 185
[5] M_A_A15 CAS#/A15 DQ15 M_A_DQ15 [5] DQS6_C M_A_DQS_DP6 VSS VSS
152 50 221 31 188
[5] M_A_A16 RAS#/A16 DQ16 M_A_DQ16 [5] DQS6_T M_A_DQS_DN7 VSS VSS
49 240 35 189
DQ17 M_A_DQ17 [5] DQS7_C M_A_DQS_DP7 VSS VSS
150 62 242 36 192
[5] M_A_BA0 BA0 DQ18 M_A_DQ18 [5] DQS7_T VSS VSS
145 63 95 39 193
[5] M_A_BA1 BA1 DQ19 M_A_DQ19 [5] DQS8_C VSS VSS
115 46 97 40 196
[5] M_A_BG0 BG0 DQ20 M_A_DQ20 [5] DQS8_T VSS VSS
113 45 43 197
[5] M_A_BG1 BG1 DQ21 M_A_DQ21 [5] VSS VSS
58 12 44 201
DQ22 M_A_DQ22 [5] DM0#/DBI0# VSS VSS
92 59 33 47 202
CB0/NC DQ23 M_A_DQ23 [5] DM1#/DBI# VSS VSS
91 70 54 48 205
CB1/NC DQ24 M_A_DQ24 [5] DM2#/DBI2# VSS VSS
101 71 75 51 206
105 83 178 52 209
88 84 199 56 210
CB4/NC DQ27 M_A_DQ27 [5] DM5#/DBI5# 1D2V_S3 VSS VSS
87 66 220 57 213
100 67 241 60 214
104 79 96 61 217
CB7/NC DQ30 M_A_DQ30 [5] DM8#/DBI#/NC VSS VSS
80 64 218
DQ31 M_A_DQ31 [5] VSS VSS
137 174 65 222
[5] M_A_CLK0 CK0_T DQ32 M_A_DQ32 [5] VSS VSS
139 173 DDR4-260P-65-GP 68 223
[5] M_A_CLK#0 CK0_C DQ33 M_A_DQ33 [5] VSS VSS
138 187 69 226
[5] M_A_CLK1 CK1_T/NF DQ34 M_A_DQ34 [5] VSS VSS
140 186 72 227
[5] M_A_CLK#1 CK1_C/NF DQ35 M_A_DQ35 [5] 1D2V_S3 3D3V_S0 VSS VSS
170 DM1C 3 OF 4 73 230
DQ36 M_A_DQ36 [5] VSS VSS
109 169 77 231
[5] M_A_CKE0 CKE0 DQ37 M_A_DQ37 [5] VSS VSS
110 183 111 255 78 234
[5] M_A_CKE1 CKE1 DQ38 M_A_DQ38 [5] VDD VDDSPD VSS VSS
182 112 81 235
DQ39 M_A_DQ39 [5] VDD VSS VSS
149 195 117 82 238
C1201
SC2D2U10V3KX-L-GP
C1228
SCD1U16V2KX-3GP
[5] M_A_CS#0 CS0# DQ40 M_A_DQ40 [5] VDD VSS VSS
1
157 194 118 257 2D5V_S3 DY DY 85 239
[5] M_A_CS#1 CS1# DQ41 M_A_DQ41 [5] VDD VPP VSS VSS
162 207 123 259 86 243
C0/CS2#/NC DQ42 M_A_DQ42 [5] VDD VPP VSS VSS
C 165 208 124 89 244 C
C1/CS3#/NC DQ43 M_A_DQ43 [5] VDD VSS VSS
2
191 129 258 0D6V_S0 90 247
DQ44 M_A_DQ44 [5] VDD VTT VSS VSS
155 190 130 93 248
[5] M_A_DIMA_ODT0 ODT0 DQ45 M_A_DQ45 [5] VDD VSS VSS
161 203 135 94 251
[5] M_A_DIMA_ODT1 ODT1 DQ46 M_A_DQ46 [5] VDD VSS VSS
204 136 98 252
SA0_CHA_DIM0 DQ47 M_A_DQ47 [5] VDD VSS VSS
256 216 141
SA1_CHA_DIM0 SA0 DQ48 M_A_DQ48 [5] VDD
260 215 142
SA2_CHA_DIM0 SA1 DQ49 M_A_DQ49 [5] VDD
166 228 147 261 DDR4-260P-65-GP
SA2 DQ50 M_A_DQ50 [5] VDD 261
229 148 262
DQ51 M_A_DQ51 [5] VDD 262
254 211 153
[13,18,56,65,67] PCH_SMBDATA SDA DQ52 M_A_DQ52 [5] VDD
253 212 154
[13,18,56,65,67] PCH_SMBCLK SCL DQ53 M_A_DQ53 [5] VDD
224 159 NP1
DQ54 M_A_DQ54 [5] VDD NP1
225 160 NP2
DQ55 M_A_DQ55 [5] VDD NP2
108 237 163
1D2V_S3 [5,13] DDR4_DRAMRST# RESET# DQ56 M_A_DQ56 [5] VDD
114 236
[5] M_A_ACT_N ACT# DQ57 M_A_DQ57 [5]
116 249
[5] M_A_ALERT_N TS#_DIMM0_1 ALERT# DQ58 M_A_DQ58 [5]
R1215 1 DY 2 134 250 DDR4-260P-65-GP
EVENT#/NF DQ59 M_A_DQ59 [5]
240R2F-1-GP 232
DQ60 M_A_DQ60 [5]
143 233
[5] M_A_PARITY PARITY DQ61 M_A_DQ61 [5]
245
M_VREF_CA_DIMMA164 DQ62 M_A_DQ62 [5]
246 UN 0225
VREFCA DQ63 M_A_DQ63 [5]
1
C1229
DDR4_DRAMRST# SCD1U16V2KX-3GP DDR4-260P-65-GP
062.10011.01C1
2
1
1D2V_S3 0D6V_S0 0D6V_S0 0D6V_S0

ED1217
AZ5725-01FDR7G-GP
???跟sw確認 DDR4 SWAP 0212
C1202
C1203
C1204
C1205
C1206
C1208
C1209
C1210
C1223
C1230
C1224
C1227
C1225
C1226
1
1
DY DY DY DY DY DY DY
2
3D3V_S0
2
2
B B
R1204 1 2 10KR2F-L1-GP SA0_CHA_DIM0
DY
Layout note: closed to Dimm
R1205 1 2 0R0402-PAD
SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC4D7U6D3V2MX-1-GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP
SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC4D7U6D3V2MX-1-GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP
SC10U6D3V3MX-GP SC10U6D3V3MX-GP
1D2V_S3
SC10U6D3V3MX-GP SC10U6D3V3MX-GP for placement modify 2015/10/19
RN1201 R1206
1 4 2R2F-GP 3D3V_S0
C1214
C1215
C1216
C1217
C1218
C1219
C1220
C1221
1
1
2 3 M_VREF_CA_DIMMA1 2 2D5V_S3
V_SM_VREF_CNTA [5] SA1_CHA_DIM0
R1208 1 DY 2 10KR2F-L1-GP DY DY DY DY
1
SRN1KJ-7-GP C1222
2
2
SCD022U16V2KX-3GP R1210 1 2 0R0402-PAD
C1211
C1212
C1231
C1232
C1207
C1213
2
1
+V_VREF_PATH1
DY DY DY DY DY
1
2
R1209 SC1U10V2KX-1GP SC1U10V2KX-1GP
24D9R2F-L-GP SC1U10V2KX-1GP SC1U10V2KX-1GP
3D3V_S0 SC1U10V2KX-1GP SC1U10V2KX-1GP
SC1U10V2KX-1GP SC1U10V2KX-1GP
2
R1211 1 2 10KR2F-L1-GP SA2_CHA_DIM0 SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP

DY SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP
R1212 1 2 0R0402-PAD SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
M_A_DQS_DN[7:0] [5]
M_A_DQS_DP[7:0] [5]
M_A_DQS_DN0 M_A_DQS_DP0
A M_A_DQS_DN2 M_A_DQS_DP2 A
M_A_DQS_DN4 M_A_DQS_DP4 <Core Design>
Wistron Corporation
Title
DDR4-SODIMM1
Custom
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = DDR4 SODIMM

20170502 DM1
144
DM2A 1 OF 4
8 M_B_DQ8 [5]
1D2V_S3
DM2C 3 OF 4 3D3V_S0
062.10011.00T1>
062.10011.01B1
[5] M_B_A0 A0 DQ0
133 7 M_B_DQ9 [5] DM2D 4 OF 4
[5] M_B_A1 A1 DQ1
132 20 M_B_DQ10 [5] 111 255
[5] M_B_A2 A2 DQ2 VDD VDDSPD
131 21 M_B_DQ11 [5] 112 1 99
[5] M_B_A3 A3 DQ3 VDD VSS VSS
128 4 117 2 102
C1329
SC2D2U10V3KX-L-GP
C1328
SCD1U16V2KX-3GP
[5] M_B_A4 A4 DQ4 M_B_DQ12 [5] VDD VSS VSS
1
126 3 M_B_DQ13 [5] 118 257 2D5V_S3 DY DY 5 103
[5] M_B_A5 A5 DQ5 VDD VPP VSS VSS
127 16 M_B_DQ14 [5] 123 259 6 106
[5] M_B_A6 A6 DQ6 VDD VPP VSS VSS
122 17 M_B_DQ15 [5] 124 9 107
2
125 28 M_B_DQ0 [5] 129 258 0D6V_S0 10 167
[5] M_B_A8 A8 DQ8 VDD VTT VSS VSS
121 29 M_B_DQ1 [5] 130 14 168
D [5] M_B_A9 A9 DQ9 VDD VSS VSS D
146 41 M_B_DQ2 [5] 135 15 171
[5] M_B_A10 A10/AP DQ10 VDD VSS VSS
120 42 M_B_DQ3 [5] 136 18 172
119 24 M_B_DQ4 [5] 141 19 175
158 25 M_B_DQ5 [5] 142 22 176
151 38 M_B_DQ6 [5] 147 261 23 180
[5] M_B_A14 WE#/A14 DQ14 VDD 261 VSS VSS
156 37 M_B_DQ7 [5] 148 262 26 181
[5] M_B_A15 CAS#/A15 DQ15 VDD 262 VSS VSS
152 50 M_B_DQ16 [5] 153 27 184
[5] M_B_A16 RAS#/A16 DQ16 VDD VSS VSS
49 M_B_DQ17 [5] 154 30 185
150 DQ17 62 159 VDD NP1 31 VSS VSS 188
[5] M_B_BA0 BA0 DQ18 M_B_DQ18 [5] VDD NP1 VSS VSS
145 63 M_B_DQ19 [5] 160 NP2 35 189
[5] M_B_BA1 BA1 DQ19 VDD NP2 VSS VSS
115 46 M_B_DQ20 [5] 163 36 192
[5] M_B_BG0 BG0 DQ20 VDD VSS VSS
113 45 M_B_DQ21 [5] 39 193
[5] M_B_BG1 BG1 DQ21 VSS VSS
58 M_B_DQ22 [5] 40 196
92 DQ22 59 DDR4-260P-64-GP 43 VSS VSS 197
CB0/NC DQ23 M_B_DQ23 [5] VSS VSS
91 70 M_B_DQ24 [5] 44 201
101 CB1/NC DQ24 71 47 VSS VSS 202
105 83 M_B_DQ26 [5] 48 205
88 CB3/NC DQ26 84 51 VSS VSS 206
87 66 M_B_DQ28 [5] 52 209
100 CB5/NC DQ28 67 DM2B 2 OF 4 56 VSS VSS 210
104 79 M_B_DQ30 [5] 57 213
CB7/NC DQ30 80 11 M_B_DQS_DN1 60 VSS VSS 214
DQ31 M_B_DQ31 [5] DQS0_C M_B_DQS_DN1 [5] VSS VSS
137 174 M_B_DQ32 [5] 13 M_B_DQS_DP1 M_B_DQS_DP1 [5] 61 217
[5] M_B_CLK0 CK0_T DQ32 DQS0_T M_B_DQS_DN0 VSS VSS
139 173 M_B_DQ33 [5] 32 M_B_DQS_DN0 [5] 64 218
[5] M_B_CLK#0 CK0_C DQ33 DQS1_C M_B_DQS_DP0 VSS VSS
138 187 M_B_DQ34 [5] 34 M_B_DQS_DP0 [5] 65 222
[5] M_B_CLK1 CK1_T/NF DQ34 DQS1_T M_B_DQS_DN2 VSS VSS
140 186 M_B_DQ35 [5] 53 M_B_DQS_DN2 [5] 68 223
[5] M_B_CLK#1 CK1_C/NF DQ35 DQS2_C M_B_DQS_DP2 VSS VSS
170 M_B_DQ36 [5] 55 M_B_DQS_DP2 [5] 69 226
109 DQ36 169 DQS2_T 74 M_B_DQS_DN3 72 VSS VSS 227
[5] M_B_CKE0 CKE0 DQ37 M_B_DQ37 [5] DQS3_C M_B_DQS_DN3 [5] VSS VSS
[5] M_B_CKE1 CKE1 DQ38 DQS3_T M_B_DQS_DN4 VSS VSS
182 M_B_DQ39 [5] 177 M_B_DQS_DN4 [5] 77 231
149 DQ39 195 DQS4_C 179 M_B_DQS_DP4 78 VSS VSS 234
[5] M_B_CS#0 CS0# DQ40 M_B_DQ40 [5] DQS4_T M_B_DQS_DP4 [5] VSS VSS
157 194 198 M_B_DQS_DN5 81 235
[5] M_B_CS#1 CS1# DQ41 M_B_DQ41 [5] DQS5_C M_B_DQS_DN5 [5] VSS VSS
165 C0/CS2#/NC DQ42 208 DQS5_T 219 M_B_DQS_DN6 85 VSS VSS 239
C C1/CS3#/NC DQ43 M_B_DQ43 [5] DQS6_C M_B_DQS_DN6 [5] VSS VSS C
191 221 M_B_DQS_DP6 86 243
DQ44 M_B_DQ44 [5] DQS6_T M_B_DQS_DP6 [5] VSS VSS
155 190 M_B_DQ45 [5] 240 M_B_DQS_DN7 M_B_DQS_DN7 [5] 89 244
[5] M_B_DIMB_ODT0 ODT0 DQ45 DQS7_C M_B_DQS_DP7 VSS VSS
161 203 M_B_DQ46 [5] 242 M_B_DQS_DP7 [5] 90 247
[5] M_B_DIMB_ODT1 ODT1 DQ46 DQS7_T VSS VSS
204 M_B_DQ47 [5] 95 93 248
SA0_CHB_DIM0 256 DQ47 216 DQS8_C 97 94 VSS VSS 251
SA0 DQ48 M_B_DQ48 [5] DQS8_T VSS VSS
SA1_CHB_DIM0 260 215 98 252
SA1 DQ49 M_B_DQ49 [5] VSS VSS
SA2_CHB_DIM0 166 228 M_B_DQ50 [5] 12
SA2 DQ50 229 DM0#/DBI0# 33
DQ51 M_B_DQ51 [5] DM1#/DBI#
254 211 M_B_DQ52 [5] 54 DDR4-260P-64-GP
[12,18,56,65,67] PCH_SMBDATA SDA DQ52 DM2#/DBI2#
253 212 M_B_DQ53 [5] 75
[12,18,56,65,67] PCH_SMBCLK SCL DQ53 DM3#/DBI3#
224 M_B_DQ54 [5] 178
DQ54 225 DM4#/DBI4# 199
DQ55 M_B_DQ55 [5] DM5#/DBI5#
108 237 M_B_DQ56 [5] 220
1D2V_S3 [5,12,13] DDR4_DRAMRST# RESET# DQ56 DM6#/DBI6#
114 236 M_B_DQ57 [5] 241
[5] M_B_ACT_N ACT# DQ57 DM7#/DBI7#
116 249 M_B_DQ58 [5] 96 1D2V_S3
[5] M_B_ALERT_N TS#_DIMM1_1 134 ALERT# DQ58 DM8#/DBI#/NC
R1312 1 DY 2 250 M_B_DQ59 [5]
240R2F-1-GP EVENT#/NF DQ59 232
DQ60 M_B_DQ60 [5]
143 233 M_B_DQ61 [5] DDR4-260P-64-GP
[5] M_B_PARITY PARITY DQ61 245 M_B_DQ62 [5]
M_VREF_CA_DIMMB 164 DQ62 246
VREFCA DQ63 M_B_DQ63 [5]
0D6V_S0 0D6V_S0 0D6V_S0 2D5V_S3
1
C1301
SCD1U16V2KX-3GP DDR4-260P-64-GP
DDR4_DRAMRST#
062.10011.01B1
2
C1324
SC10U6D3V3MX-GP
C1325
SC10U6D3V3MX-GP
C1326
C1327
C1311
C1312
C1330
C1331
C1313
C1314
1D2V_S3
1
1
跟sw確認 DDR4 SWAP 0212 DY DY DY DY DY
ED1302
AZ5725-01FDR7G-GP
2
3D3V_S0
2
R1302 1 2 10KR2F-L1-GP SA0_CHB_DIM0
C1303
C1304
C1305
C1306
C1307
C1308
C1309
C1310
DY
1
DY DY DY DY DY SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP
B B
R1303 1 2 0R0402-PAD SC1U10V2KX-1GP SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP
UN 0225 SC4D7U6D3V2MX-1-GP
2
Layout note: closed to Dimm SC4D7U6D3V2MX-1-GP
0921 Install
3D3V_S0 SC10U6D3V3MX-GP SC10U6D3V3MX-GP

1D2V_S3 SC10U6D3V3MX-GP SC10U6D3V3MX-GP M_B_DQS_DN[7:0] [5]
R1306 1 2 10KR2F-L1-GP SA1_CHB_DIM0 SC10U6D3V3MX-GP SC10U6D3V3MX-GP M_B_DQS_DN0
RN1301 SC10U6D3V3MX-GP SC10U6D3V3MX-GP M_B_DQS_DN1
1 4 R1305 R1307 1 2 0R2J-L-GP M_B_DQS_DN2
M_VREF_CA_DIMMB 1
DY M_B_DQS_DN3
2 3 2
V_SM_VREF_CNTB [5] M_B_DQS_DN4
C1315
C1316
C1317
C1318
C1319
C1320
C1321
C1322
1
1
SRN1KJ-7-GP 2R2F-GP M_B_DQS_DN5
DY DY DY DY
1
C1323 M_B_DQS_DN6
SCD022U16V2KX-3GP M_B_DQS_DN7
2
2
3D3V_S0
2
M_B_DQS_DP[7:0] [5]
+V_VREF_PATH2 R1310 1 2 10KR2F-L1-GP SA2_CHB_DIM0 M_B_DQS_DP0
DY
1
M_B_DQS_DP1
R1309 R1311 1 2 0R0402-PAD M_B_DQS_DP2
24D9R2F-L-GP SC1U10V2KX-1GP SC1U10V2KX-1GP M_B_DQS_DP3
SC1U10V2KX-1GP SC1U10V2KX-1GP M_B_DQS_DP4
2

M_B_DQS_DP7
A A
<Core Design>
Wistron Corporation
Title
DDR4-SODIMM1
Custom
Vegas SKL/KBL-U
Wednesday, November 08, 2017
A00
Date: Sheet 13 of 106
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

3D3V_S0
CPU1I 9 OF 20
CSI-2 SKYLAKE_ULT
W IFI_RF_EN R1503 1 2
A36 C37
DY
10KR2J-L-GP
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D D
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29 DC resistance < 0.5ohm.
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP R1501 1 2 100R2F-L3-GP
D31 CSI2_DN4 CSI2_COMP B7 W IFI_RF_EN
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 EMMC_D0 [63] [#545659 Rev0.7]
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3 EMMC_D1 [63]
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 EMMC_D2 [63]
A29 GPP_F16/EMMC_DATA3 AN1 EMMC_D3 [63]
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2 EMMC_D4 [63]
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4 EMMC_D5 [63]
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1 EMMC_D6 [63]
A27 CSI2_DP9 GPP_F20/EMMC_DATA7 EMMC_D7 [63]
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3 EMMC_RCLK [63]
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4 EMMC_CLK [63]
CSI2_DP11 GPP_F12/EMMC_CMD EMMC_CMD [63]
AT1 EMMC_RCOMP R1502 1 2 200R2F-L-GP
EMMC_RCOMP
SKYLAKE-U-GP
C C
GPP_F: VCCPGPPF = 1.8V Only
[61] W IFI_RF_EN
B B
A <Core Design> A
Wistron Corporation
Title
CPU_(CS-2/EMMC)
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
#543016:
CPU1H 8 OF 20
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2. SKYLAKE_ULT
SSIC / USB3
PCIE/USB3/SATA
H8 (#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
USB3_1_RXN G8 USB30_RX_CPU_N1 [36]
H13 USB3_1_RXP C13 USB30_RX_CPU_P1 [36]
[76] PEG_RX_CPU_N0
[76] PEG_RX_CPU_P0
G13 PCIE1_RXN/USB3_5_RXN
PCIE1_RXP/USB3_5_RXP
USB3_1_TXN
USB3_1_TXP
D13
USB30_TX_CPU_N1 [36]
USB30_TX_CPU_P1 [36]
USB1 (USB3.0 Port1)
C1606 1OPS2 SCD22U10V2KX-L1-GP PEG_TX_CPU_N0 B17
[76] PEG_TX_GPU_N0 PEG_TX_CPU_P0 PCIE1_TXN/USB3_5_TXN
D
[76] PEG_TX_GPU_P0 C1605 1OPS2 SCD22U10V2KX-L1-GP A17 J6 D
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_RXN H6 USB30_RX_CPU_N2 [36]
[76] PEG_RX_CPU_N1
G11
PCIE2_RXN/USB3_6_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
B13 USB30_RX_CPU_P2 [36]
USB30_TX_CPU_N2 [36]
USB2 (USB3.0 Port2)
[76] PEG_RX_CPU_P1
F11 A13 USB30_TX_CPU_P2 [36]
C1608 1OPS2 SCD22U10V2KX-L1-GP PEG_TX_CPU_N1 D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_TXP
[76] PEG_TX_GPU_N1 PEG_TX_CPU_P1 PCIE2_TXN/USB3_6_TXN
C1607 1OPS2 SCD22U10V2KX-L1-GP C16 J10
GPU [76] PEG_TX_GPU_P1 PCIE2_TXP/USB3_6_TXP USB3_3_RXN
USB3_3_RXP
H10
[76] PEG_RX_CPU_N2
H16 B15
G16 PCIE3_RXN USB3_3_TXN A15
[76] PEG_RX_CPU_P2 PEG_TX_CPU_N2 PCIE3_RXP USB3_3_TXP
[76] PEG_TX_GPU_N2 C1610 1OPS2 SCD22U10V2KX-L1-GP D17
C1609 1OPS2 SCD22U10V2KX-L1-GP PEG_TX_CPU_P2 C17 PCIE3_TXN E10
[76] PEG_TX_GPU_P2 PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
[76] PEG_RX_CPU_N3 PCIE4_RXN USB3_4_TXN
[76] PEG_RX_CPU_P3
F15 D15
C1612 1OPS2 SCD22U10V2KX-L1-GP PEG_TX_CPU_N3 B19 PCIE4_RXP USB3_4_TXP
[76] PEG_TX_GPU_N3 PEG_TX_CPU_P3 PCIE4_TXN
C1611 1OPS2 SCD22U10V2KX-L1-GP A19 AB9
0516 Swap
[76] PEG_TX_GPU_P3 PCIE4_TXP USB2N_1
USB2P_1
AB10
USB_CPU_PN0
USB_CPU_PP0
[36]
[36]
USB1 (USB3.0 port1)
[31] PCIE_RX_CPU_N5
F16
E16 PCIE5_RXN AD6
LAN [31] PCIE_RX_CPU_P5
[31] PCIE_TX_CON_N5 C1601 1 2 SCD1U16V2KX-3GP PCIE_TX_CPU_N5 C19 PCIE5_RXP
PCIE5_TXN
USB2N_2
USB2P_2
AD7
USB_CPU_PN1
USB_CPU_PP1
[36]
[36]
USB2 (USB3.0 Port2)
C1602 1 2 SCD1U16V2KX-3GP PCIE_TX_CPU_P5 D19
[31] PCIE_TX_CON_P5 PCIE5_TXP AH3
[61] PCIE_RX_CPU_N6
G18
PCIE6_RXN
USB2N_3
USB2P_3
AJ3
USB_CPU_PN2
USB_CPU_PP2
[37]
[37]
USB3 (IO BD/USB2.0 Port3)
F18
WLAN [61] PCIE_RX_CPU_P6
[61] PCIE_TX_CON_N6 C1603 1 2 SCD1U16V2KX-3GP PCIE_TX_CPU_N6 D20 PCIE6_RXP
PCIE6_TXN USB2N_4
AD9
C1604 1 2 SCD1U16V2KX-3GP PCIE_TX_CPU_P6 C20 AD10
[61] PCIE_TX_CON_P6 PCIE6_TXP USB2P_4
F20 AJ1
[60] SATA_RX_CPU_N0
E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2
USB_CPU_PN4 [55]
CAMERA (USB2.0 Port5)
HDD1 [60] SATA_RX_CPU_P0
[60] SATA_TX_CPU_N0
B21 PCIE7_RXP/SATA0_RXP
PCIE7_TXN/SATA0_TXN
USB2
USB2P_5 USB_CPU_PP4 [55]
A21 AF6
[60] SATA_TX_CPU_P0 PCIE7_TXP/SATA0_TXP USB2N_6
USB2P_6
AF7
USB_CPU_PN5
USB_CPU_PP5
[33]
[33]
Card Reader (USB2.0 Port6)
[60] SATA_RX_CPU_N1
G21
F21 PCIE8_RXN/SATA1A_RXN AH1
ODD [60] SATA_RX_CPU_P1
[60] SATA_TX_CPU_N1
D21 PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
USB2N_7
USB2P_7
AH2
USB_CPU_PN6
USB_CPU_PP6
[61]
[61]
WLAN (USB2.0 Port7)
[60] SATA_TX_CPU_P1
C21
PCIE8_TXP/SATA1A_TXP AF8
E22
PCIE9_RXN
USB2N_8
USB2P_8
AF9
USB_CPU_PN7
USB_CPU_PP7
[55]
[55]
Touch Screen (USB2.0 Port8)
E23
B23 PCIE9_RXP AG1
A23 PCIE9_TXN
PCIE9_TXP
USB2N_9
USB2P_9
AG2
USB_CPU_PN8
USB_CPU_PP8
[92]
[92]
Finger Print (USB2.0 Port9)
0511 Remove SSD F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
PCIE10_RXP USB2P_10
DC resistance < 0.5ohm.
D23
+V1.8A_SIP C23 PCIE10_TXN AB6 USBCOMP R1603 1 2 113R2F-GP
PCIE10_TXP USB2_COMP AG3 USB2_ID R1601 1 2 0R0402-PAD
PCIE_RCOMPN USB2_ID USB2_VBUSSENSE
1
F5 AG4 R1602 1 2 0R0402-PAD

R1607 R1604 1 2 PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE Unused SATA[3:0]GP pins must be terminated to either
10KR2J-L-GP 100R2F-L3-GP PCIE_RCOMPP A9 3.3V rail or GND using 8.2K to 10K on the
1 XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1# USB_OC0# [35] motherboard. Either pull-up or pull-down is acceptable.
0620 Connect to TPM TPAD14-OP-GP TP1601 1 XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2#
PROC_PREQ# GPP_E11/USB2_OC2# USB_OC2# [35]
2
TPAD14-OP-GP TP1602 PIRQA# BB11 B9 USB_OC3#

[91] PIRQA# GPP_A7/PIRQA# GPP_E12/USB2_OC3#
(#543016) When used as DEVSLP, no external pull-up or pull-down
E28 J1 HDD_DEVSLP [60] termination required from SATA Host DEVSLP.
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 SIO_EXT_SCI#
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 TP1603 TPAD14-OP-GP
C E30 PCIE11_TXP/SATA1B_TXP H2 GPP_E0/SATAXPCIE0/SATAGP0 1 C
0511 Remove SSD F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 SATA_ODD_PRSNT# [60]
A25 G4
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1
GPP_E8/SATALED# SATA_LED#_R [64] 3D3V_S0
SKYLAKE-U-GP 3D3V_S5_PCH
3D3V_S0
3D3V_S0 RN802 SIO_EXT_SCI# R1610 1 2
USB_OC2# 8 1 10KR2J-L-GP
USB_OC3# 7 2
Layout Note: USB_OC0# 6 3 SATA_LED#_R R1606 1 2
SATA_ODD_PRSNT# R1608 1 2 USB_OC1# 5 4 10KR2J-L-GP
10KR2J-L-GP
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace)
Note: Must maintain low DC resistance routing (<0.1 ohm). SRN10KJ-6-GP
2. Isolation Spacing: At least 12 mils to any adjacent
high speed I/O. (#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND
using 8.2 KΩ to 10 KΩ on the motherboard. (#543611)
Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable. The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.
PCIE Table USB 2.0 Table

Port Device Share BUS Pair Device
1 N/A USB3.0_3 0 USB3.0 port1
2 N/A USB3.0_4 1 USB3.0 Port2
3 WLAN 2 USB2.0 Port3 (IOBD)
B
4 LAN 3 Finger Print B
5(L0~L3) GPU 4 CAMERA
6(L3) HDD SATA0 5 Card Reader
6(L2) ODD SATA1 6 Touch Panel
6(L0~L1) N/A 7 WLAN
#545659 (SKL_PCH_U_Y_EDS Rev0.7)
A A
<Core Design>
Wistron Corporation
Title
CPU_(PCIE/SATA/USB)
A1
5 4 3 2 1
5 4 3 2 1
Main Func = PCH +V3.3A_SIP
1
3D3V_S5 CPU1K 11 OF 20
RN1704 R1701
1 8 AC_PRESENT 10KR2J-L-GP SYSTEM POWER MANAGEMENT
2 7 PCH_W AKE# AT11 SIO_SLP_S0# 1 TP1701 TPAD14-OP-GP
3 6 PCH_BATLOW # SKYLAKE_ULT GPP_B12/SLP_S0# AP15 SIO_SLP_S3#
GPD4/SLP_S3# SIO_SLP_S3# [24,27,40,51]
2
4 5 GPD11/LANPHYPC PCH_PLTRST# AN10 BA16 SIO_SLP_S4#
GPD11 pull high XDP_DBRESET# GPP_B13/PLTRST# GPD5/SLP_S4# SIO_SLP_S5# SIO_SLP_S4# [40,44,51]
B5 AY16 1
SRN10KJ-6-GP by Intel PDG1.3 request PM_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5# TP1703 TPAD14-OP-GP
RSMRST# AN15 SLP_SUS# 1 TP1702 TPAD14-OP-GP
BATLOW#: R1720 1 2 10KR2J-L-GP H_CPUPW RGD A68 SLP_SUS# AW15 SLP_LAN# 1 TP1704 TPAD14-OP-GP
D
Pull-up required even if not implemented. H_VCCST_PW RGD_R R1734 1
DY 2 60D4R2F-GP H_VCCST_PW RGD B65 PROCPWRGD SLP_LAN# BB17 GPD9/SLP_W LAN# 1 TP1705 TPAD14-OP-GP
D
VCCST_PWRGD GPD9/SLP_WLAN# AN16 SIO_SLP_A# 1 TP1706 TPAD14-OP-GP
SYS_PW ROK SYS_PW ROK B6 GPD6/SLP_A#
RESET_OUT# R1706 1 2 0R0402-PAD PM_PCH_PW ROK BA20 SYS_PWROK BA15 SIO_PW RBTN#
3D3V_S5 +VCCPDSW _3P3 PM_RSMRST# PCH_DPW ROK PCH_PWROK GPD3/PWRBTN# AC_PRESENT SIO_PW RBTN# [24]
R1704 1 2 0R0402-PAD BB20 AY15
DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW #
GPD0/BATLOW#
1
R1711 1 2 ME_SUS_PWR_ACK_R AR13
0R0603-PAD-2-GP-U SUSACK#_R AP11 GPP_A13/SUSWARN#/SUSPWRDNACK DY EC1707
SCD1U16V2KX-3GP
DY for OBFF disable GPP_A15/SUSACK# AU11 PME# 1 TP1707
GPP_A11/PME#
2
Layout note: 3 PAD SHARING PCH_W AKE# BB15 AP16 SM_INTRUDER# TPAD14-OP-GP
R1707 1 2 10KR2J-L-GP GPD2/LAN_W AKE# AM15 WAKE# INTRUDER#
+VCCPDSW _3P3 GPD2/LAN_WAKE#
GPD11/LANPHYPC AW17 AM10 EXT_PW R_GATE#
RTC_AUX_S5 R1710 1 2 0R0402-PAD AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11
#544669 (CRB): 330k. [24] LANW AKE# GPD7/RSVD#AT15 GPP_B2/VRALERT#
R1730 1 2 330KR2J-L1-GP SM_INTRUDER#
SKYLAKE-U-GP
3D3V_S5_PCH
(PDG#543016) 071.SKYLA.000U [#543016 Rev0.7]
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.
0516 Follow Taos DY EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k
R1731 1 DY 2 20KR2J-L2-GP EXT_PW R_GATE# pull-down that is active during the early portion of the power up sequence
RN1701
1 4 PM_PCH_PW ROK
2 3 PM_RSMRST#
SRN10KJ-5-GP
R1713 1 2 PCH_PLTRST#
SYS_PW ROK [31,55,61,63,76,91] PLT_RST#
C R1717 1DY 2 0R0402-PAD C
1
10KR2J-L-GP
1
R1715 DY DY C1701
100KR2J-1-GP SC220P50V2KX-3GP
2
2
+VCCMPHYGTAON_1P0
+VCCSTG D1702
1D0V_S5 +VCCMPHYGTAON_1P0_LS_SIP A K
ACOK_IN [24,44]
1
(ICCMAX.=3.5A)
R1724 1 2 DY R1722 RB751V-40H-GP
Q1702
0R0805-PAD-2-GP-U 100KR2J-1-GP 83.R2004.G8F
3D3V_AUX_S5 S 4 3 D AC_PRESENT
1
R1735 1 2 C1704
2
0R0805-PAD-2-GP-U SC10U6D3V3MX-GP R1716 1 2 H_VCCST_PW RGD_R G 5 2 G PM_RSMRST#
[24,40] ALL_SYS_PW RGD
100KR2F-L3-GP NON DS3 NON DS3
2
R1737 1 2 PM_RSMRST#_M D 6 1 S
1
100KR2J-1-GP
1
1
DY EC1709
SCD1U16V2KX-3GP
R1719
47KR2F-GP
DY EC1708
SCD01U50V2KX-L-GP
2N7002KDW-GP
84.2N702.A3F
2
2
2nd = 84.2N702.E3F
2
3rd = 75.00601.07C
3D3V_AUX_S5
B B
R1727 1
NON DS3
2 0516 Follow Taos DY
100KR2J-1-GP
1
XDP_DBRESET# +V1.8A_SIP
R1726 Q1701 SYS_PW ROK
10KR2J-L-GP PLT_RST#
1
S 4 3 D PM_RSMRST# R1702 1 2 1KR2J-1-GP PCH_RSMRST# RESET_OUT#
S2 PCH_RSMRST# [24] 3V_5V_POK
DY R1718
D2
2
3V_5V_POK# G 5 2 G 3V_5V_POK_C R1728 1 2 0R0402-PAD 10KR2J-L-GP

3V_5V_POK [21,40,45,53,54]
1
1
G2 G1
EC1706
SC1KP50V2KX-L-1-GP
EC1702
SC1KP50V2KX-L-1-GP
EC1703
SC1KP50V2KX-L-1-GP
AZ5325-01FDR7G-GP
EU1701
EC1705
SC1KP50V2KX-L-1-GP
DY EC1712
1
D 6 1 S SCD1U16V2KX-3GP DY DY DY DY
2
ME_SUS_PW R_ACK_R
D1 S1
2
2
PJT138KA-GP R1708 1 2 SUSACK#_R
075.00138.0A7C 0R0402-PAD
2
[24] SYS_PW ROK
[24,26,79] RESET_OUT#
A <Core Design> A
Wistron Corporation
Title
CPU_(POWER MANAGEMENT)
A3
5 4 3 2 1
5 4 3 2 1
Main Func = PCH PCH strap pin: PCH Prim PCH strap pin:
PCH Prim
eSPI or LPC Sampled at rising edge of RSMRST# 3D3V_S5_PCH BOOT HALT 3D3V_S5_PCH 3D3V_S0
R1834 1 2 10KR2J-L-GP 3D3V_S0
3D3V_S5_PCH R1835 and R1834 merge to RN1802 SML0ALERT# / This signal has a weak internal pull-down. SPI0_MOSI 0 = ENABLED R1835 1 2 10KR2J-L-GP
0 = LPC Is selected for EC. 1 = DISABLED
1
Follow Starlord
GPP_C5
1 = eSPI Is selected for EC. R1822 WEAK INTERNAL PU DY R1824
R1827 1 2 SPI_HOLD_ROM 1KR2J-1-GP 1KR2J-1-GP Q1801
1KR2J-1-GP This signal has a weak internal pull-down. This signal has a weak internal pull-up. MEM_SMBDATA 6 1
SPI_WP_ROM PCH_SMBDATA [12,13,56,65,67]
R1828 1 2
2
1KR2J-1-GP GPP_C5/SML0ALERT# SPI_SI_CPU 84.2N702.A3F 5 2
2nd = 84.2N702.E3F
1
3rd = 75.00601.07C 4 3
D
0511 Follow KY15.
DY R1823
1KR2J-1-GP
DY R1825
1KR2J-1-GP 2N7002KDW-GP D
+V1.8A_SIP
PCH_SMBCLK [12,13,56,65,67]
2
R1816 1 2 SIO_RCIN# MEM_SMBCLK
10KR2J-L-GP
3D3V_S5_PCH
RN1807
SML1_SMBDATA 8 1
SML1_SMBCLK 7 2
SML0_SMBDATA 6 3
SML0_SMBCLK 5 4
CPU1E 5 OF 20 SRN2K2J-4-GP
Resister value will check later SPI - FLASH 0516 Check with SW(Internal PH?)
SMBUS, SMLINK
R1806 1 2 0R0402-PAD SPI_CLK_CPU AV2 SKYLAKE_ULT R7 MEM_SMBCLK GPP_B23/SML1ALERT# R1820 1 2 150KR2J-GP
[25,91] SPI_CLK_ROM SPI0_CLK GPP_C0/SMBCLK
R1807 1 2 0R0402-PAD SPI_SO_CPU AW3 R8 MEM_SMBDATA
[25,91] SPI_SO_ROM SPI0_MISO GPP_C1/SMBDATA
R1808 1 2 0R0402-PAD SPI_SI_CPU AV3 Strap R10 GPP_C2/SMBALERT# GPP_C2/SMBALERT# R1821 1 2 2K2R2J-L1-GP
[25,91] SPI_SI_ROM SPI0_MOSI GPP_C2/SMBALERT#
R1809 1 2 0R0402-PAD SPI_WP_CPU AW2
[25] SPI_WP_ROM SPI_HOLD_CPU AU4 SPI0_IO2 SML0_SMBCLK
R1811 1 2 0R0402-PAD R9
[25] SPI_HOLD_ROM SPI_CS_CPU_N0 AU3 SPI0_IO3 GPP_C3/SML0CLK SML0_SMBDATA
[25] SPI_CS_ROM_N0 R1812 1 2 0R0402-PAD W2
AU2 SPI0_CS0# GPP_C4/SML0DATA W1 GPP_C5/SML0ALERT#
R1814 1 2 0R0402-PAD SPI_CS_CPU_N2 AU1 SPI0_CS1# Strap GPP_C5/SML0ALERT# MEM_SMBCLK R1805 1 2 2K2R2J-L1-GP
[91] SPI_CS_ROM_N2 SPI0_CS2# W3 SML1_SMBCLK MEM_SMBDATA R1832 1 2 2K2R2J-L1-GP
GPP_C6/SML1CLK SML1_SMBDATA SML1_SMBCLK [24,79]
0511 Follow KY15. V3
SPI - TOUCH GPP_C7/SML1DATA GPP_B23/SML1ALERT# SML1_SMBDATA [24,79]
AM7
0620 NC M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
[67] HDD_FALL_INT GPP_D2/SPI1_MISO
TPAD14-OP-GP TP1803 1 CPU_D3_TP J4 For eSPI
DVT1 add FFS 2/18 TPAD14-OP-GP TP1804 1 CPU_D4_TP V1 GPP_D3/SPI1_MOSI 20170504 0512 Modify +V1.8A_SIP
C TPAD14-OP-GP TP1805 1 CPU_D5_TP V2 GPP_D21/SPI1_IO2 R1818 C
eSPI TPAD14-OP-GP TP1806 1 CPU_D6_TP M1 GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
LPC
GPP_A1/LAD0/ESPI_IO0
AY13 ESPI_IO0_CPU R1829 1 2 15R2F-2-GP ESPI_IO0 8K2R2F-1-GP
BA13 ESPI_IO1_CPU R1830 1 2 15R2F-2-GP ESPI_IO1 CLKRUN#_R 1 DY 2
ESPI_IO[3..0] GPP_A2/LAD1/ESPI_IO1 BB13 ESPI_IO2_CPU R1831 1 2 15R2F-2-GP ESPI_IO2
[24] ESPI_IO[3..0] C LINK GPP_A3/LAD2/ESPI_IO2 ESPI_IO3_CPU ESPI_IO3
AY12 R1833 1 2 15R2F-2-GP
ESPI_IO0 G3 GPP_A4/LAD3/ESPI_IO3 BA12 ESPI_CS#_CPU R1801 1 2 0R0402-PAD ESPI_CS#
ESPI_IO1 [61] CL_CLK CL_CLK GPP_A5/LFRAME#/ESPI_CS# ESPI_RESET#_CPU ESPI_RESET#
G2 BA11 R1826 1 2 0R0402-PAD
ESPI_IO2 [61] CL_DATA CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
G1
ESPI_IO3 [61] CL_RST# CL_RST#
???
PH only? AW9 ESPI_CLK_CPU R1804 1 2 15R2F-2-GP ESPI_CLK
SIO_RCIN# AW13 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9
EC1805
SCD1U16V2KX-3GP
RCIN#:
[24] ESPI_CS# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1
1
Frequency to Avoid: 33 MHz AW11 CLKRUN#_R R1819 1 2 0R2J-L-GP

DY ESPI_ALERT# AY11 GPP_A8/CLKRUN# DY PWR_SEClET [24]
[24] ESPI_RESET# GPP_A6/SERIRQ
1
0512 DY
DY EC1802
2
SC10P50V2JN-L1-GP
[24] ESPI_ALERT# SKYLAKE-U-GP
2
[24] ESPI_CLK
CPU1J 10 OF 20
3D3V_S0
20170428
CLOCK SIGNALS
RN1812
1 8 CLKREQ_PCIE#5 D42
CLKREQ_PEG#0 [76] PEG_CLK_CPU# CLKOUT_PCIE_N0
2 7 C42 SKYLAKE_ULT
3 6 CLKREQ_PCIE#1 GPU [76] PEG_CLK_CPU
[79] CLKREQ_PEG#0
CLKREQ_PEG#0 AR10 CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
U22
4 5 CLKREQ_PCIE#2 XTAL24_IN 1 R1810 2 XTAL24_IN_R C1801 1 2 SC15P50V2JN-2-GP
B42 0R0402-PAD
[61] PEG_CLK1_CPU# CLKOUT_PCIE_N1 PCIE_CLK_XDP_N
SRN10KJ-6-GP A42 F43 1 TP1807 TPAD14-OP-GP
B
WLAN [61]
[61]
PEG_CLK1_CPU
CLKREQ_PCIE#1
CLKREQ_PCIE#1 AT7 CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
E43 PCIE_CLK_XDP_P 1 TP1808 TPAD14-OP-GP
B
1
0517 DY
RN1813 SUSCLK_R
D41 BA17 R1813 1 DY 2 X1801
R1802
1MR2J-1-GP
1 4 CLKREQ_PCIE#3 [31] PEG_CLK2_CPU#
C41 CLKOUT_PCIE_N2 GPD8/SUSCLK 0R2J-L-GP
SUS_CLK [24] U22
2 3 CLKREQ_PCIE#4 LAN [31] PEG_CLK2_CPU
AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN U22 XTAL-24MHZ-81-GP
[31] CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT 82.30004.841
XTAL24_OUT
2
SRN10KJ-5-GP 0511 Remove SSD D40 Intel recommend: 2.71k ohm 5%
CLKOUT_PCIE_N3
4
C40 E42 XCLK_BIASREF R1803 1 2
CLKOUT_PCIE_P3 XCLK_BIASREF +V1.00A_SIP
CLKREQ_PCIE#3 AT10 2K7R2F-GP
GPP_B8/SRCCLKREQ3# AM18 RTC_X1 XTAL24_OUT C1802 1U222 SC15P50V2JN-2-GP
B40 RTCX1 AM20 RTC_X2
A40 CLKOUT_PCIE_N4 RTCX2
CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 SRTC_RST#
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 RTC_RST#
E40 RTCRST#
E38 CLKOUT_PCIE_N5
CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
RTC_X1 R1815 1 2 RTC_X2

10MR2J-L-GP
SKYLAKE-U-GP
X1802
RTC_AUX_S5 1 4
RN1901
1 4 SRTC_RST#
C1804
SC3D9P50V2CN-1GP
C1803
SC3D9P50V2CN-1GP
1
1
2 3 2 3
1
SRN20KJ-1-GP C1902 DY EC1806

2
2
SC1U10V2KX-1GP SCD1U16V2KX-3GP
Q1901
2
G
[21,24] RTCRST_ON
X-32D768KHZ-65-GP
A A
1
D RTC_RST#
EC1808
SCD1U16V2KX-3GP
82.30001.A41
R1817
10KR2J-L-GP
1
DY S <Core Design>
1
C1901 G1901 DY EC1807

2N7002K-2-GP SC1U10V2KX-1GP GAP-OPEN SCD1U16V2KX-3GP
2
84.2N702.J31 Wistron Corporation

2

1
2ND = 84.2N702.031
3rd = 84.07002.I31 Taipei Hsien 221, Taiwan, R.O.C.
(#514849) Title
Layout: Place at the open door area.
Size
CPU_(LPC/SPI/SMBUS/CL/CLK)
Document Number Rev
Custom
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

CPU1G 7 OF 20
PCH strap pin:
AUDIO
SKYLAKE_ULT
Flash Descriptor Security Overide/
Intel ME Debug Mode HDA_SYNC BA22
D HDA_BITCLK AY22 HDA_SYNC/I2S0_SFRM D
HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
Low = Default * HDA_SDO/I2S0_TXD
SDIO/SDXC
HDA_SDOUT High = Enable HDA_SDIN0 BA21
AY21 HDA_SDI0/I2S0_RXD AB11
AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
FC1902
SC2P50V2CN-GP
The internal pull-down is disabled after HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
1
PLTRST# deasserts DY J5 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3
2
W10
[24,79,85] DGPU_PWROK GPP_G5/SD_CD#
AK7 W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
[27] HDA_CODEC_BITCLK GPP_F2/I2S2_TXD
AK10 BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9 CPU_A16_TP 1 TP1902
[27] HDA_CODEC_SDOUT GPP_A16/SD_1P8_SEL TPAD14-OP-GP
H5 AB7 SD_RCOMP R1901 1 2
[27] HDA_CODEC_SYNC GPP_D19/DMIC_CLK0 SD_RCOMP
D7 200R2F-L-GP
GPP_D20/DMIC_DATA0
[27] HDA_SDIN0
D8 AF13
DGPU_PWROK C8 GPP_D17/DMIC_CLK1 GPP_F23
C
GPP_D18/DMIC_DATA1 C
[24] ME_FWP
SPKR AW5
GPP_B14/SPKR
[27] SPKR
SKYLAKE-U-GP
PCH strap pin:

NO REBOOT 3D3V_S0 HDA_CODEC_BITCLK R1907 1 2 0R0402-PAD HDA_BITCLK
R2006 1DY 2 1KR2J-1-GP SPKR HDA_CODEC_SYNC R1908 1 2 0R0402-PAD HDA_SYNC

* Low = Enable (Default)
HDA_SPKR High = Disable
R1904 1UMA 2 100KR2J-1-GP DGPU_PWROK
The internal pull-down is disabled after EC1901 1DY 2 SC10P50V2JN-L1-GP HDA_CODEC_BITCLK HDA_CODEC_SDOUT R1912 1 2 0R0402-PAD HDA_SDOUT
PLTRST# deasserts
EC1903 1DY 2 SC1KP50V2KX-L-1-GP DGPU_PWROK ME_FWP R1909 1 2 1KR2J-1-GP
1
DY FC1901
SC2P50V2CN-GP
B B
2
<Core Design>
A
Wistron Corporation A
Title
CPU_(AUDIO/SDIO/SDXC)
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = PCH 3D3V_S0

CPU1F 6 OF 20 RN2007
SRN10KJ-5-GP
[68] UART_2_CRXD_DTXD LPSS ISH I2C0_SCL 1 4
[68] UART_2_CTXD_DRXD I2C0_SDA
SKYLAKE_ULT 2 DY 3
AN8 P2 USB_UART_SEL_D9 1 TP2006 TPAD14-OP-GP
EC2002 1DY 2 SC1KP50V2KX-L-1-GP AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 DGPU_HOLD_RST#
DGPU_HOLD_RST# [76] GPP_B16/GSPI0_CLK GPP_D10
VRAM_ID1 AP8 P4 RN2008
GPP_B18/GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 RTC_DET# I2C1_SCL 1 4
GPP_B18/GSPI0_MOSI GPP_D12 RTC_DET# [25]
I2C1_SDA 2
DY 3
RN2009
DGPU_HOLD_RST#
Strap I2C0_SDA
1 4 [55] DBC_PANEL_EN AM5 M4
2 3 DGPU_PWR_EN AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3 I2C0_SCL SRN2K2J-1-GP
OPS AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
SRN10KJ-5-GP TPAD14-OP-GP 1 GPP_B22 AN5 GPP_B21/GSPI1_MISO N1 I2C1_SDA
TP2008 GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 I2C1_SCL
D GPP_D8/ISH_I2C1_SCL D
AB1 (PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
AB2 GPP_C8/UART0_RXD AD11
[61] BLUETOOTH_EN GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
1.8V Only to the same voltage rail as the device/end point.
(PDG#543016) If the UART/GPIO functionality is also not used, W4 AD12
the signals can be left as no-connect. BOARD_ID2 AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
3D3V_S0 GPP_C11/UART0_CTS#
UART_2_CRXD_DTXD AD1 U1 DGPU_PWR_EN
GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA DGPU_PWR_EN [85,86]
R2048 1 2 51KR2J-1-GP UART_2_CRXD_DTXD UART_2_CTXD_DRXD AD2 U2 UART0_TXD 1 TP2007 TPAD14-OP-GP
R2049 1
Debug
2 51KR2J-1-GP UART_2_CTXD_DRXD AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 UART0_RTS# 1 TP2010 TPAD14-OP-GP
R2046 1
Debug
2 51KR2J-1-GP LPSS_UART2_CTS#
[24] SIO_EXT_WAKE#
LPSS_UART2_CTS# AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 UART0_CTS# 1 TP2011 TPAD14-OP-GP
Debug GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
R2002 1 2 10KR2J-L-GP BLUETOOTH_EN AC1 UART1_RXD 1 TP2012 TPAD14-OP-GP
DY U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
PTP [65] I2C0_SDA_TCH_PAD
[65] I2C0_SCL_TCH_PAD U6 GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AC3
FFS_INT2 [67]
AB4 UART1_CTS# 1 DVT1 add FFS 2/18
R2003 1 2 10KR2J-L-GP DBC_PANEL_EN U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS# TP2015TPAD14-OP-GP 0517 Change PH power rate +V1.8A_SIP
U9 GPP_C18/I2C1_SDA AY8 PROJECT_ID1
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 PROJECT_ID2 KB_DET# R2001 1 2 10KR2J-L-GP
RN2010 AH9 GPP_A19/ISH_GP1 BB7 KB_DET# CAMERA_DET# R2004 1 2 10KR2J-L-GP
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 KB_DET# [65]
1 4 I2C0_SDA_TCH_PAD AH10 BA7 CAMERA_DET#
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 CAMERA_DET# [55]
2 3 I2C0_SCL_TCH_PAD PCH Prim AY7 TPM_SELECT
DY AH11
GPP_F6/I2C3_SDA
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
AW7 ??? Ask SW in PH necessary
SRN2K2J-1-GP AH12 AP13 PANEL_SIZE_ID [55]
3D3V_S5_PCH GPP_F7/I2C3_SCL SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6
AF11
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
1
3D3V_S5_PCH R2007
RN2011
DY SKYLAKE-U-GP
1KR2J-1-GP
SRN10KJ-5-GP
1 4 SIO_EXT_WAKE#
2
2 3 RTC_DET#
GPP_B18/GSPI0_MOSI
+V1.8A_SIP +V1.8A_SIP
1
GPP_A19 GPP_A18
C
DY R2019 0517 Change PH power rate BIOS strap pin: C
PCH strap pin: 1KR2J-1-GP

PROJECT Strap pin PROJECT_ID2 PROJECT_ID1
2
1
No Reboot Sampled at rising edge of PCH_PWROK R2015 R2017 Turis X 0
10KR2J-L-GP DY_SKL10KR2J-L-GP
GSPI0_MOSI / 0 = Disable “No Reboot” mode. Vegas
GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO Vegas X 1
2
Timer system reboot feature). This function is useful PROJECT_ID1 PROJECT_ID2
when running ITP/XDP. 0511 Remove DB2
KBL 0 X
1
The signal has a weak internal pull-down. R2016 R2018
Turis10KR2J-L-GP KBL 10KR2J-L-GP SKL 1 X
2
0517 Change PH power rate
+V1.8A_SIP
3D3V_S0
1
GPP_C11
R2005 BIOS strap pin: R2022 GPP_A22
OPS 10KR2J-L-GP 10KR2J-L-GP BIOS strap pin:
BIOS UMA/DIS Strap pin BOARD_ID2 TPM
BIOS UMA/DIS Strap pin TPM_SELECT
2
BOARD_ID2
UMA 0 TPM_SELECT
B B
1 TPM 1
1
DIS 1
R2008 R2020 NON_TPM 0
UMA 10KR2J-L-GP 10KR2J-L-GP
NON_TPM
2
2
3D3V_S0
1
R2023 GPP_B17
10KR2J-L-GP BIOS strap pin:
VRAM_2G
BIOS VRAM Size Strap pin VRAM_ID1
2
VRAM_ID1
4G 0
1
R2024 2G 1
10KR2J-L-GP
VRAM_4G
2
A A
<Core Design>
Wistron Corporation
Title
CPU_(LPSS/ISH)
Custom
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

RTC_AUX_S5 RTC_AUX_S5 +VCCPRTC_3P3
CPU1O 15 OF 20
+V1.00A_SIP R2107 1 2
CPU POWER 4 OF 4
0R0402-PAD-2-GP
AB19 0511 Follow KY15.
C2119
C2118
C2117
SC1U10V2KX-1GP
VCCPRIM_1P0
1
AB20 AK15 +V1.8A_SIP DY
+VCCPRIM_CORE P18 VCCPRIM_1P0 SKYLAKE_ULT VCCPGPPA AG15
VCCPRIM_1P0 VCCPGPPB Y16 +VCCMPHYGTAON_1P0_LS_SIP +VCCAMPHYPLL_1P0
VCCPGPPC
2
2.57A AF18 Y15 +V3.3A_SIP
AF19 VCCPRIM_CORE VCCPGPPD T16 R2112 1 2
V20 VCCPRIM_CORE VCCPGPPE AF16 0R0603-PAD-2-GP-U
VCCPRIM_CORE 1.8V Only VCCPGPPF +V1.8A_SIP
V21 AD15
EC2101
SCD1U25V2KX-GP
C2120
SC1U10V2KX-1GP
D SCD1U16V2KX-3GP D
VCCPRIM_CORE VCCPGPPG
1
DY SCD1U16V2KX-3GP
+VCCDSW _1P0 AL1 V19 +V3.3A_SIP
DCPDSW_1P0 VCCPRIM_3P3 +V1.00A_SIP +VCCAPLL_1P0
CAP need close to VCCRTC
2
+V1.00A_SIP K17 T1 +V1.00A_SIP

L1 VCCMPHYAON_1P0 VCCPRIM_1P0 R2108 1 2
VCCMPHYAON_1P0 AA1 0R0603-PAD-2-GP-U
VCCATS_1P8 +V1.8A_SIP
N15
N16 VCCMPHYGT_1P0 AK17
VCCMPHYGT_1P0 VCCRTCPRIM_3P3 +V3.3A_SIP
N17
P15 VCCMPHYGT_1P0 AK19
VCCMPHYGT_1P0 VCCRTC +VCCPRTC_3P3
+VCCMPHYGTAON_1P0_LS_SIP P16 BB14
VCCMPHYGT_1P0 VCCRTC
K15 BB10 VCCRTCEXT C2112 1 2 SCD1U16V2KX-3GP
L15 VCCAMPHYPLL_1P0 DCPRTC
+VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0 RTC_3D3V RTC_AUX_S5
A14 +V1.00A_SIP R2113 1 2 0R0402-PAD
V15 VCCCLK1
+VCCAPLL_1P0 VCCAPLL_1P0 K19 Q2107
AB17 VCCCLK2
+V1.00A_SIP VCCPRIM_1P0
Y18 L21 S
VCCPRIM_1P0 VCCCLK3
AD17 N20
RTC_RSTD
D
+VCCPDSW _3P3 VCCDSW_3P3 VCCCLK4
1
G
AD18
AJ17 VCCDSW_3P3 L19 DMP2130L-7-GP R2104
VCCDSW_3P3 VCCCLK5
G
R2101 1 2 +VCCPAZIO AJ19 A10
84.02130.031 RTC_RST 4K7R2J-2-GP
+V3.3A_SIP VCCHDA VCCCLK6
0R0402-PAD 2nd = 84.00102.031
2
AJ16 AN11 Symbol error for layout NC 3rd = 84.03413.B31
+V3.3A_SIP VCCSPI GPP_B0/CORE_VID0 AN13 RTC_3P3_EN_D
C AF20 GPP_B1/CORE_VID1 0512 Follow SF C
+VCCMPHYGTAON_1P0_LS_SIP VCCSRAM_1P0
AF21
VCCSRAM_1P0
D
T19
T20 VCCSRAM_1P0 +V1.8A_SIP +VCCDSW _1P0 Q2110
VCCSRAM_1P0 2N7002K-2-GP
+V3.3A_SIP AJ21 D2102 RTC_RST
VCCPRIM_3P3 K A
AK20
RTC_RST 84.2N702.J31
C2108
SC1U10V2KX-1GP
C2103
SC1U10V2KX-1GP
+V1.00A_SIP VCCPRIM_1P0
1
RB751VM-40TE-17-GP 2ND = 84.2N702.031
+VCCMPHYGTAON_1P0_LS_SIP N18 83.R2004.J8F 3rd = 84.07002.I31
VCCAPLLEBB_1P0
S
4th = 84.2N702.W31
2
R2102 1 RTC_RST
2 RTC_3P3_EN_G
SKYLAKE-U-GP
[18,24] RTCRST_ON
1MR2J-1-GP
1
RTC_RST
RTC_RST
C2123
SCD022U16V2KX-3GP
1
+V3.3A_SIP +V1.00A_SIP
R2118
100KR2J-1-GP
Layout Note:
Layout Note:
2
1uF:
2
1uF:
C2105
C2106
C2107
C2109
C2110
C2111
C2101
C2104
C2116
C2121
C2122
SC22U6D3V3MX-1-GP
C2101 near AB19
1
1
DY DY DY DY C2105 near V19 DY DY DY C2104 near K17
C2106 near AK17 C2116 near A10
2
C2107 near AG15 2 C2121 near AL1

C2109 near Y16 22uF:
0.1uF: C2122 near L19
SC1U10V2KX-1GP SCD1U16V2KX-3GP C2110 near T16 SC1U10V2KX-1GP
B B
SC1U10V2KX-1GP SCD1U16V2KX-3GP C2111 near AJ19 SC1U10V2KX-1GP
SC1U10V2KX-1GP SC1U10V2KX-1GP
SC1U10V2KX-1GP SC1U10V2KX-1GP 3D3V_S5
3D3V_S5
+VCCAMPHYPLL_1P0 +VCCAPLL_1P0 0512 Follow SF R2114 1 DY 2
1
0R2J-L-GP
1
RTC_RST
R2115
Layout Note: Layout Note:
C2113
SC22U6D3V3MX-1-GP
C2114
SC22U6D3V3MX-1-GP
R2120
100KR2J-1-GP
D2101 10KR2J-L-GP
1
3V_5V_POK 1
DY DY [17,40,45,53,54] 3V_5V_POK RTC_RST
22uF: 22uF:
2
3 3V_5V_DSW _OK
C2113 near K15 C2114 near V15 RTC_RST
2
VCCDSW _EN# 2
[24] VCCDSW _EN#
BAT54A-11-GP
1
DY C2125
SC1U10V2KX-1GP
3D3V_S5 U2101
2
3D3V_S5_PCH
5
RTC_RST 1
VIN#5 EN 2
4 GND 3 3D3V_S5_PCH_Gen9
RTC_RST
R2116 1 2
VIN#4 VOUT 0R3J-L1-GP
RT9724GB-GP
74.09724.09F
A <Core Design> A
Wistron Corporation
Title
CPU_(POWER1)
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
CPU1T 20 OF 20
D SKYLAKE_ULT D
SPARE
AW69 F6
AW68 RSVD#AW69 RSVD#F6 E3 XTAL24_IN_U42
AU56 RSVD#AW68 RSVD#E3 C11
AW48 RSVD#AU56 RSVD#C11 B11
XTAL24_OUT_U42 C7 RSVD#AW48 RSVD#B11 A11
U12 RSVD#C7 RSVD#A11 D12
U11 RSVD#U12 RSVD#D12 C12
H11 RSVD#U11 RSVD#C12 F52
RSVD#H11 RSVD#F52
SKYLAKE-U-GP
C C
XTAL24_IN_U42 R2201 1U42 2 XTAL24_IN_U42_R C2201 1

U42 2 SC15P50V2JN-2-GP
0R2J-2-GP
1
1
X2201
R2203
1MR2J-1-GP
U42 U42 XTAL-24MHZ-86-GP
82.30004.891
4
XTAL24_OUT_U42 R2202 1U42 2 XTAL24_OUT_R_U42 C2202 1
U42 2 SC15P50V2JN-2-GP
B 0R2J-2-GP B
<Core Design>
A
Title
CPU_(RSVD)
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

CPU1Q 17 OF 20 CPU1R 18 OF 20
0517 Follow KY15.
CPU1P 16 OF 20 GND 2 OF 3 GND 3 OF 3
F8 L18
GND 1 OF 3 AT63 SKYLAKE_ULT BA49 G10 VSS VSS L2
AT68 VSS VSS BA53 G22 VSS SKYLAKE_ULT VSS L20
Symbol error for layout NC A5 SKYLAKE_ULT AL65 AT71 VSS VSS BA57 G43 VSS VSS L4
TPAD14-OP-GP TP2311 1 A67_TP A67 VSS VSS AL66 AU10 VSS VSS BA6 G45 VSS VSS L8
TPAD14-OP-GP TP2301 1 A70_TP A70 VSS VSS AM13 0517 Follow KY15. AU15 VSS VSS BA62 G48 VSS VSS N10
D D
AA2 VSS VSS AM21 AU20 VSS VSS BA66 G5 VSS VSS N13
AA4 VSS VSS AM25 AU32 VSS VSS BA71 Symbol error for layout NC G52 VSS VSS N19
AA65 VSS VSS AM27 AU38 VSS VSS BB18 G55 VSS VSS N21
AA68 VSS VSS AM43 TPAD14-OP-GP TP2310 1 AV1_TP AV1 VSS VSS BB26 G58 VSS VSS N6
AB15 VSS VSS AM45 AV68 VSS VSS BB30 G6 VSS VSS N65
AB16 VSS VSS AM46 AV69 VSS VSS BB34 G60 VSS VSS N68
AB18 VSS VSS AM55 AV70 VSS VSS BB38 G63 VSS VSS P17
AB21 VSS VSS AM60 TPAD14-OP-GP TP2304 1 AV71_TP AV71 VSS VSS BB43 0517 Follow KY15. G66 VSS VSS P19
AB8 VSS VSS AM61 AW10 VSS VSS BB55 H15 VSS VSS P20
AD13 VSS VSS AM68 AW12 VSS VSS BB6 H18 VSS VSS P21
AD16 VSS VSS AM71 AW14 VSS VSS BB60 H71 VSS VSS R13
AD19 VSS VSS AM8 AW16 VSS VSS BB64 J11 VSS VSS R6
AD20 VSS VSS AN20 AW18 VSS VSS BB67 Symbol error for layout NC J13 VSS VSS T15
AD21 VSS VSS AN23 AW21 VSS VSS BB70 BB70_TP 1 TP2307 TPAD14-OP-GP J25 VSS VSS T17
AD62 VSS VSS AN28 AW23 VSS VSS C1 J28 VSS VSS T18
AD8 VSS VSS AN30 AW26 VSS VSS C25 J32 VSS VSS T2
AE64 VSS VSS AN32 AW28 VSS VSS C5 J35 VSS VSS T21
AE65 VSS VSS AN33 AW30 VSS VSS D10 J38 VSS VSS T4
AE66 VSS VSS AN35 AW32 VSS VSS D11 J42 VSS VSS U10
AE67 VSS VSS AN37 AW34 VSS VSS D14 J8 VSS VSS U63
AE68 VSS VSS AN38 AW36 VSS VSS D18 K16 VSS VSS U64
AE69 VSS VSS AN40 AW38 VSS VSS D22 K18 VSS VSS U66
AF1 VSS VSS AN42 VSS VSS D25 K22 VSS VSS U67
AF10 VSS VSS AN58 AW41 VSS D26 K61 VSS VSS U69
AF15 VSS VSS AN63 AW43 VSS VSS D30 K63 VSS VSS U70
AF17 VSS VSS AP10 AW45 VSS VSS D34 K64 VSS VSS V16
C AF63 VSS VSS AP23 AW51 VSS VSS D45 K67 VSS VSS W13 C
AG16 VSS VSS AP28 AW53 VSS VSS D47 K68 VSS VSS W6
AG17 VSS VSS AP32 AW55 VSS VSS D48 K70 VSS VSS W9
AG18 VSS VSS AP35 AW57 VSS VSS D53 K71 VSS VSS Y17
AG19 VSS VSS AP38 AW6 VSS VSS D58 L11 VSS VSS Y19
AG71 VSS VSS AP63 AW64 VSS VSS D66 VSS VSS
AH13 VSS VSS AP68 AW66 VSS VSS D69
AH6 VSS VSS AP70 AW8 VSS VSS E11
AH63 VSS VSS AR11 AY66 VSS VSS E15
AH64 VSS VSS AR15 B10 VSS VSS E18 SKYLAKE-U-GP
AH67 VSS VSS AR16 B14 VSS VSS E21
AJ15 VSS VSS AR20 B18 VSS VSS E46
AJ18 VSS VSS AR23 B22 VSS VSS E50 [#543016 Rev0.9]
AK11 VSS VSS AR42 B39 VSS VSS E6
AK16 VSS VSS AR43 B44 VSS VSS E65
AK18 VSS VSS AR45 B48 VSS VSS E71 Symbol error for layout NC
AK21 VSS VSS AR46 B53 VSS VSS F1
AK22 VSS VSS AR48 0517 Follow KY15. B58 VSS VSS F13
AK68 VSS VSS AR52 TPAD14-OP-GP TP2312 1 B71_TP B71 VSS VSS F23
AK69 VSS VSS AR53 TPAD14-OP-GP TP2305 1 BA1_TP BA1 VSS VSS F27
AK8 VSS VSS AR55 BA10 VSS VSS F28
AL2 VSS VSS AR58 BA14 VSS VSS F32
AL28 VSS VSS AR63 BA18 VSS VSS F33
B AL32 VSS VSS AR8 Symbol error for layout NC BA2 VSS VSS F35 B
AL35 VSS VSS AT2 BA23 VSS VSS F37
AL48 VSS VSS AT35 F68 VSS VSS F42
AL52 VSS VSS AT4 BA45 VSS VSS BA41
AL55 VSS VSS AT42 VSS VSS
AL58 VSS VSS AT56
AL64 VSS VSS AT58
VSS VSS
SKYLAKE-U-GP
SKYLAKE-U-GP
A <Core Design> A
Wistron Corporation
Title
CPU_(VSS)
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = KBC

3D3V_S5
3D3V_S5 3D3V_S5_KBC
Layout Note: 1
RN2405
8
Need very close to EC R2446 1 2 2 7
0R0603-PAD-2-GP-U LID_CL_SIO# 3 6
TP_EN# 4 5
C2421
SCD1U16V2KX-3GP
C2416
SCD1U16V2KX-3GP
C2415
SC2D2U10V3KX-L-GP
Q2412
1
R2402 1 2 0R0402-PAD VREF_CPU
1D0V_S5 DY BAT2_LED# 1 6 BATT_WHITE_LED# [64]
1
C2406 3D3V_S5_KBC SRN100KJ-5-GP
2
SCD1U16V2KX-3GP 3D3V_S5 2 5 3D3V_S5
C2420
SCD1U16V2KX-3GP
C2412
SCD1U16V2KX-3GP
C2411
SCD1U16V2KX-3GP
C2410
SCD1U16V2KX-3GP
C2414
SCD1U16V2KX-3GP
C2413
SCD1U16V2KX-3GP
C2417
SC2D2U10V3KX-L-GP
2
1
If don't need RTC alarm wake up, 3 4 BAT1_LED#
DY can change to 3D3V_AUX_S5 [64] CHG_AMBER_LED#
0511 Follow KY15.
Q2412 and Q2413 merge 2N7002KDW-GP
2
1D8V_S5 1D8V_S5_KBC
84.2N702.A3F
0517 Change to digital GND 2nd = 84.2N702.E3F
D
3D3V_AUX_S5 RTC_3D3V R2462 1 2 D
0R0402-PAD-2-GP 3rd = 75.00601.07C 3D3V_S0
0519 Install
1
3D3V_S5_KBC TOUCH_PANEL_INTR# R2429 1DY 2
10KR2J-L-GP
R2473
0R2J-2-GP
R2472
0R0402-PAD
DY
C2423
SCD1U16V2KX-3GP
Touch Panel PH internally.
1
3D3V_S5_KBC
R2450 3D3V_S5_KBC
2
RN2408 100KR2J-1-GP +RTC_CELL_VBAT 0516 Follow CY17.
2
SRN100KJ-5-GP R2435 1 2 0R0402-PAD BKLT_IN_EC
[8] L_BKLT_EN
1
1 8 KSO8 C2428
2
4
3
1
2 7 KSO3 KSO9 SCD1U16V2KX-3GP
122
103
3 6 KSO1 RN2402 R2436
43
82
19
65
2
1
5
4 5 KSO2 KBC24 SRN4K7J-8-GP 100KR2J-1-GP
DY R2449 54
VBAT
VTR
VTR
VTR
VTR
VTR
VTR
100KR2J-1-GP VTR_33_18
[65] KSO[0..16]
2
RN2409 3D3V_S0
1
2
SRN100KJ-5-GP KSO0 2
GPIO027/KSO00/PVT_IO1
2
1 8 KSO5 KSO1 14 8 PBAT_CHG_SMBDAT

GPIO015/KSO01/PVT_CS# GPIO007/SMB01_DATA/SMB01_DATA18
1
2 7 KSO4 KSO2 15 9 PBAT_CHG_SMBCLK
3 6 KSO7 KSO3 16 GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 11 GPU_THM_SMBDAT R2438 1 2 0R0402-PAD SML1_SMBDATA R2430
4 5 KSO6 KSO4 37 GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 12 GPU_THM_SMBCLK R2439 1 2 0R0402-PAD SML1_SMBCLK 10KR2J-L-GP
KSO5 38 GPIO045/BCM_INT1#/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 89
3D3V_S5_KBC KSO6 39 GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 91 0516 NC 41, 89, 91, 97 pin
GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18
2
RN2406 RN2403 KSO7 50 96 NB_MODE# 1 TP2401 TPAD14-OP-GP R2461 1 DY 2
SRN100KJ-5-GP SRN10KJ-12-GP KSO8 46 GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18 97 0R2J-2-GP
1 8 KSO0 1 8 KSI7 KSO9 68 GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18
2 7 KSO12 2 7 KSI6 KSO10 72 GPIO102/KSO09/CR_STRAP 40 FAN1_TACH A K
GPIO106/KSO10 GPIO050/TACH0 FAN_TACH1 [26]
3 6 KSO16 3 6 KSI4 KSO11 74 41
4 5 KSO15 4 5 KSI2 KSO12 75 GPIO110/KSO11 GPIO051/TACH1 0518(CY15) D2403
KSO13 76 GPIO111/KSO12 44 KB_LED_PWM 1 TP2407 TPAD14-OP-GP RB751V-40H-GP
77 GPIO112/PS2_CLK1A/KSO13 GPIO053/PWM0 45
RN2407 RN2404
KSO14
KSO15 86 GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1
BEEP
0517 Follow Taos.
83.R2004.G8F
SRN100KJ-5-GP SRN10KJ-12-GP KSO16 92 GPIO125/KSO15 47 FAN1_PWM R2403 1 2 10KR2J-L-GP FAN1_DAC_1
1 8 KSO13 1 8 KSI5 CAP_LED# 93 GPIO132/KSO16 GPIO056/PWM3 34 FAN2_PWMVOL_LP# R2486 1 2 0R2J-2-GP SIO_SLP_S3#
GPIO140/KSO17 GPIO030/BCM_INT0#/PWM4 DY
1
2 7 KSO14 2 7 KSI1 35 LANWAKE# C2401
[65] KSI[0..7] GPIO031/BCM_DAT0/PWM5 PS_ID
3 6 KSO11 3 6 KSI3 KSI0 98 36 SC10U6D3V3MX-GP
4 5 KSO10 4 5 KSI0 KSI1 99 GPIO143/KSI0/DTR# GPIO032/BCM_CLK0/PWM6 4 PCIE_WAKE# 3D3V_S0
GPIO144/KSI1/DCD# GPIO002/PWM7
2
KSI2 6
KSI3 7 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 1 BAT2_LED# 0518(KY15)
KSI4 104 GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT 106 BAT1_LED# 0518(KY15) Q2414
GPIO147/KSI4/DSR# GPIO156/LED1
1
KSI5 105 70 BREATH_LED# 1 TP2402 TPAD14-OP-GP 2N7002K-2-GP
107 GPIO150/KSI5/RI# GPIO104/LED2 G
R2489
100KR2J-1-GP
KSI6 0516(CY17 GPIO)
20170504 ESPI KSI7 108 GPIO151/KSI6/RTS# 80 ME_FWP
GPIO152/KSI7/CTS# GPIO116/TFDP_DATA/UART_RX 81 HOST_DEBUG_TX D
C
[18] ESPI_IO[3..0] ESPI_IO0 ESPI CLK_TP_SIO 78
GPIO114/PS2_CLK0
GPIO117/TFDP_CLK/UART_TX CAP_LED#_S [65]
C
2
ESPI_IO1 DAT_TP_SIO 79 90 PTP_DIS# Need very close to EC CAP_LED# S
ESPI_IO2 SIO_PWRBTN# 52 GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK 94 H_PECI_R 0518(CY17 GPIO) R2437 1 2 43R2J-GP
ESPI_IO3 VCCDSW_EN# VCCDSW_ON GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT H_PECI [4]
0512(SF) R2411 1 DY 2 88 84.2N702.J31
GPIO127/PS2_DAT1B
1
0R2J-L-GP 95 VREF_CPU
ESPI_IO0 59 VREF_CPU
0517(CY17 GPIO)
DY C2405
SC100P50V2JN-3GP 2ND = 84.2N702.031
[18] ESPI_CS# ESPI_IO1 GPIO040/LAD0/ESPI_IO0 ICSP_CLK
60 101 3rd = 84.07002.I31
[18] ESPI_CLK GPIO041/LAD1/ESPI_IO1 GPIO145/ICSP_CLOCK
2
1D8V_S5_KBC ESPI_IO2 61 102 ICSP_DAT
[18] ESPI_ALERT# ESPI_IO3 GPIO042/LAD2/ESPI_IO2 GPIO146/ICSP_DATA ICSP_CLR
62 87
[18] ESPI_RESET# ESPI_ALERT# ESPI_CS# GPIO043/LAD3/ESPI_IO3 ICSP_MCLR
R2410 1 2 58
10KR2J-L-GP 0511(KY15) MASK_SATA_LED# 56 GPIO044/LFRAME#/ESPI_CS# 119 NB_MUTE#
[43,44] AC_DIS ESPI_CLK GPIO064/LRESET# BGPO/GPIO004 SYSPWR_PRES +RTC_CELL_VBAT
57 120
[17,44] ACOK_IN 3D3V_S5_KBC
PWR_SEClET
ESPI_ALERT#
63 GPIO034/PCI_CLK/ESPI_CLK
GPIO067/CLKRUN#
SYSPWR_PRES/GPIO003
VCI_OUT/GPIO036
121 ALWON
VCI_IN1#
0519 Follow Vendor ??? Check function with Kevin
55 126 R2452 1 2 100KR2J-1-GP
GPIO063/SER_IRQ/ESPI_ALERT# VCI_IN1#/GPIO162
1
0515(KY15) GPU_PWR_LEVEL 10 127 POWER_SW_IN# 3D3V_S5_KBC

[17,40] ALL_SYS_PWRGD PBAT_PRES# TP_EN# GPIO011/SMI#/EMI_INT# VCI_IN0#/GPIO163 HW_ACAV_IN ACOK_IN 3D3V_AUX_S5
R2415 1 2 DY R2401 49 128 R2469 1 2 0R0402-PAD
10KR2J-L-GP 10KR2F-L1-GP ESPI_RESET# 53 GPIO060/KBRST VCI_OVRD_IN/GPIO164
[40] ALWON GPIO061/LPCPD#/ESPI_RESET#
1
0511(KY15) LID_CL_SIO# 66 23 DGPU_PWROK_EC R2427 1 2 0R0402-PAD DGPU_PWROK
TP2406 GPIO100/EC_SCI# GPIO160/DAC_0 24 HW_ACAVIN_NB 1 TP2405 R2424 R2453
[27] BEEP GPIO161/DAC_1
2
TPAD14-OP-GP 1 CCG4_I2C_INT# 32 22 TPAD14-OP-GP 20KR2F-L3-GP

SYS_PWROK 28 GPIO126/SHD_SCLK DAC_VREF C2429 1 2 SCD1U16V2KX-3GP
3D3V_S5_KBC
Vref = 1.117
DY 1KR2J-1-GP
[55] BLON_OUT PBAT_PRES# GPIO133/SHD_IO0 CMP_VOUT0 CMP_VOUT0 temp around 85
29 85
GPIO134/SHD_IO1 GPIO124/CMP_VOUT0
2
0516(CY17) PRIM_PWRGD 30 20 CMP_VIN0 R2470 1 2 0R0402-PAD CMP_VIN0_R SYSPWR_PRES
[26] CMP_VIN0_R RTCRST_ON GPIO135/SHD_IO2 GPIO020/CMP_VIN0
31 25 VCREF0 0519 DY if not enable the RTC/WeekTimer
[26] CMP_VOUT0 GPIO136/SHD_IO3 GPIO165/CMP_VREF0
1
0511(KY15) PCH_RSMRST# 27
GPIO123/SHD_CS#
1
3D3V_S5 83 R2455
C2409
SCD01U50V2KX-L-GP
PROCHOT 0517(CY17 GPIO)
[18] PWR_SEClET GPIO120/CMP_VOUT1
1
0516(CY17) BKLT_IN_EC 67 21 CMP_VIN1 1 100KR2J-1-GP
R2448
10KR2F-L1-GP
3D3V_S5_KBC TP2403 0516(KY15) AC_DIS 69 GPIO101/SPI_CLK GPIO021/CMP_VIN1 26 LCD_TST TP2404 TPAD14-OP-GP
[65] CLK_TP_SIO GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK
1
TPAD14-OP-GP 1 USB_POWERSHARE_VBUS_EN 71 3D3V_S5_KBC

[65] DAT_TP_SIO GPIO105/SPI_IO1 0516 Follow KY15.
2
R2434 0511(KY15) R2412 1 2 10KR2J-L-GP FPR_SCAN# 42 118 USB_PWR_SHR_EN_L# R2493 1 2 10KR2F-L1-GP
GPIO052/SPI_IO2 GPIO024/ADC7
2
100KR2J-1-GP INT_TP# R2431 1 2 0R0402-PAD TP_WAKE_KBC# 33 117 PANEL_BKEN_EC R2497 1 2 0R0402-PAD BLON_OUT 0516(CY17 GPIO)
[19,79,85] DGPU_PWROK PM_LAN_ENABLE R2491 1 GPIO062/SPI_IO3 GPIO023/ADC6/A20M
2 0R0402-PAD AUX_ON 0518(CY17) 3 116 SIO_EXT_WAKE# R2471 1 2 0R2J-L-GP CMP_VIN0_R
GPIO001/SPI_CS#/32KHZ_OUT GPIO022/ADC5 109 MODEL_ID DY
[27] NB_MUTE# GPIO153/ADC4
2
USB_PWR_EN# R2479 1 2 0R0402-PAD USB_EN# 13 110 I_ADP R2421 1 2 1108 Install

ALL_SYS_PWRGD R2481 1 RESET_IN#/GPIO014 GPIO154/ADC3 BOARD_ID AD_IA [44]
2 0R0402-PAD RUNPWROK 48 111 330R2J-3-GP
[26] FAN1_DAC_1 GPIO057/VCC_PWRGD GPIO155/ADC2
VSS_VBAT
RESET_OUT# 73 113 LCD_VCC_TEST_EN_R R2495 1 2 LCD_VCC_TEST_EN
C2435
SC2200P50V2KX-2GP
ALL_SYS_PWRGD assert,
GPIO107/RESET_OUT# GPIO122/ADC1
VR_CAP
1
delay 10ms; RESET_OUT# assert. 114 I_BATT 0R0402-PAD 0516(CY17 GPIO)
SUS_CLK MEC_XTAL2 GPIO121/ADC0
AVSS
R2428 1 DY 2 0R2J-L-GP 125 115
XTAL2
VSS
VSS
VSS
VSS
VSS
MEC_XTAL1_R 123 ADC_VREF 3D3V_S5_KBC R2487 1 DY 2 SIO_SLP_S3# D2402
[79] GPU_PWR_LEVEL XTAL1
2
0517 DY 0R2J-L-GP LID_CL_SIO# K A TOUCH_PANEL_INTR# [4,55]
MEC1416-NU-D0-GP
[4,44,46] H_PROCHOT#
124
84
51
17
64
100
112
18
RB751V-40H-GP
C2422
SCD1U16V2KX-3GP
071.01416.000G
1
EC_AGND 83.R2004.G8F
[61,68] HOST_DEBUG_TX
1
EC_AGND
VR_CAP
R2458 D2405
[4,65] INT_TP#
2
B 0R0402-PAD PTP_DIS# K A B
R2445
PTP TP_LOCK# [65]
[17] LANWAKE#
1
1 2 C2418 RB751V-40H-GP
2
X2401 SC1U10V2KX-1GP EC_AGND 83.R2004.G8F

[55] LCD_VCC_TEST_EN XTAL_KBC_2
1 2 0R0402-PAD
2
[64] LID_CL_SIO#
XTAL-32D768KHZ-91-GP
[64] MASK_SATA_LED# 082.30003.0221 Power Switch Logic(PSL)
C2425
SC18P50V2JN-1-GP
C2424
SC18P50V2JN-1-GP
1
[19] ME_FWP Layout Note:

EC_AGND Connect GND and AGND planes via either +RTC_CELL_VBAT
[43,44] PBAT_PRES#
2
0R resistor or connect directly. I_BATT R2423 1 2 boost_mon [44]

330R2J-3-GP
[17] PCH_RSMRST#
1
C2441
SC2200P50V2KX-2GP
1
R2451
[31] PCIE_WAKE#
100KR2J-1-GP
EC LCD test R2432
[31] PM_LAN_ENABLE
2
Microchip: Use CL=9p Xtal，C = 10p R2456 1 2 0R0402-PAD 1KR2J-1-GP
[55] EC_BRIGHTNESS Layout Note:
2
1 2 POWER_SW_IN#
[40,54] PRIM_PWRGD [64] KBC_PWRBTN#
Need very close to EC
1
R2419 1 2 0R0402-PAD LCD_TST EC_AGND C2426
[43] PS_ID [55] LCD_TST_R
SC2D2U10V3KX-L-GP
[17,26,79] RESET_OUT#
2
0522 Follow KY15
[18,21] RTCRST_ON 3D3V_S5_KBC 3D3V_S5_KBC
R2418 1 DY 2
[20] SIO_EXT_WAKE#
EC_GPIO47 High Active 0R2J-L-GP
Q2408 DB3
[17] SIO_PWRBTN#
1
PROCHOT R2420 1 2 CMP_VOUT1_R G 7

0R0402-PAD R2414 R2478 R2476 1 2 0R2J-L-GP 3D3V_AUX_KBC_R 1
[17,27,40,51] SIO_SLP_S3# EC_DEBUG
1
D H_PROCHOT#_EC R2416 1 2 H_PROCHOT# 10KR2J-L-GP 100KR2J-1-GP

C2419
SCD01U50V2KX-L-GP
1
0R0402-PAD ICSP_CLK R2463 1 2 0R2J-L-GP ICSP_CLK_R 2

R2417
100KR2J-1-GP
[17,40,44,51] SIO_SLP_S4# DY DY S
EC_DEBUG ICSP_DAT R2464 1
EC_DEBUG
2 0R2J-L-GP ICSP_DATA_R 3
EC_DEBUG
2
2
1
[43,44] PBAT_CHG_SMBCLK DY C2403 4 EC_DEBUG

2
2N7002K-2-GP SC47P50V2JN-3GP HOST_DEBUG_TX R2466 1 2 0R2J-L-GP E51_TXD_R 5

[43,44] PBAT_CHG_SMBDAT EC_DEBUG
2
ICSP_CLR R2465 1 2 0R2J-L-GP ICSP_MCLR_R 6

84.2N702.J31 EC_DEBUG
2
1108 Install 8
[18,79] SML1_SMBCLK
2ND = 84.2N702.031
[18,79] SML1_SMBDATA
3rd = 84.07002.I31 20.K0691.006
[18] SUS_CLK
ACES-CON6-58-GP
[17] SYS_PWROK 3D3V_S5
A 3D3V_S5 A
[65] TP_EN#
MODEL_ID
1
PCB_REV
[35] USB_PWR_EN#
1
R2442
64K9R2F-1-GP
R2443
10KR2F-L1-GP
[21] VCCDSW_EN#
2
MODEL_ID
<Core Design>
2
BOARD_ID R2474 1 2 BOARD_ID_R

1
0R0402-PAD
C2407
SCD1U16V2KX-3GP
1
1
C2408
SCD1U16V2KX-3GP
R2441
100KR2F-L3-GP
Wistron Corporation
1
R2444
100KR2F-L3-GP

2

2
2
2
Title
KBC SMSC 1416
EC_AGND EC_AGND Custom
Date: Friday, November 10, 2017 Sheet 24 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = SPI Flash

SPI Flash ROM1(16M) for PCH
3D3V_S5_PCH
3D3V_S5_PCH
D D
1
0519 Follow KY15. 3D3V_S5_PCH C2501
SKT251 SC10U6D3V3MX-GP
DY C2502
4
3
SPI_CS_ROM_N0 1 8 SCD1U16V2KX-3GP
2
SPI_SO_ROM_R 2 7 SPI_HOLD_ROM_R
R2501
4K7R2J-2-GP
RN2501
SPI_WP_ROM_R 3 6 SPI_CLK_ROM_R
4
EVT 5 SPI_SI_ROM_R
DY SRN4K7J-8-GP
2
SKT-G6179HT0321-001-GP
1
2
Layout Note : 62.10089.011
Co-lay with SPI25 SPI25 3D3V_S5_PCH
SPI_CS_ROM_N0 1 8 RN2503
[18] SPI_CS_ROM_N0 SPI_SO_ROM_R CS# VCC SPI_HOLD_ROM_R
R2507 1 2 2 7 SRN0J-6-GP
[18,91] SPI_SO_ROM SPI_WP_ROM_R SO IO3 SPI_CLK_ROM_R
10R2F-L1-GP 3 6 1 4
IO2 SCLK SPI_SI_ROM_R SPI_CLK_ROM [18,91]
4 5 2 3
VSS SI SPI_SI_ROM [18,91]
C C
GD25B128CSIGR-GP
1 4
072.25128.0H01 SPI_WP_ROM_R 2 3
SPI_HOLD_ROM [18]
SPI_WP_ROM [18]
RN2502
SRN0J-6-GP
3D3V_AUX_S5
Main Func = RTC
1
R2503
1K6R2F-GP
0511 Follow KY15.
2
3D3V_RTC_SYS
B
+RTC_VCC B
1
1 +RTC_VCC R2505
AFTP2502 47KR2F-GP
D2501 RTC_3D3V
1
2
RTC1 3
1 R2502 1 2 RTC_PWR 2
PWR 2 1KR2J-1-GP 1 C2503
GND NP1 BAT54C-12-GP SCD47U10V2KX-GP
NP1 NP2
NP2 75.00054.A7D
2
BAT-AAA-BAT-054-P06-GP-U
1 AFTP2501 <Core Design>
62.70001.061 Q2505
G
Wistron Corporation
1
A
D RTC_DET# [20] A
R2504 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
S Taipei Hsien 221, Taiwan, R.O.C.
10MR2J-L-GP
2N7002K-2-GP Title
Flash/RTC
2
84.2N702.J31
2ND = 84.2N702.031 Size Document Number Rev
A4
5 4 3 2 1
5 4 3 2 1
Main Func = Thermal Sensor

3D3V_S5_KBC
KBC T8
1
Q2602
R2607
10KR2J-L-GP
DY G
D
[17,24,79] RESET_OUT# D
DY D
R2602 PURE_HW_SHUTDOWN# [40,79]
2
1 2 THERM_SYS_SHDN# S
C2610
SCD1U16V2KX-3GP
[24] CMP_VOUT0 DY
1
0R2J-2-GP 2N7002K-2-GP
DY
84.2N702.J31
2
2ND = 84.2N702.031
R2612 1 2 0R0402-PAD
Close to Thermal sensor

3D3V_AUX_S5 3D3V_S5_KBC
1
C
DY R2609
24K9R2F-L-GP
R2608
25K5R2F-GP
Close to KBC C
VD_IN1 for system thermal sensor
2
CMP_VIN0_R [24]
thermistor
1
1
R2610 C2612 C2613
NTC-100K-8-GP SCD1U16V2KX-3GP SC100P50V2JN-3GP
2
2
2
VD_IN1_C 1 R2611 2
0R0402-PAD
Fan controller1
5V_S0
AFTP2602 1FAN_TACH1_C R2605 FAN261
B AFTP2603 1FAN_VCC1 0R2J-2-GP B
1 DY 2 FON# 1 8
2 FSM# GND 7
5V_S0 VIN GND
FAN_VCC1 3 6
C2605
SCD1U16V2KX-3GP
C2611
SC4D7U6D3V3KX-GP
FAN_VCC1 VOUT GND
1
FAN_TACH1 4 5
[24] FAN1_DAC_1 VSET GND
FAN_VCC1
2
APL5606AKI-TRG-GP
EC2602
SC10P50V2JN-L1-GP
Layout Note: 74.05606.A71

1
DY DY EC2601
Need 10 mil trace width. 2rd = 74.02113.0E1
SCD1U16V2KX-3GP
3rd = 74.03940.A71
2
FAN1
5
3
1 R2606 2 FAN_TACH1_C 2
[24] FAN_TACH1
0R0402-PAD
FAN_VCC1 1
FAN_VCC1
4
D2601 <Core Design>
SC2200P50V2KX-2GP
C2603
K
ETY-CON3-11-GP
RB551V30-GP
1
C2604 020.F0283.0003
A
Layout Note: SC4D7U6D3V3KX-GP DY DY DY Wistron Corporation
A
Signal Routing Guideline: 2nd = 20.F1621.003 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
Trace width = 15mil 1 Taipei Hsien 221, Taiwan, R.O.C.

A
AFTP2601
Title
83.R5003.H8H
change the fan define & connect P/N 020.F0283.0003 by Andy 1/27
THERMAL NCT7718W/Fan
Custom
Date: Wednesday, November 08, 2017
Sheet 26 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = Audio

[29] AUD_HP1_JACK_L LINE1_VREFO [29]
moat
Audio Codec Chip ALC3204 [29] AUD_HP1_JACK_R
AUD_AGND
MIC2_VREFO [29]
+5V_AVDD
R2703 1 2
5V_S0
5V_S0 +5V_PVDD 0R0603-PAD-2-GP-U

LDO1_CAP
C2706
SCD1U16V2KX-3GP
C2707
SC10U6D3V3MX-GP
1
1
R2701 1 2
C2708
1
C2709
SC2D2U10V2KX-GP
C2702
SC2D2U10V2KX-GP
C2703
SC2D2U10V2KX-GP
0R0805-PAD-2-GP-U
1
R2707 1 2
R2702
100KR2J-1-GP
CPVDD
2
0R0805-PAD-2-GP-U
C2704
SCD1U16V2KX-3GP
C2705
SC2D2U10V2KX-GP
2
1
SC2D2U10V3KX-L-GP
Layout Note:
LINE1_VREFO
2
MIC2_VREFO
1D8V_S0 CPVDD
AUD_VREF
Place close to Pin 20
LDO1_CAP
D D
2
Analog
CPVEE
R2709 1 2 AUD_AGND
moat
CBN
CBP
0R0402-PAD-2-GP
AUD_AGND EC2701 1DY 2 SCD1U25V2KX-GP
1DY 2
Digital 1.8V power rail should be supplied by
EC2702
EC2703 1DY 2
SCD1U25V2KX-GP
SCD1U25V2KX-GP
30
29
28
27
26
25
24
23
22
21
linear regulator, not awitching HDA27 EC2704 1DY 2 SCD1U25V2KX-GP
regulator.if switch regulator is EC2705 1DY 2 SCD1U25V2KX-GP
CBP
LINE1-VREFO-L
CPVEE
HP-OUT-L
MIC2-VREFO
LDO1-CAP
CPVDD
CBN
HP-OUT-R
VREF
unavilable, please make sure that switch
frequency operates at out-band(over 20KHz)
1D8V_S0 R2719 1 2
0R0402-PAD-2-GP +5V_AVDD AUD_AGND
1
C2710 31
AUD_AGND AVSS2
SC10U6D3V3MX-GP 20
C2711 2 1 LDO2_CAP 32 AVDD1
AUD_AGND LDO2-CAP
2
19
AVSS1 AUD_AGND
SC10U6D3V3MX-GP +3V_1D8V_AVDD 33 R2704 1 2 0R0603-PAD
>2A moat AUD_AGND
AVDD2 18 LINE1_L R2705 1 2 0R0603-PAD
R2713 1 2 0R0805-PAD-2-GP-U +5V_PVDD1 34 LINE1-L LINE1_L [29] R2706 1 2 0R0603-PAD
+5V_PVDD PVDD1 LINE1_R
R2714 1 2 0R0805-PAD-2-GP-U
ALC3204 17
LINE1-R LINE1_R [29]
1
1
C2713 C2714 AUD_SPK_L+ 35
[29] AUD_SPK_L+ SPK-L+ 16 V3D3_STB
SC10U6D3V3MX-GP
SCD1U16V2KX-3GP
QFN40 (5X5)
AUD_SPK_L- 36 VD33STB AUD_AGND Layout Note:
[29] AUD_SPK_L- SPK-L-
2
2
15 MIC_CAP C2715 1 2 SC10U6D3V3MX-GP Tied at point only under
AUD_SPK_R- MIC2-CAP AUD_AGND
37 Codec or near the Codec
[29] AUD_SPK_R- SPK-R- 14 SLEEVE
AUD_SPK_R+ 38 SLEEV/MIC2-R SLEEVE [29]
[29] AUD_SPK_R+ SPK-R+ 13 RING2
GPIO0/DMIC-DATA12
+5V_PVDD1 39 RING2/MIC2-L RING2 [29]
PVDD2 12 AUD_SENSE_A
GPIO1/DMIC-CLK
Layout Note: HP/LINE1-JD_JD1
1
C2717 C2718 PDB_R 40

PDB 11 AUD_PC_BEEP
Speaker trace
SC10U6D3V3MX-GP
SCD1U16V2KX-3GP
SDATA-OUT
41 PCBEEP
LDO3-CAP
DVDD must >= DVDD_IO width >40mil @
SDATA-IN
GND
DVDD-IO
2
DC_DET
BIT-CLK
2W4ohm speaker
DVDD
SYNC
3D3V_S0 +3V_1D8V_DVDD power
R2715 1 2 ALC3204-CG-GP-U
Analog
10
+3V_1D8V_DVDD
0R0603-PAD-2-GP-U
moat
C2741
SCD1U16V2KX-3GP
C2740
SC2D2U10V2KX-GP
Digital
HDA_SDOUT_CODEC_R
HDA_BITCLK_CODEC_R
1
C +3V_1D8V_DVDD C
HDA_CODEC_SDIN0
place close to pin8
HDA_CODEC_SYNC
C2723
SC4D7U6D3V3KX-GP
2
1
+3V_1D8V_DVDD
DMIC_DATA_R
C2720
SC10U6D3V3MX-GP
C2721
SCD1U16V2KX-3GP
DMIC_CLK_R
1
LDO3_CAP
2
1
DY R2717
DVSS
2
2
100KR2J-1-GP Open drain output.
pull up to DVDD or
max. 5V
2
R2712 1 2 PDB_R place close to pin1 R2708 1 2 0R0402-PAD-2-GP V3D3_STB

[24] NB_MUTE# RTC_AUX_S5
1
0R0402-PAD C2722
SC10U6D3V3MX-GP 3D3V_S0 R2716 1 DY 2 100KR2J-1-GP DVSS
2
R2718 1 2 0R0402-PADDMIC_DATA_R AUD_SENSE R2711 1 2 AUD_SENSE_A
[55] DMIC_DATA [29] AUD_SENSE
200KR2F-L-GP
R2720 1 2 22R2J-2-GP DMIC_CLK_R
[55] DMIC_CLK R2710 1 2
+3V_1D8V_DVDD
1
DY C2725 100KR2J-1-GP
SC10P50V2JN-L1-GP
0602 DY
2
Close pin3
Azalia I/F EMI D2703
HDA_CODEC_SDOUT R2741 1 2 HDA_SPKR_R 1
HDA_CODEC_BITCLK [19] SPKR
0R0402-PAD-2-GP C2735
DMIC_DATA R2724 1 2 22R2J-2-GP HDA_CODEC_SDIN0 3 AUD_PC_BEEP_C 1 2 AUD_PC_BEEP
[19] HDA_SDIN0
1
HDA_CODEC_SYNC R2734 1 2 KBC_BEEP_R 2

DY EC2709 EC2710DY EC2711
[19] HDA_CODEC_SYNC [24] BEEP
SCD1U16V2KX-3GP
SC22P50V2JN-4GP
SC22P50V2JN-4GP
SC22P50V2JN-4GP
0R0402-PAD-2-GP
1
R2722 1 2 HDA_SDOUT_CODEC_R
C2739
SC100P50V3JN-2GP
BAT54C-12-GP
[19] HDA_CODEC_SDOUT
2
1
R2735
1KR2J-1-GP
0R0402-PAD-2-GP
HDA_BITCLK_CODEC_R 75.00054.A7D DY
R2723 1 2 22R2J-2-GP
[19] HDA_CODEC_BITCLK
2
B B
2
0602 Delete C2727
1D8V_S5 Q2704 1D8V_S0

DMP2130L-7-GP
150mA S
D
1
C2737
SCD1U16V2KX-3GP
D
1
3D3V_S0
G
0602 Delete R2739 R2736 C2738

1
10KR2J-L-GP SCD22U10V2KX-L1-GP DY C2736

G
SCD1U16V2KX-3GP
2
2
1
DY R2737 1D8V_EN_R#
0R2J-2-GP R2738 1 2
4K7R2J-2-GP
84.02130.031
1D8V_EN#
2
Q2705
R2740 1 2 Q4009_G G
[17,24,40,51] SIO_SLP_S3# 2nd = 84.00102.031
0R0402-PAD-2-GP
D 3rd = 84.03413.B31
S
2N7002K-2-GP
A A
<Core Design>
Wistron Corporation
Title
Audio Codec ALC3204

A2
Turis/Vegas KBL-R X00
5 4 3 2 1
5 4 3 2 1
Main Func = Audio
Layout Note: Speaker

Speaker trace width >40mil @ 2W4ohm speaker power
SPK1
D 5 D
R2904 1 2 0R0603-PAD-2-GP-U AUD_SPK_R+_C 1 CONN Pin Net name
[27] AUD_SPK_R+
R2903 1 2 0R0603-PAD-2-GP-U AUD_SPK_R-_C 2 Pin1 SPK_R+
[27] AUD_SPK_R- R2902 1 2 0R0603-PAD-2-GP-U AUD_SPK_L+_C 3
[27] AUD_SPK_L+ 2 0R0603-PAD-2-GP-U AUD_SPK_L-_C
[27] AUD_SPK_L-
R2901 1 4 Pin2 SPK_R-
6
Pin3 SPK_L+
ACES-CON4-29-GP
20.F1639.004 Pin4 SPK_L-
2nd = 020.F0700.0004
3rd = 20.F1804.004
EC2901
SC1KP50V2KX-L-1-GP
EC2902
SC1KP50V2KX-L-1-GP
EC2903
SC1KP50V2KX-L-1-GP
EC2904
SC1KP50V2KX-L-1-GP
1
1
2
2
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904
C C
Universal Jack (Moved to I/O Board)

RN2901
2 3
[27] MIC2_VREFO 1 4
SRN2K2J-1-GP
[27] RING2 R2906 1 2 0R0603-PAD-2-GP-U RING2_R
R2908 1 2 10R2F-L1-GP AUD_HP1_JACK_L1 R2907 1 2 0R0603-PAD-2-GP-U AUD_PORTA_L_R_B RING2_R [66]
[27] AUD_HP1_JACK_L AUD_PORTA_L_R_B [66]
C2907 1 2 LINE1-L_C R2922 1 2 1KR2J-1-GP
[27] LINE1_L SC10U6D3V3MX-L-GP JACK_PLUG
C2908 1 2 LINE1-L_R R2921 1 2 1KR2J-1-GP JACK_PLUG [66]
[27] LINE1_R SC10U6D3V3MX-L-GP R2910 1 2 10R2F-L1-GP AUD_HP1_JACK_R1 R2909 1 2 0R0603-PAD-2-GP-U AUD_PORTA_R_R_B
[27] AUD_HP1_JACK_R AUD_PORTA_R_R_B [66]
[27] SLEEVE R2911 1 2 0R0603-PAD-2-GP-U SLEEVE_R
SLEEVE_R [66]
1
D2901
EC2908
SC100P50V2JN-3GP
EC2907
SC100P50V2JN-3GP
EC2906
SC100P50V2JN-3GP
EC2905
SC100P50V2JN-3GP
1
1
1 LINE1_VREFO_D1 R2912 1 2
R2920
10KR2J-L-GP
R2919
10KR2J-L-GP
4K7R2J-2-GP
DY DY DY DY DY DY
B B
3
[27] LINE1_VREFO
2
2
2
2
2 LINE1_VREFO_D2 R2913 1 2
4K7R2J-2-GP
BAT54A-11-GP
AUD_AGND AUD_AGND AUD_AGND
Delay circuit
(JACK_PLUG_DET: on IO Board)
10 mils
JACK_PLUG 10 mils R2923 1 2
0R0603-PAD-2-GP-U AUD_SENSE [27]
1
DY C2902
SC10U6D3V3MX-GP
2
<Core Design>
A AUD_AGND A
Wistron Corporation
Title
Audio IO
Custom
5 4 3 2 1
5 4 3 2 1
Main Func = LAN
Layout:
For RTL8111G(S) Ca: colse to Pin8
* Place Ca~Cd close to each VDD10 pin-- 8, 30, 3, 22 Cb close to Pin30
LAN CHIP (10/100/1000M & 10/100M co-lay)

For RTL8106E Cc: close to Pin3
* Place Ca,Cb close to each VDD10 pin-- 8, 30 Cd: close to Pin22
Ra LAN power Noise 1V_LAN_VDD10 < 100mV Vpeak to Vpeak.
D REGOUT R3101 1 2 VDD10 D

C3101,R3101: 0R0603-PAD-2-GP-U
8111G/LAN_SW
8111G/LAN_SW
Only for
RTL8111 LDO mode. Ci Cj Ca Cb Cc Cd
LAN_SW
LAN_SW
R3102 C3102
PCIE_RX_CON_P5 1 2 SCD1U16V2KX-3GP
C3108
SC4D7U6D3V3KX-GP
C3115
SCD1U16V2KX-3GP
C3112
SCD1U16V2KX-3GP
C3119
SCD1U16V2KX-3GP
C3123
SCD1U16V2KX-3GP
C3122
SCD1U16V2KX-3GP
L3101 La 2K49R2F-2-L-GP
PCIE_RX_CPU_P5 [16]
1
C3118 1 2 RTL8111GUS-CG RTL8111G-CGT RTL8106EUS-CG RTL8106E-CG 1 2 PCIE_RX_CON_N5 1 2 SCD1U16V2KX-3GP
PCIE_RX_CPU_N5 [16]
8111G IND-4D7UH-242-GP
PCIE_TX_CON_P5
C3107
2
LAN_SW PCIE_TX_CON_P5 [16]
2
PCIE_TX_CON_N5
SCD1U16V2KX-3GP
Ch 71.08111.W03 71.08111.U03 71.08106.003 071.08106.0003
PCIE_TX_CON_N5 [16]
68.4R71E.10G
SWR mode LDO mode SWR mode LDO mode PEG_CLK2_CPU [18]
PEG_CLK2_CPU# [18]
3D3V_LAN_S5
LANXOUT
10/100/1000M 10/100/1000M 10/100M 10/100M
LANXIN
VDD10
LED0 1 TP3103 TPAD14-OP-GP
RSET
LED1 1 TP3102 TPAD14-OP-GP
Layout: LED2 1 TP3101 TPAD14-OP-GP
For RTL8111G(S)
* Place Ce and Cf close to each VDD33 pin-- 11, 32
32
31
30
29
28
27
26
25
For RTL8106E LOM31
* Place Cg and Cf close to each VDD33 pin-- 23, 32
AVDD33
AVDD10
CKXTAL2
CKXTAL1
LED0
(GPO) LED1/GPO
(LED1) LED2
RSET
33 3D3V_S5
GND
3D3V_LAN_S5 VDDREG
1
1 2 C3104
40 mils R3104 1 2 0R0603-PAD 1
(NC) REGOUT
24 REGOUT SC1U10V2KX-1GP
R3103
10KR2J-L-GP
[32] LAN_MDI0P MDIP0
8106E
2 23 VDDREG C3114 1 2 SCD1U16V2KX-3GP

[32] LAN_MDI0N MDIN0 (DVDD33) VDDREG
1
1
8111G/LAN_SW
C3113 C3117 C3103 LAN_SW VDD10 3 22 VDD10

AVDD10 (NC) (NC) DVDD10
2
4 21 PCIE_WAKE#
LAN_SW [32] LAN_MDI1P MDIP1 71.08111.U03 LANWAKE# PCIE_WAKE# [24]
1
5 20 R3109 1 2
SCD1U16V2KX-3GP
Cf: close to Pin32 C3124 Ck Cl ISOLATE#
[32] LAN_MDI1N MDIN1 ISOLATE# 3D3V_S0
2
6 19 PLT_RST#_LAN
Ce Cf Cg Ce: close to Pin11 C3110
[32] LAN_MDI2P MDIP2 (NC) (071.08106.0003) PERST#
1KR2J-1-GP
1
SC4D7U6D3V3KX-GP 7 18 PCIE_RX_CON_N5
Cg: close to Pin23 [32] LAN_MDI2N MDIN2 (NC) HSON
2
VDD10 8 17 PCIE_RX_CON_P5 R3113
AVDD10 HSOP 15KR2J-1-GP
AVDD33 (NC)
SCD1U16V2KX-3GP
MDIP3 (NC)
MDIN3 (NC)
REFCLK_N
REFCLK_P
SCD1U16V2KX-3GP
X5R
CLKREQ#
2
SCD1U16V2KX-3GP
HSIN
HSIP
C C
RTL8107E-CG PN:071.08106.0003
RTL8111G-CGT-1-GP-U2 Manual: :071.08106.0003
9
10
11
12
13
14
15
16
3D3V_LAN_S5
RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW.
RTL8106E-CG (071.8107E.0A03): 10/100M <70mW.
C3109
SC4D7U6D3V3KX-GP
C3111
SC4D7U6D3V3KX-GP
[32] LAN_MDI3P
1
DY DY [32] LAN_MDI3N
3D3V_LAN_S5
2
LAN_CLKREQ_LAN# C3116
PCIE_TX_CON_P5 LANXOUT 1 2
PCIE_TX_CON_N5
PEG_CLK2_CPU SC15P50V2JN-2-GP
R3110 1 2 PLT_RST#_LAN PEG_CLK2_CPU#
[17,55,61,63,76,91] PLT_RST# 0R0402-PAD Layout:
C3109 : close to Pin32
3
0512 Deleted DY part C3111 : close to Pin11 LAN_CLKREQ_LAN#
X3101
[18] CLKREQ_PCIE#2 R3105 1 2 XTAL-25MHZ-260-GP
0R0402-PAD 082.30005.0041
0512 Deleted DY part
2
C3125
3D3V_LAN_S5 rise time must be controlled LANXIN 1 2
between 0.5 mS and 100 mS.
SC15P50V2JN-2-GP
LAN power Noise 3D3V_LAN_VDD33 < 200mV Vpeak to Vpeak.
3D3V_S5 3D3V_LAN_S5
Q3101
DMP2130L-7-GP
85mA S
D
C3121
SCD1U16V2KX-3GP
D
1
1
G
B C3120 B
1
SCD1U16V2KX-3GP
R3106 DY
G
10KR2J-L-GP C3105
2
SC1U10V2KX-1GP
R3111
2
2
1 2 PM_LAN_ENABLE_C
LAN_ENABLE_R_C
20KR2J-L2-GP 84.02130.031
2nd = 84.00102.031
3rd = 84.03413.B31
Q3102
G
[24] PM_LAN_ENABLE
1
D
R3107
100KR2J-1-GP
2N7002K-2-GP
2
BOM Option 1.0V

Source Ra Ch Cc Cd Ce La Ci Cj Ck Cl Cg
RTL8111G-CGT LDO
(71.08111.U03) 8111G O O O O O X X X X X X
A A
RTL8111GUS-CG
(71.08111.W03)/ SWR X X O O O O O O O O X
LAN_SW
RTL8106EUS-CG
(71.08106.003) <Core Design>
Wistron Corporation
RTL8106E-CG 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
(071.08106.0003) 8106E LDO X X X X X X X X X X O Taipei Hsien 221, Taiwan, R.O.C.
Title
LAN RTL8106
A2
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = LAN LAN TransFormer (10/100/1000M & 10/100M co-lay)

RJ45
9
1 CHASSIS#9
Layout: MDO0+
MDO0+
XF3201 XFORM-12P-48-GP
12 1CT:1CT 1 MDO3- Place near RJ45 MDO0- 2
[31] LAN_MDI3N MDO0-
D
AFTE14P-GP AFTP3204 1 MDO0+ MDO1+ 3 D
3 MCT0 1 MDO0- MDO2+ 4 MDO1+
AFTE14P-GP AFTP3201 MDO2+
AFTE14P-GP AFTP3202 1 MDO1+ MDO2- 5
11 2 MDO3+ 1 MDO2+ MDO1- 6 MDO2-
[31] LAN_MDI3P AFTE14P-GP AFTP3205 MDO1-
AFTE14P-GP AFTP3203 1 MDO2- MDO3+ 7
10 1 MDO1- MDO3- 8 MDO3+
AFTE14P-GP AFTP3208 MDO3-
AFTE14P-GP AFTP3207 1 MDO3+ 10
[31] LAN_MDI2N 8 10/100/1000
1CT:1CT 5 MDO2- AFTE14P-GP AFTP3206 1 MDO3- CHASSIS#10
RJ45
4 MCT1 RJ45-8P-186-GP
7 6 MDO2+ 022.10001.00C1
[31] LAN_MDI2P
2nd = 022.10001.0D41
9 3rd = 022.10001.0C41
68.68167.30D
MCT3
XF3202 XFORM-12P-48-GP MCT2
9 MCT1
C MCT0 C
[31] LAN_MDI1N 7 6 MDO1-
4
3
2
1
4 MCT2
RN3201
[31] LAN_MDI1P 8 5 MDO1+ SRN75J-1-GP
1CT:1CT
10
5
6
7
8
11 2 MDO0-
LOM_TCT
[31] LAN_MDI0N
3 MCT3
MCT
[31] LAN_MDI0P 12 1 MDO0+
1
C3202
1CT:1CT
68.68167.30D SC56P3KV8JN-1-GP
2
Layout note: Layout note:
30 mil spacing between MDI differential pairs. 30 mil spacing between MDI differential pairs.
1
C3201
B SCD01U50V2KX-L-GP B
2
Follow Reference Schematic 0.01uF~0.4uF
ED3202 ED3201
LAN_MDI0P 1 10 LAN_MDI0P LAN_MDI2P 1 10 LAN_MDI2P

LAN_MDI0N 2 IN1 NC#10 9 LAN_MDI0N LAN_MDI2N 2 IN1 NC#10 9 LAN_MDI2N
3 IN2 NC#9 8 3 IN2 NC#9 8
LAN_MDI1P 4 GND GND 7 LAN_MDI1P LAN_MDI3P 4 GND GND 7 LAN_MDI3P
LAN_MDI1N 5 IN3 NC#7 6 LAN_MDI1N LAN_MDI3N 5 IN3 NC#7 6 LAN_MDI3N
IN4 DY NC#6 IN4 DY NC#6
<Core Design>
TVWDF1004AD0-1-GP TVWDF1004AD0-1-GP
A
75.01004.073 75.01004.073 Wistron Corporation A
Title
XFOM&RJ45
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Card Reader
D D
R3301 1 2 0R0402-PAD-2-GP
[16] USB_CPU_PN5 USB_PN5_C [66]
C R3302 1 2 0R0402-PAD-2-GP C
[16] USB_CPU_PP5 USB_PP5_C [66]
Layout Note:
Close to CON1
B B
<Core Design>
A
Title
Size
Card Reader-RTS5170
Document Number Rev
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = USB3.0 Port1

USB3.0 Port1
USB30_VCCC
2A
D D
Layout Note: Close USB1

5V_S5
U3501 USB30_VCCC
C3507
SCD1U16V2KX-3GP
C3508
SC1U10V2KX-1GP
C3512
SC22U6D3V3MX-1-DL-GP
C3513
1
1
5 1 DY TC3501
IN OUT 2 SC100U6D3V6MX-GP
4 GND 3
C3510
SC1U10V2KX-1GP
[24,35] USB_PWR_EN# EN# OC# USB_OC0# [16] 78.10710.52L
2
1
Active Low
SY6288DAAC-GP
2
074.06288.009B
0817 Change Cap Size
C C

USB2.0 Port3 (IO Board)
USB20_VCCA
5V_S5
Support 2A USB20_VCCA 2A
U3503
C3517
SCD1U16V2KX-3GP
C3518
SC1U10V2KX-1GP
C3515
SC22U6D3V5MX-L3-GP
1
1
5 1 DY
IN OUT 2
4 GND 3
[24,35] USB_PWR_EN# EN# OC# USB_OC2# [16]
2
B Active Low B
1
C3504 SY6288DAAC-GP
SCD1U16V2KX-3GP 074.06288.009B
2
Layout Note: Close CON1
<Core Design>
A
Title
USB switch
5 4 3 2 1
5 4 3 2 1

USB3.0 Port1
USB1
USB30_VCCC
EL3601 1 10
1 2 USB_PP0_C VBUS CHASSIS#10 11 USB30_VCCC 1 AFTP3601
[16] USB_CPU_PP0 USB_PN0_C CHASSIS#11 USB_PN0_C
2 12 1 AFTP3602
4 3 USB_PN0_C USB_PP0_C 3 D- CHASSIS#12 13 USB_PP0_C 1 AFTP3603
[16] USB_CPU_PN0 D+ CHASSIS#13
FILTER-4P-137-GP-U
D USB3_PRX_CTX_N1_C 5 D
68.01012.20B USB3_PRX_CTX_P1_C 6 SSRX-
SSRX+ 4 1 AFTP3604
USB3_PTX_CRX_N1_C 8 PGND
C3602 USB3_PTX_CRX_P1_C 9 SSTX- 7
SCD1U16V2KX-3GP SSTX+ GND
1 2 USB3_PTX_CRX_N1_R R3605 1 2 USB3_PTX_CRX_N1_C USB3.0
[16] USB30_TX_CPU_N1
0R0402-PAD-2-GP SKT-USB13-179-GP
C3601 022.10005.00B1
SCD1U16V2KX-3GP 2nd = 022.10005.0831
1 2 USB3_PTX_CRX_P1_R R3606 1 2 USB3_PTX_CRX_P1_C 3rd = 022.10005.00A1
[16] USB30_TX_CPU_P1
0R0402-PAD-2-GP
Stuff for ESD R2 spec
ED3602
USB3_PRX_CTX_N1_C 1 10 USB3_PRX_CTX_N1_C
USB3_PRX_CTX_P1_C 2 LINE_1 NC#10 9 USB3_PRX_CTX_P1_C
R3607 1 2 0R0402-PAD-2-GP USB3_PRX_CTX_N1_C 3 LINE_2 NC#9 8
[16] USB30_RX_CPU_N1 USB3_PTX_CRX_N1_C GND GND USB3_PTX_CRX_N1_C
4 7
R3608 1 2 0R0402-PAD-2-GP USB3_PRX_CTX_P1_C USB3_PTX_CRX_P1_C 5 LINE_3 NC#7 6 USB3_PTX_CRX_P1_C
[16] USB30_RX_CPU_P1 LINE_4 NC#6
C AZ1045-04F-R7G-GP C
75.01045.073

USB3.0 Port2
USB2
USB30_VCCC 1 10
VBUS CHASSIS#10 11
USB_PN1_C 2 CHASSIS#11 12
USB_PP1_C 3 D- CHASSIS#12 13
EL3602 D+ CHASSIS#13
4 3 USB_PN1_C
[16] USB_CPU_PN1 USB3_PRX_CTX_N2_C 5
1 2 USB_PP1_C USB3_PRX_CTX_P2_C 6 SSRX-
[16] USB_CPU_PP1 SSRX+ 4 1 AFTP3608
FILTER-4P-137-GP-U USB3_PTX_CRX_N2_C 8 PGND
USB3_PTX_CRX_P2_C 9 SSTX- 7
68.01012.20B SSTX+ GND
USB3.0
C3605 SKT-USB13-179-GP
B SCD1U16V2KX-3GP B
1 2 USB3_PTX_CRX_N2_R R3609 1 2 USB3_PTX_CRX_N2_C 022.10005.00B1
[16] USB30_TX_CPU_N2
0R0402-PAD-2-GP 2nd = 022.10005.0831
3rd = 022.10005.00A1
C3604
SCD1U16V2KX-3GP
1 2 USB3_PTX_CRX_P2_R R3610 1 2 USB3_PTX_CRX_P2_C
[16] USB30_TX_CPU_P2
0R0402-PAD-2-GP
ED3603
USB3_PRX_CTX_N2_C 1 10 USB3_PRX_CTX_N2_C
USB3_PRX_CTX_P2_C 2 LINE_1 NC#10 9 USB3_PRX_CTX_P2_C
3 LINE_2 NC#9 8
R3611 1 2 0R0402-PAD-2-GP USB3_PRX_CTX_N2_C USB3_PTX_CRX_N2_C 4 GND GND 7 USB3_PTX_CRX_N2_C
[16] USB30_RX_CPU_N2 USB3_PTX_CRX_P2_C LINE_3 NC#7 USB3_PTX_CRX_P2_C
5 6
R3612 1 2 0R0402-PAD-2-GP USB3_PRX_CTX_P2_C LINE_4 NC#6
[16] USB30_RX_CPU_P2
AZ1045-04F-R7G-GP
75.01045.073
2nd = 75.00107.073
ED3604 <Core Design>
A USB_PN1_C 1 6 USB_PP1_C USB30_VCCC A
2
I/O1 I/O4
5 USB30_VCCC 1 AFTP3605
Wistron Corporation
GND VDD 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
USB_PN1_C 1 AFTP3606 Taipei Hsien 221, Taiwan, R.O.C.
1
USB_PN0_C 3 4 USB_PP0_C USB_PP1_C

I/O2 I/O3 DY C3618
SCD1U16V2KX-3GP
1 AFTP3607
Title
USB30
2
AZC099-04S-2-GP
075.09904.0A7C Custom
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
D D
USB port 3 (USB2.0 only) CMC
R3701 1 DY 2
0R2J-L-GP
Layout Note:
Close to CON1
EL3706
1 2 USB_PN2_C
[16] USB_CPU_PN2 USB_PN2_C [66]
4 3 USB_PP2_C
[16] USB_CPU_PP2 USB_PP2_C [66]
C C
FILTER-4P-137-GP-U
68.01012.20B
R3702 1 DY 2
0R2J-L-GP
USB ESD Diode

ED3704 USB20_VCCA
B USB_PP2_C 1 6 USB_PN2_C B
I/O1 I/O4
2 5
GND VDD
3
DY 4
I/O2 I/O3
Layout Note:
1
Close to CON1 DY C3706
SCD1U16V2KX-3GP
AZC099-04S-2-GP
2
075.09904.0A7C
<Core Design>
A
Title
USB20
A4
5 4 3 2 1
5 4 3 2 1
Main Func = Power Plane & Sequence 3D3V_S0
Power Good
ROSA Run Power
1
R4005
0519 Follow KY15 to delete DY part

U4001 5V_S0
5V_S0 1KR2J-1-GP
2
5V_S0 Comsumption R4011 1 2
[51] PWR_VDDQ_PG ALL_SYS_PWRGD [17,24]
1 13 0R0402-PAD
5V_S5
2 VIN1#1 VOUT1#13 14 Peak current 5A
VIN1#2 VOUT1#14 3D3V_S0 R4002 1 2
3D3V_S5 6
7 VIN2#6
VIN2#7
VOUT2#8
VOUT2#9
8
9 3D3V_S0 RSMRST_PWRGD# 3
D4002
1
2
0R0402-PAD
VR_EN [46]
C4005
SC10U6D3V3MX-GP
DY
1
D 12 3V5V_CT1 3D3V_S0 Comsumption D
4 SS1 10 3V5V_CT2 LBAS16LT1G-GP
5V_S5 VBIAS SS2 Peak current 2.5A
2
C4002
SC470P50V2KX-3GP
C4001
SC470P50V2KX-3GP
C4004
SC10U6D3V3MX-GP
83.00016.P11
1
R4010 1 2 3V5V_S0_ON 3 11
[17,24,27,40,51] SIO_SLP_S3# EN1 GND
0R0402-PAD 5 15 3D3V_S5 3D3V_S5_KBC
EN2 GND
2
AP22966DC8-7-GP
074.22966.0093 [#543016] Optional, Added for addition system robustness
1
R4031 DY R4032
R4029 1 2 0R0402-PAD 100KR2J-1-GP 100KR2J-1-GP
[53] 1D0V_S5_PWRGD
0522 Follow EC vendor Marc suggest. 0511 Follow KY15. R4030 1 2 0R0402-PAD
[24,54] PRIM_PWRGD
2
R4012 1 DY 2
0R2J-L-GP R4033 1 2 0R2J-2-GP RSMRST_PWRGD#
[17,21,45,53,54] 3V_5V_POK DY
NON DS3: PH 3V_5V_POK to 3D3V_AUX_S5 at page17
D4001
2
[45] 3V_5V_EN 1 3 PURE_HW_SHUTDOWN# [26,79]
5V_S5
1
LBAS16LT1G-GP
C4009
SC10U6D3V3MX-GP
1
R4006
20KR2J-L2-GP
83.00016.P11
VCCSTG and VCCIO
2
R4009 1 2 10KR2J-L-GP
C4029
SC1U10V2KX-1GP
ALWON [24]
2
1
DY
+VCCIO(ICCMAX = 2.73A)
2
U4002 +VCCIO +VCCSTG
0519 Follow KY15 to change cap value
1 8 R4048 1 2
C 2 VIN VOUT#8 7 0R0805-PAD-2-GP-U C
3 VIN VOUT#7 6
R4034 1 2 VCCSTG_EN_R 4 VBIAS VOUT#6 5 1D0V_S5
[17,24,27,40,51] SIO_SLP_S3# 0R0402-PAD EN GND
C4007
SC10U6D3V3MX-GP
1
9
VIN
1
DY C4017
VIL > 0.7 V, VIH < 2 V SCD1U16V2KX-3GP
C4016
SC10U6D3V3MX-GP
2
1
Rds(on) = 11 mΩ @ VDD = 4 V APE8939GN3-GP
2
Ids(max) 10 A
2
074.08939.0093
VCCSTG should only ramp up equal to or after VCCST.
+VCCSTG(ICCMAX.=0.16A)
U4002 U4006 change to 074.08939.0093 Trise=10US < TR < 65US
for quality issue change 2/26
MANAGEMENT RAIL POWER GENERATION

5V_S5
EOPIO and EDRAM
VIL > 0.7 V, VIH < 2 V
1
Rds(on) = 11 mΩ @ VDD = 4 V
C4028 DY Ids(max) 10 A
SC1U10V2KX-1GP +V1.00U_CPU
20170428
2
B 1
U4006
VIN VOUT#8
8 +V1.00U_CPU_LS R4025 1 2
VCCST B
2 7 0R0805-PAD-2-GP-U
3 VIN VOUT#7 6
C4012
SC10U6D3V3MX-GP
VBIAS VOUT#6
1
R4024 1 2 VCCSTU_EN_R 4 5
[17,44,51] SIO_SLP_S4#
0R0402-PAD EN GND
VIN
9 1D0V_S5 V1.8S
2
C4018
SCD1U16V2KX-3GP
C4013
SC10U6D3V3MX-GP
1
DY APE8939GN3-GP
20170428
2
074.08939.0093
U4002 U4006 change to 074.08939.0093
for quality issue change 2/26 +V1.00U_CPU +VCCST_CPU
R4036 1 2 0.04 A
0R0402-PAD-2-GP
VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization.
A A
<Core Design>
Wistron Corporation
Title
Power Plane Enable

Custom
Vegas SKL/KBL-U
Wednesday, November 08, 2017
A00
Date: Sheet 40 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = Power & Sequence
D D
3D3V_S5 3D3V_S5_PCH
R4101 1 2
0R0805-PAD-2-GP-U
C C
B B
<Core Design>
A
Title
Connected_Standby(1/2)+DS3
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = ADT Input 3D3V_S5 3D3V_S5
1
PR4306 1 DY 2 75.00099.O7D
33R2J-2-GP PR4304
Layout Note: 2nd = 75.00099.K7D 2K2R2J-L1-GP 20170502 remove DCIN2
PSID Layout width > 25mil PQ4301 3rd = 75.00099.Q7D
DMN5L06K-7-GP PD4302
2
LBAV99LT1G-1-GP
PR4317 1 2 PS_ID_R2 D S PS_ID_R1 PR4305 1 2 PS_ID [24]
0R0603-PAD 33R2J-2-GP
2
D D
84.05067.031
1
PR4309
G
EL4303 1 2 PD4303 100KR2J-1-GP 5V_S5
0R0805-PAD-2-GP-U PESD24VS2UT-GP
EL4304 1 2 PSID_DISABLE#_R_C PR4303 1 2
2
0R0805-PAD-2-GP-U 10KR2J-L-GP
C
PQ3802_1 B PQ4302
JGND LMBT3904LT1G-GP
1
DCIN1 84.T3904.H11
E
8 PR4302
6 1 AFTP4301 15KR2F-GP
5 1 AFTP4315 Id=-9.6A
4 PS_ID_R
Qg=-25nC
2
3
2 20170810 +DC_IN Rdson=18~30mohm AD+
0921 Install ESD 600W TVS PU4301
1 +DC_IN 1 S D 8
7 2 S D 7
K
3 S D 6
EC4301
SC10U25V5KX-L-GP
EC4302
SCD1U25V2KX-GP
PD4301
P6SMBJ24A-H-GP
PC4302
SCD1U50V3KX-GP
PC4303
PC4304
PC4305
PC4306
SC10U25V5KX-L-GP
1
1
4 G D 5
PC4301
SC1U50V3KX-GP
ACES-CON6-63-GP DY 1 DY DY
PR4307
240KR3-GP
20.F2132.006 PR4312 PR4314 AC_DIS [24,44] AON7403-GP-U
2
2
2nd = 20.F2505.006 DY 100KR2J-1-GP 3K3R6J-GP PQ4305 84.07403.037
2
A
2
R2
PQ4304
2
C AD_OFF_L 1
2
2
JGND JGND B R1 R1
3 AD_OFF_R
E SCD01U50V2KX-L-GP
C PQ4306 R2 LTA024EUB-FS8-GP SCD01U50V2KX-L-GP C
1
PQ3809_D 3 4 LMUN5212T1G-GP SCD01U50V2KX-L-GP
84.00024.01K
PR4308
47KR3J-L-GP
AC_IN#_G 2 5
84.05212.B11
1 6 AC_IN_KBC# 1 TP4301
2
1
1 +DC_IN TPAD14-OP-GP
AFTP4313 1 PS_ID_R PR4313 2N7002KDW-GP
AFTP4312 1 +DC_IN 0R0402-PAD
AFTP4314 84.2N702.A3F
2nd = 84.2N702.E3F
2
3rd = 75.00601.07C
Main Func = M-BAT Input 20170502 remove BATT2
Placement: Close to Batt Connector

BT+
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
B B
K
1
DY EC4308 EC4307
SCD1U50V3KX-GP
SCD1U25V2KX-GP
DY PD4304
SMF18A-GP
2
Batt Connecter
A
3
D4304 D4305 D4306
BATT1 LBAV99LT1G-1-GP LBAV99LT1G-1-GP LBAV99LT1G-1-GP
0921 Install 9
1
75.00099.O7D 75.00099.O7D 75.00099.O7D
2
2
PBAT_CHG_SMBCLK RN4302 2 3 SRN100J-3-GP PBAT_SMBCLK1 3
[24,44] PBAT_CHG_SMBCLK PBAT_CHG_SMBDAT PBAT_SMBDAT1
1 4 4
[24,44] PBAT_CHG_SMBDAT PBAT_PRES1# 5
PBAT_PRES# R4302 1 2 SYS_PRES1# 6
[24,44] PBAT_PRES# 3D3V_S5_KBC
100R2J-L-GP 7
8
EC4309
EC4310
EC4306
2nd = 75.00099.K7D 2nd = 75.00099.K7D 2nd = 75.00099.K7D

1
DY DY DY 10
R4301 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D
0R0402-PAD ALP-CON8-17-GP-U1
2
20.82003.008
2
2nd = 20.81775.008
PBAT_PRES1# 1 AFTP4303 3rd = 020.80842.0008
PBAT_SMBDAT1 1 AFTP4308 SC10P50V2JN-L1-GP
PBAT_SMBCLK1 1 AFTP4304 SC10P50V2JN-L1-GP Layout note: 1 AFTP4311
A BT+ 1 AFTP4307 SC10P50V2JN-L1-GP SYS_PRES1# >40 mil 1 AFTP4309 <Core Design> A
BT+ 1 AFTP4306 1 AFTP4310
BT+ 1 AFTP4302
SYS_PRES1# 1 AFTP4305
Wistron Corporation
Title
Size Document Number

DCIN Rev
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Charger

AD+ +SDC_IN DCBATOUT
+VCHGR
PR4426
PQ4410 D01R3721F-GP-U PQ4401
8 D S 1 1 2 1 S D 8
7 D S 2 2 S D 7
6 D S 3 3 S D 6
5 D G 4 4 G D 5
1
AON7403-GP-U PR4441 AON7403-GP-U
2
84.07403.037 100KR2J-1-GP 84.07403.037
PG4429 PG4407
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP AD+
2
D PR4440 D
1
1
20KR3J-1-GP
PR4420 1 2 AD+_R
10KR2F-L1-GP AD+_G_2
1PG_1
1PG_2
1
PR4445
1
470KR2J-L1-GP
PR4422 PR4467 PR4468
10KR2F-L1-GP 0R0402-PAD-1-GP 2R2F-GP
DC_IN_D
2
PQ4412
PC4466 G AC_DIS_R PR4444 1 2
AC_DIS [24,43]
2
SCD1U25V2KX-GP 1KR2J-1-GP
1 2 D
AD+_G_1
1
2N7002KDW-GP PC4471
S
PC4467
SC2K2P50V2KX-L-GP
SCD22U10V2KX-L1-GP
1
3 4 DY DY PC4468
2
SC2K2P50V2KX-L-GP 2N7002K-2-GP
ACOK_IN 2 5 84.2N702.J31
2
1 6 2ND = 84.2N702.031
PWR_CHG_ACP
PWR_CHG_ACN
3rd = 84.07002.I31
PQ4405
84.2N702.A3F DCBATOUT
2nd = 84.2N702.E3F
4th = 84.DMN66.03F
1
3rd = 75.00601.07C
PR4477
1KR2F-L1-GP DCBATOUT
2
PC4418 PC4427 PC4438 PC4459
PWR_CHG_REGN
SC1KP50V2KX-L-1-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
PC4456
SCD1U25V2KX-GP
PC4409
symbol name change by Andy 1/19
1
1
1
PR4454 DY
1
1
PR4417 100R5F-2-GP
100KR2J-1-GP 1 2 BT+ BT+
2
2
2
2
SC1KP50V2KX-L-1-GP
PC4407
VAC DET AD+
Greater than 2.633 V
2
1
C [17,24] ACOK_IN PC4408 C
Less than 3.5 V
SC1KP50V2KX-L-1-GP
PC4401
SC10U25V5KX-L-GP
PC4410
SC10U25V5KX-L-GP
1
1
1
PR4418
PWR_CHG_BATDRV2
1
PWR_CHG_ASGATE
191KR2F-1-GP
PWR_CHG_CMSRC
PR4452
2
PWR_CHG_ACN
PWR_CHG_ACP
5
6
7
8
AC_IN:3.35~3.75V 150KR2F-L-GP
D
D
D
D
PU4411
PWR_OPCN
PWR_OPCP
2
PWR_VBAT
3D3V_AUX_S5 VDD SM4378NSKPC-TRG-GP
2
PWR_CHG_ACDET
65 BOM
4
G
1
PR4416
18K7R2F-GP
PC4419
SCD01U50V2KX-L-GP
S
S
S
1
084.04378.0037
3
2
1
+VCHGR BT+
32
31
30
29
28
27
26
25
1
PU4401 PL4401 PR4443
2
PR4435
10KR2F-L1-GP
PR4449
10KR2F-L1-GP
PR4450
100KR2F-L3-GP
PR4434
300KR2F-L-GP
PR4451
100KR2F-L3-GP
DY DY DY
CSIP
QPCP
ASGATE
BGATE
CSIN
CMSRC
QPCN
VBAT
2
PWR_CHG_PHASE 1 2 1 2
DY DY PC4452 PC4453
COIL-4D7UH-33-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
PC4464
SCD1U25V2KX-GP
PR4428 PC4431
68.4R71A.20H D01R3721F-GP-U
2
1
SCD22U25V3KX-GP
0R0603-PAD-1-GP-U DY
2
2
PR4474 1 24 PWR_CHG_BTST 1 2PWR_CHG_BTST1 1 2
ACIN BOOT
5
6
7
8
0R0402-PAD PG4428 PG4426
2
D
D
D
D
PR4470 ACOK_IN 1 2 PWR_CHG_ACOK 2 23 PWR_CHG_HIDRV PU4412
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
0R0402-PAD ACOK UGATE SM4378NSKPC-TRG-GP
1
1
1 2 PWR_CHG_SDA 3 22 PWR_CHG_PHASE
[24,43] PBAT_CHG_SMBDAT SDA PHASE 65 BOM
1 2 PWR_CHG_SCL 4 21 PWR_CHG_LODRV 4
PWR_CHG_SRN_R
[24,43] PBAT_CHG_SMBCLK
PWR_CHG_SRP_R
SCL ISL95521AHRZ-T-GP LGATE
S
S
S
0R0402-PAD H_PROCHOT# 5 20 PWR_CHG_REGN VDD
PROCHOT# 074.95521.0A73 VDDP PWR_CHG_REGN 084.04378.0037
3
2
1
PR4471 PR4438
PR4475 1 2 0R0402-PAD PWR_CHG_AMON 6 19 VDD 1 2 PR4481
[24] AD_IA AMON VDD 4D7R3F-L-GP 0R2J-2-GP BT+
PR4476 1 2 0R0402-PAD PWR_CHG_BMON 7 18 PWR_CHG_DCIN 2
[24] boost_mon BMON Use bom change to ISL88739
DCIN DY 1
1
(P/N: 074.88739.0073) PC4446 PC4445
8 17 PWR_CHG_NTC SC1U10V2KX-1GP SC1U10V2KX-1GP
[46] P_SYS PSYS NTC
2
1
1
PC4402 PC4403 PC4404
BATGONE
1
SC2K2P50V2KX-L-GP
SC2K2P50V2KX-L-GP
SC2K2P50V2KX-L-GP
PR4411
1KR2F-L1-GP
DY PR4456 PR4457
CCLIM
ACLIM
COMP
PROG
AD+
CSON
CSOP
DY 33 FSET
DY PR4410 2R2F-GP 0R0402-PAD-1-GP
GND
2
2
7K15R2F-L-GP PD4410
PR4437 1 PQ4416 PC4463
2
2
B 2R2F-GP SCD1U25V2KX-GP B
LTA024EUB-FS8-GP
2
9
10
11
12
13
14
15
16
PWR_CHG_NTC_1 1 2PWR_CHG_DCIN_R 3 1 2
84.00024.01K
R2
DY DY
R1
1
2
PC4435 2 PWR_CHG_DCIN_D
PWR_CHG_BATGONE
VDD SC1U50V3KX-GP PQ4415 PC4461 PC4462
1
PWR_CHG_COMP
PWR_CHG_PROG
DY PR4412 BAT54C-12-GP LMUN5212T1G-GP SC2K2P50V2KX-L-GP SC2K2P50V2KX-L-GP

PWR_CHG_FSET
1
NTC-220K-1-GP-U 75.00054.A7D 84.05212.B11
C PQ4416_1
1
PR4402 PR4401 B R1
[17,40,51] SIO_SLP_S4#
2
E
200KR2F-L-GP
200KR2F-L-GP
R2
PWR_CHG_SRP
2
CCLIM PWR_CHG_SRN
ACLIM
3D3V_AUX_S5 AD+
PR4407
100R2F-L3-GP SCD022U25V2KX-DLGP
CPU PROCHOT# Circuit

1
PR4406 0R0402-PAD
PR4404 PR4403
1
82K5R2F-GP
95K3R2F-GP
DY DY PR4431
2
PC4406
SC470P50V2KX-L-GP
DY PR4409 100KR2J-1-GP
1
1
PR4405
147KR2F-GP
100KR2F-L3-GP
2
2
PC4405
PR_2
2
PR4439 1 2 PBAT_PRES#
PBAT_PRES# [24,43,44]
1
1
Need fine tune 100KR2F-L3-GP
2
PR4414
1MR2J-1-GP
DY
1
PC4436
E PQ4409_E
SC10P50V2JN-L1-GP
2
3D3V_S5
Battery PROCHOT# Circuit
2
2
Change net name from BAT_IN# to PBAT_PRES# H_PROCHOT# [4,24,44,46]
1
2
by power team Edward 1/30
84.2N702.A3F
PR4472
100KR2F-L3-GP
DY PR4458
PD4404 0R0402-PAD 2nd = 84.DM601.03F
K A PD4404_A B PQ4409 3rd = 84.2N702.E3F
MMBT3906-7F-GP
PQ4406 4th = 84.2N702.F3F
2
1
RB551V30-GP 84.03906.P11
C
PD4404_K PQ4406_3 3 4
[24,43,44] PBAT_PRES#
2
A A
PR4459 PQ4409_C 2 1 PQ4406_2 2 5 PQ4406_5
0R0402-PAD PR4462
1
1 6
PC4439
SC1U10V2KX-1GP 10KR2F-L1-GP
PC4433 0R0402-PAD
1
SCD47U25V3KX-1GP
1
1
2N7002KDW-GP
2
<Core Design>
PR4455 DY PR4408
1
PQ4402 680KR2F-GP 0R2J-2-GP
PQ4406_6
G BP_G
PR4413
100KR2F-L3-GP
DCBATOUT
PR4415 Wistron Corporation
2
2
1 2 BP_D D
PWR_CHG_ACOK
[4,24,44,46] H_PROCHOT# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1
1
2
S
PR4453
0R0402-PAD PR4478
100KR2J-1-GP 3D3V_S5
Title
2N7002K-2-GP
84.2N702.J31 Charger
2
2
2ND = 84.2N702.031 Size Document Number Rev
3rd = 84.07002.I31 A2 A00
Vegas SKL/KBL-U
5 4 3 2 1
A B C D E
Main Func = 3D3V_5V
3D3V_AUX_S5
1
PR4501
4 0R2J-2-GP DY 4
2
PR4502
PR4530
0R0402-PAD
2 1 PWR_5V_EN1_R 1 2 PWR_5V_EN1 DCBATOUT
DY PWR_DCBATOUT_5V
0R2J-2-GP PG4520
1
2 1
PR4504
0R0402-PAD GAP-CLOSE-PWR
PG4536
PR4503 2 1
2
0R0402-PAD
1 2 PWR_3D3V_EN2 GAP-CLOSE-PWR
[40] 3V_5V_EN
PG4518
2 1
DCBATOUT PWR_DCBATOUT_3D3V GAP-CLOSE-PWR

PG4534
PG4525 2 1
2 1
GAP-CLOSE-PWR
GAP-CLOSE-PWR PG4542
PG4521 2 1
2 1
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4524 Change PU4503 from 074.06575.0A to 2
PG4543
1
2 1
74.51225.073 by power change 2/26 GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4531
2 1
GAP-CLOSE-PWR
PWR_DCBATOUT_3D3V DCBATOUT
3 3
PWR_DCBATOUT_5V
PC4509
SC4D7U25V5KX-L2-GP
PC4525
SCD1U50V3KX-GP
PC4528
SC10U25V5KX-L-GP
PC4519
SC10U25V5KX-L-GP
PC4531
SCD01U50V2KX-L-GP
1
1
1
DY
Design Current=3.5A
5.25A<OCP>6.3A
2
2
PC4530
SCD1U50V3KX-GP
PC4529
SC4D7U25V5KX-L2-GP
PC4527
SC10U25V5KX-L-GP
5
6
7
8
1
8
7
6
5
1
D
D
D
D
5V_S5
D
D
D
D
PU4504 PU4501 5V_PWR

AON7410-GP AON7410-GP PG4527
12
2
65 BOM 84.07410.A37 PU4503 84.07410.A37 2 1
65 BOM
VIN
PR4528
PC4535 Design Current=6.85A GAP-CLOSE-PWR
2 1PWR_3D3V_VBST2_1
1 2 PWR_3D3V_VBST2 PC4516
G
S
S
S
PG4519
S
S
S
G
3D3V_S5 3D3V_PWR 1D5R3-GP PR4524 10.275A<OCP>12.33A 2 1
4
3
2
1
1
2
3
4
PG4526 9 17 PWR_5V_VBST1 1 2 PWR_5V_VBST1_1 1 2

2 1 SCD1U50V3KX-GP VBST2 VBST1
1D5R3-GP GAP-CLOSE-PWR
3D3V_PWR PL4502 PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 SCD1U50V3KX-GP PL4501 5V_PWR PG4538
DRVH2 DRVH1 2 1
GAP-CLOSE-PWR
PG4517 1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2
2 1 SW2 SW1
GAP-CLOSE-PWR
1
IND-3D3UH-57-GP-U PWR_3D3V_DRVL2 11 15 PWR_5V_DRVL1 IND-2D2UH-46-GP-U1 PG4537

DRVL2 DRVL1
1
GAP-CLOSE-PWR 68.3R310.20A 68.2R210.20B 2 1
5
6
7
8
PG4528 PR4533 DY PR4529 PG4532 PC4518
8
7
6
5
D
D
D
D
14 PWR_5V_VO1
2 1 PC4517 PT4502 PG4535 2D2R5F-2-GP
VO1
PU4502 DY 2D2R5F-2-GP GAP-CLOSE-PWR
1
1
SCD1U16V2KX-3GP
D
D
D
D
GAP-CLOSE-PWR-3-GP
PU4505 AON7506-GP PG4533
2
1
PWR_3D3V_FB2 4 2 PWR_5V_FB1 2 1
SCD1U16V2KX-3GP
AON7410-GP
SE220U6D3VM-38-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR
VFB2 VFB1 65 BOM DY PT4501
2
PG4522 DY 65 BOM
PWR_3D3V_SNUB
SE220U6D3VM-38-GP
2
2
2
2 1 4 79.22710.3KL GAP-CLOSE-PWR
G
2
2
1PWR_5V_SNUB
S
S
S
PG4523
PR4517 change to 127K PWR_3D3V_EN2 6 20 PWR_5V_EN1 2 1
GAP-CLOSE-PWR 84.07506.037
S
S
S
G
EN2 EN1
3
2
1
PG4529 by PWR team Jerry
1
2
3
4
2 1 GAP-CLOSE-PWR
3V_FEEDBACK
PWR_3D3V_CS2 5 1 PWR_5V_CS1 PG4541

CS2 CS1 2 1
PC4520
SC330P50V2KX-3GP
GAP-CLOSE-PWR TP4501
1
1
1
DY TPS51225RUKR-GP
19
TPAD14-OP-GP
PWR_5V_VCLK 1
79.22710.3KL 84.07410.A37 PR4517
VCLK
PR4531 GAP-CLOSE-PWR
127KR2F-L-GP 74.51225.073 127KR2F-L-GP DY PC4536 PG4540
2
SC560P50V-GP 2 1
2
7 21
PGOOD GND
2
2
GAP-CLOSE-PWR
VREG3
VREG5
2 PG4545 2
2 1
1
1
PR4531 change to 127K GAP-CLOSE-PWR
3
13
PR4512 PR4535 by PWR team Jerry PR4525 PG4544
1
6K65R2F-GP 3D3V_PWR_2 2 1
DY0R2J-2-GP 3D3V_S5
5V_PWR_2 0R2J-2-GP DY
PR4527
PR4534 PWR_5V_FB1_R 15K4R2F-GP GAP-CLOSE-PWR
2
1 2
1 2
PWR_3D3V_FB2_R
100KR2J-1-GP
PC4523
2
1
DYSC18P50V2JN-1-GP PC4522 DY
DY PC4526 PC4524 SC18P50V2JN-1-GP
2
2
SC4D7U6D3V3KX-GP SC1U50V3KX-GP 20170810
2
5V output voltage modify

2
1
1
PR4523 PR4526
10KR2F-L1-GP 10KR2F-2-GP
[17,21,40,53,54] 3V_5V_POK
PH at Page17
2
2
3D3V_PWR_2 3D3V_AUX_S5
Close to VFB Pin (pin2)

1 2
Close to VFB Pin (pin5)
PR4505
0R0402-PAD
I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B
Inductor: CHIP IND 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL
O/P capCHIP CAP EL 220U 6.3V M6.3*4.4 /Chemi-con/ 18mOhm / 79.22710.3KL H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
1
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037
1
L/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
<Core Design>
Wistron Corporation
Title
DCDC-3D3V&5V
A2
Vegas SKL/KBL-U A00
A B C D E
5 4 3 2 1
Main Func = CPU_CORE

+VCCST_CPU
https://shop62935598.taobao.com
20170427
1
PR4606
PR4605
PR4604
PC4602
+VCCST_CPU SCD1U25V2KX-GP
2
1
1
1
1
DY
PR4603
DY 1KR2F-L1-GP
D D
2
2
2
2
PR4607 VR_SVID_CLK [7]
100R2F-L3-GP VR_SVID_ALERT# [7]
1 2
[4,24,44] H_PROCHOT# VR_SVID_DATA [7]
PR4608
1
45D3R2F-L-GP
75R2F-2-GP
100R2F-L3-GP
90K9R2F-GP PC4603
1 U42 2 SCD1U25V2KX-GP
2
PR4672
88K7R2F-GP DCBATOUT 5V_S5 PWR_VCCSA_ISUMN [50]
1 U22 2
1
1
1
PR4612
0R0402-PAD-1-GP
PR4610
1R2J-GP
PC4604 PR4611
SC330P50V2KX-3-DL-GP
1 2
3D3V_S0 PR4615 DY PR4613 NTC-10K-29-GP-U
DY 1KR2F-L1-GP 0R2J-L-GP
Place near high side MOSFET of Phase1 B=3370K
1
B=3940K
PR4624
PR4623
PR4622
20170810 20170810 Place near Phase1 choke
2
New Common Part IA VRHot PR4609 PR4618
2
PR4616 DY 10KR2F-L1-GP 11KR2F-L-GP
PWR_VCCSA_ISUMN_RC
1
5K76R2F-2-GP PC4605 PWR_VCCSA_ISUMN_P_1 PWR_VCCSA_ISUMN_P_2
1
1
1
PR4617 1 2 NTC-470K-9-GP-U PWR_VCCGT_NTC1 2 1 SCD068U25V2KX-GP
1
AFTP4601 1 VR_RDY
2
PR4621 1 2
PC4606
SCD22U25V3KX-GP
PC4607
SC1U10V2KX-1GP
27K4R2F-GP PR4620 PR4625
2
1 2
392R2F-GP DY PC4608
SCD033U25V2KX-GP
2K61R2F-1-GP
PC4610
2
2
2
SC33P50V2JN-3GP
[40] VR_EN
1
49D9R2F-L1-GP
0R0402-PAD-1-GP
10R2F-L1-GP
1
PC4651 2 1 SC1KP50V2KX-L-1-GP PR4626
3K3R2F-2-GP PWR_VCCSA_ISUMP [50]
PC4612 2 1 SC2K2P50V2KX-L-GP PWR_VCCGT_COMP1 1 2 PC4613
SCD01U50V2KX-L-GP
2
DY PC4611 1 2
0707 Modify by PWR Jerry SC2K2P50V2KX-L-GP
PWR_VCORE_VRHOT#
PWR_VCORE_ALERT#
PWR_VCORE_PROG1
PWR_VCORE_PROG2
1
1
1
PC4661 2U42 1 SC470P50V2KX-3GP PR4627 1 DY 2
PWR_VCORE_SCLK
PR4628 PR4629
PWR_VCORE_SDIO
PWR_VCORE_VCC
PWR_VCORE_VIN
9K31R2F-GP
88K7R2F-GP
PR4630 100R2F-L3-GP
2KR2F-L1-GP
PC4614 2U22 1 SC330P50V2KX-3GP PWR_VCCGT_FB1 1 2 0517 Modify PR4602 1 2 0R0402-PAD-1-GP
VSSSA_SENSE [7]
[44] P_SYS
2
1
1
C
DY PC4615 20170811 DY PC4616 C
SCD01U50V2KX-L-GP PR4671 1U22 2 1K54R2F-GP SA compensation SC1KP50V2KX-L-1-GP
PR4614 PR4632 PC4617
2
2
PR4633 1U42 2 3K01R2F-3-GP 1 DY 2 1KR2F-3-GP SC1KP50V2KX-L-1-GP
PR4631 1 DY 2 2 1 PWR_VCCSA_FB_RC 1 2 PWR_VCCSA_FB2 PR4601 1 2 0R0402-PAD-1-GP
40
39
38
37
36
35
34
33
32
31
VCC_CORE VCCSA_SENSE [7]
100R2F-L3-GP PR4636 0R2J-L-GP PU4601
PR4665 499R2F-2-GP
VR_READY
ALERT#
SDA
VR_ENABLE
VR_HOT#
SCLK
PROG1
PROG2
VCC
VIN
1
1 2 PWR_VCCGT_FB2 PC4618 1U22 2 PWR_VCCGT_FB_RC 1 2
[7] VCC_SENSE PR4637 DY PC4620
SC1KP50V2KX-L-1-GP 1K69R2F-2-GP SCD01U50V2KX-L-GP
0R0402-PAD-1-GP 1 30 1 2
PSYS PWM_C PWR_VCCSA_PWM [50]
2
1
PC4662 1U42 2 PWR_VCCGT_IMON 2 29

DY PC4619 PWR_VCCGT_NTC 3 IMON_B FCCM_C 28 PWR_VCCSA_ISUMNB PWR_VCCSA_FCCM [50]
SC1KP50V2KX-L-1-GP SC220P50V2KX-3GP
PR4666 PWR_VCCGT_COMP 4 NTC_B ISUMN_C 27 PWR_VCCSA_ISUMP PR4638 PC4621
COMP_B ISUMP_C
2
0R0402-PAD-1-GP 0707 Modify by PWR Jerry PWR_VCCGT_FB 5 26 PWR_VCCSA_RTN 2KR2F-L1-GP SC680P50V2KX-2GP

1 2 PWR_VCCGT_RTN 6 FB_B RTN_C 25 PWR_VCCSA_FB 2 DY 1 PWR_VCCSA_FB1 2 1
[7] VSS_SENSE PWR_VCCGT_ISUMP 7 RTN_B FB_C 24 PWR_VCCSA_COMP DY
PR4639 1 DY 2 PWR_VCCGT_ISUMNB 8 ISUMP_B COMP_C 23 PWR_VCCSA_IMON
PR4669 1 2 0R2J-L-GP PWR_VCCGT_ISEN1 9 ISUMN_B IMON_C 22
100R2F-L3-GP DY PWR_VCCGT_ISEN2 10 ISEN1_B PWM_A 21 PWR_VCORE_PWM [47]
PR4640 PC4601
2K49R2F-2-L-GP SC2200P50V2KX-2DLGP
ISEN2_B FCCM_A PWR_VCORE_FCCM# [47] PWR_VCCSA_COMP_RC 1
PC4622 2 1 1 2 2
ISUMN_A
ISUMP_A
PWM1_B
PWM2_B
COMP_A
FCCM_B
2
IMON_A
SCD01U50V2KX-L-GP PC4623 20170810
NTC_A
RTN_A
IA OCP 5V_S5 41
SC2K2P50V2KX-L-GP
20170811
FB_A
GND SA compensation PC4624 20170811
1
SA compensation
PC4625
SCD022U25V2KX-DLGP
PC4626
SCD022U25V2KX-DLGP
20170810 SC33P50V2JN-3GP
1
IA RC time constant PR4642 PR4670 PR4635 ISL95859AHRTZ-T-GP 1 2

PWR_VCCGT_ISUMN_RC
[48] PWR_VCCGT_ISUMP
11
12
13
14
15
16
17
18
19
20
1
1
324R2F-GP
267R2F-1-GP
1KR2F-L1-GP
U42 U42 074.95859.0B33

1
PC4609
SCD01U50V2KX-L-GP
PC4628
SCD033U25V2KX-GP
PC4653
SCD047U25V2KX-GP
U42 U22 U22 PC4629

1
PR4641 U22 U42 SC330P50V2KX-3-DL-GP

2
PWR_VCORE_ISUMNA
2K61R2F-1-GP 2 1
PWR_VCORE_ISUMP
2
PWR_VCORE_COMP
PWR_VCORE_IMON
PWR_VCORE_NTC
PWR_VCORE_RTN
2
PC4630
SCD1U25V2KX-GP
20170810
PWR_VCORE_FB
2
New Common Part

PR4643
11KR2F-L-GP
PR4644
PWR_VCCGT_ISUMN_P_2 1 2
2
20170810
1
GT OCP 113KR2F-1-GP
2
PWR_VCCGT_ISUMN_P_1
PR4645
1KR2F-L1-GP
PR4646
2
NTC-10K-29-GP-U PR4648 1 2 274R2F-GP PWR_VCORE_ISUMN [47]

PR4647
1
Place near Phase1 choke 0R0402-PAD-1-GP PR4649
2
1
B=3370K
0R0402-PAD-1-GP
PC4631 PR4650
B SCD1U25V2KX-GP NTC-10K-29-GP-U B
2
2
PC4632 PR4651 PR4652
[48] PWR_VCCGT_ISUMN
2
B=3370K
11KR2F-L-GP
SC2K2P50V2KX-L-GP 1KR2F-L1-GP
1
2 1PWR_VCORE_ISUMN_RC 1 2 Place near Phase1 choke
[48] PWR_VCCGT_FCCM#
1
PC4633
[48] PWR_VCCGT_PWMA
2
SCD1U25V2KX-GP PWR_VCORE_ISUMN_P_1 PWR_VCORE_ISUMN_P_2
[48] PWR_VCCGT_PWMB
1
2
PC4634
SCD1U25V2KX-GP
PC4652
SCD022U25V2KX-DLGP
PC4635
SCD022U25V2KX-DLGP
1
2
20170810 20170810 DY PR4653
GT VRHot GT compensation 2K61R2F-1-GP
2
1
PR4662 PR4656
[48] PWR_VCCGT_ISEN1
1
4K75R2F-1-GP
2K87R2F-1-GP
PR4658
1
499R2F-2-GP
PWR_VCORE_ISUMP [47]
1
PR4657 PC4637
[48] PWR_VCCGT_ISEN2
2KR2F-L1-GP
SCD01U50V2KX-L-GP 20170810
2
1 2 GT RC time constant
2
1
PC4639
PWR_VCORE_COMP1
PWR_VCORE_FB_RC
SC33P50V2JN-3GP
U22 U42
PWR_VCORE_FB1
2
20170810 PR4659 1 DY 2
GT load line 100R2F-L3-GP PR4668
1
PWR_VCORE_NTC1
PC4625 DY PC4625 0.022u(78.22321.2FL) PR4660 0R0402-PAD-1-GP
2 1
1K91R2F-1-GP
20170810
New Common Part VSSGT_SENSE [7]
1
PC4626 DY PC4626 0.022u(78.22321.2FL) PR4661

1
1
88K7R2F-GP
PR4654
NTC-470K-9-GP-U
PC4638 DY PC4642
2
1
PC4641 SC1KP50V2KX-L-1-GP
1
1
PR4669 DY PR4669 DY PC4640 PC4643 PR4667

PWR_VCORE_FB2
2
2
SC4700P50V2KX-1DLGP
SC1KP50V2KX-L-1-GP
0R0402-PAD-1-GP
2
2
2
PR4655 2 1
2
VCCGT_SENSE [7]
27K4R2F-GP
PR4635 1K(64.10015.6DL) PR4635 DY 20170810 20170811 20170810

2
GT IMON GT compensation New Common Part PR4663 1 DY 2

+VCCGT
PR4670 267(64.26705.6DL) PR4642 316(64.31605.6DL) 100R2F-L3-GP
1
PC4644 1 2 SCD01U50V2KX-L-GP
DY
PC4630 0.1u(78.10422.5FL) PC4630 0.1u(78.10422.5FL)
Place near high side MOSFET of Phase1
A
B=3940K A
PC4609 0.01u(78.10324.L0L) PC4628 0.022u(78.22322.2FL)
PC4653 DY PC4653 47n(78.47322.2FL)
1.54K(64.15415.6DL) PR4633 3.01K(64.30115.6DL) <Core Design>

PR4671
PR4672 88.7K(64.88725.6DL) PR4608 90.9K(64.90925.6DL) Wistron Corporation

PC4614 330p(78.33124.2FL) PC4661 470p(78.47124.2FL)
Title
PC4618 1000p(78.10224.2FL) PC4662 220p(78.22124.2FL) NCP81208MN_CPU_VCORE(1/3)

A2 Vegas SKL/KBL-R A00
5 4 3 2 1
5 4 3 2 1

20170427
DCBATOUT PW R_DCBATOUT_VCORE
PG4701
1 2
GAP-CLOSE-PWR-3-GP PW R_DCBATOUT_VCORE
D PG4702 D
1 2
PC4701
PC4702
PC4703
PC4704
GAP-CLOSE-PWR-3-GP
1
PG4703 DY DY
1 2
2
GAP-CLOSE-PWR-3-GP
PG4704
1 2
GAP-CLOSE-PWR-3-GP SC10U25V5KX-L-GP
PG4705 SC10U25V5KX-L-GP
1 2 SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
GAP-CLOSE-PWR-3-GP
PG4706
1 2
GAP-CLOSE-PWR-3-GP
PR4702
1 2
PW R_VCORE_PW M [46]
PR4706 0R0402-PAD
1 2
[46] PW R_VCORE_FCCM#
0R0402-PAD PW R_VCORE_BOOT_RC
5V_S5
1
C PR4704 C
1
2D2R2F-GP PR4712 PR4705 PC4707
1 2 5K11R2F-L1-GP 2D2R3F-L-GP SCD22U25V3KX-GP
2
PC4708
SC1U10V2KX-1GP
PU4701
2
1
PW R_VCORE_FCCM#_R 1 8 PW R_VCORE_PW M_R SKL_U22_15W

SKIP# PWM
PW R_VCORE_VCC_R 2
VDD BOOT
7 PW R_VCORE_BOOT Icc(max)=29A
2
3 6 PW R_VCORE_BOOTR
PW R_VCORE_SW 4 PGND
VSW
BOOT_R
VIN
5 PW R_DCBATOUT_VCORE
TDC=21A
9
PGND
Confirm with EE
CSD97396Q4M-GP 22uF/0805 total 33pcs
074.97396.0043 (78.22610.L2L)
+VCCGT
PL4701
COIL-D15UH-2-GP
Cyntec. 6.8mm x6.4mmx4.0mm
DCR: 0.66m Ohm +/-7%
PW R_VCORE_SW 1 2 Idc : 26A , Isat : 52A
68.R1510.20A
1
PR4703
DY 2D2R6J-3-GP 2 PT4701
1
SE330U2VDM-4-GP
PG4707 PG4708 PANASONIC
2
B GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP B
ESR: 9 mohm
2
PW R_VCORE_SNB
1
1
1
DY PC4706 PW R_VCORE_ISUMP_G PW R_VCORE_ISUMN_G

SC1KP50V2KX-L-1-GP
2
1
PR4708 PR4701
3K65R2F-1-GP 0R0402-PAD
2
[46] PW R_VCORE_ISUMP 2
[46] PW R_VCORE_ISUMN
A <Core Design> A
Wistron Corporation
Title
NCP81382MN_CPU_VCORE(2/3)
5 4 3 2 1
5 4 3 2 1

20170427
DCBATOUT PWR_DCBATOUT_VCCGTA PWR_DCBATOUT_VCCGTA
PG4802 GAP-CLOSE-PWR-3-GP
2 1
PC4802
PC4803
PC4804
PC4805
1
1
DY DY
PG4803 GAP-CLOSE-PWR-3-GP DCBATOUT
2 1
2
D PG4804 GAP-CLOSE-PWR-3-GP D
1
2 1 SC10U25V5KX-L-GP PT4805 PT4806
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP SKL_U22_15W ST100U25VDM-1-GP SE33U25VM-11-GP
Icc(max)=31A
2
PG4805 GAP-CLOSE-PWR-3-GP SC10U25V5KX-L-GP
2 1
TDC=18A
0920 Change acoustic solution
PG4806 GAP-CLOSE-PWR-3-GP 1101 Change acoustic solution
2 1 Confirm with EE
PR4802 22uF/0805 total 36pcs
1 2
PWR_VCCGT_PWMA [46] (78.22610.L2L) For acoustic noice
PWR_VCCGT_PWMA_RA
0R0402-PAD
PR4806
1 2 PWR_VCCGT_BOOTA_RC
[46,48] PWR_VCCGT_FCCM#
1
0R0402-PAD
5V_S5
PR4817
5K11R2F-L1-GP
PR4804
2D2R3F-L-GP
1
PC4808
1
SCD22U25V3KX-GP VCC_CORE
PR4803 DCR: 0.66m Ohm +/-7%
Idc : 26A , Isat : 52A
2
2D2R2F-GP PU4801
PWR_VCCGT_FCCM#_RA 1 8 PL4801
SKIP# PWM
2
PWR_VCCGT_VCCDA 2 7 PWR_VCCGT_BOOTA COIL-D15UH-2-GP
3 VDD BOOT 6 PWR_VCCGT_BOOTRA
PWR_VCCGT_SWA 4 PGND BOOT_R 5 1 2
PC4809
SC1U10V2KX-1GP
VSW VIN PWR_DCBATOUT_VCCGTA
1
9
PGND 68.R1510.20A
2
1
CSD97396Q4M-GP DY PR4805
1
2D2R6J-3-GP PT4801
074.97396.0043
1
SE330U2VDM-4-GP
PG4808 PG4809 PANASONIC
2
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PWR_VCCGT_SNB1 ESR: 9 mohm
2
1
C
DY PC4810 C
SC1KP50V2KX-L-1-GP
PWR_VCCGT_ISUMP_GA PWR_VCCGT_ISUMN_GA
2
PR4821 1U42 2
[46,48] PWR_VCCGT_ISEN1 100KR2F-L3-GP
1
PR4809 DY PR4822
10R2F-L1-GP 100KR2F-L3-GP
PR4808 1 2
[46,48] PWR_VCCGT_ISUMP 3K65R2F-1-GP
2
[46,48] PWR_VCCGT_ISUMN
DCBATOUT PWR_DCBATOUT_VCCGTB [46,48] PWR_VCCGT_ISEN2

PWR_DCBATOUT_VCCGTB
2 1
1
PC4816 PC4817 PC4814 PC4815

PG4816 GAP-CLOSE-PWR-3-GP U42 U42 U42 U42
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
2 1
2
2 1
2 1
B 2 1 B
PR4811
1 2
PWR_VCCGT_PWMB [46]
0R0402-PAD
PWR_VCCGT_PWMB_RA
PR4812
1 2 0R0402-PAD PWR_VCCGT_BOOTB_RC
[46,48] PWR_VCCGT_FCCM#
1
1
5V_S5 PR4818 PR4810
1
5K11R2F-L1-GP 2D2R3F-L-GP U42 PC4811
1
VCC_CORE
U42 U42 SCD22U25V3KX-GP
PR4813
2D2R2F-GP
DCR: 0.66m Ohm +/-7%

2
2
U42 PU4802
Idc : 26A , Isat : 52A
PWR_VCCGT_FCCM#_RB 1 8 PL4802
SKIP# PWM
2
PWR_VCCGT_VCCDB 2 7 PWR_VCCGT_BOOTB COIL-D15UH-2-GP

3 VDD BOOT 6 PWR_VCCGT_BOOTRB
PWR_VCCGT_SWB 4 PGND BOOT_R 5 1 2
PC4812
SC1U10V2KX-1GP
VSW U42 VIN PWR_DCBATOUT_VCCGTB U42

1
U42 9
PGND
2
1
CSD97396Q4M-GP DY PR4814
074.97396.0043 2D2R6J-3-GP U42
1
PT4803
PG4813 PG4815 SE330U2VDM-4-GP
2
2
PWR_VCCGT_SNB2
2
1
DY PC4813
SC1KP50V2KX-L-1-GP
PWR_VCCGT_ISUMP_GB
2
PWR_VCCGT_ISUMN_GB
PR4823 1U42 2
[46,48] PWR_VCCGT_ISEN2 100KR2F-L3-GP
A A
1
PR4816 1U42 2
[46,48] PWR_VCCGT_ISUMP 3K65R2F-1-GP U42 PR4815 DY PR4824
10R2F-L1-GP 100KR2F-L3-GP
<Core Design>
2
[46,48] PWR_VCCGT_ISUMN Wistron Corporation
Title
[46,48] PWR_VCCGT_ISEN1
NCP81382MN_CPU_VCCGT(3/3)
5 4 3 2 1
5 4 3 2 1
20170427
DCBATOUT PW R_DCBATOUT_VCCSA
PG5002
GAP-CLOSE-PWR-3-GP
D 2 1 D
PG5003
GAP-CLOSE-PWR-3-GP
2 1
SKL_U22_15W
PW R_DCBATOUT_VCCSA
Icc(max)=4.5A
TDC=3.7A
Confirm with EE
1
PC5002 DY PC5003 PC5004
22uF/0805 total 6pcs
SC10U25V5KX-L-GP
SC10U25V5KX-L-GP
SCD1U25V2KX-GP
(78.22610.L2L)
2
5
6
7
8
PU5002
D
D
D
D
AON7410-GP
PW R_VCCSA_BST_RC
C C
Cyntec. 7.3mm x6.8mm x3.0mm
G
S
S
S
1
1 PC5005
DCR: 4.0~4.2 mohm
4
3
2
1
PR5001 SCD22U25V3KX-GP
2D2R3F-L-GP Idc : 17.5A , Isat : 26A
2
PL5001 +VCCSA
PU5001
2
PW R_VCCSA_DRVH 1 8 PW R_VCCSA_SW 1 2
PW R_VCCSA_BST 2 UGATE PHASE 7 IND-D47UH-22-GP-U
BOOT FCCM PW R_VCCSA_FCCM [46]
3 6 5V_S5
[46] PW R_VCCSA_PW M PWM VCC
4 5
GND LGATE
5
6
7
8
9 PU5003
GND
1
D
D
D
D
PC5001 AON7410-GP
SC2D2U10V3KX-L-GP
2
ISL95808HRZ-T-1-GP PG5011 PG5001
2
074.95808.0B73
G
S
S
S
1
4
3
2
1
If no need support PS4 mode
PWR_VCCSA_ISUMP_R
PWR_VCCSA_ISUMN_R
PW R_VCCSA_DRVL
please change to ISL6208C
74.06208.B73
B B
1
PR5003
3K65R2F-1-GP PR5004
0R0402-PAD
2
[46] PW R_VCCSA_ISUMP
[46] PW R_VCCSA_ISUMN
A <Core Design> A
Wistron Corporation
Title
NCP81253MN_CPU_VCCSA
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p2v& 2D5V
DCBATOUT PWR_DCBATOUT_VDDQ VID

PG5117 Logic-High = 0.75V
GAP-CLOSE-PWR-3-GP Logic-Low = 0.6V
1 2
PR5107
5D1R2F-GP
D PG5118 PWR_VDDQ_VID 1 2 D
5V_S5
GAP-CLOSE-PWR-3-GP
1
1 2 PC5102
SC1U10V2KX-1GP PWR_1D2V 1D2V_S3
PWR_DCBATOUT_VDDQ PG5119
2
GAP-CLOSE-PWR-3-GP
1 2
0620 Change Res value
by PWR team Jerry
OCP setting PR5109 PG5120
1
PWR_VDDQ_CS PWR_VDDQ_VDD
0R0402-PAD-1-GP
1 2
DY PC5103 PC5104 PC5105 GAP-CLOSE-PWR-3-GP
1 2
SC4D7U25V5KX-L2-GP
SC4D7U25V5KX-L2-GP
SCD1U25V2KX-GP
5V_S5
2
1
3D3V_S5
1
PR5114 PC5107 PG5121
5
6
7
8
255KR2F-GP SC1U10V2KX-1GP GAP-CLOSE-PWR-3-GP
D
D
D
D
1
PR5111 PU5102 1 2
2
DY 10KR2F-L1-GP AON7410-GP
2
84.07410.A37
65 BOM PG5122
GAP-CLOSE-PWR-3-GP
2
PU5101 1 2
G
S
S
S
RT8231AGQW-GP
13
11
12
[40] PWR_VDDQ_PG
4
3
2
1
074.08231.0073
PR5112 PC5108 PG5123
CS
VID
VDD
PWR_DCBATOUT_VDDQ
Freq. setting 18 PWR_VDDQ_BOOT
2D2R3F-L-GP
1 2 PWR_VDDQ_BOOT_A
SCD1U50V3KX-GP
1 2
GAP-CLOSE-PWR-3-GP
1 2
PWR_VDDQ_PG 10 BOOT
750K -> 350K Hz PR5113
750KR2F-L-GP PGOOD DCR=5~5.5mohm
1 2 PWR_VDDQ_TON 9 17 PWR_VDDQ_HG IDC=15.5A, Isat=25A PG5124
TON UGATE PL5101 GAP-CLOSE-PWR-3-GP
PWR_VDDQ_EN 8 1 2
S5
COIL-D68UH-5-GP-U Design Current=6.9A PWR_1D2V
PG5115 PWR_VTT_EN 7 16 PWR_VDDQ_PH 1 2 10.4A<OCP>13.8A

GAP-CLOSE-PWR-3-GP S3 PHASE PG5127
1 2 PWR_VDDQ_VLDOIN 19 GAP-CLOSE-PWR-3-GP
1D2V_S3 VLDOIN
1
PC5110 PC5111 PC5112 PC5113 PC5114 1 2
1
1
1
1
15 PWR_VDDQ_LG
PC5109
LGATE
PR5120 DY
PG5116 SC10U6D3V3MX-GP Close to output cap pin1, not DY 2D2R5F-2-GP
5
6
7
8
GAP-CLOSE-PWR-3-GP PG5125
inside of the output cap
2
2
2
2
D
D
D
D
1 2 PU5105 GAP-CLOSE-PWR-3-GP
2
C 1 14 AON7506-GP 1 2 C
VTTGND PGND PG5101 PWR_VDDQ_SNUB
PWR_VDDQ_VTT GAP-CLOSE-PWR-3-GP 65 BOM
1
5 PWR_VDDQ_VDDQ 1 2 4 DY PC5120 PG5126
G
2D5V_PWROK PWR_VDDQ_EN VDDQ PWR_1D2V
PR5128 1 2 0R0402-PAD SC2200P50V2KX-2GP SC22U6D3V3MX-1-DL-GP 20170810 GAP-CLOSE-PWR-3-GP
S
S
S
20 6 PWR_VDDQ_FB SC22U6D3V3MX-1-DL-GP New Common Part 1 2
VTT FB 84.07506.037
3
2
1
2
1
DY PC5106 2
SCD1U16V2KX-3GP SC22U6D3V3MX-1-DL-GP
VTTSNS
VTTREF
R1 DY SC22U6D3V3MX-1-DL-GP PG5128
2
S5
GAP-CLOSE-PWR-3-GP
GND
GND
1
PC5115 1 2
PR5116 SC18P50V2JN-1-GP
15K8R2F-GP
21
2
PG5129
GAP-CLOSE-PWR-3-GP
2
1 2
PWR_VDDQ_VTTREF
PR5116 from 12.1Kohm change to 15.8Kohm(64.15825.6DL) to setting VDDQ =1.2V
PR5126 1 2 0R2J-2-GP PWR_VTT_EN Due to pin 11 VID is pull high, Vref. should be 0.675V
[17,24,27,40] SIO_SLP_S3# DY by power team Edward 1/30 PG5130
PR5127 1 2 0R0402-PAD GAP-CLOSE-PWR-3-GP
[5] SM_PGCNTL_R
1 2
R2
S3
1
PR5117
20KR2F-L3-GP
Vout Setting
Vout = Vref * ( 1 + R1/R2 )
2
1
PC5116 = 0.675 * ( 1 + 12.1K / 20K)

= 1.2V
2
VID vs Vref Table

VID Logic-High => Vref = 0.675 V
VID Logic-Low => Vref = 0.75 V
Vout = 0.6V note. Vref can only be changed form
Iomax = 1.2A 0.675v to 0.75v after power-on
B B
PWR_VDDQ_VTT PG5113 0D6V_S0
GAP-CLOSE-PWR-3-GP
2 1
PG5114
PC5118
SC10U6D3V3MX-GP
PC5117
SC10U6D3V3MX-GP
GAP-CLOSE-PWR-3-GP
1
DY 2 1
2
APL5930 for VPP_2D5V
5V_S5 3D3V_S5
Design Current = 700mA

3D3V_S5
PC5152
SC10U6D3V3MX-GP
1
1
1
PC5156
PR5155 SC1U50V3KX-GP 2D5V_PWR
2
10KR2F-L1-GP 2D5V_PWR 2D5V_S3

PU5151
EE needs check sequence control
2
5 PG5151 1 2 GAP-CLOSE-PWR
6 VIN#5 4
2D5V_PWROK PR5158 1 2 0R0402-PAD PWR_2D5V_POK 7 VCNTL VOUT#4 3 PG5152 1 2 GAP-CLOSE-PWR
POK VOUT#3
1
1 2 0R0402-PAD PWR_2D5V_EN 8 2
PC5153
SC68P50V2JN-1GP
PC5154
PR5153 20170810
[17,40,44] SIO_SLP_S4# EN FB
1
9 1 New Common Part

PR5151
43K2R2F-L-GP
DY
PWR_2D5V_FB
VIN#9 GND
SC4700P50V2KX-1GP
2
1
APL5930KAI-TRG-GP
2
DY
PC5155
A A
PR5152
47KR2J-2-GP
DY 74.05930.03D
2ND = 74.G9731.03D
2
2
PR5154
20KR2F-L3-GP <Core Design>
SCD047U25V2KX-GP
Vout=0.8V*(R1+R2)/R2 Wistron Corporation

2

Title
RT8231_VDDQ/VTT
A2 Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p0v
D D
DCBATOUT PW R_DCBATOUT_1D0V
PG5301
GAP-CLOSE-PWR-3-GP
1
PG5302
2 AOZ2262 for 1D0V PW R_1D0V 1D0V_S5
GAP-CLOSE-PWR-3-GP 5V_S5 PG5304
1 2 GAP-CLOSE-PWR-3-GP
1 2
PG5303 DCR=5~5.5mohm
PC5302
SC4D7U25V5KX-L2-GP
GAP-CLOSE-PWR-3-GP PG5305
IDC=15.5A, Isat=25A
1
PL5301 1 2
PU5301 COIL-1UH-34-GP-U1 PW R_1D0V
2
design current : 8.92A PG5306

C 21 18 PW R_1D0V_PH 1 2 GAP-CLOSE-PWR-3-GP C
VCC LX#18 17 1 2
LX#17 68.1R01A.20B
1
PW R_DCBATOUT_1D0V 16
PC5301
PC5303
PC5305
PC5307
PC5306
PC5304
LX#16
1
11 SCD1U25V2KX-GP DY PG5307
LX#11
2
IN#7 LX#10
2
8 DY PR5309 PG5310 1 2
IN#8
2
9 20 PW R_1D0V_BT 2D2R5F-2-GP
PC5308
SCD1U25V2KX-GP
PC5309
SC10U25V5KX-L-GP
PC5310
SC10U25V5KX-L-GP
IN#9 BST GAP-CLOSE-PW R-3-GP

1
PR5301 PG5308
1
95K3R2F-GP 5 PW R_1D0V_VFB GAP-CLOSE-PWR-3-GP
FB
2
1 2 PW R_1D0V_TON 6 1 2
TON
2
PW R_1D0V_SNUB PW R_1D0V_VFB_A SC22U6D3V3MX-1-DL-GP 20170810

PW R_1D0V_PG 1 4 SC22U6D3V3MX-1-DL-GP New Common Part PG5309
PGOOD AGND
PC5312
SC220P50V2KX-3GP
DY PC5315 SC22U6D3V3MX-1-DL-GP GAP-CLOSE-PWR-3-GP
1
PW R_1D0V_EN 2 19 1 2
PR5302
2K55R2F-GP
SC2200P50V2KX-2GP SC22U6D3V3MX-1-DL-GP
EN PGND
1
14 DY SC22U6D3V3MX-1-DL-GP
PGND
2
PW R_1D0V_PFM 3 13
PFM# PGND
PGND
12 R1 PG5311
GAP-CLOSE-PWR-3-GP
2
PW R_1D0V_SS 22 15 1 2
SS PGND
2
1
PG5312
1
PR5304
10KR2F-L1-GP
PR5303 AOZ2262QI-10-GP-U GAP-CLOSE-PWR-3-GP
1
1 2
100KR2F-L3-GP PC5313
SCD01U50V2KX-L-GP
074.02262.0043 Vo=0.8x(1+R1/R2) R2
=0.8x(1+7.5/30) PG5313
=1.00
2
GAP-CLOSE-PWR-3-GP
2
1 2
5V_S5
PG5314
GAP-CLOSE-PWR-3-GP
B B
1
1 2
DY PR5308
100KR2J-1-GP
2
PR5305 1 2 PW R_1D0V_PG
[40] 1D0V_S5_PW RGD
0R0402-PAD
PR5306 1 2 PW R_1D0V_EN
[17,21,40,45,54] 3V_5V_POK
0R0402-PAD
1
PC5314
SC1KP50V2KX-L-1-GP
2
A <Core Design> A
Wistron Corporation
Title
AOZ2262QI_1D0V
Custom Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = 1D8V
D D
APL5930 for 1D8V_S5 1D8V_PWR 1D8V_S5

PG5405
1 2
GAP-CLOSE-PWR
PG5406
1 2
GAP-CLOSE-PWR
PG5407
1 2
5V_S5 3D3V_S5
GAP-CLOSE-PWR
3D3V_S5
C C
PC5403
SC10U6D3V3MX-GP
PC5401
1
SC1U10V2KX-1GP
1
PR5402
100KR2F-L3-GP
DY
2
PH at Page40 PU5401
1D8V_PWR
2
5 Design Current = 1.1A
0511 Follow KY15. 6 VIN#5 4
PR5408 1 2 0R0402-PAD PWR_1D8V_POK 7 VCNTL VOUT#4 3
[24,40] PRIM_PWRGD POK VOUT#3
PWR_1D8V_EN 8 2
EN FB
1
9 1
PR5403
16K5R2F-2-GP
PC5405
SC68P50V2JN-1GP
PC5402
PC5404
1.8V_RUN_FB
VIN#9 GND
1
20170810
1 PR5406 2
DY DY New Common Part
PC5406
SC4700P50V2KX-1GP
[17,21,40,45,53] 3V_5V_POK
1
1
PR5401
47KR2J-2-GP
0R0402-PAD DY APL5930KAI-TRG-GP
2
DY 74.05930.03D
2
2
[#544669 Rev0.53] 2ND = 74.G9731.03D
2
B B
1
PR5404 SC22U6D3V3MX-1-DL-GP
13KR2F-GP
Vout=0.8V*(R1+R2)/R2
2
<Core Design>
Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Title
LDO-V1D5V&V1D8V
A4 Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = LCD LCDVDD_LCD LCDVDD INVERTER POWER Main Func = CAMERA
R5523
1 2 DCBATOUT DCBATOUT_LCD
LCD1 0R5J-5-GP EE note: Never change R5229 to short pad after MP
43 EE note: Never change R5211 to short pad after MP
F5503 800mA Reserved for one time fuse: 69.43001.201
41 1 2
1 3D3V_S0 3D3V_CAMERA_S0
C5535
SCD1U50V3KX-GP
C5515
SC1KP50V2KX-L-1-GP
DCBATOUT_LCD POLYSW-1D1A24V-GP-U
1
DBC_EN_R R5518 1 2
2 LCDVDD_LCD DBC_PANEL_EN [20] DY
100R2J-L-GP R5532 1 2
3 69.50007.A31 0R5J-5-GP
2
4 Trace width = 80mil
EC5503
SC33P50V2JN-3GP
C5539
SC4D7U6D3V3KX-GP
1
1
5 0517 Change PH power rate DY
D 6 CAMERA_DET#_R R5501 1 2 D
C5538
SC10U6D3V3MX-GP
C5536
SC1U10V2KX-1GP
CAMERA_DET# [20]
1
7 0R0402-PAD-2-GP 1D8V_S5
2
8 DBC_EN_R
9 EDP_HPD_CONN
1
10 LCD_TST_C add for camera detect pin 1/25
11 eDP_AUX_CON_P LCD R5521
12 eDP_AUX_CON_N 10KR2J-L-GP
13
14 eDP_TX_CON_N0 For ESD R5533 1 DY 2
2
15 eDP_TX_CON_P0 0R2J-L-GP
16 PANEL_SIZE_ID_CONN R5525 1 DY 2 PANEL_SIZE_ID
eDP_TX_CON_N1 PANEL_SIZE_ID [20]
17 100R2J-L-GP
18 eDP_TX_CON_P1 For AUDIO Grade B or C selection. EL5507
1
19 USB_CAMERA_PN4 1 2
20 LCD_BRIGHTNESS USB_CPU_PN4 [16]
21 BLON_OUT_C
DY R5526 USB_CAMERA_PP4 4 3
0R2J-2-GP
22
23
PANEL_SIZE_ID_CONN PU/PD FOR AUX CHANNEL USB_CPU_PP4 [16]
COIL-90OHM-100MHZ-5-GP
2
24 SKL PDG (#543016): 68.00396.001
25 Recommends having a pull-up resistor of 100 kΩ for AUXN
26 MIC_GND and a pull-down resistor of 100 kΩ for AUXP R5534 1 DY 2
27 DMIC_CLK_EDP
28 DMIC_DATA_EDP Camera between the AC capacitor and the connector,
to assist source detection by the sink device.
0R2J-L-GP
29
30 USB_CAMERA_PN4
31 USB_CAMERA_PP4 DMIC_DATA_EDP R5502 1 2 100R2J-L-GP
eDP_AUX_CON_P DMIC_CLK_EDP R5503 1 DMIC_DATA [27]
32 3D3V_CAMERA_S0 R5528 1 DY 2 100KR2J-1-GP 2 100R2J-L-GP DMIC_CLK [27]
33 CAMERA_DET#_R
34 USB_CON_PN7 eDP_AUX_CON_N R5529 1 2 100KR2J-1-GP
EC5501
SC22P50V2JN-4GP
EC5502
SC22P50V2JN-4GP
DY 3D3V_S0
1
35 USB_CON_PP7
36 Touch Panel DY
37 TP_RS
2
38 TP_RESET
39 RN5502
C 40 1 8 BKLT_CTRL C
TPAN_VDD BLON_OUT_C
2 7
42 3 6 EDP_HPD
4 5
44 R5524 1 DY 2 0R2J-2-GP
Layout Note:
IPEX-CON40-3-GP Colse to LCD1. SRN100KJ-5-GP
20.F2406.040 R5531 RN5501 D5503
2nd = 20.F1407.040 1 2 SRN100J-3-GP 1 eDP_BKLT_CTRL
LCD_TST_C 1 4
LCD_BRIGHTNESS 2 3 BKLT_CTRL LCD_TST_R [24] 3
0R0402-PAD
MIC_GND
BLON_OUT_C 1 4 2
EDP_HPD_CONN 2 3 BLON_OUT [24] EC_BRIGHTNESS [24]
EDP_HPD [8]
RN5503
BAT54C-12-GP EC (BIST MODE)
75.00054.A7D
SRN100J-3-GP
LCD_BRIGHTNESS
[8] eDP_TX_CPU_N0 C5508 1 2 SCD1U16V2KX-3GP eDP_TX_CON_N0

3D3V_S0 5V_S0
Main Func = Touch panel
C5532 1 2 SCD1U16V2KX-3GP eDP_TX_CON_P0
[8] eDP_TX_CPU_P0
1
Touch Panel
R5522
0R3J-L1-GP
DY R5527 ED5501
0R0603-PAD-2-GP-U TPAN_VDD
C5534 1 2 SCD1U16V2KX-3GP eDP_TX_CON_N1 USB_CON_PN7 1 6 USB_CON_PP7
[8] eDP_TX_CPU_N1
1 2 SCD1U16V2KX-3GP eDP_TX_CON_P1
69.50007.A31 I/O1 I/O4
[8] eDP_TX_CPU_P1 C5537
2
1
F5502 1 2 POLYSW-1D1A24V-GP-U TP_RS R5537 1 2 2 5

DY EC5504 DY TOUCH_PANEL_INTR# [4,24] GND DYVDD TPAN_VDD
SC22P50V2JN-4GP 0R0402-PAD-2-GP
1
TPAN_VDD_F R5520 1 2 0R0603-PAD-2-GP-U 3 4
DY C5541 I/O2 I/O3
2
1
1 2 SCD1U16V2KX-3GP eDP_AUX_CON_N
C5543
SC2D2U10V3KX-L-GP
[8] eDP_AUX_CPU_N C5533 SC10P50V2JN-L1-GP DY C5501
1
C5531 1 2 SCD1U16V2KX-3GP eDP_AUX_CON_P SCD1U16V2KX-3GP
[8] eDP_AUX_CPU_P DY
2
B EE note: Never change R5232 to short pad after MP B
AZC099-04S-2-GP
2
Reserved for one time fuse: 69.43001.201
Brightness 075.09904.0A7C
2
R5530 1 2 0R0402-PAD eDP_BKLT_CTRL
[8] L_BKLT_CTRL TP_RESET R5538 1 2
PLT_RST# [17,31,61,63,76,91]
0R0402-PAD-2-GP
1
DY C5540
SC10P50V2JN-L1-GP
2
LCDVDD D5502
1
[8] EDP_VDD_EN
3 LCDVDD_EN
1
2 USB_CON_PN7 R5535 1 2 0R0402-PAD-2-GP

[24] LCD_VCC_TEST_EN USB_CPU_PN7 [16]
R5506
BAT54C-12-GP 100KR2J-1-GP USB_CON_PP7 R5536 1 2 0R0402-PAD-2-GP
USB_CPU_PP7 [16]
3D3V_S0
75.00054.A7D U5501
2
1 5
2 EN VIN#5
3 GND 4
LCDVDD VOUT VIN#4
C5506
SC22U6D3V3MX-1-GP
C5505
SC4D7U6D3V3KX-GP
1
Layout Note: RT9724GB-GP
Trace width = 80mil 74.09724.09F

2
A A
<Core Design>
Wistron Corporation
Title
LCD&CAM&DMC&Touch
Custom
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = CRT 5V_CRT_S0_R
5V_HDMI_S0 5V_CRT_S0_R
D5604
A K
For EMI R2 SPEC Reserved
5V_CRT_S0_R CRT Connector Vegas
4
3
C5623 VGA1 RB551V30-GP
CRT_G
CRT_R
CRT_B
SCD01U16V2KX-3GP 83.R5003.H8H RN5601 Vegas
1DY 2 9 4 SRN2K2J-1-GP
VCC_CRT NC#4 11
NC#11
1
D D
DY ED5603 DY ED5602 DY ED5601
1
2
CRT_DDCDATA_CON 12 CRT_DDCDATA_CON
CRT_DDCCLK_CON 15 DDCDATA_ID1
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
DDCCLK_ID3 5 CRT_DDCCLK_CON
CRT_R 1 GND 6
CRT_G 2 CRT_RED Vegas GND 7 CRT_DDCCLK_CON_R R5602 1 2 0R0402-PAD CRT_DDCCLK_CON
CRT_GREEN GND
2
CRT_B 3 8 CRT_DDCDATA_CON_R R5603 1 2 0R0402-PAD CRT_DDCDATA_CON
CRT_BLUE GND 10
CRT_VSYNC_CON 14 GND 16 DP_CRT_HSYNC_CON R5612 1 2 47R2J-2-GP CRT_HSYNC_CON
CRT_HSYNC_CON 13 VSYNC GND 17 DP_CRT_VSYNC_CON R5611
Vegas
1 2 47R2J-2-GP CRT_VSYNC_CON
HSYNC GND Vegas
CRT_PCH_HPD R5605 1 2 0R0402-PAD 83.05725.0A0 83.05725.0A0
CPU_DP2_HPD [8]
D-SUB-15-297-GP 83.05725.0A0
020.20067.0015
2nd = 20.20975.015
CRT_HSYNC_CON
CRT_VSYNC_CON
DP_CRT_R EL5601 1Vegas 2 CRT_R CRT_DDCDATA_CON
BLM18BB470SN1D-GP CRT_DDCCLK_CON
DP_CRT_G EL5603 1Vegas 2 CRT_G
C5617
C5616
C5622
C5607
3D3V_S0 VDD_DAC_33
1
BLM18BB470SN1D-GP DY DY DY DY
C C
DP_CRT_B EL5602 1Vegas 2 CRT_B R5609 1 2
2
BLM18BB470SN1D-GP 0R0603-PAD-2-GP-U
1
1
Vegas C5615
SC10U6D3V3MX-GP
R5607
R5608
R5606
C5612
C5611
C5613
C5619
C5614
C5618
1
2
Vegas Vegas Vegas Vegas Vegas Vegas
2
2
Vegas Vegas Vegas SC18P50V2JN-1-GP SC100P50V2JN-3GP
SC18P50V2JN-1-GP SC100P50V2JN-3GP
3D3V_S0 AVCC33
75R2F-2-GP
SC15P50V2JN-2-GP SC15P50V2JN-2-GP 5V_CRT_S0_R 1 R5610 1 2
CRT_VSYNC_CON AFTP5604 AFTE14P-GP
75R2F-2-GP
SC15P50V2JN-2-GP SC15P50V2JN-2-GP 1 0R0603-PAD-2-GP-U
AFTP5602 AFTE14P-GP
2
75R2F-2-GP
SC15P50V2JN-2-GP SC15P50V2JN-2-GP CRT_HSYNC_CON 1
Layout note: Layout note: CRT_DDCDATA_CON 1
AFTP5603 AFTE14P-GP Vegas C5621
SC10U6D3V3MX-GP
R5607, R5608, R5606 need to close U5601 C5611 & C5612 & C5613 & C5614 & C5618 & C5619 & L5601 & L5602 & L5603 CRT_DDCCLK_CON AFTP5609 AFTE14P-GP
1
AFTP5608 AFTE14P-GP
1
Trace length not over 300 mil need to close connect CRT_R 1
CRT_G AFTP5605 AFTE14P-GP
1
CRT_B AFTP5607 AFTE14P-GP
1
AFTP5606 AFTE14P-GP
U5601
3D3V_S0 5V_S0
B SCD1U16V2KX-3GP 2
Vegas 1 C5620 VCCK_12 4 Vegas 2 PCH_DPC_AUXP_U SCD1U16V2KX-3GP 2Vegas
1 C5624 B
AVCC_12 AUX_P PCH_DPC_AUXN_U PCH_DPC_AUXP [8]
3 SCD1U16V2KX-3GP 2Vegas
1 C5625
AUX_N PCH_DPC_AUXN [8]
1
SCD1U16V2KX-3GP 2
Vegas 1 C5609 VCCK_12 25
SC2D2U10V3KX-L-GP
2 1 C5608 VCCK_12 5 PCH_DPC_P0_U SCD1U16V2KX-3GP 2Vegas
1 C5601
R5613
4K7R2J-2-GP
Vegas
C5629
SC4D7P50V2BN-GP
Vegas
C5602
SCD1U16V2KX-3GP
Vegas LANE0_P PCH_DPC_P0 [8]
1
PCH_DPC_N0_U
DY Vegas 1 C5606 AVCC33
SCD1U16V2KX-3GP 2 1
AVCC_33 LANE0_N
6
7 PCH_DPC_P1_U
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2Vegas
1 C5605
2Vegas
1 C5603
PCH_DPC_N0 [8]
LANE1_P PCH_DPC_P1 [8]
SCD1U16V2KX-3GP 2
Vegas 1 C5626 3D3V_S0 14 8 PCH_DPC_N1_U SCD1U16V2KX-3GP 2Vegas
1 C5604 PCH_DPC_N1 [8]
VCC_33 LANE1_N
2
2
SCD1U16V2KX-3GP 2
Vegas 1 C5627 VDD_DAC_33 20 17
SPI_CLK_CRT
VDD_DAC_33 HVSYNC_PWR 5V_S0

SC10U6D3V3MX-GP 2 1 C5628 19 DP_CRT_HSYNC_CON
Vegas HSYNC
Vegas 1 C5610 3D3V_S0
SCD1U16V2KX-3GP 2 26
PVCC_33 VSYNC
18 DP_CRT_VSYNC_CON 0523 Follow vendor suggest.
21 DP_CRT_B
CRT_DDCCLK_CON_R 15 BLUE_P 22 DP_CRT_G
CRT_DDCDATA_CON_R 16 VGA_SCL GREEN_P 23 DP_CRT_R Layout note:
VGA_SDA RED_P
close to pin17
30 27
[12,13,18,65,67] PCH_SMBCLK SMB_SCL LDO_RSTB EXT_CLK_IN_CRT
29 28
[12,13,18,65,67] PCH_SMBDATA SMB_SDA EXT_CLK_IN 31
RN5603 SPI_CLK_CRT 11 EXT1.2V_CTRL 32 CRT_PCH_HPD
GPI1/SPI_CLK HPD
1
1 4 SPI_SI_CRT 12
3D3V_S0 GPI2/SPI_SI
2 3 SPI_SO_CRT 13
R5616
4K7R2J-2-GP
DY GPI3/SPI_SO 24 <Core Design>

GND DY
2 3 POL1/SPI_CEB 10 33
1 Vegas 4 POL2 9 POL1/SPI_CEB GND
A 3D3V_S0 A
POL2
Wistron Corporation
2
RN5602
SRN4K7J-8-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SRN4K7J-8-GP RTD2166-CGT-GP Taipei Hsien 221, Taiwan, R.O.C.
071.02166.0003 Title
CRT
Custom
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = HDMI
HDMI_CLK_R ER5706 1 2 HDMI_CLK_R_C HDMI_DATA1_R ER5705 1 2 HDMI_DATA1_R_C

C5701 1 2 SCD1U16V2KX-3GP HDMI_CLK#_R 0R0402-PAD-2-GP 0R0402-PAD-2-GP
[8] HDMI_CLK#
1
C5704 1 2 SCD1U16V2KX-3GP HDMI_CLK_R
[8] HDMI_CLK R5702 R5708
C5705 1 2 SCD1U16V2KX-3GP HDMI_DATA0#_R 150R2J-L1-GP-U 150R2J-L1-GP-U
[8] HDMI_DATA0# C5703 1 2 SCD1U16V2KX-3GP HDMI_DATA0_R
D D
[8] HDMI_DATA0
2
HDMI_CLK#_R ER5714 1 2 HDMI_CLK#_R_C HDMI_DATA1#_R ER5704 1 2 HDMI_DATA1#_R_C
0R0402-PAD-2-GP 0R0402-PAD-2-GP
C5707 1 2 SCD1U16V2KX-3GP HDMI_DATA1#_R

[8] HDMI_DATA1# C5706 1 2 SCD1U16V2KX-3GP HDMI_DATA1_R
[8] HDMI_DATA1
C5708 1 2 SCD1U16V2KX-3GP HDMI_DATA2#_R
[8] HDMI_DATA2# C5709 1 2 SCD1U16V2KX-3GP HDMI_DATA2_R HDMI_DATA0_R ER5713 1 2 HDMI_DATA0_R_C HDMI_DATA2_R ER5717 1 2 HDMI_DATA2_R_C
[8] HDMI_DATA2 0R0402-PAD-2-GP 0R0402-PAD-2-GP
1
R5701 R5703
150R2J-L1-GP-U 150R2J-L1-GP-U
8
7
6
5
8
7
6
5
RN5703 RN5701
2
5V_S0 SRN470J-3-GP SRN470J-3-GP HDMI_DATA0#_R ER5715 1 2 HDMI_DATA0#_R_C HDMI_DATA2#_R ER5716 1 2 HDMI_DATA2#_R_C
Q5701
0R0402-PAD-2-GP 0R0402-PAD-2-GP
G
1
2
3
4
1
2
3
4
D HDMI_PLL_GND
R5719 1 DY 2 S
1
100KR2J-1-GP
2N7002K-2-GP DY R5707
84.2N702.J31 0R2J-2-GP 5V_S0
2ND = 84.2N702.031 HDMI CONN
2
5V_HDMI_S0 HDMI1
3rd = 84.07002.I31
C C
3
18 15 DDC_CLK_HDMI
D5701 +5V_POWER SCL 16 DDC_DATA_HDMI
LBAW 56LT1G-GP SDA
1
C5702 HDMI_DATA0_R_C 7
69.50007.691:
83.00056.Y11 HDMI_DATA0#_R_C 9 TMDS_DATA0+ 13
SCD1U16V2KX-3GP
OBS REASON: Please transfer to down size item 69.48001.081 for cost reduction and good cost down trend HDMI_DATA1_R_C 4 TMDS_DATA0- CEC 17
TMDS_DATA1+ DDC/CEC_GROUNG
DDC_DATA_PH2 1
2
HDMI_DATA1#_R_C 6 19
5V_S0 5V_HDMI_S0 HDMI_DATA2_R_C 1 TMDS_DATA1- HOT_PLUG_DETECT
TMDS_DATA2+
DDC_CLK_PH1
HDMI_DATA2#_R_C 3 14
F5701 TMDS_DATA2- RESERVED#14
1 2 8
5 TMDS_DATA0_SHIELD
POLYSW -1D1A6V-9-GP-U 2 TMDS_DATA1_SHIELD
TMDS_DATA2_SHIELD 20
11 GND 21
69.48001.081 TMDS_CLOCK_SHIELD GND
1
2
3D3V_S0 HDMI_CLK_R_C 10 22
2ND = 69.50011.081 RN5702 HDMI_CLK#_R_C 12 TMDS_CLOCK+ HDMI GND 23
R5718 1 DY 2 3RD = 69.50013.061 SRN2K2J-1-GP TMDS_CLOCK- (A_Type) GND
0R3J-L1-GP
SKT-HDMI23-168-GP
Q5702
022.10025.0161
HPD_HDMI_CON
4
3
4 3 DDC_CLK_HDMI
[8] CPU_DP1_CTRL_CLK 2nd = 022.10025.0181
5 2 3rd = 022.10025.0051
6 1
3D3V_S0
B 2N7002KDW-GP B
[8] CPU_DP1_CTRL_DATA
84.T3904.H11 R5710
C
DDC_DATA_HDMI 150KR2F-L-GP
Q5703 B HDMI_HPD_B 2 1
84.2N702.A3F
1
2nd = 84.2N702.E3F LMBT3904LT1G-GP
E
3rd = 75.00601.07C R5711
R5712 1 2 HDMI_HPD_E 200KR2F-L-GP
[8] CPU_DP1_HPD
0R0402-PAD
2
R5709
10KR2J-L-GP
EMI Request:
2
HDMI_DATA1#_R_C HDMI_DATA0#_R_C DDC_CLK_HDMI
HDMI_DATA1_R_C HDMI_DATA0_R_C DDC_DATA_HDMI
HDMI_DATA2#_R_C HDMI_CLK_R_C HPD_HDMI_CON
HDMI_DATA2_R_C HDMI_CLK#_R_C
ED5703
ED5701 1 10
1 10 1 ED5702 10
2 9
2 9 2 9
3
3 3 8
8 8 4 DY 7
4 DY 7 4 DY 7
5 6
A
5 6 5 6 <Core Design> A
RCLAMP0524P-2-GP Wistron Corporation

RCLAMP0524P-2-GP RCLAMP0524P-2-GP 75.00524.A73 Taipei Hsien 221, Taiwan, R.O.C.
75.00524.A73 75.00524.A73
Title
HDMI
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = HDD

SATA HDD Connector
5V_HDD_S0 ED6001
5V_S0
SATA_TX_CON_P0 1 10 SATA_TX_CON_P0
SATA_TX_CON_N0 2 LINE_1 NC#10 9 SATA_TX_CON_N0
E
80 mils 1
R6001
2 3 LINE_2 NC#9 8
E
0R0805-PAD-2-GP-U SATA_RX_CON_N0 4 GND DY GND 7 SATA_RX_CON_N0

SATA_RX_CON_P0 5 LINE_3 NC#7 6 SATA_RX_CON_P0
C6002
SC10U6D3V3MX-GP
C6001
SCD1U16V2KX-3GP
C6007
SCD1U16V2KX-3GP
C6008
SC10U6D3V3MX-GP
LINE_4 NC#6
1
1
1
DY DY
AZ1045-04F-R7G-GP
2
2
2
75.01045.073
Swap based on the swap report.
Layout Note:
Place near HDD1
Close to HDD1
HDD1
14
12
[16] SATA_TX_CPU_P0 C6005 1 2 SCD22U10V2KX-L1-GP SATA_TX_CON_P0 11
[16] SATA_TX_CPU_N0 C6006 1 2 SCD22U10V2KX-L1-GP SATA_TX_CON_N0 10
9
D D
C6004 1 2 SCD22U10V2KX-L1-GP SATA_RX_CON_N0 8
[16] SATA_RX_CPU_N0 C6003 1 2 SCD22U10V2KX-L1-GP SATA_RX_CON_P0 7
[16] SATA_RX_CPU_P0 6
R6002 1 2 0R0402-PAD HDD_DEVSLP_R 5
[16] HDD_DEVSLP
4
5V_HDD_S0 3
2
[67] FFS_INT2_Q 1
13
5V_HDD_S0 1 AFTP6001 AFTE14P-GP
STAR-CON12-1-GP
020.K0049.0012
2nd = 020.K0125.0012
3rd = 020.K0190.0012
ODD1
Main Func = ODD ODD Connector
C C
22
20
19
18
5V_S0 ODD_PWR_5V TP6001 1 SATA_ODD_DA#_C 17
TPAD14-OP-GP 16
R6003 1 2 15
0R0805-PAD-2-GP-U 14
13
C6009
SC10U6D3V3MX-GP
C6018
SCD1U16V2KX-3GP
1
ODD_PWR_5V 12
ODD ODD 11
10
2
9 ODD
R6004 1 2 0R0402-PAD-2-GP SATA_ODD_PRSNT#_R 8
[16] SATA_ODD_PRSNT#
7
C6011 1 2 SCD01U50V2KX-L-GP SATA_RX_CON_P1 6
[16] SATA_RX_CPU_P1
C6010
ODD
1 2 SCD01U50V2KX-L-GP SATA_RX_CON_N1 5
B [16] SATA_RX_CPU_N1 ODD 4
B
C6013 1 2 SCD01U50V2KX-L-GP SATA_TX_CON_N1 3

[16] SATA_TX_CPU_N1
C6014
ODD
1 2 SCD01U50V2KX-L-GP SATA_TX_CON_P1 2
[16] SATA_TX_CPU_P1 ODD
1
21
ACES-CON20-30-GP-U1
20.K0708.020
2nd = 020.K0050.0020
<Core Design>
Wistron Corporation
A Taipei Hsien 221, Taiwan, R.O.C. A
Title
INT IO (HDD/ODD)
Custom
Vegas SKL/KBL-U A00
Date: Wednesday, November 08, 2017
Sheet 60 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = WLAN

3D3V_S0 3D3V_WLAN_S0
1.1A R6117 USB_CON_PP6 R6111 1 2 0R0402-PAD-2-GP USB_CPU_PP6
1 2
0R0805-PAD-2-GP-U USB_CON_PN6 R6110 1 2 0R0402-PAD-2-GP USB_CPU_PN6
C6105
SC10U6D3V3MX-GP
C6101
SCD1U16V2KX-3GP
C6102
SCD1U16V2KX-3GP
C6106
SC10U6D3V3MX-GP
C6104
SCD1U16V2KX-3GP
C6103
SCD1U16V2KX-3GP
1
1
DY DY DY DY
D
[18] PEG_CLK1_CPU# D
[18] PEG_CLK1_CPU
2
[16] PCIE_RX_CPU_N6
[16] PCIE_RX_CPU_P6
[16] PCIE_TX_CON_N6
[16] PCIE_TX_CON_P6
WLAN1
[18] CLKREQ_PCIE#1
77
3D3V_WLAN_S0
[15] WIFI_RF_EN NP
74 75
[20] BLUETOOTH_EN
72 73
70 71
[24,68] HOST_DEBUG_TX
68 69
66 67
64 65
[17,31,55,63,76,91] PLT_RST#
62 63
60 61
C TP6103 1 TPAD14-OP-GP E51_RX2 58 59 C
[18] CL_RST# WIFI_RF_EN WLAN_DISABLE#1
R6114 1 2 0R0402-PAD 56 57 TP6101
BLUETOOTH_EN R6113 1 2 0R0402-PAD BLUETOOTH_EN_NGFF 54 55 WLAN_WAKE 1 TPAD14-OP-GP
[18] CL_CLK PLT_RST# R6116 1 2 0R0402-PAD PLT_RST_NGFF# 52 53 WLAN_CLKREQ_WLAN# R6112 1 2 CLKREQ_PCIE#1
[18] CL_DATA
50 51 0R0402-PAD
48 49 PEG_CLK1_CPU#
[16] USB_CPU_PN6 E51_RX1 PEG_CLK1_CPU
TP6102 1 46 47
[16] USB_CPU_PP6 E51_TX1
TPAD14-OP-GP 44 45
CL_CLK R6109 1 DY 2 0R2J-L-GP CL_CLK_R 42 43 PCIE_RX_CPU_N6
CL_DATA R6119 1 DY 2 0R2J-L-GP CL_DATA_R 40 41 PCIE_RX_CPU_P6
CL_RST# R6108 1 DY 2 0R2J-L-GP CL_RST#_R 38 39
36 37 PCIE_TX_CON_N6
3160 does not support C-Link 34 35 PCIE_TX_CON_P6
32 33
30 31
Reserved for NGFF Debug Card 28 29
24 27
3D3V_S5 3D3V_WLAN_S0 26 25
R6118 1 DY
Ra 2
22
20
23
21
B 0R2J-L-GP 18 19 B
16 17
HOST_DEBUG_TX R6115 1 DY 2 E51_TX1 14 15
0R2J-L-GP 12 13
10 11
EE Note: Rb 3D3V_WLAN_S0 8
6
9
7
For NFGG Debug Card: 4 5 USB_CON_PN6
Stuff Ra, Rb; DY Rc. 3 USB_CON_PP6
Note:pin 76 and pin 77 need contact to GND 2
NP 1
76
Support: Intel Dual Band Wireless-AC 3160
PAD-SKT-NGFF75P-GP
062.10003.0621
<Core Design>
2nd = 062.10007.0081
3rd = 062.10007.0391
A
AFTE14P-GP
AFTE14P-GP
AFTP6101
AFTP6105
1 3D3V_WLAN_S0
1 WLAN_CLKREQ_WLAN# Wistron Corporation A
1 WLAN_DISABLE#1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AFTE14P-GP AFTP6106 Taipei Hsien 221, Taiwan, R.O.C.
AFTE14P-GP AFTP6107 1 BLUETOOTH_EN_NGFF
AFTE14P-GP AFTP6108 1 PLT_RST_NGFF#
1 USB_CON_PN6 Title
AFTE14P-GP AFTP6109
AFTE14P-GP AFTP6110 1 USB_CON_PP6
NGFF_WLAN CONN
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = eMMC

1D8V_S5
1
EMMC eMMC R6311
0R3J-L1-GP
1 OF 2
U6301A
[15] EMMC_D7 3D3V_S5
[15] EMMC_D6
2
EMMC_VCCQ C6 A3 EMMC_D0_R R6312 1 2 10R2F-L1-GP EMMC_D0
D [15] EMMC_D5
M4 VDD DAT0 A4 EMMC_D1_R R6313 1
eMMC
2 10R2F-L1-GP EMMC_D1
D
[15] EMMC_D4 VDD DAT1 eMMC
1
C6316 C6317 N4 A5 EMMC_D2_R R6314 1 2 10R2F-L1-GP EMMC_D2
[15] EMMC_D3
P3 VDD DAT2 B2 EMMC_D3_R R6316 1
eMMC
[15] EMMC_D2 eMMC R6325
0R3J-L1-GP
SCD1U16V2KX-3GP SC4D7U6D3V3KX-GP
P5 VDD DAT3 B3 EMMC_D4_R R6317 1
eMMC
[15] EMMC_D1 eMMC VDD DAT4 eMMC
2
B4 EMMC_D5_R R6318 1 2 10R2F-L1-GP EMMC_D5
[15] EMMC_D0 eMMC E6 DAT5 B5 EMMC_D6_R R6319 1
eMMC
VDDF DAT6 eMMC
2
EMMC_VCC F5 B6 EMMC_D7_R R6315 1 2 10R2F-L1-GP EMMC_D7
[15] EMMC_CLK
J10 VDDF DAT7 eMMC
[15] EMMC_CMD VDDF
1
eMMC C6318 eMMC C6319 C6320 K9
SC1U10V2KX-1GP SCD1U16V2KX-3GP SC1U10V2KX-1GP VDDF A6 Change 10 ohm follow PDG
[15] EMMC_RCLK
2 1 EMMC_VDDI C2
eMMC VSS C4 modify date 4/17
VDDI VSS
2
eMMC E7
VSS G5
[17,31,55,61,76,91] PLT_RST# VSS H10
EMMC_CLK R6320 1eMMC 2 0R2J-2-GP EMMC_CLK_R M6 VSS J5
EMMC_CMD R6321 1eMMC 2 0R2J-2-GP EMMC_CMD_R M5 CLK VSS K8
CMD VSS N2
EMMC_RCLK R6322 1eMMC 2 10R2F-L1-GP EMMC_RCLK_R H5 VSS N5
EMMC_RESET# K5 DATA_STROBE VSS P4
RST# VSS P6
VSS
072.KMBG4.0C0U
C C
U6301B 2 OF 2
A1 J3
A2 NC#A1 NC#J3 J12
A8 NC#A2 NC#J12 J13
eMMC_E9 1 TP6301 TPAD14-OP-GP A9 NC#A8 NC#J13 J14
eMMC_E10 1 TP6302 TPAD14-OP-GP A10 NC#A9 NC#J14 K1
eMMC_F10 1 TP6303 TPAD14-OP-GP A11 NC#A10 NC#K1 K2
eMMC_K10 1 TP6304 TPAD14-OP-GP A12 NC#A11 NC#K2 K3
A13 NC#A12 NC#K3 K12
A14 NC#A13 NC#K12 K13
B1 NC#A14 NC#K13 K14
B7 NC#B1 NC#K14 L1
B8 NC#B7 NC#L1 L2
B9 NC#B8 NC#L2 L3
B10 NC#B9 NC#L3 L12
B11 NC#B10 NC#L12 L13
B12 NC#B11 NC#L13 L14
B13 NC#B12 NC#L14 M1
B14 NC#B13 NC#M1 M2
C1 NC#B14 NC#M2 M3
C3 NC#C1 NC#M3 M7
C5 NC#C3 NC#M7 M8
C7 NC#C5 NC#M8 M9
C8 NC#C7 NC#M9 M10
0510 C9 NC#C8 NC#M10 M11
EMMC_VCCQ Corrected to S5 C10 NC#C9 NC#M11 M12
B C11 NC#C10 NC#M12 M13 B
1D8V_S5 C12 NC#C11 NC#M13 M14
NC#C12 NC#M14
1
C13 N1
C14 NC#C13 NC#N1 N3
R6323
10KR2J-L-GP
G D1 NC#C14 NC#N3 N6
D2 NC#D1 NC#N6 N7
eMMC D D3 NC#D2 NC#N7 N8
eMMC NC#D3 NC#N8
2
D4 N9
EMMC_RESET# S PLT_RST# D12 NC#D4 NC#N9 N10
Q6301 Vth(max)=1.0V D13 NC#D12 NC#N10 N11
PJA138KA-GP D14 NC#D13 NC#N11 N12
E1 NC#D14 NC#N12 N13
084.00138.0A31 E2 NC#E1 NC#N13 N14
E3 NC#E2 NC#N14 P1
E12 NC#E3 NC#P1 P2
E13 NC#E12 NC#P2 P8
1
DY 2 E14 NC#E13 NC#P8 P9
F1 NC#E14 eMMC NC#P9 P11
R6324 F2 NC#F1 NC#P11 P12
0R2J-2-GP F3 NC#F2 NC#P12 P13
F12 NC#F3 NC#P13 P14
F13 NC#F12 NC#P14
F14 NC#F13
G1 NC#F14 A7
G2 NC#G1 RFU#A7 E5
G12 NC#G2 RFU#E5 E8
G13 NC#G12 RFU#E8 E9 eMMC_E9
G14 NC#G13 RFU#E9 E10 eMMC_E10
H1 NC#G14 RFU#E10 F10 eMMC_F10
A NC#H1 RFU#F10 <Core Design> A
H2 G3
H3 NC#H2 RFU#G3 G10
NC#H3 RFU#G10
H12
H13 NC#H12
NC#H13
RFU#K6
RFU#K7
K6
K7 Wistron Corporation
H14 K10 eMMC_K10 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
J1 NC#H14 RFU#K10 P7 Taipei Hsien 221, Taiwan, R.O.C.
J2 NC#J1 RFU#P7 P10
NC#J2 RFU#P10 Title
072.KMBG4.0C0U
eMMC
A3
Vegas SKL/KBL-R A00
5 4 3 2 1
5 4 3 2 1
Main Func = Power BTN

Power button
Layout note: PW R1
G6401 place to buttom 6
RN6401 4
1 4
G6402 place to top LID_CLOSE#_C 3
[24] LID_CL_SIO# KBC_PW RBTN#_C
2 3 2
[24] KBC_PW RBTN#
1
D SRN100J-3-GP 3D3V_S5 1 D
5
EC6401
SCD1U16V2KX-3GP
EC6403
SC1KP50V2KX-L-1-GP
ED6401
AZ5725-01FDR7G-GP
G6401
GAP-OPEN
G6402
GAP-OPEN
DY
1
DY DY ACES-CON4-88-GP
C6401
SCD1U16V2KX-3GP
020.K0005.0004
1
3D3V_S5 1 AFTP6402 DY
2
2nd = 020.K0264.0004
LID_CLOSE#_C 1 AFTP6401 1 AFTP6403
2
KBC_PW RBTN#_C1 AFTP6404
Main Func = Battery LED

5V_S5
Low actived from KBC GPIO Q6403
E
R2
R6405 1 2 CHG_AMBER_LED_R# B
[24] CHG_AMBER_LED#
0R0402-PAD
R1
C AMBER_LED_BAT R6407 1
422R2F-2-GP
2 BAT_AMBER
Battery LED1
EC6402
SCD1U25V2KX-GP
RN2418-GP
(AMBER_LED)
1
084.02418.0011 DY LED1
2
C 1 + Yellow C
- 3
2 + White
5V_S5
Low actived from KBC GPIO Q6404
E
R2
LED-YW -5-GP
R6404 1 2 BATT_W HITE_LED_R# B
[24] BATT_W HITE_LED#
0R0402-PAD
R1
C W HITE_LED_BAT R6406 1 2 BAT_W HITE
083.1212A.0070
274R2F-GP
EC6404
Battery LED2
SCD1U25V2KX-GP
RN2418-GP 1
084.02418.0011 DY
(WHITE_LED)
2
Main Func = HDD LED 0516 Follow KY15 1D8V_S0

1
R6401
10KR2J-L-GP
SATA HDD LED HWHDLED

LOW actived from PCH GPIO
2
B B
[24] MASK_SATA_LED#
G
S D BATT_W HITE_LED_R#
[16] SATA_LED#_R
Q6401
DMN5L06K-7-GP
HWHDLED
A <Core Design> A
Wistron Corporation
Title
LED Board&Power Button

A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = KB Main Func = TPAD 3D3V_S0 3D3V_S5
Internal Keyboard Connector

[20] KB_DET#
1
0R0402-PAD-2-GP
R6521
TP_VDD
R6520
0R2J-2-GP
KB1
32 NON_PTP
AFTP6519 1 30
AFTP6523 1 KSI7 29 TP_VDD Discharge Circuit
2
AFTP6511 1 KSI6 28
1
AFTP6521 1 KSI4 27
3D3V_TP_S5_R
AFTP6533 1 KSI2 26 R6522
AFTP6513 1 KSI5 25 DY 100R3J-4-GP
AFTP6540 1 KSI1 24 C6503 Q6505
AFTP6502 1 KSI3 23 SCD1U16V2KX-3GP TP_ON#_GATE G
[24] KSI[0..7]
2
AFTP6507 1 KSI0 22 1 2
AFTP6536 1 KSO5 21 D Q6205_Q
1 KSO4 20
DY
D [24] KSO[0..16] AFTP6522 D
AFTP6534 1 KSO7 19 R6516 TP_VDD S
R6509
S
AFTP6512 1 KSO6 18 1KR2J-1-GP
AFTP6505 1 KSO8 17 TP_EN# 1 2 TP_ON#_GATE G 1 2 TP_LOCK# 2N7002K-2-GP
[24] TP_EN#
AFTP6518 1 KSO3 16 G
84.2N702.J31
AFTP6517 1 KSO1 15 2ND = 84.2N702.031
1 KSO2 14 Q6504 D 100KR2J-1-GP
AFTP6510 3rd = 84.07002.I31
AFTP6520 1 KSO0 13 TP_VDD DMP2130L-7-GP
D
AFTP6538 1 KSO12 12 84.02130.031
AFTP6508 1 KSO16 11 2ND = 84.03413.A31
AFTP6515 1 KSO15 10
AFTP6535 1 KSO13 9
1 KSO14 8 TP_VDD
Precision Touch Pad Connector
AFTP6539 3D3V_S0
2
1
AFTP6516 1 KSO9 7
AFTP6506 1 KSO11 6 RN6504 R6517 1 DY 2
AFTP6503 1 KSO10 5 SRN10KJ-5-GP 0R3J-L1-GP
CAP_LED 4
3 Pin number Pin name
2 Support PTP TP_VDD
3
4
TP1 1 VDD
AFTP6537 1 1 9
31 1
2 DAT(I2C)
RN6503 1 4 TPCLK_C
PTWO-CON30-10-GP PS2 [24] CLK_TP_SIO
[24] DAT_TP_SIO
2 3 TPDATA_C I2C1_SDA_R 2
3 CLK(I2C)
SRN33J-5-GP-U I2C1_SCL_R 3
20.K0621.030
1
4
4 GND
1
2nd= 20.K0592.030 R6518 1
NON_PTP 2 0R2J-2-GP I2C1_SCL_R C6504 R6513 INT_TP# 5
[20] I2C0_SCL_TCH_PAD 2 0R2J-2-GP I2C1_SDA_R TP_LOCK#
1 6 ATTN
SCD1U16V2KX-3GP
I2C
3nd= 20.K0565.030 R6519 NON_PTP 4K7R2J-2-GP 5
[20] I2C0_SDA_TCH_PAD TPDATA_C 7
CAP LED Control NON_PTP
2
TPCLK_C 8 GPIO
6
2
1 10
LOW actived from KBC GPIO 5V_S0 DAT(PS2)
EC6503
SC33P50V2JN-3GP
EC6501
SC33P50V2JN-3GP
EC6504
SC33P50V2JN-3GP
EC6502
SC33P50V2JN-3GP
AFTP6531 7
Q6502
1
DY DY DY DY
E CLK(PS2)
R2
STAR-CON8-2-GP 8
R6508 1 2 CAP_LED_R# B
[24] CAP_LED#_S 020.K0182.0008
2
0R0402-PAD
R1
C CAP_LED_Q R6506 1 2 CAP_LED
1KR2J-1-GP 2nd = 020.K0243.0008
Change TP1 pin define ,
RN2418-GP pin1 connect VDD 1/26
C 084.02418.0011 C
1 CAP_LED Need to check if it is Active High or Active Low
AFTP6532 5V_S0 TP_VDD
and check if there is PH on TPAD side.
2
1
R6512
0502 Deleted KB2

0R0402-PAD RN6502
PTPSRN2K2J-1-GP TP side has pull high
2
Q6204_G TP_VDD
0524 Deleted KBBL1 block
3
4
Q6503 R6514 1 2 INT_TP#
I2C0_SCL_TCH_PAD 1 6 I2C1_SCL_R 10KR2J-L-GP
2 5
84.2N702.A3F
2nd = 84.2N702.E3F
PTP
3rd = 75.00601.07C 3 4 I2C1_SDA_R
2N7002KDW-GP
I2C0_SDA_TCH_PAD TP_VDD 1
TPCLK_C 1 AFTP6529
TPDATA_C 1 AFTP6530
I2C1_SCL_R 1 AFTP6524
I2C1_SDA_R 1 AFTP6528
INT_TP# 1 AFTP6527
Vages install Non PTP TP_LOCK# 1 AFTP6525
AFTP6526
SMBUS
R6515 1 2 0R2J-2-GP I2C1_SCL_R
[12,13,18,56,67] PCH_SMBCLK DY I2C1_SDA_R
R6511 1 DY 2 0R2J-2-GP
[12,13,18,56,67] PCH_SMBDATA
EC6505
EC6506
1
1
DY DY
Need to check with SW.
[4,24] INT_TP#
2
B
[24] TP_LOCK# B
SC33P50V2JN-3GP
SC33P50V2JN-3GP
A A
<Core Design>
Wistron Corporation
Title
Key Board&Touch Pad

Custom
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = IO Connector
I/O Board Connector

D D
IOBD1
31
1
2
3
Cardreader [33] USB_PN5_C
[33] USB_PP5_C 4
5
6
USB3(USB2.0) [37] USB_PN2_C
[37] USB_PP2_C 7
8
9
USB20_VCCA 10
11
12
13
14
3D3V_S0 15
16
17
AUD_AGND 18
19
Universal Jack [29] AUD_PORTA_L_R_B
[29] AUD_PORTA_R_R_B
[29] SLEEVE_R
20
21
C 22 C
23
[29] RING2_R 24
25
26
[29] JACK_PLUG 27
AUD_AGND 28
29
30
32
R6601 1 DY 2 ACES-CON30-9-GP-U2
0R3J-L1-GP 20.K0510.030
2nd = 20.K0580.030
AUD_AGND
Pitch: 1mm
Power: 6 pins
GND: 7 pins
AGND: 2 Pins
B B
USB_PN5_C 1
USB_PP5_C AFTP6601 AFTE14P-GP
1
USB_PN2_C AFTP6602 AFTE14P-GP
1
USB_PP2_C AFTP6603 AFTE14P-GP
1
RING2_R AFTP6604 AFTE14P-GP
1
AUD_PORTA_L_R_B AFTP6605 AFTE14P-GP
1
JACK_PLUG AFTP6606 AFTE14P-GP
1
AFTP6607 AFTE14P-GP
AUD_PORTA_R_R_B 1
SLEEVE_R AFTP6608 AFTE14P-GP
1
USB20_VCCA AFTP6609 AFTE14P-GP
1
AFTP6610 AFTE14P-GP
AUD_AGND 1
AFTP6611 AFTE14P-GP
1
AFTP6612 AFTE14P-GP
Wistron Confidential document, Anyone can not

Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
A <Core Design> A
Wistron Corporation
Title
IO Board Connector
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
SSID = User.interface
Free Fall Sensor
DVT1 add FFS 2/18
D D
3D3V_S0
R6701 1 2 3D3V_RUN_FFS 3D3V_S0

0R0603-PAD-2-GP-U
C6701
SCD1U16V2KX-3GP
C6702
SCD1U16V2KX-3GP
C6703
SC10U6D3V3MX-GP
1
1
FFS FFS DY U6701
9 2
DY R6702
100KR2J-1-GP
VDD CS
2
5
10 RES
VDD_IO
2
12
INT1 11 HDD_FALL_INT [18]
FFS INT2
1
[12,13,18,56,65] PCH_SMBCLK SCL/SPC
4 6
[12,13,18,56,65] PCH_SMBDATA 3D3V_RUN_FFS SDA/SDI/SDO GND
3 7
SDO/SA0 GND 8
GND
C C
LNG2DMTR-GP
074.LNG2D.00BZ
3D3V_S0
1
FFS R6703
100KR2J-1-GP
2
FALL_INT2
Q6701
3
5V_S0 2N7002KDW-GP
84.2N702.A3F 3D3V_S0
FFS 2nd = 084.27002.003F
1
3rd = 84.2N702.E3F
1
R6705
100KR2J-1-GP
4
DY DY R6704
100KR2J-1-GP
2
2
HDD [60] FFS_INT2_Q FFS_INT2 [20] PCH
1
B R6706 1 DY 2 R6707 B
0R2J-2-GP
FFS 1MR2J-1-GP
2
2014.04.24 Venrer suggest,reserve to prevent error trigger
Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
A <Core Design> A
Wistron Corporation
Title
Free Fall Sensor

A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Debug
D D
ESPI Debug Connector

DBG1
15
0607 Modify 1
TPAD14-OP-GP TP6801 1 ESPI_CLK_CON 2

3
0522 Modify TPAD14-OP-GP TP6802 1 ESPI_RESET#_CON 4
20.F0765.014
TPAD14-OP-GP TP6803 1 ESPI_CS#_CON 5
3D3V_S0 TPAD14-OP-GP TP6804 1 ESPI_IO3_CON 6
UART
C C
TPAD14-OP-GP TP6805 1 ESPI_IO2_CON 7
[24,61] HOST_DEBUG_TX 10
HOST_DEBUG_TX R6807 1 2 0R2J-2-GP HOST_DEBUG_TX_CON 11
[20] UART_2_CTXD_DRXD Debug 12
UART_2_CTXD_DRXD R6808 1 2 0R2J-2-GP UART_2_CTXD_DRXD_CON 13
[20] UART_2_CRXD_DTXD
UART_2_CRXD_DTXD R6809
Debug
1 2 0R2J-2-GP UART_2_CRXD_DTXD_CON 14
Debug 16
BOM:DVT2 DY
DM-ACES-CON14-5-GP-01
ZZ.F0765.01401
B B
<Core Design>
A
Title
Dubug connector
A4
Vegas SKL/KBL-R A00
Date: Friday, November 10, 2017 Sheet 68 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU GFX & GPP, 85Ω

GFX & GPP CLK, 85Ω
GPU1A 1 OF 7
20170502
PEG_TX_GPU_P0 AF30 AH30 PEG_RX_GPU_P0 C7601 1OPS2 SCD22U10V2KX-L1-GP
[16] PEG_TX_GPU_P0 PCIE_RX0P PCIE_TX0P PEG_RX_CPU_P0 [16]
PEG_TX_GPU_N0 AE31 AG31 PEG_RX_GPU_N0 C7602 1OPS2 SCD22U10V2KX-L1-GP
[16] PEG_TX_GPU_N0 PCIE_RX0N PCIE_TX0N PEG_RX_CPU_N0 [16]
D D
PEG_TX_GPU_P1 AE29 AG29 PEG_RX_GPU_P1 C7603 1OPS2 SCD22U10V2KX-L1-GP

PEG_TX_GPU_N1 AD28 AF28 PEG_RX_GPU_N1 C7604 1OPS2 SCD22U10V2KX-L1-GP
PEG_TX_GPU_P2 AD30 AF27 PEG_RX_GPU_P2 C7605 1OPS2 SCD22U10V2KX-L1-GP

PEG_TX_GPU_N2 AC31 AF26 PEG_RX_GPU_N2 C7606 1OPS2 SCD22U10V2KX-L1-GP
PEG_TX_GPU_P3 AC29 AD27 PEG_RX_GPU_P3 C7607 1OPS2 SCD22U10V2KX-L1-GP

PEG_TX_GPU_N3 AB28 AD26 PEG_RX_GPU_N3 C7608 1OPS2 SCD22U10V2KX-L1-GP
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N
Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N
C C
V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23
U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26
PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23
N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26
M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23
B L29 M27 B
DGPU_HOLD_RST# 3D3V_VGA_S0 K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
H dGPU mode
1
L IGPU DY R7625
10KR2J-L-GP AK30
CLOCK
[18] PEG_CLK_CPU PCIE_REFCLKP
H IGPU with BACO AK32
[18] PEG_CLK_CPU# PCIE_REFCLKN
2
R7623 1 2 CALIBRATION
0R0402-PAD R7601 Y22 PCIE_CALR_TX 1K69R2F-2-GP 2 1 R7622
1KR2F-L1-GP PCIE_CALR_TX OPS 0D95V_VGA_S0
1OPS 2 PW RGOOD_TEST N10 AA22 PCIE_CALR_RX R7618 1OPS 2
2 TEST_PG PCIE_CALR_RX 1KR2F-L1-GP
[20] DGPU_HOLD_RST#
3 ATI_RST# R7621 1 2 VGA_RST# AL27
DY 0R0402-PAD PERST#
1
C7609
SC47P50V2JN-3GP
[17,31,55,61,63,91] PLT_RST#
1
DY JET-XT-S3-GP
D7601 OPS
BAW 56-5-GP
2
A <Core Design> A
Wistron Corporation
Title
076_GPU(1/5) PEG
Size Project Name Rev
<Project Name>
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU GPU1G 7 OF 7
GPU1E 5 OF 7 DP POWER NC/DP POWER
AG15 AE11
AG16 NC_DP_VDDR#AG15 NC#AE11 AF11
AA27 A3 1.8V and 0.95V for Clock resource AF16 NC_DP_VDDR#AG16 NC#AF11 AE13
AB24 GND GND A30 AG17 NC_DP_VDDR#AF16 NC#AE13 AF13
AB32 GND GND AA13 1D8V_VGA_S0 DPLL_PVDD AG18 NC_DP_VDDR#AG17 NC#AF13 AG8
AC24 GND GND AA16 AG19 NC_DP_VDDR#AG18 NC#AG8 AG10
D
AC26 GND GND AB10 R7704 1 2 0R0603-PAD 40mA AF14 NC_DP_VDDR#AG19 NC#AG10
D
AC27 GND GND AB15 DP_VDDR

GND GND
1
AD25 AB6 DY C7713 OPS C7711 OPS C7710
AD32 GND GND AC9 SC10U6D3V3MX-GP SC1U10V2KX-1GP SCD1U16V2KX-3GP
AE27 GND GND AD6
GND GND
2
AF32 AD8 AG20 AF6
AG27 GND GND AE7 AG21 NC_DP_VDDC#AG20 NC#AF6 AF7
AH32 GND GND AG12 0D95V_VGA_S0 DPLL_VDDC AF22 NC_DP_VDDC#AG21 NC#AF7 AF8
K28 GND GND AH10 AG22 NC_DP_VDDC#AF22 NC#AF8 AF9
K32 GND GND AH28 R7705 1 2 0R0603-PAD 32mA AD14 NC_DP_VDDC#AG22 NC#AF9
L27 GND GND B10 DP_VDDC
GND GND
1
M32 B12 OPS C7715 OPS C7714
N25 GND GND B14 SC1U10V2KX-1GP SCD1U16V2KX-3GP
N27 GND GND B16 AG14 AE1
GND GND NC_DP_VSSR#AG14 NC#AE1
2
P25 B18 AH14 AE3
P32 GND GND B20 AM14 NC_DP_VSSR#AH14 NC#AE3 AG1
R27 GND GND B22 AM16 NC_DP_VSSR#AM14 NC#AG1 AG6
T25 GND GND B24 AM18 NC_DP_VSSR#AM16 NC#AG6 AH5
T32 GND GND B26 AF23 NC_DP_VSSR#AM18 NC#AH5 AF10
C U25 GND GND B6 GPU1F 6 OF 7 AG23 NC_DP_VSSR#AF23 NC#AF10 AG9 C
U27 GND GND B8 AM20 NC_DP_VSSR#AG23 NC#AG9 AH8
GND GND BALL: AB11, AB12 NC_DP_VSSR#AM20 NC#AH8
V32 C1 AM22 AM6
W25 GND GND C32 R16 : NC AM24 NC_DP_VSSR#AM22 NC#AM6 AM8
W26 GND GND E28 AB11 MESO : VDDC AF19 NC_DP_VSSR#AM24 NC#AM8 AG7
W27 GND GND F10 NC_VARY_BL AB12 AF20 NC_DP_VSSR#AF19 NC#AG7 AG11
Y25 GND GND F12 NC_DIGON AE14 NC_DP_VSSR#AF20 NC#AG11
Y32 GND GND F14 DP_VSSR
GND GND F16
GND F18
GND F2 AL15 AF17 AE10
GND F20 NC_UPHYAB_TMDPA_TX0N AK14 NC_UPHYAB_DP_CALR NC#AE10
M6 GND F22 NC_UPHYAB_TMDPA_TX0P
N13 GND GND F24 AH16
N16 GND GND F26 NC_UPHYAB_TMDPA_TX1N AJ15 JET-XT-S3-GP
N18 GND GND F6 NC_UPHYAB_TMDPA_TX1P
N21 GND GND
GND F8 AL17
P6 GND GND G10 NC_UPHYAB_TMDPA_TX2N AK16 OPS
P9 GND GND G27 NC_UPHYAB_TMDPA_TX2P
R12 GND GND G31 AH18
R15 GND GND G8 NC_UPHYAB_TMDPA_TX3N AJ17
B B
R17 GND GND H14 NC_UPHYAB_TMDPA_TX3P
R20 GND GND H17 AL19
T13 GND GND H2 NC_TXOUT_L3P AK18
T16 GND GND H20 NC_TXOUT_L3N
T18 GND GND H6
T21 GND GND J27 TMDP
T6 GND GND J31
U15 GND GND K11 AH20
U17 GND GND K2 NC_UPHYAB_TMDPB_TX0N AJ19
U20 GND GND K22 NC_UPHYAB_TMDPB_TX0P
U9 GND GND K6 AL21
V13 GND GND NC_UPHYAB_TMDPB_TX1N AK20
V16 GND NC_UPHYAB_TMDPB_TX1P
V18 GND AH22
Y10 GND NC_UPHYAB_TMDPB_TX2N AJ21
Y15 GND NC_UPHYAB_TMDPB_TX2P
<Core Design>
Y17 GND AL23
Y20 GND NC_UPHYAB_TMDPB_TX3N AK22
GND NC_UPHYAB_TMDPB_TX3P
A
R11
T11 GND VSS_MECH
A32
AM1
VSS_MECH1 1
VSS_MECH2 1
TP7701
TP7702 AK24 Wistron Corporation A
AA11 GND VSS_MECH AM32 VSS_MECH3 1 TP7703 NC_TXOUT_U3P AJ23 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
M12 GND VSS_MECH NC_TXOUT_U3N Taipei Hsien 221, Taiwan, R.O.C.
N11 GND
V11 GND Title
GND
077_GPU (2/5) DIGITALOUT
JET-XT-S3-GP
JET-XT-S3-GP Size Project Name Rev
OPS
OPS Vegas SKL/KBL-U X00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU [81] DQA0_0 [81] DQA1_0

GPU1C 3 OF 7
[81] DQA0_1 [81] DQA1_1
[81] DQA0_2 [81] DQA1_2 GDDR5/DDR3 GDDR5/DDR3
[81] DQA0_3 [81] DQA1_3 DQA0_0 MAA0_0
K27 K17
[81] DQA0_4 [81] DQA1_4 DQA0_1 DQA0_0 MAA0_0 MAA0_1
J29 J20
H30 H23 ADD
H32 G23
G29 G24
DQ F28 H24
F32 J19
F30 K19
D C30 G20 D
[81] DQA0_12 [81] DQA1_12 DQA0_9 DQA0_8 MAA0_8
F27 L17
A28
C28 J14
E27 K14
G26 J11
D26 J13
F25 H11
A25 G11
C25 J16
E25 L15
D24 G14
E23 L16
MEMORY INTERFACE
F23
[81] DQA0_25 [81] DQA1_25 DQA0_22 DQA0_21 W CKA0_0
D22 E32
[81] DQA0_26 [81] DQA1_26 DQA0_23 DQA0_22 WCKA0_0 W CKA0b_0
F21 E30
[81] DQA0_27 [81] DQA1_27 DQA0_24 DQA0_23 WCKA0#_0 W CKA0_1
E21 A21
D20 C21 DM
F19 E13
A19 D12
D18 E3
DQA0_29 F17 DQA0_28 WCKA1_1 F4 W CKA1b_1
[81] MAA0_0 DQA0_30 A17 DQA0_29 WCKA1#_1
[81] MAA0_1 DQA0_31 C17 DQA0_30 H28 EDCA0_0
[81] MAA0_2 DQA1_0 E17 DQA0_31 EDCA0_0 C27 EDCA0_1
[81] MAA0_3 DQA1_1 D16 DQA1_0 EDCA0_1 A23 EDCA0_2
[81] MAA0_4 Please MVREF drivers and Caps close to ASIC DQA1_2 F15 DQA1_1 EDCA0_2 E19 EDCA0_3
[81] MAA0_5 DQA1_3 A15 DQA1_2 EDCA0_3 E15 EDCA1_0
[81] MAA0_6 DQA1_4 D14 DQA1_3 EDCA1_0 D10 EDCA1_1
DQS
[81] MAA0_7 DQA1_5 F13 DQA1_4 EDCA1_1 D6 EDCA1_2
C
[81] MAA0_8 DDR3/GDDR3 Memory Stuff Option(R16) DQA1_6 A13 DQA1_5 EDCA1_2 G5 EDCA1_3
C
DQA1_7 C13 DQA1_6 EDCA1_3

[81] MAA1_0 DQA1_8 E11 DQA1_7 H27 DDBIA0_0
[81] MAA1_1 DQA1_9 A11 DQA1_8 DDBIA0_0 A27 DDBIA0_1
[81] MAA1_2 GDDR5 GDDR3 DDR3 DQA1_10 DQA1_9 DDBIA0_1 DDBIA0_2
C11 C23
[81] MAA1_3 DQA1_11 F11 DQA1_10 DDBIA0_2 C19 DDBIA0_3
[81] MAA1_4 DQA1_12 A9 DQA1_11 DDBIA0_3 C15 DDBIA1_0
[81] MAA1_5 MVDDQ 1.5V 1D35V 1.5V DQA1_13 DQA1_12 DDBIA1_0 DDBIA1_1
C9 E9
[81] MAA1_6 DQA1_14 F9 DQA1_13 DDBIA1_1 C5 DDBIA1_2
[81] MAA1_7 DQA1_15 D8 DQA1_14 DDBIA1_2 H4 DDBIA1_3
[81] MAA1_8 Ra 40.2R 40.2R 40.2R DQA1_16 DQA1_15 DDBIA1_3
E7
DQA1_17 A7 DQA1_16 L18 ADBIA0
DQA1_18 C7 DQA1_17 ADBIA0 K16
[81] EDCA0_0 Rb 100R 100R 100R DQA1_19 DQA1_18 ADBIA1
ADBIA1 Ctrl
F7
[81] EDCA0_1 DQA1_20 A5 DQA1_19 H26 CLKA0
[81] EDCA0_2 DQA1_21 E5 DQA1_20 CLKA0 H25 CLKA0b
[81] EDCA0_3 DQA1_22 C3 DQA1_21 CLKA0#
1D35V_VGA_S0 1D35V_VGA_S0 3.24 DQA1_23 E1 DQA1_22 G9 CLKA1
CLK
[81] EDCA1_0 DQA1_24 G7 DQA1_23 CLKA1 H9 CLKA1b
[81] EDCA1_1 DQA1_25 G6 DQA1_24 CLKA1#
[81] EDCA1_2 DQA1_25
1
1
DQA1_26 G1 G22 RASA0b
[81] EDCA1_3 DQA1_27 G3 DQA1_26 RASA0# G17
R7817
Ra R7810
DQA1_28 J6 DQA1_27 RASA1#
RASA1b
[81] DDBIA0_0 Ra 40D2R2F-GP 40D2R2F-GP
DQA1_29 J1 DQA1_28 G19 CASA0b
CMD
[81] DDBIA0_1 OPS OPS DQA1_30 J3 DQA1_29 CASA0# G16 CASA1b
[81] DDBIA0_2 DQA1_30 CASA1#
2
MVREFDA MVREFSA DQA1_31 J5

[81] DDBIA0_3 DQA1_31 H22 CSA0b_0
CSA0#_0
1
MVREFDA K26 J22

B [81] DDBIA1_0 MVREFDA CSA0#_1
1
1
J26 B
[81] DDBIA1_1 Rb R7818
100R2F-L3-GP
OPS C7805
SC1U10V2KX-1GP
Rb R7814
100R2F-L3-GP
OPS C7801
SC1U10V2KX-1GP
MVREFSA
MVREFSA G13 CSA1b_0
Ctrl, CS
[81] DDBIA1_2
OPS OPS
Jet Setting J25 CSA1#_0 K13
[81] DDBIA1_3 NC#J25 CSA1#_1
2
R7809 1 2 120R2F-GP MEM_CALRP0 K25

OPS MEM_CALRP0
2
K20 CKEA0
[81] W CKA0_0 CKEA0 J17 CKEA1
[81] W CKA0b_0 CKEA1 Ctrl
[81] W CKA0_1 G25 W EA0b
[81] W CKA0b_1 DRAM_RST_VGA1 L10 WEA0# H10 W EA1b
[81] W CKA1_0 DRAM_RST# WEA1# CMD
[81] W CKA1b_0 CLKTESTA K8
[81] W CKA1_1 Place all these componets very close to GPU (within 25mm) and keep all CLKTESTB L7 CLKTESTA
[81] W CKA1b_1 components close to each other CLKTESTB
This basic topology should be used for DRAM_RST for DDR3/GDDR5
1
C7822
DY DY C7821 JET-XT-S3-GP
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
[81] ADBIA0 ??? OPS
2
1D35V_VGA_S0
[81] ADBIA1
Difference with AMD
CLKTESTA_C
CLKTESTB_C
1
[81] CSA0b_0 Debug only, for

[81] CSA1b_0 DY R7802
2K2R2J-L1-GP
clock observation,
if not needed, DNI
[81] CKEA0
1
R7803
[81] CKEA1
2
R7804 1OPS 2 DRAM_RST_R 1 2 DRAM_RST_VGA1 R7821 R7820

[81] DRAM_RST
49D9R2F-L1-GP
OPS 51D1R2F-GP 51D1R2F-GP
[81] W EA0b 0510
DY DY
C7802
SC100P50V2JN-3GP
10R2J-L-GP
[81] W EA1b
1
Follow AMD adding DY cap

OPS
2
1
A R7819 DY C7803 <Core Design> A

[81] CASA0b
5K1R2F-2-GP
SC68P50V2JN-1GP
[81] CASA1b OPS

2
[81] RASA0b
2
[81] RASA1b Wistron Corporation

2

[81] CLKA0 Taipei Hsien 221, Taiwan, R.O.C.
[81] CLKA0b
[81] CLKA1 Title
[81] CLKA1b
078_GPU (3/5) VRAM I/F
Vegas SKL/KBL-U
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU #3 PS0 ~ PS3 Setting

R16: DY GPU1B 2 OF 7
MESO : 上件
3D3V_VGA_S0 3
RN7905
2 MESO_U1 AMD suggest Aperture Size = 256MB
1D8V_VGA_S0 MESO_U3
4 MESO 1 AF2
2 1 5K1R2F-2-GP TESTEN NC#AF2 AF4
1D8V_VGA_S0
11001
R7903 DY PINs for debug NC#AF4
SRN10KJ-5-GP
1
N9 AG3
R7902 1OPS 2 1KR2F-L1-GP TESTEN SMB_CLK_VGA_R R7912 1 2 0R0402-PAD SMB_CLK_VGA L9 DBG_DATA16 NC#AG3 AG5 R7926
AE9 DBG_DATA15 NC#AG5
SMB_DATA_VGA_R R7914 1 2 0R0402-PAD SMB_DATA_VGA Y11 DBG_DATA14 DPA
AH3
OPS 8K45R2F-2-GP
RN7904 R_pu
3 2 XO_IN AE8 DBG_DATA13 NC#AH3 AH1
DBG_DATA12 NC#AH1
2
4 1 XO_IN2 AD9 PS_0
OPS AC10 DBG_DATA11 AK3
3D3V_VGA_S0
DBG_DATA10 NC#AK3
1
SRN10KJ-5-GP AD7 AK1
DBG_DATA9 NC#AK1
1
AC8
R7927
2KR2F-L1-GP
DBG_DATA8 DVO DY C7918
1
AC7 AK5 OPS SCD082U16V2KX-GP
AB9 DBG_DATA7 NC#AK5 AM3
R7942
10KR2J-L-GP
D
DBG_DATA6 NC#AM3 R_pd D
2
AB8
DBG_DATA5
2
R7904 DY AB7 AK6
0R2J-2-GP AB4 DBG_DATA4 NC#AK6 AM5
DBG_DATA3 NC#AM5
2
1 DY 2DGPU_PWROK_R AB2 DPB
[19,24,85] DGPU_PWROK DBG_DATA2
Q7903 Y8 AJ7
G Y7 DBG_DATA1 NC#AJ7 AH6
DY DBG_DATA0 NC#AH6
D AK8
CLKREQ_PEG#0 [18] NC#AK8 AL7
1D8V_VGA_S0
11000
S NC#AL7
3D3V_VGA_S0
GEN3
1
2N7002K-2-GP W6 R_pu R7928
V6 NC#W6
NC#V6 OPS 8K45R2F-2-GP
R7943 1OPS 2 V4
NC#V4
4
3
0R2J-2-GP AC6 U5
NC#AC6 NC#U5
2
RN7902 AC5 PS_1
NC#AC5 W3
OPS SRN4K7J-8-GP NC#W3
1
AA5 V2
NC#AA5 NC#V2
1
AA6
R7929
2KR2F-L1-GP
2N7002KDW-GP NC#AA6 DPC
Y4
R_pd DY C7919
NC#Y4 OPS SCD68U16V3KX-GP-U
1
2
6 1 SMB_CLK_VGA_R W5
[18,24,79] SML1_SMBCLK NC#W5
R7938
680nF
2
16K2R2F-GP
2
5 2 MESO_U1 U1 AA3 NC#AA3 2 DY 1
W1 NC#U1 NC#AA3 Y2 R7929 cgange to 2K ohm 1/21
4
OPS 3 MESO_U3 U3 NC#W1 NC#Y2
Y6 NC#U3 J8
Q7901 1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8
TP7902 NC#AA1 1D8V_VGA_S0
Circuit checklist
[18,24,79] SML1_SMBDATA SMB_DATA_VGA_R Test only, 11000
1
Connect to GND through a 16.2-K resistor.
The resistor is not needed on production. R7930
I2C
R1
DY 8K45R2F-2-GP
BALL: U10,T10,Y9,W10 SCL
3D3V_VGA_S0 R3 R_pu
R16: NC SDA
2
PS_2
MESO : VDDC AM26 NC_R 1 TP7922
NC_R
1
AK26
GENERAL PURPOSE I/ONC_AVSSN#AK26
1
1
1 GPU_DPRSLP R7911 1 2 GPU_DPRSLP_R U6
R7931
4K75R2F-1-GP
TP7918 DY U10 GPIO_0 AL25
DY C7920
R7921 0R2J-2-GP
T10 NC_GPIO_1 NC_G AJ25
OPS SCD68U16V3KX-GP-U
C Q7902 10KR2J-L-GP
NC_GPIO_2 NC_AVSSN#AJ25 R_pd 680nF C
2
R7937 1 2 GPU_PWR_LEVEL_R G SMB_DATA_VGA U8
[24] GPU_PWR_LEVEL OPS OPS SMBDATA
2
0R0402-PAD SMB_CLK_VGA U7 AH24
SMBCLK NC_B
2
D GPIO_5_AC_BATT T9 AG25
R7913 1 DY 2 T8 GPIO_5_AC_BATT NC_AVSSN#AG25 R7941
S [85] TOPAZ_OCP T7 GPIO_6 DAC1 AH26
0R2J-2-GP 4K7R2J-2-GP
1 GPIO_8_ROMSO P10 NC_GPIO_7 NC_HSYNC AJ27 NC_VSYNC 2
TP7905 1 GPIO_9_ROMSI P4 GPIO_8_ROMSO NC_VSYNC MESO1 ## PS_3[3-1] => MEM_ID setting, need decide for AMD
2N7002K-2-GP TP7906 1 GPIO_10_ROMSCK P2 GPIO_9_ROMSI 1D8V_VGA_S0
TP7901 N6 GPIO_10_ROMSCK AD22
NC_GPIO_11 NC_RSET R16 : DY
N5
NC_GPIO_12 MESO : 上件
1
Pre-PWROK METAL VID CODES N3 AG24
Y9 NC_GPIO_13 NC_AVDD AE22
JET_SVD N1 NC_GPIO_14 NC_AVSSQ VRAM R7932
3K24R2F-GP
1 GPIO16_VGA M4 GPIO_15_PWRCNTL_0 AE23
SVC SVD Output Voltage GPIO_16 NC_VDD1DI R_pu
TP7903 1 GPIO_17_THERMAL_INT R6 AD23
GPIO_17_THERMAL_INT NC_VSS1DI
2
TP7923 W10 PS_3
0 0 1.1 GPIO_19_CTF NC_GPIO_18
R7922 1OPS 2 M2 FutureASIC/SEYMOUR/PARK
GPIO_19_CTF
1
JET_SVC P8 AM12
0 1 1.0 10KR2J-L-GP
GPIO_20_PWRCNTL_1 CEC_1
1
P7
R7933
5K62R2F-GP
1 GPIO_22_ROMCS# N8 GPIO_21 VRAM DY C7921
AMD suggestion 1 0 0.9 TP7910 H_VID3 GPIO_22_ROMCS# MESO_SVD
SCD01U50V2KX-L-GP
1 AK10 AK12 R_pd
GPIO_29 NC_SVI2#AK12
2
TP7919 1 H_VID4 AM10 AL11 MESO_SVT
1 1 0.8 GPIO_30 NC_SVI2#AL11
2
TP7920 N7 AJ11 MESO_SVC
CLKREQ# NC_SVI2#AJ11
1 JTAG_TRST#_VGA L6
BALL: AB13, W9, AC14 TP7907 JTAG_TDI_VGA JTAG_TRST#
1 L5
R16: NC TP7908 1 JTAG_TCK_VGA L3 JTAG_TDI
R7919 1 2 0R0402-PAD JET_SVC MESO : VDDC TP7911 1 JTAG_TMS_VGA L1 JTAG_TCK AL13
[79,85] VGA_SVC JET_SVD TP7912 JTAG_TDO_VGA JTAG_TMS NC_GENLK_CLK
R7920 1 2 0R0402-PAD 1 K4 AJ13
[79,85] VGA_SVD TP7913 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
AF24 TESTEN
NC#AF24 AG13
NC_SWAPLOCKA AH12
PWR_VGA_CORE_VDDIO AB13 NC_SWAPLOCKB
W8 NC_GENERICA
W9 NC_GENERICB
W7 NC_GENERICC AC19 PS_0
AD10 NC_GENERICD PS_0
NC_GENERICE_HPD4 #3
1
AJ9 AD19 PS_1

AL9 NC#AJ9 PS_1
R7940
10KR2J-L-GP
R7924
10KR2J-L-GP
R7923
10KR2J-L-GP
DBG_CNTL0 AE17 PS_2

MESO
MESO
B B
AC14 PS_2
DY 1 PX_EN AB16 NC_HPD1 AE20 PS_3
PX_EN PS_3
2
TP7904
R7944 1 MESO 2 0R2J-2-GP MESO_SVD
[79,85] VGA_SVD 1 2 0R2J-2-GP MESO_SVT AE19
[85] VGA_SVT
R7945 MESO TS_A
R7946 1 MESO 2 0R2J-2-GP MESO_SVC AC16
[79,85] VGA_SVC NC_DBG_VREFG
BALL: AC11,AC13
MESO non-install R16: NC
MESO : VDDC
1
DDC/AUX
AE6
R7925
10KR2J-L-GP
R7934
10KR2J-L-GP
R7939
10KR2J-L-GP
PLL/CLOCK NC_DDC1CLK AE5

MESO
MESO
NC_DDC1DATA 3D3V_S0
DY
NC_AUX1P
AD2 GPU thermal sensor
2
AD4
NC_AUX1N 3D3V_S0
AC11 3D3V_S0
C2615
SC10U6D3V3MX-GP
C2616
SCD1U16V2KX-3GP
NC_DDC2CLK
1
AC13
GPU_T8
NC_DDC2DATA DY GPU T8 2
R2613 1 18K7R2F-GP GPU_ALERT#
XTL_27M_X1_VGA AM28 AD13
XTALIN NC_AUX2P GPU T8 2
1
2
XTL_27M_X2_VGA AK28 AD11 R2614 1 2KR2F-L1-GP GPU_T_CRIT#
XTALOUT NC_AUX2N RN7903
XO_IN AC22 AD20
SVID PWR Sequencing XO_IN2 AB22 XO_IN NC#AD20 AC20 GPU T8
SRN4K7J-8-GP
3D3V_VGA_S0
XO_IN2 NC#AC20 NCT7718_DXP
R16 R7919 R7920 PR8611 PC8607 / PR8612 PC8612 AE16 THM262
NC#AE16
4
3
1
AD16 6 1 SMB_CLK_THM_R
NC#AD16 C
C2614
1
GPU T8 8 SMB_CLK_THM_R [18,24,79] SML1_SMBCLK
R7935
10KR2J-L-GP
Q7905 SC2200P50V2KX-2GP VDD SCL
1
SEYMOUR/FutureASIC AC1 B 2 7 SMB_DATA_THM_R 5 2
NC_DDCVGACLK D+ SDA
DY 1 GPU_DPLUS T4
DPLUS NC_DDCVGADATA
AC3 GPU T8 GPU T8 3
D- ALERT#
6 GPU_ALERT#
GPU T8 3
TP7909 1 GPU_DMINUS T2 THERMAL GPU_T_CRIT# 4 5 4
C2617
SCD1U16V2KX-3GP
C2618
SCD1U16V2KX-3GP
DMINUS T_CRIT# GND
2
1
TP7914 MLPS_EN# LMBT3904LT1G-GP DY DY
C7901 Q7904
1
R5 NCT7718_DXN
SC6D8P50V2CN-DL-GP 1D8V_VGA_S0 13mA GPIO28_FDO
NCT7718W-GP 2N7002KDW-GP
2
XTL_27M_X1_VGA 1 2 AD17 74.07718.0B9
R7936
10KR2J-L-GP
OPS AC17 TSVDD [18,24,79] SML1_SMBDATA SMB_DATA_THM_R

TSVSS Layout Note:
1
X7901 OPS OPS C7904 Both DXN and DXP routing 10 mil trace width
SC1U10V2KX-1GP
2
1
4 1 and 10 mil spacing.

OPS Q2605
2
G
R7901
1MR2J-1-GP
JET-XT-S3-GP
A [17,24,26] RESET_OUT# A
OPS 0: Enable MLPS, disable GPIO PINSTRAP D
3 2 1: Disable MLPS, enable GPIO PINSTRAP OPS GPU T8
PURE_HW_SHUTDOWN# [26,40]
2
R2615 1 2 GPU_T_CRIT_R# S
C7903 0R0402-PAD
XTL_27M_X2_VGA
XTAL-27MHZ-159-GP SC6D8P50V2CN-DL-GP
1 2
R_pu (Ω) R_pd (Ω) Bits [3:1] 2N7002K-2-GP
<Core Design>
OPS NC 4750 000 84.2N702.J31
8450 2000 001 2ND = 84.2N702.031
4530 2000 010 3rd = 84.07002.I31 Wistron Corporation
6980 4990 011 Cap Value (nF) Bits [5:4] 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
680 00 Taipei Hsien 221, Taiwan, R.O.C.
4530 4990 100
3240 5620 101 82 01 Title
3400 10000 110 10 10 079_GPU (4/5) GPIO/STRAP
4750 NC 111 NC 11 Size Project Name Rev
Note: 0402 1% resistors are required. Vegas SKL/KBL-U
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU

20170502 0D95V_VGA_S0
AMD schematic Review need GPU1D 4 OF 7 1D8V_VGA_S0
10uF x 1, 2.2uFx5, 0.1uF x1, 0.01uF x1
0.1A
1
1D35V_VGA_S0 AM30 C8010 C8016
MEM I/O PCIE_PVDD
PCIE
1A DY OPS
1
H13 AB23 DY C8008 OPS C8002
VDDR1 NC#AB23
2
H16 AC23 SC1U10V2KX-1GP SC10U6D3V3MX-GP
VDDR1 NC#AC23
1
D OPS C8001 DY C8007 DY C8014 H19 AD24 D
VDDR1 NC#AD24
2
SC10U6D3V3MX-GP SCD1U16V2KX-3GP SCD01U50V2KX-L-GP J10 AE24
J23 VDDR1 NC#AE24 AE25 SC10U6D3V3MX-GP
VDDR1 NC#AE25
2
J24 AE26 SC10U6D3V3MX-GP
J9 VDDR1 NC#AE26 AF25
1D35V_VGA_S0 K10 VDDR1 NC#AF25 AG26
K23 VDDR1 NC#AG26 0D95V_VGA_S0
K24 VDDR1 AMD schematic Review need 10uF x 2, 1uFx3, 0.1uF x2
K9 VDDR1 L23 2.5A
VDDR1 PCIE_VDDC
1
1
C8003 C8004 C8005 C8006 C8009 C8031 C8032 C8033 C8034 C8042 L11 L24
VDDR1 PCIE_VDDC
1
OPS OPS DY DY DY DY DY DY OPS DY L12 L25 C8011 C8012 C8013 C8015 C8057
L13 VDDR1 PCIE_VDDC L26 OPS OPS OPS OPS OPS
VDDR1 PCIE_VDDC
2
2
L20 M22
VDDR1 PCIE_VDDC
2
L21 N22
SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP L22 VDDR1 PCIE_VDDC N23
SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP VDDR1 PCIE_VDDC N24 SCD1U16V2KX-3GP SC1U10V2KX-1GP
SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP PCIE_VDDC R22 SCD1U16V2KX-3GP SC1U10V2KX-1GP
SC1U10V2KX-1GP PCIE_VDDC T22 SC1U10V2KX-1GP
LEVEL PCIE_VDDC U22
TRANSLATION PCIE_VDDC V22
1D8V_VGA_S0
13mA AA20 PCIE_VDDC
AA21 VDD_CT
VDD_CT
1
C8017 AB20 AA15
SC1U10V2KX-1GP AB21 VDD_CT CORE VDDC N15 VGA_CORE
VDD_CT VDDC N17
AMD ORB 10U x 6 LF145M 4.7U x 6
OPS
VDDC 2.2U x 16 1U x 20
2
R13
I/O VDDC R16
25mA VDDC
1
AA17 R18 C8018 C8019 C8020 C8021 C8022 C8023 C8025 C8026 C8027
AA18 VDDR3 VDDC Y21 OPS OPS OPS OPS OPS OPS OPS OPS OPS
C AB17 VDDR3 VDDC T12 C
VDDR3 VDDC
2
3D3V_VGA_S0 AB18 T15
VDDR3 VDDC T17
1 C8024 V12 VDDC T20 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
SC1U10V2KX-1GP Y12 NC_VDDR4#V12 VDDC U13 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
OPS U12 NC_VDDR4#Y12 VDDC U16 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
NC_VDDR4#U12 VDDC
2
U18
VDDC V21
VDDC V15 VGA_CORE
VDDC V17
NC on JET
VDDC V20 AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13
VDDC Y13
POWER
Memory phase lock loop power: Dedicated VDDC
1
Y16 C8028 C8029 C8030 C8035 C8036 C8037 C8058 C8059 C8060
1D8V_VGA_S0 analogue power in for memory PLLs MPV18 VDDC Y18 OPS OPS OPS OPS OPS OPS OPS OPS OPS
VDDC AA12
VDDC
2
L8001 1 OPS 2 MMZ1005S241C-GP M11
VDDC N12
VDDC
1
C8043 C8044 C8045 U11 SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP

SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC1U10V2KX-1GP VDDC SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
OPS OPS OPS SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
2
PLL
0D95V_VGA_S0
Engine phase loop power: Dedicated analogue R21
MPV18 BIF_VDDC U21 1.4A
1D8V_VGA_S0 power pin for engine PLL SPV18 BIF_VDDC
90mA
1
L8 C8065
L8002 1OPS 2 BLM15AG121SN-1GP MPLL_PVDD SC1U10V2KX-1GP
B B
ISOLATED OPS
2
1
68.00084.921 C8053 C8054 SPV18 CORE I/O

SC10U6D3V3MX-GP SC1U10V2KX-1GP M13
OPS OPS 75mA H7 VDDCI M15 5A
SPLL_PVDD VDDCI
2
M16
VDDCI M17
SPV10 VDDCI M18
AMD ORB 10U x 2 LF145M 4.7U x 2
VDDCI M20 1U x 3 1U x 3 VGA_CORE
100mA H8 VDDCI M21 0.1U x2 0.1U x 2
SPLL_VDDC VDDCI N20
Engine phase loop power: Dedicated digital J7 VDDCI
power pin for engine PLL SPLL_PVSS
1
0D95V_VGA_S0 SPV10 C8046 C8047 C8048 C8049 C8050 C8051 C8052
L8003 1OPS 2 BLM15AG121SN-1GP

OPS OPS OPS OPS OPS OPS OPS
2
JET-XT-S3-GP
1
68.00084.921 C8055 C8056

SC1U10V2KX-1GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SC1U10V2KX-1GP SC4D7U6D3V3KX-GP
OPS OPS SCD1U16V2KX-3GP SC1U10V2KX-1GP SC4D7U6D3V3KX-GP
2
SC1U10V2KX-1GP
VGA_CORE
VGA_CORE
1
C8038 C8039 C8040 C8041 C8063 C8064

OPS OPS OPS OPS OPS OPS
C8066
SC22U6D3V3MX-1-GP
C8061
SC1U10V2KX-1GP
C8062
SC1U10V2KX-1GP
2
1
OPS OPS OPS
A <Core Design> A
2
2
Wistron Corporation
Title
080_GPU (5/5) PWR/GND

<Project Name>
5 4 3 2 1
5 4 3 2 1
SSID = Vram (GDDR5)

[78] DQA0_0 1D35V_VGA_S0 1 OF 2 1D35V_VGA_S0 1 OF 2
VRAM1A VRAM2A
[78] DQA0_1
[78] DQA0_2 C5 B5 C5 B5
[78] DQA0_3 C10 VDD VSS B10 C10 VDD VSS B10
[78] DQA0_4 D11 VDD OPS VSS D10 D11 VDD OPS VSS D10 0510
[78] DQA0_5 G1 VDD VSS G5 G1 VDD VSS G5 Follow AMD Change to 1%
[78] DQA0_6 G4 VDD VSS G10 G4 VDD VSS G10
[78] DQA0_7 G11 VDD VSS H1 G11 VDD VSS H1 1D35V_VGA_S0
[78] DQA0_8 G14 VDD VSS H14 G14 VDD VSS H14 Close to VRAM1
[78] DQA0_9 L1 VDD VSS K1 L1 VDD VSS K1 R8101 1OPS 2 60D4R2F-GP CLKA0
[78] DQA0_10 L4 VDD VSS K14 L4 VDD VSS K14
[78] DQA0_11 L11 VDD VSS L5 L11 VDD VSS L5 R8102 1OPS 2 60D4R2F-GP CLKA0b
[78] DQA0_12 L14 VDD VSS L10 L14 VDD VSS L10
[78] DQA0_13 P11 VDD VSS P10 P11 VDD VSS P10
[78] DQA0_14 1D35V_VGA_S0 R5 VDD VSS T5 1D35V_VGA_S0 R5 VDD VSS T5 1D35V_VGA_S0
[78] DQA0_15 R10 VDD VSS T10 R10 VDD VSS T10 Close to VRAM2
D [78] DQA0_16 D
VDD VSS VDD VSS R8103 1OPS 2 60D4R2F-GP CLKA1
[78] DQA0_17 B1 A1 B1 A1
[78] DQA0_18 B3 VDDQ VSSQ A3 B3 VDDQ VSSQ A3 R8104 1OPS 2 60D4R2F-GP CLKA1b
[78] DQA0_19 B12 VDDQ VSSQ A12 B12 VDDQ VSSQ A12
[78] DQA0_20 B14 VDDQ VSSQ A14 B14 VDDQ VSSQ A14
[78] DQA0_21 D1 VDDQ VSSQ C1 D1 VDDQ VSSQ C1
[78]
[78]
DQA0_25
DQA0_26
E5 VDDQ
VDDQ
VSSQ
VSSQ
C12 E5 VDDQ
VDDQ
VSSQ
VSSQ
C12 Frame Buffer Patition A-Lower Half
E10 C14 E10 C14
[78] DQA0_27 F1 VDDQ VSSQ E1 F1 VDDQ VSSQ E1
[78] DQA0_29 F12 VDDQ VSSQ E12 F12 VDDQ VSSQ E12 1D35V_VGA_S0 1D35V_VGA_S0
[78] DQA0_31 G2 VDDQ VSSQ F5 G2 VDDQ VSSQ F5
G13 VDDQ VSSQ F10 G13 VDDQ VSSQ F10 0510 0510
[78] DQA1_0 VDDQ VSSQ VDDQ VSSQ
1
H3 H2 H3 H2 Follow AMD to dummy Follow AMD to dummy
1
H12 H13 H12 H13 C8101 DY OPS R8105 C8102 DY R8106
[78] DQA1_2 K3 VDDQ VSSQ K2 K3 VDDQ VSSQ K2
[78] DQA1_3 K12 VDDQ VSSQ K13 K12 VDDQ VSSQ K13
SC1U10V2KX-1GP 2K37R2F-GP SC1U10V2KX-1GP OPS 2K37R2F-GP
2
L2 M5 L2 M5
2
L13 M10 L13 M10 VREFC_A0 VREFC_A1
[78] DQA1_6 M1 VDDQ VSSQ N1 M1 VDDQ VSSQ N1
1
M3 N3 M3 N3
1
M12 N12 M12 N12 C8103 OPS OPS R8107 C8104 OPS R8108
[78] DQA1_9 M14 VDDQ VSSQ N14 M14 VDDQ VSSQ N14
[78] DQA1_10 N5 VDDQ VSSQ R1 N5 VDDQ VSSQ R1
SC1U10V2KX-1GP 5K49R2F-GP SC1U10V2KX-1GP OPS 5K49R2F-GP
2
N10 R3 N10 R3
2
P1 R4 P1 R4
[78] DQA1_13 P3 VDDQ VSSQ R11 P3 VDDQ VSSQ R11
[78] DQA1_16 T1 VDDQ VSSQ U1 T1 VDDQ VSSQ U1
[78] DQA1_20 VDDQ VSSQ VDDQ VSSQ Place close VRAM2 VDD ball Place close VRAM1 VDD ball
[78] DQA1_21 VREFC_A0 J14 A5 VREFC_A1 J14 A5
[78] DQA1_22 VREFC VPP/NC#A5 U5 VREFC VPP/NC#A5 U5 1D35V_VGA_S0 1D35V_VGA_S0
[78] DQA1_23 A10 VPP/NC#U5 A10 VPP/NC#U5 0.1uF(X7R) 0.1uF(X7R)
C C
[78] DQA1_24 U10 VREFD U10 VREFD K0402 ×4 K0402 ×4
[78] DQA1_25 0510 VREFD 0510 VREFD
[78] DQA1_26
1
Follow AMD to remove net Follow AMD to remove net C8105 C8106 C8107 C8108 C8109 C8110 C8111 C8112
[78] DQA1_27 Symbol error for layout NCH5GQ2H24AFR-T2C-GP Symbol error for layout NCH5GQ2H24AFR-T2C-GP
[78] DQA1_28 OPS OPS OPS OPS OPS OPS OPS OPS
[78] DQA1_29
2
[78] DQA1_30
[78] DQA1_31
SCD1U16V2KX-3GP SCD1U16V2KX-3GP
[78] MAA0_0 SCD1U16V2KX-3GP SCD1U16V2KX-3GP
[78] MAA0_1
[78]
[78]
MAA0_2
MAA0_3
Normal(MF=0) Mirrored(MF=1) SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
[78] MAA0_4 VRAM1B 2 OF 2 VRAM2B 2 OF 2
[78] MAA0_5
[78] MAA0_6 MAA0_7 K4 A4 DQA0_30 MAA1_0 K4 A4 DQA1_18 1D35V_VGA_S0 10uF(X5R)
[78] MAA0_7 MAA0_1 H5 A8/A7 DQ0 A2 DQA0_28 MAA1_6 H5 A8/A7 OPS DQ0 A2 DQA1_17
1.0uF(X7R) M0603 ×2
[78] MAA0_8 MAA0_0 H4 A9/A1 OPS DQ1 B4 DQA0_31 MAA1_7 H4 A9/A1 DQ1 B4 DQA1_20 Place close VRAM2 VDDQ ball K0402 ×8
MAA0_6 K5 A10/A0 DQ2 B2 DQA0_29 MAA1_1 K5 A10/A0 DQ2 B2 DQA1_21
A11/A6 DQ3 3 A11/A6 DQ3 2
1
MAA0_8 J5 E4 DQA0_24 MAA1_8 J5 E4 DQA1_22 C8113 C8114 C8115 C8116 C8117 C8118 C8119 C8120 C8121 C8122
[78] MAA1_0 A12/RFU#J5/NC#J5 DQ4 E2 DQA0_27 A12/RFU#J5/NC#J5 DQ4 E2 DQA1_16
[78] MAA1_1 MAA0_2 H11 DQ5 F4 DQA0_25 MAA1_4 H11 DQ5 F4 DQA1_23 OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS
[78] MAA1_2 BA0/A2 DQ6 BA0/A2 DQ6
2
MAA0_5 K10 F2 DQA0_26 MAA1_3 K10 F2 DQA1_19
[78] MAA1_3 MAA0_4 K11 BA1/A5 DQ7 A11 DQA0_16 MAA1_2 K11 BA1/A5 DQ7 A11 DQA1_26
[78] MAA1_4 MAA0_3 H10 BA2/A4 DQ8 A13 DQA0_19 MAA1_5 H10 BA2/A4 DQ8 A13 DQA1_31 SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V3MX-GP
[78] MAA1_5 BA3/A3 DQ9 B11 DQA0_18 BA3/A3 DQ9 B11 DQA1_29 SC1U10V2KX-1GP SC1U10V2KX-1GP SC10U6D3V3MX-GP
[78] MAA1_6 ADBIA0 J4 DQ10 B13 DQA0_17 ADBIA1 J4 DQ10 B13 DQA1_30
[78]
[78]
MAA1_7
MAA1_8
RASA0b
CSA0b_0
G3 ABI#
RAS#
DQ11
DQ12
E11 DQA0_23
DQA0_21
2 CASA1b G3 ABI#
RAS#
DQ11
DQ12
E11 DQA1_27
DQA1_24
3 SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
G12 E13 WEA1b G12 E13
CASA0b L3 CS# DQ13 F11 DQA0_22 RASA1b L3 CS# DQ13 F11 DQA1_25
WEA0b L12 CAS# DQ14 F13 DQA0_20 CSA1b_0 L12 CAS# DQ14 F13 DQA1_28
[78] DDBIA0_0 WE# DQ15 U11 DQA0_4 WE# DQ15 U11 DQA1_15
[78] DDBIA0_1 CLKA0 J12 DQ16 U13 DQA0_3 CLKA1 J12 DQ16 U13 DQA1_14
[78] DDBIA0_2 J11 CK DQ17 T11 DQA0_5 J11 CK DQ17 T11 DQA1_13 1D35V_VGA_S0 10uF(X5R)
CLKA0b CLKA1b 1.0uF(X7R)
[78] DDBIA0_3 CKEA0 J3 CK# DQ18 T13 DQA0_2 CKEA1 J3 CK# DQ18 T13 DQA1_11 M0603 ×2
CKE# DQ19 N11 DQA0_7 0 CKE# DQ19 N11 DQA1_12 1 Place close VRAM1 VDDQ ball K0402 ×8
[78] DDBIA1_0 DDBIA0_3 D2 DQ20 N13 DQA0_1 DDBIA1_2 D2 DQ20 N13 DQA1_10
[78] DDBIA1_1 DBI0# DQ21 DBI0# DQ21
1
DDBIA0_2 D13 M11 DQA0_6 DDBIA1_3 D13 M11 DQA1_9 C8123 C8124 C8125 C8126 C8127 C8128 C8129 C8130 C8131 C8132
[78] DDBIA1_2 DDBIA0_0 P13 DBI1# DQ22 M13 DQA0_0 DDBIA1_1 P13 DBI1# DQ22 M13 DQA1_8
[78] DDBIA1_3 DDBIA0_1 P2 DBI2# DQ23 U4 DQA0_15 DDBIA1_0 P2 DBI2# DQ23 U4 DQA1_0 OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS
DBI3# DQ24 DBI3# DQ24
2
B U2 DQA0_8 U2 DQA1_3 B
DRAM_RST J2 DQ25 T4 DQA0_11 DRAM_RST J2 DQ25 T4 DQA1_1
[78] CSA0b_0 RESET# DQ26 RESET# DQ26
T2 DQA0_10 T2 DQA1_2
[78] WEA0b
[78] RASA0b R8111 1OPS 2 1KR2J-L2-GP SEN_A0
ZQ_A0
J10
SEN
DQ27
DQ28
N4 DQA0_14
DQA0_9
1 R8113 1OPS 2 1KR2J-L2-GP SEN_A1
ZQ_A1
J10
SEN
DQ27
DQ28
N4 DQA1_7
DQA1_4
0 SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
[78] CASA0b R8110 1OPS 2 120R2F-GP J13 N2 R8109 1OPS 2 120R2F-GP J13 N2 SC1U10V2KX-1GP SC1U10V2KX-1GP
R8112 1OPS 2 1KR2J-L2-GP MF_A0 J1 ZQ DQ29 M4 DQA0_13 R8114 1OPS 2 1KR2J-L2-GP MF_A1 J1 ZQ DQ29 M4 DQA1_6 SC1U10V2KX-1GP SC1U10V2KX-1GP
MF DQ30 DQA0_12 1D35V_VGA_S0 MF DQ30 DQA1_5
[78] CSA1b_0 M2 M2
WCKA0_1 D4 DQ31 WCKA1_1 D4 DQ31
[78] WEA1b WCK01 WCK01
WCKA0b_1 D5 C2 EDCA0_3 WCKA1b_1 D5 C2 EDCA1_2
[78] RASA1b WCK01# EDC0 WCK01# EDC0
C13 EDCA0_2 C13 EDCA1_3
[78] CASA1b EDC1 EDC1
WCKA0_0 P4 R13 EDCA0_0 WCKA1_0 P4 R13 EDCA1_1
WCKA0b_0 P5 WCK23 EDC2 R2 EDCA0_1 WCKA1b_0 P5 WCK23 EDC2 R2 EDCA1_0
WCK23# EDC3 WCK23# EDC3
[78] ADBIA0
[78] ADBIA1
H5GQ2H24AFR-T2C-GP H5GQ2H24AFR-T2C-GP
[78] CLKA0
[78] CLKA0b
[78] CKEA0
[78] CLKA1
[78] CLKA1b
[78] CKEA1
[78] WCKA0_0
[78] WCKA0b_0
[78] WCKA0_1
[78] WCKA0b_1
[78] WCKA1_0
[78] WCKA1b_0
[78] WCKA1_1
[78] WCKA1b_1
[78] EDCA0_0
[78] EDCA0_1
[78] EDCA0_2
[78] EDCA0_3
A A
[78] EDCA1_0
[78] EDCA1_1
[78] EDCA1_2
[78] EDCA1_3
<Core Design>
[78] DRAM_RST
Wistron Corporation
Title
GPU-VRAM1,2 (1/4)
A2
Vegas SKL/KBL-R A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU power DCBATOUT PWR_DCBATOUT_VGA_CORE2 DCBATOUT PWR_DCBATOUT_VGA_CORE1
PG8501 PG8511
1
1 2 1 2
PR8501
10KR2J-L-GP
PR8502
10KR2J-L-GP
OPS
OPS
GAP-CLOSE-PWR GAP-CLOSE-PWR
PG8502 PG8512
1 2 1 2
2
0926 Modify PC8502 voltage 1st source: 075.06994.0037
PWR_VGA_CORE_UGATE_LX_NB
PR8503 1OPS 2 10KR2F-L1-GP EN/DEM_VGA PG8503 PG8513
3D3V_VGA_S0
2nd source: 075.00998.0073
PWR_VGA_CORE_LGATE_NB
PC8502 OPS1 2 SCD1U25V2KX-1-DL-GP 1 2 1 2 PWR_DCBATOUT_VGA_CORE1
PWR_VGA_CORE_VDDIO PG8504 PG8514
PR8546 1MESO 2 0R2J-2-GP 1 2 1 2
PC8526
SC4D7U25V5KX-L2-GP
PC8527
SC4D7U25V5KX-L2-GP
PC8528
SC10U25V5KX-L-GP
PC8529
SC10U25V5KX-L-GP
PC8530
SCD1U25V2KX-GP
D 1D8V_VGA_S0 PU8502 PU8503 D
1
PR8505 1 2 0R0402-PAD FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP
3D3V_VGA_S0 1OPS2 2 2
OPS OPS OPS OPS OPS
PC8503 SC1KP50V2KX-L-1-GP GAP-CLOSE-PWR GAP-CLOSE-PWR
PG8505 PG8515 3 3
2
1 2 1 2 1 4 1 4
10 10
PU8201_36
PU8201_39
GAP-CLOSE-PWR GAP-CLOSE-PWR 65
9 BOM 9
PG8506 PG8516 7 7
1 2 1 2 8 6 8 6
5 5
5V_S5
40
39
38
37
36
35
34
33
32
31
PU8501 ZZ.00215.037 ZZ.00215.037
ISUMP_NB
UGATE_NB
ISUMN_NB
VSEN_NB
PHASE_NB
BOOT_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
5V_S5
PC8507
PR8507 SCD22U25V3KX-GP
PR8506 1OPS 2 PWR_VGA_CORE_NTC_NB 1 30 PWR_VGA_CORE_BOOT2 1OPS 2 PWR_VGA_CORE__BOOT2_1 1 2
NTC_NB BOOT2 OPS PR8510
100KR2F-L3-GP 1R2F-GP TDC=34A
1
PR8508 1OPS 2 PWR_VGA_CORE_IMON_NB 2 29 PWR_VGA_CORE_UGATE2 2D2R3F-L-GP 1 2 PWR_VGA_CORE_UGATE1
100KR2F-L3-GP
PWR_VGA_CORE_SVC
IMON_NB UGATE2
PWR_VGA_CORE_PHASE2
OPS PC8508 SC1U10V2KX-1GP OCP<??A
PR8509 1 2 3 28
[79] VGA_SVC SVC PHASE2
0R0402-PAD OPS
PR8511 1 2 PWR_VGA_CORE_VR_HOT# 4 27 PWR_VGA_CORE_LGATE2 VGA_CORE
[79] TOPAZ_OCP VR_HOT# LGATE2
2
0R0402-PAD
PWR_VGA_CORE_SVD
PL8501 OPS
PR8512 1 2 5 26
[79] VGA_SVD SVD VDDP PWR_VGA_CORE_PHASE1 1 2
0R0402-PAD
6 25 PWR_VGA_CORE_VDD 1 2
PWR_VGA_CORE_VDDIO VDDIO VDD
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
IND-D33UH-7-GP-U
PC8509 SC1U10V2KX-1GP
1
PR8513 1 2 PWR_VGA_CORE_SVT 7 24 PWR_VGA_CORE_LGATE1 PWR_VGA_CORE_LGATE1
PT8506
SE330U2VDM-4-GP
PT8507
SE330U2VDM-4-GP
[79] VGA_SVT SVT LGATE1 68.R3310.201 OPS OPS
1
0R0402-PAD OPS PR8541
2
PR8514 1 2 PWR_VGA_CORE_ENABLE 8 23 PWR_VGA_CORE_PHASE1 2D2R3J-2-GP
PG8507
ENABLE
ISL62771HRTZ-GP-U
PHASE1 DY
PG8508
0R0402-PAD
2
PWR_VGA_CORE_PWROK 9 22 PWR_VGA_CORE_UGATE1
PWROK 74.62771.033 UGATE1
PC8510
2
PWR_VGA_SNUB1
OPS PR8515 SCD22U25V3KX-GP
1
PWR_VGA_CORE_IMON 10 21 PWR_VGA_CORE_BOOT1 1OPS 2PWR_VGA_CORE__BOOT1_1 1 2
PD8501
IMON BOOT1 OPS
1
K DY AEN/DEM_VGA PC8506 DY
[20,86] DGPU_PWR_EN
1
41 2D2R3F-L-GP SC330P50V2KX-3GP
PWR_VGA_CORE_PH1
GND
PWR_VGA_CORE_VO1
RB551VM-30TE-17-GP 3D3V_VGA_S0
2
1
PR8516 OPS PC8511
PGOOD
C C
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
[86] EN/DEM_VGA 133KR2F-GP SC1KP50V2KX-L-1-GP
NTC
RTN
1
OPS
FB
2
PE_GPIO1 is for PR8518

11
12
13
14
15
16
17
18
19
20
turning off PWR IC
1KR2J-1-GP
PWR_VGA_CORE_ISUMP
PR8517 79.33719.20C79.33719.20C
OPS 1 OPS 2
2
PWR_VGA_CORE_PGOOD 1 PR8520 2 3K65R2F-1-GP
PWR_VGA_CORE_NTC
PWR_VGA_CORE_ISEN2
PWR_VGA_CORE_ISEN1
PWR_VGA_CORE_ISUMP
PWR_VGA_CORE_ISUMN
PWR_VGA_CORE_VSEN
PWR_VGA_CORE_RTN
DGPU_PWROK [19,24,79]
0R0402-PAD
1
PWR_VGA_CORE_ISEN1 PR8519 1 2
PC8512 OPS
SC100P50V2JN-3GP 10KR2F-L1-GP
2
OPS OPS
PC8513 PWR_VGA_CORE_VSUM- PR8521 1 2 1R2F-GP
PR8523 SC1KP50V2KX-L-1-GP
PWR_VGA_CORE_FB 2 OPS 1 PWR_VGA_CORE_FB_R 1OPS2
301R2F-GP
PWR_VGA_CORE_ISEN2 PR8522 1OPS 2 10KR2J-L-GP
1
PC8514
OPS PWR_VGA_CORE_COMP 2
OPS
1
PR8525
1OPS 2 PWR_VGA_CORE_VSEN
PR8524
100KR2F-L3-GP
SC180P50V2JN-1GP
1K13R2F-1-GP
1st source: 075.06994.0037
2
PR8526
OPS1PWR_VGA_CORE_FB2_R1 PR8527 PC8516
2 OPS 2 1OPS 2 PWR_VGA_CORE_COMP_1 1 OPS 2
2nd source: 075.00998.0073 PWR_DCBATOUT_VGA_CORE2
1 PC8515 2KR2F-L1-GP SC330P50V2KX-3GP

PR8528 33KR2F-GP
SC330P50V2KX-3GP
32K4R2F-1-GP DY
PC8517
SCD22U10V2KX-L1-GP
PC8518
SCD22U10V2KX-L1-GP
PC8520
SC4D7U25V5KX-L2-GP
PC8532
SC4D7U25V5KX-L2-GP
PC8519
SC10U25V5KX-L-GP
PC8531
SC10U25V5KX-L-GP
PC8521
SCD1U25V2KX-GP
PU8504 PU8505
1
1
FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP
OPS OPS OPS OPS OPS OPS OPS
2
2 2
3 3
2
2
1 4 1 4
10 10
1
OPS 9 9
PR8529 7 65 BOM 7
2K61R2F-1-GP PR8530 1 2 PR8531 1OPS 2 10R2J-L-GP 8 6 8 6
0R0402-PAD 5 5
1VGA_VSUM-_1
PC8522
SCD022U25V2KX-DLGP
PC8523
SCD1U25V2KX-GP
2
B PC8501 VGA_VDD_RUN_FB_L 1 B
1
1
PR8532
11KR2F-L-GP
OPS DY OPS SCD01U50V2KX-L-GP

1OPS2
TP8501
ZZ.00215.037 ZZ.00215.037
2
PC8524
2
SC330P50V2KX-3GP
PR8533 1DY 2
NTC-10K-29-GP-U VGA_VDD_RUN_FB_H 1
TP8502 PWR_VGA_CORE_UGATE2
OPS 1 PR8534 2 PR8535 1OPS 2 10R2J-L-GP
VGA_CORE
0R0402-PAD
PR8536
2
PWR_VGA_CORE_VSUM- 1OPS 2
1K65R2F-GP
1
PC8525
VGA_CORE
OPS SCD1U25V2KX-GP
PL8502 OPS
2
PWR_VGA_CORE_PHASE2 1 2
PWR_VGA_CORE_PWROK 1 PR8544 2 IND-D33UH-7-GP-U
1
PWR_VGA_CORE_LGATE2
PWR_VGA_CORE_PGOOD
0R0402-PAD 68.R3310.201
PR8542 PC8534 PC8535
1
2D2R3J-2-GP DY PG8509 PG8510
2
GAP-CLOSE-PWR-3-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
79.33719.20C PT8508OPS OPS
SE330U2VDM-4-GP
GAP-CLOSE-PWR-3-GP
2
2
PWR_VGA_SNUB2
OPS
1
1
PC8533
SC330P50V2KX-3GP
PWR_VGA_CORE_PH2
DY
PWR_VGA_CORE_VO2
2
PR8539 1 DY 2 PWR_VGA_CORE_EN_R#
3D3V_S5
100KR2J-1-GP
6
PQ8501
2N7002KDW-GP VGA_CORE PR8537
PWR_VGA_CORE_ISUMP 1
A DY OPS 2 A
3K65R2F-1-GP
1
DY PR8545 PWR_VGA_CORE_ISEN2PR8538 1 2
100R2J-L-GP OPS
10KR2F-L1-GP
2
<Core Design>
EN/DEM_VGA PQ8206_3 PWR_VGA_CORE_VSUM- 1 2
PR8540 OPS
1R2F-GP Wistron Corporation
PWR_VGA_CORE_ISEN1 PR8543 1OPS 2 10KR2J-L-GP Taipei Hsien 221, Taiwan, R.O.C.
Title
Flash/RTC
A2
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
3D3V_S0 to 3D3V_VGA_S0 Transfer GPU PWR Sequencing

1D8V_S5 1D8V_VGA_S0
PQ8607
DMP2130L-7-GP
0926 Modify PC8502 voltage 400mA OPS
3D3V_S0 3D3V_VGA_S0 S
3D3V_VGAS0
3D3V_S5 1D8V_VGA_S0 D
1
PR8601 1 2 0R2J-2-GP
D
PC8635
SCD1U25V2KX-1-DL-GP
DY 25mA
G
3D3V_VGA_S0 OPS PR8650 DY PC8634
=> 0D95V_VGA_S0/1D8V_VGA_S0
1
OPS 10KR2J-L-GP SC1U10V2KX-1GP DY PC8636
G
S D
SCD1U16V2KX-3GP
2
2
084.03419.0031 OPS
=> 1D5V_VGA_S0
2
1
D PQ8609 D
PC8604
PC8605
PC8603
SCD1U16V2KX-3GP
1
1
PJA3419-GP PR8651 1OPS 2 1D8V_VGA_EN_R#
PR8606
100KR2J-1-GP
DY DY DY 2K2R2J-L1-GP
PR8619
100KR2J-1-GP
OPS 3D3V_VGA discharge
G
=> VGA_CORE
1
DY DY PC8601 84.02130.031
2
1
SCD1U16V2KX-3GP PQ8608
2
0D95V_VGA_EN PR8603 1OPS 2 1D8V_VGA_EN G
DY PR8609 OPS 2nd = 84.00102.031
2
75R2F-2-GP 1KR2J-1-GP
1
3.3V_ALW_1 PC8612 D 1D8V_VGA_EN#
OPS SCD22U10V2KX-L1-GP
3rd = 84.03413.B31
All the ASIC supplies must reach their respective nominal
3.3V_RUN_VGA_1 2
SC22U6D3V3MX-1-DL-GP S
voltages withing 20ms of the start of the ramp-up sequence,
2
6
4
2N7002K-2-GP
PQ8604 though a shorter ramp-up duration is preferred. The maximum
2N7002KDW-GP OPS slew rate on all rails is 50mV/us.
3
It is recommended that the 3.3V rail ramp up first.
It is recommended that the 0.95V rail reach at least 90% of its

PR8661 1OPS 2 DGPU_PWR_EN_R
[20,85] DGPU_PWR_EN
10KR2J-L-GP High Active normal value no later than 2ms from the start of VDDC ramping
up.
1
OPS PC8602
SCD47U25V3KX-1GP
PWR_0D95V_PVDD 3D3V_S5
C C
PG8601
2 1
SYW232 for 0.95V_S5
1
PC8621 PC8622 PC8623 GAP-CLOSE-PWR
DY PG8602
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC1U10V2KX-1GP
OPS OPS 2 1
2
DCBATOUT PWR_DCBATOUT_1D35V
PG8651 3D3V_S5 GAP-CLOSE-PWR
GAP-CLOSE-PWR-3-GP
1 2
PC8655
SC1U10V2KX-1GP
1
OPS PU8601 Design Current =1.35A

PG8652 MagLayer. 6.86 x 6.47 x 3.0mm
GAP-CLOSE-PWR-3-GP PR8674 PC8656 5 3
DCR: 5~5.5mOhm NC#5 IN
2
1 2 0R0603-PAD-1-GP-U SCD1U25V2KX-GP
PWR_1D35V_BOOT 1 2 PWR_1D35V_BOOT_A 1 2
OPS Idc :15.5A , Isat : 25A design current = 3.56A OPS PWR_0D95V 0D95V_VGA_S0
PL8651 3D3V_VGA_S0 8 1 PWR_0D95V_FB
PWR_1D35V_VCC 1D35V_VGA_S0 SGND FB 0D95V_VGA_S0_PG PL8601
PU8651 IND-D68UH-36-GP-U 2 PG8603
4 PG 6 PWR_0D95V_PHASE 1 2 1 2
OPS PGND LX OPS
1
PWR_1D35V_VCC 17 6 PWR_1D35V_PH 1 2 9 7 0D95V_VGA_EN_R
VCC LX#6 19
OPS PR8625 PGND EN GAP-CLOSE-PWR
LX#19 IND-1UH-281-GP
1
1
15 20 10KR2J-L-GP PG8604
R1
PC8657
PC8658
PC8659
PC8660
PC8661
BYP LX#20 68.R681A.10A
1
OPS PC8654 OPS OPS OPS OPS DY OPS SYW232DFC-GP PR8622 OPS PC8624 1 2
PWR_DCBATOUT_1D35V SC2D2U10V3KX-L-GP 2 10 PWR_1D35V_PG 74.00232.033 30K1R2F-L-GPOPS
IN#2 NC#10
2
2
2
SC22P50V2JN-4GP
3 12 GAP-CLOSE-PWR
IN#3 NC#12
2
4 16 PWR_1D35V_VCC PG8653
IN#4 NC#16
2
5 GAP-CLOSE-PWR-3-GP 0D95V_VGA_EN PR8621 1 2
IN#5 0R0402-PAD PC8625 PC8626
PC8651
SCD1U25V2KX-GP
PC8652
SC10U25V5KX-L-GP
1
1
1
PWR_1D35V_EN 11 7 PWR_0D95V_FB
OPS OPS PWR_1D35V_BOOT 1 EN GND 8 SC22U6D3V3MX-1-DL-GP
DY PC8607
SCD1U16V2KX-3GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
PWR_1D35V_PG 9 BS GND 18 SC22U6D3V3MX-1-DL-GP
PG GND OPS OPS
2
2
PWR_1V35V_ILMT 13 21 PWR_1D35V_FB_A SC22U6D3V3MX-1-DL-GP
ILMT GND
1
PWR_1D35V_FB 14 SC22U6D3V3MX-1-DL-GP
FB SC22U6D3V3MX-1-DL-GP
R2
1
PR8623 OPS
1
SY8286RAC-GP PC8662 PR8675 51K1R2F-GP

PR8673 074.08286.0B43 SC470P50V2KX-L-GP OPS OPS 24K9R2F-L-GP
2
100KR2J-1-GP
2
3D3V_S5
1OPS 2
2
VOUT=0.6*(1+(R1/R2)) Close Pin1

1
PR8676
16K5R2F-2-GP
Vo=0.6x(1+R1/R2)
B OPS =0.6x(1+30.1/51.1) B
PG8655 PR8677 1 DY 2 PWR_1D35V_VCC

=0.953
2
GAP-CLOSE-PWR-3-GP 0R2J-2-GP
0D95V_VGA_S0_PG 1 2 D8601
1
0D95V_VGA_EN_R 2
PR8671
0R0402-PAD-1-GP 3 3.3V_RUN_VGA_1 3D3V_S5
OPS
1
1D8V_VGA_EN 1
PR8672
1MR2J-1-GP
1
EN rating 23V OPS D8602
2 BAT54C-12-GP PR8624
EN Rising Threshold : 0.8V [85] EN/DEM_VGA
10KR2J-L-GP
ILIM LOW , ILIM=6.5A 75.00054.A7D
2
3 3.3V_RUN_VGA_1
ILIM FLOAT , ILIM=9.5A OPS OPS
ILIM HIGH , ILIM=12.5A
2
PWR_1D35V_EN 1
0D95V_VGA_S0_PG
BAT54C-12-GP
75.00054.A7D 2015/02/09 modify
For power down sequence
2015/02/09 modify
A A
<Core Design>
Wistron Corporation
Title
GPU Discrete Power

5 4 3 2 1
5 4 3 2 1
Main Func = UnusedParts

H11
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 HT85B85X925R29-S-GP H12 H13 H14 H15 H16 H17
HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP HOLE335R115-GP HT85B85X925R29-S-GP HOLE276R91-GP HT85BE95R29-U-5-GP HOLE384X421R115-GP
1
1
1
ZZ.00PAD.D81 ZZ.00PAD.D01 ZZ.00PAD.D01 ZZ.00PAD.D81 ZZ.00PAD.CZ1 ZZ.00PAD.D31 ZZ.SCREW.681
ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.7F1 ZZ.00PAD.D01 ZZ.00PAD.D01
D D
DCBATOUT 0927 Change acoustic solution

0502 Changed PN 0512 Deleted HS2 1101 Change acoustic solution
SPR1 SPR2 SPR3 SPR5 SPR4
SPRING-63-GP SPRING-63-GP SPRING-63-GP SPRING-63-GP SPRING-43-GP-U HS1
STF237R128H128-3-GP
1
DY PT8901 OPS PT8902
SE33U25VM-11-GP ST100U25VDM-1-GP
2
Spring Spring Spring Spring Spring
1
1
34.4LO45.201
1
34.4Y806.001 34.4Y806.001 34.4Y806.001 34.4Y806.001 34.15J03.001
2nd = 34.4LO45.301
For acoustic noice
For RF solution DVT1 3/2

Main Func = EMI & RF Capacitors 3D3V_S0 5V_S0 +VCCGT 1D35V_VGA_S0 AUD_AGND VGA_CORE
EC9745
SC1KP50V2KX-L-1-GP
Mind the voltage rating of the caps.
FC9702
FC9703
FC9704
SCD1U25V2KX-GP
FC9706
FC9707
FC9708
EC9727
EC9725
EC9726
EC9730
EC9728
EC9729
EC9731
EC9739
EC9744
EC9743
EC9746
EC9750
EC9751
EC9752
EC9753
1
1
C
DCBATOUT
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY C
2
EC9701
EC9702
EC9703
EC9704
EC9705
EC9706
EC9707
EC9708
EC9709
EC9710
1
DY DY DY DY SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP

SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP
2
SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SCD1U25V2KX-GP SCD1U25V2KX-GP

SC1U10V2KX-1GP
SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-L-1-GP

SCD1U25V2KX-GP
0921 Uninstall
1D2V_S3 3D3V_S5
0921 Uninstall 0921 Install

EC9712
EC9713
EC9715
EC9716
EC9717
EC9711
EC9714
1
DY DY
EC8901
EC8902
EC8903
EC8904
EC8905
EC8906
EC8907
EC8908
EC8909
EC8916
EC8917
EC8918
EC8919
EC8920
EC8921
EC8922
EC8923
EC8924
EC8925
EC8926
EC8927
EC8928
2
1
DY DY DY DY DY
2
2
B SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-L-1-GP B
SCD1U25V2KX-GP
SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP
SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP
5V_S0 SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC8910
EC8911
EC8912
EC8913
EC8914
EC8915
1
1
EC9718
EC9719
EC9720
EC9721
EC9722
EC9723
EC9724
DY DY
1
DY DY
2
2
2
SCD1U25V2KX-GP SCD1U25V2KX-GP
SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP
SCD1U25V2KX-GP
3D3V_S0 5V_S5 DCBATOUT

EC9735
EC9736
EC9737
EC9738
EC9732
EC9733
EC9734
EC9741
EC9742
EC9747
EC9749
EC9740
EC9748
A <Core Design> A
1
DY DY DY DY
Wistron Corporation
2

SCD1U25V2KX-GP SCD1U25V2KX-GP SCD1U25V2KX-GP SC1KP50V2KX-L-1-GP Title

SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SC1KP50V2KX-L-1-GP
UNUSED PARTS/EMI Capacitors
SCD1U25V2KX-GP SCD1U25V2KX-GP Size Document Number Rev
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
SSID = TPM
3D3V_S5
??? RTC Gen9 power 3D3V_TPM
R1
TPM_65x
R9149 1 2
0R2J-2-GP
C9114
SC2200P50V2KX-2GP
C9115
SC2200P50V2KX-2GP
C9116
SCD1U16V2KX-3GP
1
1
3D3V_S0
D
DY DY TPM D
R9150 1 2
2
0R0402-PAD-2-GP
R2
0523 Change to 0402
0920 Change to Pad
3D3V_S0 3D3V_S5
TPM IC Mounted Unmounted
R9140 1TPM 2
0R0402-PAD-2-GP C9109
R9145
3D3V_TPM
1
10KR2J-L-GP
NPC65x R1 R2
R9146
0R2J-L-GP
DY
R9130 1 2 0R0402-PAD SPI_CS2#_R_TPM2
[18] SPI_CS_ROM_N2
NPC75x R2 R1 R9132 1 2 33R2J-2-GP SPI_SO_ROM_TPM2
[18,25] SPI_SO_ROM TPM
2
R9133 1 2 33R2J-2-GP SPI_SI_ROM_TPM2
C
[18,25] SPI_SI_ROM
R9138
TPM
1 2 33R2J-2-GP SPI_CLK_ROM_TPM2
C
[18,25] SPI_CLK_ROM TPM
SC4D7U6D3V3KX-GP
C9112
SCD1U16V2KX-3GP
1
1
modify 0.1u->4.7u
TPM TPM
20160627(DVT1)
2
modify from 3D3V_S5_PCH to 3D3V_S5
20160909(DVT2)
U9103 3D3V_S0
+UZ12_TPM 8 29 TPM_GPIO0 R9121 1TPM 2

VDD SDA/GPIO0 30 10KR2J-L-GP
3D3V_S5 3D3V_TPM_1 TPM_VDD14 14 GPIO1/SCL 3 TPM_GPIO2 R9120 1 DY 2
22 VHIO GPX/GPIO2 6 10KR2J-L-GP
VHIO GPIO3/BADD 13 TPM_GPIO4 R9122 1 DY 2 SPI_CS2#_R_TPM2
R9143 1 2 R9144 1 2 TPM_VSB 1 CLKRUN#/GPIO4/SINT# 2K2R2J-L1-GP
0R0402-PAD-2-GP 0R0402-PAD-2-GP VSB 12
RESERVED#12
C9106
SC4D7U6D3V3KX-GP
C9108
SCD1U16V2KX-3GP
1
SPI_SO_ROM_TPM2 24 2
TPM TPM SPI_SI_ROM_TPM2 21 LAD0/MISO NC#2 7
PIRQA# R9152 1 2 SPI_IRQ#_TPM2 18 LAD1/MOSI NC#7 10
B TPM B
2
LAD2/SPI_IRQ# NC#10
2
0R0402-PAD-2-GP 15 11
LAD3 NC#11 25
PLT_RST# R9136 1 2 PLT_RST#_Q_TPM2 17 NC#25 26
0R0402-PAD-2-GP SPI_CLK_ROM_TPM2 19 LRESET#/SPI_RST#/SRESET# NC#26 31
SPI_CS2#_R_TPM2 20 LCLK/SCLK NC#31
SERIRQ_TPM 27 LFRAME#/SCS#
28 SERIRQ 9
LPCPD# GND
1
3D3V_TPM 16
GND 23
R9147 1 2 TPM_VDD14
TPM R9141
10KR2J-L-GP 4 GND 32
0R0402-PAD-2-GP 0512 Deleted C9110 5 PP GND 33
0523 Modify C9113 TEST GND
TPM_65x
2
C9107
SCD1U16V2KX-3GP
C9111
SCD1U16V2KX-3GP
C9113
SC4D7U6D3V3KX-GP
TPM TPM
1
NPCT750JAAYX-GP
071.00750.0003 <Core Design>
2
A
Title
[17,31,55,61,63,76] PLT_RST# TPM

A4
[16] PIRQA# Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
SSID = Finger Print
R9203 1 2 0R0402-PAD-2-GP USB_PN8_C

D
[16] USB_CPU_PN8 D
R9204 1 2 0R0402-PAD-2-GP USB_PP8_C
[16] USB_CPU_PP8
0524 Follow new FPR pin define

3D3V_S0 FPR1
8
6
0R0402-PAD-2-GP C9202
R9202
1
5
USB_PP8_C 4
USB_PN8_C 3
2
FPR
2
C FP_PWR 1 C
7
SC1U10V2KX-1GP
C9201
SCD1U16V2KX-3GP
1
FPR FPR HRS-CON6-15-GP

020.K0237.0006
2
2nd = 020.K0002.0006
For EMI Reserved

USB_PN8_C
USB_PP8_C
ED9201
USB_PP8_C 1 6 USB_PN8_C
I/O1 I/O4
2 5
EC9201
SC22P50V2JN-4GP
EC9202
SC22P50V2JN-4GP
B 3D3V_S0 B
GND VDD
1
DY DY 3
DY 4
I/O2 I/O3
2
AZC099-04S-2-GP
075.09904.0A7C
Layout Note:
close to FPR1
AFTE14P-GP AFTP8902 1 FP_PWR

AFTE14P-GP AFTP8903 1 USB_PN8_C <Core Design>
AFTE14P-GP AFTP8904 1 USB_PP8_C
A
Title
Finger Print
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
D D
PCH_JTAG_TMS test point

XDP_TMS
PCH_JTAG_TDI test point

XDP_TDI
XDP_TCLK test point

XDP_TCK_JTAGX
XDP_TDO_CPU test point
PCH_JTAG_TDO
C C
B B
<Core Design>
A
Title
Debug (XDP debug)
A4
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
CLK Block Diagram
Intel CPU
D
KBL-R D
M_A_CLK0
CK0_T DDR0_CKP[0]
M_A_CLK0#
CK0_C DDR0_CKN[0]
DDR4 DIMM1
M_A_CLK1
CK1_T DDR0_CKP[1]
M_A_CLK1#
CK1_C DDR0_CKN[1]
PEG_CLK1_CPU
CLKOUT_PCIE_P1 REFCLKP0
M_B_CLK0
WLAN
CK0_T
M_B_CLK0#
DDR1_CKP[0]
CLKOUT_PCIE_N1
PEG_CLK1_CPU#
REFCLKN0 NGFF
CK0_C DDR1_CKN[0]
DDR4 DIMM2
M_B_CLK1
CK1_T DDR1_CKP[1]
M_B_CLK1#
CK1_C DDR1_CKN[1]
LAN
PEG_CLK2_CPU
RTL8106E/RTL8111G
CLKOUT_PCIE_P2 REFCLK_P
CLKA0 PEG_CLK2_CPU#
C CK CLKOUT_PCIE_N2 REFCLK_N C
VRAM1 CK#
CLKA0b GPU
AMD R17-M1-30 LANXIN
CKXTAL1
CLKA0 PEG_CLK_CPU#
CK ‧ CLKA0 PEX_REFCLK# CLKOUT_PCIE_N0
CLKA0b
VRAM2 CK# ‧ CLKA0# X3001
25MHz
PEG_CLK_CPU
PEX_REFCLK CLKOUT_PCIE_P0
LANXOUT
CKXTAL2
CLKA1
CK 27MHZ_IN
XTAL_IN
VRAM3 CK#
CLKA1b
X7901
27MHz
HDA_BITCLK /
Audio
CK
CLKA1
CLKA1b ‧ CLKA1
27MHZ_OUT
HDA_BCLK/I2S0_SCLK HDA_CODEC_BITCLK
HDA_BITCLK_CODEC_R
BIT-CLK Realtek
VRAM4 CK# ‧ CLKA1# XTAL_OUT R2723
22R2J ALC3223
KBC
B B
RTC_X1
RTCX1
MEC1416-NU-D0-GP
ESPI_CLK_CPU ESPI_CLK
GPP_A9/CLKOUT_LPC0/ESPI_CLK GPIO034/PCI_CLK/ESPI_CLK
X1901
32.768KHz R1804
15R2F
RTC_X2
RTCX2
XTAL24_IN
XTAL24_IN
X1801
24MHz
XTAL24_OUT
XTAL24_OUT
A A
<Core Design>
Wistron Corporation
Title
CLK Block Diagram
A2
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
Change notes -
DATE VERSON DATE Page Modify List OWNER
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
Change History
A3
Vegas SKL/KBL-U A00
5 4 3 2 1
5 4 3 2 1
KBL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform] POWER UP SEQUENCE DIAGRAM (NON Deep Sx Platform)
a b c d e f g h i
Red: Power Rail
Orange: Output from KBC
Light Blue: Output from CPU
1 2 3a 4 4a 4b 5 6 7 8 8a 8b 9 10
DC SI7121DN-T1-GE3
BT+ Page43
Battery
a Page43 Page43
V8P10-5300M3-86A d
AC +DC_IN AON7403
a Adapter in
Page43
3V_5V_EN
Page43
AD+
e
D EN1 EN2 D
3D3V_S5
Charger
DCBATOUT TPS51225RUKR
ISL88739 VIN
DC/DC
(3.3V/5V) 5V_S5
ACOK Page44 3 5
Page45 DDR_VTT_PG_CTRL Level SM_PGCNTL_R
b PWR_CHG_ACOK
Shifter
3D3V_AUX_S5 f
PR4474 d
SIO_SLP_S4#
SIO_SLP_S3#
Page44 R2446 3V_5V_POK
3V_5V_EN Page24
R4009
ALWON
c SLP_S4# SLP_S3# DDR_PG_CTL
VCI_OUT/
GPIO036
KBC_PWRBTN#
VCI_IN0#/ DPWROK
GPIO163 GPIO34
1
The DSW rails must be stable for at least
10 ms before DSW_PWROK is asserted to PCH.
PCH_RSMRST#
GPIO66 DSW_PWROK
f PM_RSMRST#
ACOK_IN b VCI_OVRD_IN/
GPIO164 GPIO20
RSMRST#
KBL-R
SIO_PWRBTN#
RSMRST_PWRGD#
TBD KBC 2 PWRBTN#
h ALL_SYS_PWRGD and VR_RDY assert,
MEC1416
Delay 10ms
delay 10ms; PCH_PWROK assert.
RSMRST#_KBC: Delay 10 ms after receive
RSMRST_PWRGD# and PM_SLP_SUS#. 8b
AND
RSMRST#_KBC RESET_OUT# SIO_SLP_S0#
GPIO36 GPIO107 PCH_PWROK SLP_S0#
ALL_SYS_PWRGD assert, PM_SUSWARN# 9

delay 10ms; PCH_PWROK assert. GPIO02 SUSWARN# PROCPWRGD
ALL_SYS_PWRGD
7 GPIO57 i
GPIO81 SUSACK#
PLTRST# 10 PCH_PLTRST#
It is recommended that SYS_PWROK be asserted after AND

both PWROK assertion and processor core VR PWRGD assertion.
PM_SLP_S4#
GPIO44
3
PM_SLP_S3# 8d
4 GPIO01 H_VCCST_PWRGD ALL_SYS_PWRGD
C VCCST_PWRGD
Level Shifter C
8c SYS_PWROK
74LVC1G07GW Page17
GPIO141 SYS_PWROK
Page24
EXT_PWR_GATE#
PWR_VDDQ_PG 7
EXT_PWR_GATE#
e 6 ALL_SYS_PWRGD
ALL_SYS_PWRGD assert, SLP_SUS#
delay 100ms; SYS_PWROK assert. RSMRST_PWRGD#
h DY
SIO_SLP_SUS#
DS3
3D3V_S5
SVID Transanctions
IMVP8
Vin CPU SVID Rails
3D3V_S5_PCH 6 PWR_VDDQ_PG SA/Core/GT/GTx
PCH_ALW_ON EN SW VR_ON
VR_RDY
SY6288C10CAC VR_READY
(DS3) Page41 8a
PWR_DCBATOUT_1D0V
1D0V_S5
VIN
Vin
1D0V_PWR
3V_5V_POK RSMRST_PWRGD# 3V_5V_POK LX
APE8939GN3
f 0R 0402 EN
AOZ2262QI 1D0V_S5_PWRGD 5 SIO_SLP_S3# +VCCIO +VCCSTG
h f PGOOD EN SW 0R 0402
g
1D8V_S5_PWROK
0R 0402 Page53 g
Page40
1D0V_S5_PWRGD
0R 0402 DY
g 1D0V_PWR VCCPRIM_CORE
0R
5V_S5 3D3V_S5
1D0V_S5 5V_S5
3D3V_S5 5V_S5
Vin1 Vin2
3 4 5V_S0
Vin VDD
5 SIO_SLP_S3# AP22966DC8 VOut1 3D3V_S0
Vin VCNTL SIO_SLP_S4# EN VOut2
3V_5V_POK EN SW +V1.00U_CPU(VCCST)
1D8V_S5
f
EN Vout
APE8939GN3 Page40
APL5930KAI 1D8V_S5_PWROK
PGOOD Page40
Page54 g
B B
3D3V_S5
1D8V_S5 +V1.8A_SIP
0R
3 4a
Vin
SIO_SLP_S4# 2D5V_S3
LX
EN
APL5930KAI PWR_2D5V_PG
PGOOD
Page54 4b
4b 4c
AMD GPU Power sequence
PWR_2D5V_PG 1D2V_S3
For DDR4 power sequence S5
RT8231AGQW
SIO_SLP_S3# 0D6V_S0
S3
3D3V_VGAS0 2D5V_S3 PWR_VDDQ_PG
=> 0D95V_VGA_S0/1D8V_VGA_S0 5 PGOOD
Page51
=> 1D5V_VGA_S0 1D2V_S3 6
20ms
=> VGA_CORE
All the ASIC supplies must reach their respective nominal
voltages withing of the start of the ramp-up sequence, 0D6V_S0
though a shorter ramp-up duration is preferred. The maximum
slew rate on all rails is 50mV/us.
It is recommended that the 3.3V rail ramp up first.
It is recommended that the 0.95V rail reach at least 90% of its
normal value no later than 2ms from the start of VDDC ramping
up.
3D3V_VGA_S0
0D95V_VGA_S0/
1D8V_VGA_S0
1D5V_VGA_S0
VGA_CORE
A A
<Core Des ign>
Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.
Title
Size
Power Sequence
Docum ent Num ber Rev
A0
Vegas SKL/KBL-U A00
Date: Wednes day, Novem ber 08, 2017 Sheet 102 of 105
5 4 3 2 1
5 4 3 2 1
DCBATOUT
Adapter EN/DEM_VGA 0D95V_VGA_S0_PG VR_EN
3V_5V_POK
2D5V_PWROK EN EN
EN
RT8231AGQW EN(S5) ISL62771HRTZ SY8288RAC-GP EN AOZ2262QI-10
51
EN(S3) SM_PGCNTL 86 86
ISL95859AHRTZ 46
53
Charger CSD97396Q4M 48
CSD97396Q4M 47
ISL95808HRZ 50
D Battery ISL88739HRZ VGA_CORE 1D35V_VGA_S0 D
BT+ 0D6V_S0 1D2V_S3

44
+VCCSA +VCCGT VCC_CORE
0 ohm
0 ohm 0 ohm
3V_5V_EN +VDDQ_CPU_CLK
GTX_CORE GT_CORE
EN
TPS51225RUKR 45
5V_S5 3D3V_S5
USB_PWR_EN# PM_SLP_S3# PM_SLP_S3#
SIO_SLP_S4# 3V_5V_POK 3D3V_VGA_S0 PM_LAN_ENABLE
EN EN EN
C SY6288DAAC x2 AP22966DC8 EN EN EN EN
C
35
40
APL5930KAI APL5930KAI SYW232DFC 86
0 ohm DMP2130L
51 54 31
5V_S0 3D3V_S0
USB20_VCCA 2D5V_S3 1D8V_S5 0D95V_VGA_S0 3D3V_S5_PCH 3D3V_LAN_S5
USB30_VCCC 3D3V_S5_KBC
+VCCPDSW_3P3
DGPU_PWR_EN 3D3V_VGA_S0
0 ohm
EN EN
RT9724GB 55 PJA3419 0 ohm 0 ohm DMP2130L
86 86
1D0V_S5
ODD_PWR_5V
TPAN_VDD
5V_HDMI_S0 LCDVDD 3D3V_VGA_S0 +V1.8A_SIP 1D8V_VGA_S0 APE8939GN3
5V_HDD_S0 +3V_1D8V_DVDD 40
+5V_AVDD VDD_DAC_33 0 ohm APE8939GN3 0 ohm
+5V_PVDD AVCC33 41 42
3D3V_WLAN_S0
3D3V_CAMERA_S0
+V1.00U_CPU
B
+VCCPRIM_CORE +VCCIO +V1.00A_SIP B
0 ohm
0 ohm 0 ohm
+VCCST_CPU
+VCCSTG +VCCAPLL_1P0
0 ohm
+VCCMPHYGTAON_1P0_LS_SIP
+VCCAMPHYPLL_1P0
A A
<Core Design>
Power Shape Wistron Corporation

Title
Regulator LDO Switch
Power Block Diagram
Custom
Vegas SKL/KBL-U A00
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram 3D3V_S0

KBC SMBus Block Diagram
3D3V_S5_PCH
‧ TP_VDD
‧
3D3V_S0 SRN10KJ-5-GP
‧
SRN2K2J-1-GP SMBus Address:0xA0/0xA1
1 ‧ 1
DIMM 1 SRN10KJ-5-GP
TouchPad Conn.
GPP_C0/SMBCLK MEM_SMBCLK PCH_SMBCLK SCL
‧ ‧
GPP_C1/SMBDATA MEM_SMBDATA
‧ ‧ PCH_SMBDATA SDA
GPIO114/PS2_CLK0 CLK_TP_SIO
SRN33J
TPCLK_C TPCLK
‧
SMBus Address:0xA0/0xA1 GPIO115/PS2_DAT0 DAT_TP_SIO
‧ TPDATA_C TPDATA
2N7002SPT
DIMM 2 3D3V_AUX_KBC
‧PCH_SMBCLK SCL
‧ PCH_SMBDATA SDA
‧
3D3V_S5_PCH
SRN4K7J-8-GP
TPAD
‧
‧
PCH_SMBCLK
PCH_SMBDATA
SCL
SDA GPIO010/SMB01_CLK/SMB01_CLK18
SRN100J Battery Conn.
‧ ‧ SMBCLK1 PBAT_SMBCLK1 CLK_SMB
SMBus address:16
SRN2K2J-1-GP GPIO007/SMB01_DATA/SMB01_DATA18
‧SMBDA1 PBAT_SMBDAT1 DAT_SMB
LNG2DMTR
ISL88739
GPP_C3/SML0CLK SML0_SMBCLK
PCH_SMBCLK SCL/SPC
2 GPP_C4/SML0DATA SML0_SMBDATA ‧ 2
PCH_SMBDATA SDA/SDI/SDO
‧ SCL
MEC1416 SDA SMBus address:12
RTD2166
PCH_SMBCLK SMB_SCL
PCH_SMBDATA SMB_SDA(Janus Only)

0R2J
SMBCLK2 GPIO013/SMB02_CLK/SMB02_CLK18
SMBDA2 GPIO012/SMB02_DATA/SMB02_DATA18
PCH 0R2J
3D3V_VGA_S0 SMBus Address:
0x94/0x95/0x96/0x97
3D3V_S5_PCH
SMBus Address:0x9E/0x9F
‧SRN4K7J-8-GP
3D3V_VGA_S0
SRN2K2J-8-GP
‧
dGPU
GPP_C6/SML1CLK
‧ ‧SML1_SMBCLK SMB_CLK_VGA
‧
SMBCLK
3 3
GPP_C7/SML1DATA
‧ ‧ SML1_SMBDATA SMB_DATA_VGA
‧
SMBDATA
SMBus Address:0x82/0x83
SMBus Address:0x98/0x99
SCL Thermal GPU T8
SDL
NCT7718W
3D3V_S0 5V_S0
‧ ‧
3D3V_S0
SRN2K2J-1-GP SRN2K2J-1-GP
‧
GPP_E18/DDPB_CTRLCLK CPU_DP1_CTRL_CLK DDC_CLK_HDMI
‧ ‧
GPP_E19/DDPB_CTRLDATA
‧CPU_DP1_CTRL_DATA ‧‧ DDC_DATA_HDMI
‧ HDMI CONN
2N7002DW-1-GP
4 4
<Core Design>
Wistron Corporation
Title
SMBUS Block Diagram

A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

3D3V_S5_PCH 3D3V_S0
Thermal
1 1
SPKR_L+
SPKR_L-
NCT7718 EN
3V/5V
Codec SPKR_R-
SPKR_R+ SPEAKER
PCH PURE_HW_SHUTDOWN# ALC3204
SML1CLK/GPIO75 SML1_CLK SCL
‧ ‧SMB_CLK_VGA_R
2N7002
T_CRIT# GPU_T_CRIT# 2N7002 AUD_HP1_JACK_L
SML1DATA/GPIO74 SML1_DATA
‧ ‧ SMB_DATA_VGA_R SDA
AUD_HP1_JACK_R HP MIC
SLEEVE
COMBO
0R2J
0R2J
RING2
SMBDA2
SMBCLK2
Put under CPU(T8 HW shutdown)

DMIC_DATA_R R2714 DMIC_DATA
GPIO012/SMB02_DATA/SMB02_DATA18 GPIO0/DMIC-DATA12
2
GPIO013/SMB02_CLK/SMB02_CLK18
SMBCLK VGA GPIO1/DMIC-CLK DMIC_CLK_R
0R2J-2-GP
R2716 DMIC_CLK
HDMI
2
KBC SMBDATA R17M-M1-30 0R2J-2-GP
MEC1416
GPIO056/PWM3 GPIO050/TACH0
FAN_TACH1
FAN1_DAC_1
TACH
3 3
FAN
VIN
FAN_VCC1
5V
VIN VSET VOUT
FAN CONTROL
APL5606AKI <Core Design>
4 4
Wistron Corporation
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
Vegas SKL/KBL-U A00
A B C D E

Vegas Sklkbl-U 17841-1 Rev A00

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5 4 3 2 1

DY : None Installed <Core Design>

OPS: DISCRTE OPTIMUS installed Title

25W Kabylake-U 4+2 NCP81382MNTXG x 2

(TURIS only) USB2.0 x1 10 USB 2.0/1.1 ports

ACPI 5.0 USB2.0 x1 BT V4.0 combo CPU VCCPRIM_CORE

Kyloren EOPIO/EDRAM (23e)

SPI Flash ROM Vegas

Vegas USB3(USB2.0) USB2.0 x1 <Core Design>

Main Func = CPU

#544669 CRB Rev0.52

+VCCSTG = 1.0 V XDP_TMS R421 1 2 51R2J-2-GP

M1,2,3,4,5: <3 inches

Main Func = CPU

M _A_DQS_DN[7:0] [12] M _B_DQS_DN0 M _B_DQS_DN[7:0] [13]

M _B_DQS_DP0 M _B_DQS_DP[7:0] [13]

Main Func = CPU C PU1S 19 OF 20

1 R SVD_F65 F65 AW71 R SVD_TP_AW 71 1 T P614 TPAD14-OP-GP

PCH strap pin:

DISPLAY PORT PRESENCE STRAP

CFG TERMINATIONS #544669 Rev0.52 (CRB)

Main Func = CPU

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Main Func = CPU

E55 SKYLAKE_ULT C47

(#543016) eDP_RCOMP Guideline 0 = Port B is not detected.

PU to 3.3 V with 2.2-k

Main Func = CPU

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC10U6D3V3MX-GP SC4D7P50V2BN-GP SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

PC1091 PC1092 PC1093 PC1094 PC1095 PC1096 PC1053 PC1065

SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP

Main Func = CPU

SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP

C1174 near N15

C1173 near AF20

A SC1U10V2KX-1GP SC1U10V2KX-1GP SC22U6D3V3MX-1-GP A

Main Func = DDR4 SODIMM

1D2V_S3 0D6V_S0 0D6V_S0 0D6V_S0

???跟sw確認 DDR4 SWAP 0212

R1211 1 2 10KR2F-L1-GP SA2_CHA_DIM0 SC4D7U6D3V2MX-1-GP SC1U10V2KX-1GP

Main Func = DDR4 SODIMM

R1302 1 2 10KR2F-L1-GP SA0_CHB_DIM0

3D3V_S0 SC10U6D3V3MX-GP SC10U6D3V3MX-GP

SC1U10V2KX-1GP SC1U10V2KX-1GP M_B_DQS_DP6

Main Func = PCH

Main Func = PCH

F5 AG4 R1602 1 2 0R0402-PAD

TPAD14-OP-GP TP1602 PIRQA# BB11 B9 USB_OC3#

PCIE Table USB 2.0 Table

1 N/A USB3.0_3 0 USB3.0 port1

2 N/A USB3.0_4 1 USB3.0 Port2

3 WLAN 2 USB2.0 Port3 (IOBD)

5(L0~L3) GPU 4 CAMERA

6(L3) HDD SATA0 5 Card Reader

6(L2) ODD SATA1 6 Touch Panel