5 4 3 2 1

D D

Vegas Schematic
C
SKL/KBL-U C

2016/06/27
REV : A00
B B

DY : None Installed <Core Design>

A UMA: UMA only installed Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
A

OPS: DISCRTE OPTIMUS installed Title

Cover Page
Size Document Number Rev
A4
Vegas SKL/KBL-U A00
Date: Monday, June 27, 2016 Sheet 1 of 105
5 4 3 2 1
 5 4 3 2 1

CHARGER
ISL88739 44
Project code:4PD09P010001
PCB P/N: 15341-SD
Vegas SKL-U/KBL-U Block Diagram INPUTS
AD+
OUTPUTS
DCBATOUT
BT+
Revision: A00
SYSTEM DC/DC
TPS51225RUKR-GP 45
INPUTS OUTPUTS
2GB = 256b x 16 x 4pcs 3D3V_PWR
D 3D3V_S5 D
DCBATOUT 5V_PWR

GPU Intel CPU DDR4 1866

5V_S5

VRAM(DDR3L) *4 AMD CPU Core Power

GDDR5 PCIE x 4 DDR4 1866/2133MHz Channel A NCP81208MNTXG 46~50
33
2GB(256Mbx16) R16M-M1-20
Skylake-U 2+3e SODIMM A NCP81382MNTXG x 2
78,79
25W
12 NCP81382MNTXG (23e)
73,74,75,76,77 Kabylake-U 2+3e VEGAS only NCP81253MNTBG
DIS only 15W (UMA&DIS)
DDR4 1866 INPUTS OUTPUTS
28W (UMA)
DDR4 1866/2133MHz Channel B DCBATOUT VCC_CORE
DCBATOUT +VCCGT
SODIMM B
DCBATOUT +VCCGT (23e)
12
14"/15" LCD eDP x2 SKL PCH-LP
55 KBL PCH-LP DCBATOUT+VCCSA

10 USB 2.0/1.1 ports DDR4 SUS

Touch Panel FRINGERPRINT RT8231AGQW-GP
USB2.0 x1 6 USB 3.0 ports USB2.0 x1 51
CRW-CP-GHC-F1 APL5930KAI-TRG
High Definition Audio 92 INPUTS OUTPUTS
3 SATA ports VEGAS only 1D2V_S3
Camera USB2.0 x1 6 PCIE ports
DCBATOUT
0D6V_S0
C
Digital MIC 3D3V_S5 C
LPC I/F 2D5V_S3
PCIE x1 NGFF WLAN
ACPI 5.0 CPU VCCPRIM_CORE
LAN 10/100 TURIS only 802.11a/b/g/n 1V
REALTEK RTL8106G USB2.0 x1 BT V4.0 combo
11
RJ45 Conn. PCIE x1 61
INPUTS OUTPUTS
32 LAN 10/100/1000
REALTEK RTL8111G 1D0V_S5 +VCCPRIM_CORE
31 VEGAS only
SATA (Gen3) x1 CPU DCDC-V1D00A
DDI1 HDD AOZ2262QI-10-GP-U 53
HDMI V1.4a 57 60
INPUTS OUTPUTS
DCBATOUT 1D0V_S5

DP/VGA Converter LDO-V1D8V

VGA Conn. DDI2 SATA (Gen1) x1 ODD
REALTEK RTD2166 APL5930KAI-TRG 54
56 56 60
VEGAS only VEGAS only INPUTS OUTPUTS
3D3V_S5 1D8V_S5
Left side TPM 2.0 5V/3V S0
USB2.0 x1
NPCT650JBAWX TPS22966DPUR-GP 40
USB1(USB3.0) 91
INPUTS OUTPUTS
B B
USB3.0 x1 5V_S5 5V_S0
36 3D3V_S5 3D3V_S0
LPC BUS LPC debug port EOPIO/EDRAM (23e)
68 TPS22961DNYT 40
Left side
USB2.0 x1 INPUTS OUTPUTS
+V_EDRAM_VR
USB2(USB3.0) 1D0V_S5

EC FAN Control 1D0V_S5 +V_EOPIO_VR

USB3.0 x1 3D3V VGA
36 SMSC MEC1404-NU-GP 26
AO3419L 86
24
INPUTS OUTPUTS
3D3V_S0 3D3V_VGA_S0

2CH SPEAKER
(2CH 2W/4ohm) SPI Flash ROM VGA_CORE
Audio Codec 16MB Int. KB ISL62771HRTZ-GP-U 85
HDA 25
ALC3246 65 INPUTS OUTPUTS
27 26 DCBATOUT VGA_CORE
29

1D5V_VGA_S0
MIC_IN/GND Y8288RAC-GP 86
HP_R/L
PS2
Universal Jack INPUTS OUTPUTS
PrecisionTouch pad DCBATOUT 1D5V_VGA_S0
A A
I2C
65
USB3(USB2.0) USB2.0 x1 <Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CardReader Title
SD Card Slot Realtek RTS5170
USB2.0 x1 Block Diagram
Size Document Number Rev
IO Board C Vegas SKL/KBL-U A00
Date: Tuesday, June 21, 2016 Sheet 2 of 105
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4
Vegas SKL/KBL-U A00
Date: Thursday, June 16, 2016 Sheet 3 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

#544669 CRB Rev0.52
#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm +VCCST_CPU
#544669 Rev0.52:
Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm

1
R419

+VCCSTG
+VCCSTG = 1.0 V 1KR2J-1-GP +VCCSTG = 1.0 V

2
R420 +VCCSTG
PCH_THERMTRIP 1 2
D
DY H_THERMTRIP# 40 D

1
R401 0R2J-2-GP XDP_TMS 1 DY 2
[PECI] and [PROCHOT#] Rb 1KR2J-1-GP XDP_TDI 51R2J-2-GP1 DY 2 R421
TP401 CPU1D 4 OF 20 51R2J-2-GP R422
Impedance control: 50 ohm
TPAD14-OP-GP XDP_TDO_CPU 1 2

2
1 H_CATERR# SKYLAKE_ULT 51R2J-2-GP R423
D63 CATERR# DY
24 H_PECI A54 PECI
499R2F-2-GP 1 R403 2 H_PROCHOT#_R C65 JTAG
24,44,46 H_PROCHOT# PROCHOT#
PCH_THERMTRIP C63 PCH_JTAG_TDI 1 2
Ra THERMTRIP#
TPAD14-OP-GP TP402 1SKTOCC# A65 SKTOCC# PROC_TCK B61 XDP_TCLK 51R2J-2-GP R408
CPU MISC D60 XDP_TDI PCH_JTAG_TDO 1 2
PROC_TDI
TPAD14-OP-GP TP405 1XDP_BPM0 C55 BPM#[0] PROC_TDO A61 XDP_TDO_CPU 100R2J-2-GP R409
TPAD14-OP-GP TP406 1XDP_BPM1 D55 BPM#[1] PROC_TMS C60 XDP_TMS PCH_JTAG_TMS 1 2
TPAD14-OP-GP TP407 1XDP_BPM2 B54 BPM#[2] PROC_TRST# B59 XDP_TRST# 51R2J-2-GP R416
TPAD14-OP-GP TP408 1XDP_BPM3 C56 BPM#[3]
XDP_TCK_JTAGX 1 DY 2
1KR2J-1-GP R417
1 GPP_E3/CPU_GP0 A6 B56 PCH_JTAG_TCK
TPAD14-OP-GP TP403 GPP_E3/CPU_GP0 PCH_JTAG_TCK PCH_JTAG_TDI
24,55 TOUCH_PANEL_INTR# A7 GPP_E7/CPU_GP1 PCH_JTAG_TDI D59
TOUCHPAD_INTR# PCH_JTAG_TDO XDP_TRST# R402 2 51R2J-2-GP
GPP_B4/CPU_GP3
BA5 GPP_B3/CPU_GP2 PCH_JTAG_TDO A56
PCH_JTAG_TMS XDP_TCLK R406
1 DY
TPAD14-OP-GP TP404 1 AY5 GPP_B4/CPU_GP3 PCH_JTAG_TMS C59 1 2 51R2J-2-GP
C61 XDP_TRST# PCH_JTAG_TCK R407 1 DY 2 51R2J-2-GP
CPU_POPIRCOMP PCH_TRST# XDP_TCK_JTAGX
AT16 PROC_POPIRCOMP JTAGX A59
24,65 INT_TP# 1 R410 2 PCH_POPIRCOMP AU16 PCH_OPIRCOMP
0R0402-PAD EDRAM_OPIO_RCOMP H66
EOPIO_RCOMP OPCE_RCOMP
H65 OPC_RCOMP

SKYLAKE-U-GP

XDP_TRST#
C C

071.SKYLA.000U

49D9R2F-GP 2 R412 1 CPU_POPIRCOMP

2 1 PCH_POPIRCOMP EC401

1
49D9R2F-GP R413
DY SC1KP50V2KX-1GP

2
49D9R2F-GP 2 R414 1 EDRAM_OPIO_RCOMP
2 1 EOPIO_RCOMP
49D9R2F-GP R415

(#543016) PROCHOT# Routing Guidelines

B B

M1,2,3,4,5: <3 inches

M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_(JTAG/CPU SIDE BAND)
Size Document Number Rev
A3 A00
Vegas SKL/KBL-U
Date: Monday, June 27, 2016 Sheet 4 of 105
5 4 3 2 1
 5 4 3 2 1

Main Func = CPU

DDR4 ball type: Interleaved Type

D D

CPU1B 2 OF 20 CPU1C 3 OF 20

SKYLAKE_ULT
M_A_DQ0 AL71 AU53 M_A_DQ32 AY39 SKYLAKE_ULT AN45
12 M_A_DQ0 M_A_DQ1 DDR0_DQ[0] DDR0_CKN[0] M_A_CLK#0 12 12 M_A_DQ32 M_A_DQ33 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] M_B_CLK#0 13
12 M_A_DQ1 AL68 AT53 12 M_A_DQ33 AW39 AN46
M_A_DQ2 DDR0_DQ[1] DDR0_CKP[0] M_A_CLK0 12 M_A_DQ34 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] M_B_CLK#1 13
12 M_A_DQ2 AN68 AU55 12 M_A_DQ34 AY37 AP45
M_A_DQ3 DDR0_DQ[2] DDR0_CKN[1] M_A_CLK#1 12 M_A_DQ35 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] M_B_CLK0 13
12 M_A_DQ3 AN69 AT55 12 M_A_DQ35 AW37 AP46
M_A_DQ4 DDR0_DQ[3] DDR0_CKP[1] M_A_CLK1 12 M_A_DQ36 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] M_B_CLK1 13
M_A_DQ[0:7] 12 M_A_DQ4 AL70
DDR0_DQ[4] M_A_DQ[32:39]12 M_A_DQ36 BB39
DDR0_DQ[36]/DDR1_DQ[4]
M_A_DQ5 AL69 BA56 M_A_DQ37 BA39 AN56
12 M_A_DQ5 DDR0_DQ[5] DDR0_CKE[0] M_A_CKE0 12 12 M_A_DQ37 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] M_B_CKE0 13
M_A_DQ6 AN70 BB56 M_A_DQ38 BA37 AP55
12 M_A_DQ6 DDR0_DQ[6] DDR0_CKE[1] M_A_CKE1 12 12 M_A_DQ38 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] M_B_CKE1 13
M_A_DQ7 AN71 AW56 M_A_DQ39 BB37 AN55
12 M_A_DQ7 DDR0_DQ[7] DDR0_CKE[2] 12 M_A_DQ39 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2]
M_A_DQ8 AR70 AY56 M_A_DQ40 AY35 AP53
12 M_A_DQ8 DDR0_DQ[8] DDR0_CKE[3] 12 M_A_DQ40 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3]
M_A_DQ9 AR68 M_A_DQ41 AW35
12 M_A_DQ9 DDR0_DQ[9] 12 M_A_DQ41 DDR0_DQ[41]/DDR1_DQ[9]
M_A_DQ10 AU71 AU45 M_A_DQ42 AY33 BB42
12 M_A_DQ10 DDR0_DQ[10] DDR0_CS#[0] M_A_CS#0 12 12 M_A_DQ42 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] M_B_CS#0 13
M_A_DQ11 AU68 AU43 M_A_DQ43 AW33 AY42
12 M_A_DQ11 DDR0_DQ[11] DDR0_CS#[1] M_A_CS#1 12 12 M_A_DQ43 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] M_B_CS#1 13
M_A_DQ[8:15] M_A_DQ12 AR71 AT45 M_A_DQ[40:47]12 M_A_DQ44 BB35 BA42
12 M_A_DQ12 DDR0_DQ[12] DDR0_ODT[0] M_A_DIMA_ODT0 12 M_A_DQ44 DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0] M_B_DIMB_ODT0 13
M_A_DQ13 AR69 AT43 M_A_DQ45 BA35 AW42
12 M_A_DQ13 DDR0_DQ[13] DDR0_ODT[1] M_A_DIMA_ODT1 12 12 M_A_DQ45 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1] M_B_DIMB_ODT1 13
M_A_DQ14 AU70 M_A_DQ46 BA33
12 M_A_DQ14 M_A_DQ15 DDR0_DQ[14] M_A_A5 12 M_A_DQ46 M_A_DQ47 DDR0_DQ[46]/DDR1_DQ[14] M_B_A5
12 M_A_DQ15 AU69 BA51 M_A_A5 12 12 M_A_DQ47 BB33 AY48 M_B_A5 13
M_B_DQ0 DDR0_DQ[15] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M_A_A9 M_B_DQ32 DDR0_DQ[47]/DDR1_DQ[15] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M_B_A9
13 M_B_DQ0 AF65 DDR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BB54 M_A_A9 12 13 M_B_DQ32 AU40 AP50 M_B_A9 13
M_B_DQ1 DDR1_DQ[0]/DDR0_DQ[16] M_A_A6 M_B_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M_B_A6
13 M_B_DQ1 AF64 DDR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] BA52 M_A_A6 12 13 M_B_DQ33 AT40 BA48 M_B_A6 13
M_B_DQ2 DDR1_DQ[1]/DDR0_DQ[17] M_A_A8 M_B_DQ34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M_B_A8
13 M_B_DQ2 AK65 AY52 M_A_A8 12 13 M_B_DQ34 AT37 BB48 M_B_A8 13
M_B_DQ3 DDR1_DQ[2]/DDR0_DQ[18]DDR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] M_A_A7 M_B_DQ35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M_B_A7
13 M_B_DQ3 AK64 AW52 M_A_A7 12 13 M_B_DQ35 AU37 AP48 M_B_A7 13
M_B_DQ4 DDR1_DQ[3]/DDR0_DQ[19]DDR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] M_B_DQ36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
M_B_DQ[0:7] 13 M_B_DQ4 AF66
DDR1_DQ[4]/DDR0_DQ[20]DDR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
AY55 M_A_BG0 12 M_B_DQ[32:39]13 M_B_DQ36 AR40
DDR1_DQ[36]/DDR1_DQ[20] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
AP52 M_B_BG0 13
13 M_B_DQ5 M_B_DQ5 AF67 AW54 M_A_A12 M_A_A12 12 13 M_B_DQ37 M_B_DQ37 AP40 AN50 M_B_A12 M_B_A12 13
M_B_DQ6 DDR1_DQ[5]/DDR0_DQ[21]DDR0_DQ[21]DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M_A_A11 M_B_DQ38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] M_B_A11
13 M_B_DQ6 AK67 BA54 M_A_A11 12 13 M_B_DQ38 AP37 AN48 M_B_A11 13
M_B_DQ7 DDR1_DQ[6]/DDR0_DQ[22]DDR0_DQ[22]DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_B_DQ39 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M_B_ACT_N
13 M_B_DQ7 AK66 BA55 M_A_ACT_N 12 13 M_B_DQ39 AR37 AN53 M_B_ACT_N 13
M_B_DQ8 DDR1_DQ[7]/DDR0_DQ[23]DDR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# M_B_DQ40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
13 M_B_DQ8 AF70 AY54 M_A_BG1 12 13 M_B_DQ40 AT33 AN52 M_B_BG1 13
M_B_DQ9 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_B_DQ41 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
13 M_B_DQ9 AF68 13 M_B_DQ41 AU33
M_B_DQ10 DDR1_DQ[9]/DDR0_DQ[25] M_A_A13 M_B_DQ42 DDR1_DQ[41]/DDR1_DQ[25] M_B_A13
13 M_B_DQ10 AH71 AU46 M_A_A13 12 13 M_B_DQ42 AU30 BA43 M_B_A13 13
M_B_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M_A_A15 M_B_DQ43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] M_B_A15
13 M_B_DQ11 AH68 AU48 M_A_A15 12 13 M_B_DQ43 AT30 AY43 M_B_A15 13
M_B_DQ12 DDR1_DQ[11]/DDR0_DQ[27] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] M_A_A14 M_B_DQ44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] M_B_A14
M_B_DQ[8:15] 13 M_B_DQ12 AF71
DDR1_DQ[12]/DDR0_DQ[28] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
AT46 M_A_A14 12 M_B_DQ[40:47]13 M_B_DQ44 AR33
DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AY44 M_B_A14 13
13 M_B_DQ13 M_B_DQ13 AF69 AU50 M_A_A16 M_A_A16 12 13 M_B_DQ45 M_B_DQ45 AP33 AW44 M_B_A16 M_B_A16 13
M_B_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M_B_DQ46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
13 M_B_DQ14 AH70 AU52 M_A_BA0 12 13 M_B_DQ46 AR30 BB44 M_B_BA0 13
M_B_DQ15 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_A2 M_B_DQ47 DDR1_DQ[46]/DDR1_DQ[30] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_A2
13 M_B_DQ15 AH69 AY51 M_A_A2 12 13 M_B_DQ47 AP30 AY47 M_B_A2 13
M_A_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M_A_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
12 M_A_DQ16 BB65 AT48 M_A_BA1 12 12 M_A_DQ48 AY31 BA44 M_B_BA1 13
M_A_DQ17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_A10 M_A_DQ49 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_A10
12 M_A_DQ17 AW65 AT50 M_A_A10 12 12 M_A_DQ49 AW31 AW46 M_B_A10 13
M_A_DQ18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M_A_A1 M_A_DQ50 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M_B_A1
C
12 M_A_DQ18 AW63 BB50 M_A_A1 12 12 M_A_DQ50 AY29 AY46 M_B_A1 13 C
M_A_DQ19 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] M_A_A0 M_A_DQ51 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M_B_A0
M_A_DQ[16:23] 12 M_A_DQ19 AY63
DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
AY50 M_A_A0 12 M_A_DQ[48:55]12 M_A_DQ51 AW29
DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
BA46 M_B_A0 13
M_A_DQ20 BA65 BA50 M_A_A3 M_A_A3 12 M_A_DQ52 BB31 BB46 M_B_A3 M_B_A3 13
12 M_A_DQ20 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] 12 M_A_DQ52 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3]
M_A_DQ21 AY65 BB52 M_A_A4 M_A_A4 12 M_A_DQ53 BA31 BA47 M_B_A4 M_B_A4 13
12 M_A_DQ21 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4] 12 M_A_DQ53 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4]
M_A_DQ22 BA63 M_A_DQ54 BA29
12 M_A_DQ22 M_A_DQ23 DDR0_DQ[22]/DDR0_DQ[38] M_A_DQS_DN0 12 M_A_DQ54 M_A_DQ55 DDR0_DQ[54]/DDR1_DQ[38] M_A_DQS_DN4
12 M_A_DQ23 BB63 AM70 12 M_A_DQ55 BB29 BA38
M_A_DQ24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[0] M_A_DQS_DP0 M_A_DQS0 M_A_DQ56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0] M_A_DQS_DP4 M_A_DQS4
12 M_A_DQ24 BA61 AM69 12 M_A_DQ56 AY27 AY38
M_A_DQ25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[0] M_A_DQS_DN1 M_A_DQ57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] M_A_DQS_DN5
12 M_A_DQ25 AW61 AT69 12 M_A_DQ57 AW27 AY34
M_A_DQ26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] M_A_DQS_DP1 M_A_DQS1 M_A_DQ58 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] M_A_DQS_DP5 M_A_DQS5
12 M_A_DQ26 BB59 AT70 12 M_A_DQ58 AY25 BA34
M_A_DQ27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1] M_B_DQS_DN0 M_A_DQ59 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] M_B_DQS_DN4
M_A_DQ[24:31] 12 M_A_DQ27 AW59
DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQSN[2]
AH66 M_A_DQ[56:63]12 M_A_DQ59 AW25
DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2]
AT38
12 M_A_DQ28
M_A_DQ28 BB61
DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQSP[2]
AH65 M_B_DQS_DP0 M_B_DQS0 12 M_A_DQ60
M_A_DQ60 BB27
DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2]
AR38 M_B_DQS_DP4 M_B_DQS4
M_A_DQ29 AY61 AG69 M_B_DQS_DN1 M_A_DQ61 BA27 AT32 M_B_DQS_DN5
12 M_A_DQ29 DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQSN[3] 12 M_A_DQ61 DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[5]/DDR1_DQSN[3] M_B_DQS5
M_A_DQ30 BA59 AG70 M_B_DQS_DP1 M_B_DQS1 M_A_DQ62 BA25 AR32 M_B_DQS_DP5
12 M_A_DQ30 DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQSP[3] 12 M_A_DQ62 DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3]
M_A_DQ31 AY59 BA64 M_A_DQS_DN2 M_A_DQ63 BB25 BA30 M_A_DQS_DN6
12 M_A_DQ31 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] 12 M_A_DQ63 DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSN[6]/DDR1_DQSN[4]
13 M_B_DQ16 M_B_DQ16 AT66
DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4]
AY64 M_A_DQS_DP2 M_A_DQS2 13 M_B_DQ48 M_B_DQ48 AU27
DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4]
AY30 M_A_DQS_DP6 M_A_DQS6
M_B_DQ17 AU66 AY60 M_A_DQS_DN3 M_B_DQ49 AT27 AY26 M_A_DQS_DN7 1D2V_S3
13 M_B_DQ17 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] 13 M_B_DQ49 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5]
13 M_B_DQ18 M_B_DQ18 AP65 BA60 M_A_DQS_DP3 M_A_DQS3 13 M_B_DQ50 M_B_DQ50 AT25 BA26 M_A_DQS_DP7 M_A_DQS7
M_B_DQ19 DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5] M_B_DQS_DN2 M_B_DQ51 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] M_B_DQS_DN6
M_B_DQ[16:23] 13 M_B_DQ19 AN65 AR66 M_B_DQ[48:55]13 M_B_DQ51 AU25 AR25

1
DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQ[51] DDR1_DQSN[6] M_B_DQS6
13 M_B_DQ20 M_B_DQ20 AN66
DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6]
AR65 M_B_DQS_DP2 M_B_DQS2 13 M_B_DQ52 M_B_DQ52 AP27
DDR1_DQ[52] DDR1_DQSP[6]
AR27 M_B_DQS_DP6
13 M_B_DQ21 M_B_DQ21 AP66 AR61 M_B_DQS_DN3 13 M_B_DQ53 M_B_DQ53 AN27 AR22 M_B_DQS_DN7 R505
DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[53] DDR1_DQSN[7] M_B_DQS7
13 M_B_DQ22 M_B_DQ22 AT65
DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7]
AR60 M_B_DQS_DP3 M_B_DQS3 13 M_B_DQ54 M_B_DQ54 AN25
DDR1_DQ[54] DDR1_DQSP[7]
AR21 M_B_DQS_DP7 470R2F-GP
13 M_B_DQ23 M_B_DQ23 AU65 13 M_B_DQ55 M_B_DQ55 AP25
M_B_DQ24 DDR1_DQ[23]/DDR0_DQ[55] M_B_DQ56 DDR1_DQ[55]
13 M_B_DQ24 AT61 AW50 M_A_ALERT_N 12 13 M_B_DQ56 AT22 AN43 M_B_ALERT_N 13

2
M_B_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# M_B_DQ57 DDR1_DQ[56] DDR1_ALERT#
13 M_B_DQ25 AU61 AT52 M_A_PARITY 12 13 M_B_DQ57 AU22 AP43 M_B_PARITY 13
M_B_DQ26 DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR M_B_DQ58 DDR1_DQ[57] DDR1_PAR SM_DRAMRST#
13 M_B_DQ26 AP60 M_B_DQ[56:63]13 M_B_DQ58 AU21 AT13 1 R504 2 DDR4_DRAMRST# 12,13
M_B_DQ27 DDR1_DQ[26]/DDR0_DQ[58] M_B_DQ59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP_0
M_B_DQ[24:31] 13 M_B_DQ27 AN60 AY67 V_SM_VREF_CNTA 12 13 M_B_DQ59 AT21 AR18 1 R501 2 121R2F-GP
M_B_DQ28 DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA M_B_DQ60 DDR1_DQ[59] DDR_RCOMP[0] SM_RCOMP_1
13 M_B_DQ28 AN61 AY68 13 M_B_DQ60 AN22 AT18 1 R502 2 80D6R2F-L-GP 0R0402-PAD
M_B_DQ29 DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ M_B_DQ61 DDR1_DQ[60] DDR_RCOMP[1] SM_RCOMP_2
13 M_B_DQ29 AP61 BA67 V_SM_VREF_CNTB 13 13 M_B_DQ61 AP22 AU18 1 R503 2 100R2F-L1-GP-U
M_B_DQ30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_VREF_DQ M_B_DQ62 DDR1_DQ[61] DDR_RCOMP[2]
13 M_B_DQ30 AT60 13 M_B_DQ62 AP21
M_B_DQ31 DDR1_DQ[30]/DDR0_DQ[62] SM_PGCNTL M_B_DQ63 DDR1_DQ[62]
13 M_B_DQ31 AU60 AW67 13 M_B_DQ63 AN21 DDR CH - B

2
DDR1_DQ[31]/DDR0_DQ[63] DDR CH - A DDR_VTT_CNTL DDR1_DQ[63]
#543016
SKYLAKE-U-GP SKYLAKE-U-GP
ED502
071.SKYLA.000U 071.SKYLA.000U DY AZ5725-01FDR7G-GP
83.05725.0A0

1
3D3V_S0
Layout Note:
3D3V_S5 Design Guideline:
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. SM_RCOMP keep routing length less than 500 mils.

1
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential

1
B R506 B
clock pair to clock pair swapping within a channel is not allowed. R507 220KR2F-GP close to CPU
10KR2J-3-GP

2
Q502

2
Q502_G G
SM_PGCNTL_R 51
D
PDG: DDR/ODT D S
Q501
DMN5L06K-7-GP 2N7002K-2-GP
SM_PGCNTL G 84.2N702.J31
2ND = 84.2N702.031
84.05067.031 3rd = 84.07002.I31
S

M_A_DQS_DN[7:0] 12 M_B_DQS_DN[7:0] 13
M_B_DQS_DN0
M_A_DQS_DN0 M_B_DQS_DN1
M_A_DQS_DN1 M_B_DQS_DN2
M_A_DQS_DN2 M_B_DQS_DN3
M_A_DQS_DN3 M_B_DQS_DN4
M_A_DQS_DN4 M_B_DQS_DN5
M_A_DQS_DN5 M_B_DQS_DN6
M_A_DQS_DN6 M_B_DQS_DN7
M_A_DQS_DN7
M_B_DQS_DP[7:0] 13
M_B_DQS_DP0
M_B_DQS_DP1
A M_B_DQS_DP2 A
M_A_DQS_DP[7:0] 12
M_A_DQS_DP0 M_B_DQS_DP3
M_A_DQS_DP1 M_B_DQS_DP4
M_A_DQS_DP2 M_B_DQS_DP5
M_A_DQS_DP3 M_B_DQS_DP6
M_A_DQS_DP4 M_B_DQS_DP7
M_A_DQS_DP5 <Core Design>
M_A_DQS_DP6
M_A_DQS_DP7
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_(DDR)
Size Document Number Rev
A2 A00
Vegas SKL/KBL-U
Date: Monday, June 27, 2016 Sheet 5 of 105
5 4 3 2 1