CMOS COMPARATORS

COMPARATOR DESIGN CONSIDERATIONS

Comparator =
 Preamp (optional in some cases)
 + Reference Subtraction (optional for single-bit case)
 + Regenerative Latch

Design Considerations
 Accuracy (dynamic and static offset, noise, resolution)
 Settling time (tracking BW, regeneration speed)
 Sensitivity/resolution (gain)
 Metastability (ability to make correct decisions)
 Overdrive recovery (memory)
 Power consumption
EXAMPLE CMOS COMPARATOR
 Several Preamp and latch topologies are
possible
VDD

M3 M4 M5 M6
 Input-referred offset Vos introduced due
Vos
Vo+
Φ
V o-
to:
M1 M2
Vi M9  Preamp input pair mismatch
M7 M8  PMOS loads and current mirror
 Latch offset
VSS
 Charge-Injection mismatch in the reset switch
Preamp Latch
 Clock feed-through imbalance of the reset switch
 Clock routing
 Parasitic mismatch
LATCH REGENERATION
VDD
PA tracking Latch
Φ Latch reseting regenrating
M5 M6

Φ VDD
Vo+ Vo-
Vo+
CL M9 CL
Vo
M7 M8
Vo-
VSS VSS

 Exponential regeneration due to positive feedback of cross-coupled pair M7 and M8

REGENERATION SPEED – LINEAR MODEL

Vo+ Vo- Vo+

-1
CL CL
 CL gmVo-
M7 M8 Vo-

 
 Vo   Vo

1 1  Vo  
        0
   
 Vo  gm  Vo /sCL 1 gm /sCL  Vo 

Δs  gm /sCL  1  0  sp  gm /CL , singleRHP pole

Vout  t   Vo  exp  t  gm / CL 
REG. SPEED – LINEAR MODEL
Vo+ Vo-

CL CL
Vo(t=0)
t Vo = 1V
M7 M8

Vo Vo(t=0) t/(CL/gm)
1V 100mV 2.3
1V 10mV 4.6 CL  V t 
t  ln  o 
1V 1mV 6.9 gm  Vo (0) 
1V 100μV 9.2
REG. SPEED – LINEAR MODEL
Reg. Speed – Linear Model
M3 M4 Vm+ M5 M6 Vm- gm5Vm+ gm5Vm-

Vm+ V m- Φ=1 R9 R9
M1 M2 x Vo + Vo-
 Vo+ 2 2 Vo-
Vi M9 X
-1 -1
M7 M8
gm7 gm7

gm1 gm5R9 R9 1
A V1  A V2  ,  to be amplifier.
gm3 2  gm7R9 2 gm7

Vo 0  Vi 0 A V  Vi 0 A V1A V2

Vo t   Vi 0 A V1A V2  expt  gm /CL 

COMPARATOR METASTABILITY
Reg. SpeedT/2
– Linear Model
Vo t   Vi 0 A V1A V2  expt  gm /CL 
Φ

Curve AV1AV2 Vi(t=0)

 10 10 mV
1 2 3 4
Vo+  10 1 mV
 10 100 μV
Vo-
 10 10 μV

Settling time is dependent upon initial signal and regenerative gain

When input is sufficiently close to the comparator threshold
 Comparator fails to produce valid logic outputs within T/2
 Sets the comparator resolution (Δ)
COMPARATOR METASTABILITY
Reg. SpeedD – Linear Model o
Δ Assuming that the input is uniformly
j+1 distributed over VFS, then

Δ
Vi BER 
1LSB

j
Vo t   Vi 0 A V1A V2  expt  gm /CL 
Vos
 Cascade pre-amp stages for larger gain
 Pipelined multi-stage latches (with increased latency)
• pre-amp can be pipelined too
CHARGE-INJECTION AND CLOCK-FEEDTHROUGH IN LATCH
Reg. Speed – Linear Model
Φ
M5 M6
Φ

Vo+ Vo-
Cgs Cgd
CM
M9 jump
CL CL Vo+
M7 M8
Vo-

• In the above latch, regeneration starts when Φ goes low

 Charge injection (CI) and clock-feedthrough (CF) introduce common-mode jump into Vo+ and Vo-
 Mismatch/imbalance in CI and/or CF induces dynamic offset in the latch
DYNAMIC AND STATIC OFFSETS IN A LATCH
Reg. Speed – Linear Model
Dynamic offset induced due to:

Φ • Imbalanced CI and CF
• Imbalanced load capacitance

0.5V CM jump 
  50mV offset
10% imbalance 

Vo+ Static offset induced due to:

• Mismatch in the cross-coupled pairs
Vo- • Mismatch in the signal input circuitry
CMOS COMPARATOR
Reg. Speed – Linear Model
VDD
• Input-referred latch offset gets divided by
M3 M4 M5 M6 the gain of the preamp

Φ • Preamp introduces its own offset (mostly

Vos
Vo +
Vo -
static due to Vth, W, and L mismatches)
M1 M2
Vi M9 • Preamp also reduces kickback noise

M7 M8

VSS

Preamp Latch

• Rapidly varying regeneration nodes couple kickback noise to the input

• Kickback noise disturbs reference voltages, must settle before next sample
COMPARATOR OFFSET
Reg. Speed – Linear Model
VDD

M3 M4 M5 M6
Differential pair mismatch:
2
 W 
Δ
1 2 L 
Φ
Vos
  ΔVth   Vov 
Vo+ V o- 2
M1 M2 Vos2 
4 W
Vi M9  
 L 
M7 M8

gm1 gm5R9
VSS
A V1  A V2 
Preamp Latch
gm3 2  gm7R9

Vos,34  Vos,56
2 2 2 2
Total input-referred Vos,78 Vos,dyn
Vos  V   
2 2
os,12
comparator offset: A V1
2 2
A V1 A V2
2 2
A V1 A V2
2
REVIEW: TRANSISTOR MATCHING
Reg. Speed – Linear Model
Suppose parameter P of two rectangular devices has a mismatch error of ΔP. The
variance of parameter ΔP b/t the two devices is

2
A 1st term dominates
σ ΔP   P  SP D2 ,
2 2

WL for small devices

where, W and L are the effective width and length, D is the distance

A Vth2
Threshold : σ  Vth  =
2
+ S Vth2D2
WL
σ β  A β2
2

Current factor :   Sβ 2D2

β 2
WL

Ref: M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989.
RECALL: DEVICE SIZING FOR MISMATCH
Reg. Speed – Linear Model
R1 R2

W X X X X X X … X X

L
10 identical resistors

L  L 
R1  RS  with std σR1 R2  RS 10    10R1 with std σR2 ,
W W
10
σR22   σR j 2  10σR12  σR2  10σR1
j1

σR2 10σR1 1  σR1  σR 1 1 “Spatial

       averaging”
R2 10R1 10  R1  R A WL
PRE-AMP DESIGN
A fully-differential gain-stage
 Avoid or use simple CMFB
 Pre-amp gain reduces input referred offset due to the latch
 Autozero techniques for offset storage and reduction

Pre-amp open-loop gain vs tracking bandwidth trade-off

N stages:
 Multiple stages of pre-amp limit bandwidth N 
N

 A0   A0 
 Optimum value of stages 2-4 AN  ω     
 1  j  ω / ω0   1 ω / ω 2 
  0 
1
A 0N
A N  ω  ω3dB   , ω3dB  ω0 2N  1
2
PRE-AMP (PA) AUTOZERO
Φ2'
M3 M4
+
Φ1 C Vos Vo Vo-
Vi Φ2'
Vo
M5 M6
Φ2 A
Vi+ M1 M2 Vi-

 Finite preamp gain :

VOS , preamp
VOS ,in 
A

 For the overall comparator :

 2V  2V
 2
 OS , pre
 OS , Latch

1  A 
VOS ,in 2 2
A pre
pre
PRE-AMP DESIGN: PULL-UP LOAD
 NMOS diode pull  up :
gm1 W L 1
Pull-up AV   
gmL W L L
Vo+ Vo-
 PMOS diode pull  up :
μ W L 1
+
Vi M1 M2 Vi- gm1
AV    n
gmL μp W L L

 Resistorpull  up :
A V  gm1  RL

• NMOS pull-up suffers from body-effect, affecting gain accuracy

• PMOS pull-up is free from body-effect, but subject to P/N mismatch

• Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion, well, etc.) don’t track transistors; but it is
fast!
PRE-AMP DESIGN: MORE GAIN
M3 Ip Ip M4
Vo + Vo-
gm1 μ  I 2  W L 1
AV    n
gm3 μp  I 2  Ip  W L 3
Vi+ M1 M2 Vi-

• Ip diverts current away from PMOS diodes (M3 & M4), reducing (W/L)3

• Higher gain without CMFB

• Needs biasing for Ip

• M3 & M4 may cut off for large Vin, resulting in a slow recovery
FASTER SETTLING PRE-AMP
M3 M5 M6 M4 1
ro3
-1
ro5
+ gm3 gm5
Vo Vo-
Vid gm1Vid ro1 Vod

Vi+ M1 M2 Vi-
 1  1   g r
 gm1   //   //ro1//ro3 //ro5    m1 o1
dm
DM gain : A V
M7  gm3  gm5   3

• NMOS diff-pair loaded with PMOS diodes and a PMOS cross-coupled latch

• High DM gain, low CM gain, good CMRR

• Simple, no CMFB required

• (W/L)34 > (W/L)56 needs to be ensured for stability

Ref: K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,” IEEE JSSC, vol. 32, pp. 1887-1895, issue 12, 1997.
PRE-AMP EXAMPLE
M3 M4

RL RL
+
Vo Vo-
X

Vi+ M1 M2 Vi-

M5

• NMOS diff. pair loaded with PMOS diodes and resistors

• High DM gain, low CM gain, good CMRR
• Simple, no extra CMFB required
• Gain not well-defined
Ref: B.-S. Song et al., “A 1 V 6 b 50 MHz current-interpolating CMOS ADC,” in IEEE Symp. VLSI Circuits, 1999, pp. 79-80.
PRE-AMP EXAMPLE
 NMOS diff. pair loaded with PMOS Current mirror
 Simple CMFB circuit using triode PMOS

 Large DM gain, small CM gain

Ref: V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, “A Distortion Compensating Flash Analog-to-Digital Conversion

Technique," IEEE JSSC, vol. 41, no. 9, pp. 1959-1969, Sep. 2006.
LATCH DESIGN
• Regenerative latches for faster settling
• See lecture notes

• At least one cross-coupled regenerative core

• Numerous methods for applying the input initial signal for regeneration
• Latches can have large static and dynamic offsets

• Large Regenerative gain for resolving small inputs

• Metastability (wrong or incomplete decisions) when latch can’t make decision
• Pre-amp used for larger gain (slower tracking BW)

• One topology doesn’t fit all the applications

• Speed vs power consumption trade-off
STATIC LATCH EXAMPLE
• Active pull-up and pull-down
M3 M4 • full CMOS logic levels
Vi+ Vi-
M1 M2
• Very fast!
Φ
• Q+ and Q- are not well defined in reset mode (Φ = 1)
Q+ Q- • Large short-circuit current in reset mode
M7
• Zero DC current after full regeneration
M5 M6
• Supply is very noisy
SEMI-DYNAMIC LATCH EXAMPLE
• Latch is disabled in reset mode
Φ M8
• less static current
M3 M4
Vi+
M1 M2
Vi- • Pull-up not as fast
Φ • Q+ and Q- are still not well defined in reset mode (Φ
= 1)
Q+ Q-
M7 • Zero DC current after full regeneration
• Supply still very noisy
M5 M6
DYNAMIC LATCH EXAMPLE
• Zero DC current in reset mode
Φ M7 M5 M6 M8 Φ • Q+ and Q- are both reset to “0”
• Full logic level after regeneration
Q+ Q- • Slow
Φ M9 M10 Φ

Vi+ M1 M3 M4 M2 Vi-
DYNAMIC LATCH EXAMPLE 2
• Zero DC current in reset mode
Φ M7 M5 M6 M8 Φ
• Q+ and Q- are both reset to “0”

Q+ Q- • Full logic level after regeneration

• Slow
Φ M9 M10 Φ

M3 M4

Vi+ M1 M2 Vi-

Ref: T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” JSSC, vol. 30, pp. 166-172, issue 3, 1995.
CURRENT-STEERING/CML LATCH

• Current mode logic (CML) latch

• Constant bias current
• supply very quite

• Higher gain in tracking mode

• Cannot produce full logic levels
• Fast
• Popular for high-speed designs
COMPARATOR WITH PA AUTOZERO

I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” IEEE JSSC March 2000, pp. 318-25.
LOW-POWER LATCH WITH REFERENCE SUBTRACTION

• Energy efficient comparator for medium speed data converters

• Large number of clock phases
• Driving and routing at higher clock rates leads to more power consumption

S. Pavan, N. Krishnapura, R. Pandarinathan, P. Sankar, "A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications," IEEE JSSC, vol. 43, no. 2,

pp. 351-360, Feb. 2008.

AUTOZERO AND REFERENCE SUBTRACTION

Pre-amp

V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, “A Distortion Compensating FlashAnalog-to-Digital Conversion Technique," IEEE JSSC, vol. 41, no. 9, pp.

1959-1969, Sep. 2006.

CML BASED COMPARATOR

CML-Latch

V. Singh, N. Krishnapura, S. Pavan, B. Vigraham, D. Behera, and N. Nigania, “A 16MHz BW 75dB DR CT ΔΣ ADC Compensated for More Than

One Cycle Excess Loop Delay," IEEE JSSC, vol. 47, no. 8, Aug. 2012.
COMPARATORS FOR PIPELINED ADCS
• Pipelined ADCs employ at least 0.5 bit/stage redundancy
 Can tolerate large offsets and large noise with appropriate redundancy

• Should consume negligible power in a good design

• 50-100 μW or less per comparator

• Lots of implementation options

 Resistive/capacitive reference generation
 Different pre-amp/latch topologies
COMPARATORS FOR PIPELINED ADCS
COMPARATOR EXAMPLE

A 6-b 1.3-Gsample/s A/D Converter in 0.35-m CMOS IEEE JSSC, vol. 36, no. 12, Dec 2001.
LATCH EXAMPLE

A 0.9-V 60-W 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range IEEE JSSC, vol. 43,
no. 2, Feb. 2008
COMPARATOR EXAMPLE

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΔΣ Modulator, IEEE

JSSC, vol. 43, no. 4, Apr 2008
COMPARATOR EXAMPLE

I. Galdi, 40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW, IEEE JSSC,
vol. 39, no. 8, pp. 1341–1346, Aug. 2004.
COMPARATOR EXAMPLE

Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE JSSC, vol. 39, pp.
2139 - 2151, December 2004.
COMPARATOR EXAMPLE

B. Min, P. Kim, F. W. Bowman, D. M. Boisvert, and A. J. Aude, "A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC,"
IEEE JSSC, vol. 38, pp. 2031 - 2039, Dec. 2003.
COMPARATOR EXAMPLE

J. Lin and B. Haroun, "An embedded 0.8 V/480 µW 6B/22 MHz flash ADC in 0.13 µm digital CMOS Process using a
nonlinear double interpolation technique," IEEE JSSC, vol. 37, pp. 1610 - 1617, Dec. 2002.
COMPARATOR EXAMPLE

S . Limotyrakis, S. D. Kulchycki, D. Su, and B. A. Wooley, "A 150MS/s 8b 71mW time-interleaved ADC in 0.18µm CMOS,"
proc. IEEE ISSCC, pp. 258 - 259, Feb 2004.
EXERCISE
Compare the latches with respect to
 Static power dissipation
 Dynamic and Static Offsets
 Kickback noise at the input
 Number of clock phases
 Maximum achievable clock speed
REFERENCES
1. Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters,” 2nd Ed., Springer,
2005.

2. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.

3. N. Krishnapura, Analog IC Design Lectures, IIT Madras, 2008.

4. B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.