Lab 8 - Latches

CPE 301 – Logic Circuit
Experiment 8: Latches
Objective/s:
1. To learn the design and operation of different types of latches

2. To convert one type of latches to another
Equipment Required
1. Software simulation: The Logisim software package
Theory
S-R latch
An S-R latch consists of two cross-coupled NOR gates, as shown below. The truth table and the
block diagram of the latch are also shown. An S-R latch can also be design using cross-coupled NAND
gates. The S-R latch could be envisioned as a basic 1-bit memory cell. The user of an S-R latch could store
binary 1 (which is known as SET), store binary 0 (which is known as RESET), or keep the stored value
as it is (which is known as HOLD). The following truth table shows the values of S and R to hold, set,
or reset the latch. The outputs of the latch are the stored bit (Q) and its complement (Q'). Accordingly,
having S and R high simultaneously is not allowed. In the truth table, Q means the value (also known
as the state) of the latch before changing S and R; whereas, Q+ means he value (or the state) of the latch
after changing S and R.
Gated S-R latch
A gated S-R latch (also called a latch with enable or control) has an additional gate input. The
gate (or the enable) input works as an enable for the operation of the latch. It allows the designer to
change the state of the latch at specific time. This, in turn, allows for the synchronization between
modules in large digital systems. The following figure shows a NAND-based gated S-R latch with its truth
table. In this gated latch, S and R inputs are effective only when the enable (CK or EN) is high. When the
enable goes low, irrespective of S and R, the state of the latch is hold and cannot change until the enable
goes high again.
Prepared by: Rodolfo G. Doromal, Jr. Ph.D. Page 1

Conversion of an S-R latch to D latch
A D latch combines the S and R inputs of an S-R latch into one input by adding an inverter. When
the enable is high, the output (Q) follows the D input, and when the enable goes low, the state is
latched. The following figure shows the schematic of the D latch with its block diagram and truth table.
Conversion of an S-R latch to J-K latch
The J-K latch overcome the problem of the "not-allowed" state in the S-R latch. Beside the
enable, it has two inputs J and K, which are corresponding to S and R, respectively. When both J and K
are active simultaneously, the J-K latch will toggle (i.e., complement) its previous state of Q. The
following figure shows the schematic of the J-K latch with its truth table.
Conversion of a J-K latch to T latch
The J-K latch could be converted into a T latch by connecting J and K inputs together. The T latch
either holds its current value or toggles it. It is very useful in building different types of counters. The
following figure shows the schematic of the T latch with its truth table.
Master Slave Flip Flops
Latches are said to be level-sensitive. As long as the enable input is active, the output could
continuously change. Therefore, if a designer wants the output to change at a certain moment, the
enable should be activated for a very short period of time, corresponding to this moment. The
generation of this narrow pulse is not easy. On the other hand, flip flops are edge-sensitive.
Their output changes only at the edge of the clock. Otherwise, the flip flop holds its current
value till an edge transition occurs at the clock again. The flip flop could be designed to be rising edge
sensitive or falling edge sensitive. Using flip flops, the designer could decide the moments at which the
states would change by only adjusting the clock frequency (i.e., when the edges occur). There is no need
to have a sophisticated pulse generator, as in the case of latches. The following figure shows an example
circuit of the D flip flop with its block diagram and truth table. In the block diagram, notice the small
triangle of the clock input. This indicates that the module is an edge-sensitive flip flop rather than a
level-sensitive latch. The small circle beside

the triangle indicates that the flip flop is negative-edge sensitive. i.e., the output would change only on
the falling edge of the clock, as shown in the truth table.
Similar to the D flip flop, there are S-R, J-K, and T flip flops. The difference between these flip flops
and their corresponding latches is that they are edge-sensitive rather than level-sensitive. The following
figure shows an example block diagram of the J-K flip flop. The small triangles indicate that these are
flip flops rather than latches. Moreover, the small bubble beside the triangle indicates that this flip flop
is falling (negative) edge sensitive, rather than a rising (positive) edge sensitive.
Equipment Required:
• Software simulation: The Logisim software package is installed on every PC in the lab.
Procedures/Lab Work:
Software Simulation
S-R Latch
1. Start a new Logisim project
2. Construct the S-R latch according to the circuit shown.
3. Use the poke tool to simulate the latch. Change the values of S and R according to the following
table and fill in the values of Q and Q'. In the action column, write whether the latch is set, reset,
hold, or not allowed.

Gated S-R Latch
1. Start a new Logisim project
2. Construct the gated S-R latch according to the circuit shown
3. Use the poke tool to simulate the latch. Change the values of CK, S, and R according to the
following table and fill in the values of Q and Q'. In the action column, write whether the latch
is set, reset, hold, or not allowed.
Conversion of an S-R latch to D Latch

1. Convert the S-R latch you build to a D latch according to the circuit shown.
2. Use the poke tool to simulate the D latch. Change the values of C and D according to the
following table and fill in the values of Q and Q'. In the action column, write whether the latch
is set, reset, or hold.
3. Save you D latch as you will use it in the following subsection to build the D flip flop.
Questions/Exercises:
1. Design a 4-bit ripple down counter using T flip flops. Your counter should count down from 15 to
0 then underflow back to 15. Draw your circuit and simulate it using logisim to ensure its proper
operation. Snapshots from Logisim should be included in your report.
Reference(s)
1. Introduction to Logic Circuits & Logic Design with Verilog, 1st Edition, Brock J. LaMeres
2. Digital Design, 3rd Edition, M. Morris Mano
3. Digital Principles and Logic Design, A. Saba & N Manna

Laboratory Report Format
CPE 306 – Introduction to HDL
Name: _____________________________________ Yr. & Sec. ____________ Date: ______________
Experiment Title
Experiment No. _
I. Introduction
II. Objectives
III. Materials and Components
IV. Procedure (include screenshots/images)
V. Results and Discussion
VI. Conclusion

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CPE 301 – Logic Circuit

1. To learn the design and operation of different types of latches

1. Software simulation: The Logisim software package

Gated S-R latch

Prepared by: Rodolfo G. Doromal, Jr. Ph.D. Page 1

Conversion of an S-R latch to J-K latch

Conversion of a J-K latch to T latch

Master Slave Flip Flops

Prepared by: Rodolfo G. Doromal, Jr. Ph.D. Page 2

Prepared by: Rodolfo G. Doromal, Jr. Ph.D. Page 3

Conversion of an S-R latch to D Latch

Prepared by: Rodolfo G. Doromal, Jr. Ph.D. Page 4

CPE 306 – Introduction to HDL

Name: _______________________ Yr. & Sec. Date:

III. Materials and Components

IV. Procedure (include screenshots/images)

V. Results and Discussion

Prepared by: Rodolfo G. Doromal, Jr. Ph.D. Page 5

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