Electronics and Communication Circuits Lab. Experiment #7 Class A Common Emitter Amplifier
Electronics and Communication Circuits Lab. Experiment #7 Class A Common Emitter Amplifier
Electronics and Communication Circuits Lab. Experiment #7 Class A Common Emitter Amplifier
EXPERIMENT #7
Objective:
- To understand and Design a Class A Common Emitter Amplifier
Theory Overview:
- The most common amplifier configuration for an NPN transistor is that of the Common
Emitter Amplifier circuit.
- Common Emitter (CE) amplifiers are designed to produce a large output voltage swing
from a relatively small input signal voltage of only a few millivolt’s and are used mainly as
“small signal amplifiers”.
- Biasing is very important in amplifier design as it establishes the correct operating point
(Q-Point) of the transistor amplifier ready to receive signals, thereby reducing any
distortion to the output signal.
- The following Figure 1 shows DC load line on a family of collector characteristic curves
illustrating the cutoff region, saturation region and active region.
DC
L oa
dL
i ne
Figure (1)
- Amplifier Without Bias:
When the amplifier does not use bias, it causes the output signal to be distorted as
shown in Figure 2.
VCE
Figure (2)
- DC Bias:
Bias establishes the dc operating point (Q-point) for proper linear operation of an amplifier. If an
amplifier is not biased with correct dc voltages on the input and output, it can go into saturation
or cutoff when an input signal is applied.
Figures below shows the effects of proper and improper dc biasing of an inverting amplifier. In
figure (a), the output signal is an amplified replica of the input signal except that it is inverted,
which means that it is 180⸰ out of phase with the input. The output signal swings equally above
and below the dc bias level of the output, VCE.
Improper biasing can cause distortion in the output signal, as illustrated in figures (b), (c) and
(d). Figure (b) illustrates limiting of the positive portion of the output voltage as a result of a Q-
point (dc operating point) being too close to cutoff.
Figure (c) shows limiting of the negative portion of the output voltage as a result of a dc
operating point being too close to saturation.
Figure (d) illustrates limiting into both saturation and cutoff because the input signal is too large.
VCE = 5.12 V
Figure (a)
VCE
Figure (b)
VCE
Figure (c)
VCE
Figure (d)
Note: We can conclude from the previous figures that the best value of V CEQis
This type of biasing arrangement uses two resistors as a potential divider network
across the supply with their center point supplying the required Base bias voltage
to the transistor. Voltage divider biasing is commonly used in the design of bipolar
transistor amplifier circuits.
This method of biasing the transistor greatly reduces the effects of varying Beta,
(β) by holding the Base bias at a constant steady voltage level allowing for best
stability. The quiescent Base voltage (VBQ) is determined by the potential divider
network formed by the two resistors, R1, R2 and the power supply voltage Vcc as
shown with the current flowing through both resistors.
Materials Needed:
- Multisim Simulator.
- BC549 NPN Transistor with β=400.
- Multimeter, Oscilloscope.
- 14V VCC.
- R1=432 KΩ, R2=82.5 KΩ, Rs= 50 Ω, RC= 5.6 KΩ, RE= 1.37 KΩ.
- C1=180µf, C2=33 µf, C3= 1.2mf.
- VS =10 mv (peak) == 7.07 mv rms / 100HZ
Procedure: