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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

A Continuous-Time Delta-Sigma Modulator

Using ELD-Compensation-Embedded SAB
and DWA-Inherent Time-Domain Quantizer
Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Member, IEEE, Chang-Tsung Fu,
and Tsung-Hsien Lin, Senior Member, IEEE

Abstract—This paper presents an energy-efficient third-order In high-order CTDSMs, several design techniques are pre-
3 bit continuous-time delta-sigma modulator (CTDSM). In this sented in prior publications to facilitate low-power operation.
work, several architectural and circuit techniques are adopted to For example, in the modulators reported in [1] and [2], some
facilitate a low-power modulator. In the loop filter design, a single-
amplifier biquad (SAB) topology is incorporated to realize the stages of the loop filter are implemented with passive resistor–
desired transfer function. With the SAB architecture, only two capacitor (RC) networks, instead of using active circuits to
amplifiers are needed for implementing a third-order CTDSM. realize the entire loop filter. In [1], the summing of the input
Furthermore, in the proposed SAB, the excess-loop-delay (ELD) and feedback signals is performed in the current or charge
compensation is implemented without using an extra summing domain at the input of the modulator; the summed current then
circuit. For the 3 bit quantizer, a time-domain quantizer is pro-
posed, where the data-weighted-averaging function is embedded charges a capacitor to realize a first-order integration function.
in this quantizer to mitigate the nonlinearity issue due to the mis- However, replacing the active op-amp integrator with a pas-
match of digital-to-analog converter (DAC) unit cells. Fabricated sive RC circuit implies that the signal summing takes place at
in a 90 nm CMOS technology and clocked at 300 MHz sampling a nonvirtual-ground node. As a result, the output of feedback
frequency, the proposed SAB-based modulator achieves a 67.2 dB digital-to-analog converter (DAC) may experience a large sig-
SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The
overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit nal swing, which increases the design effort on the feedback
of 135 fJ/conversion-step. current DAC. Furthermore, without a virtual short node, the
driving capability requirement on the previous stage becomes
Index Terms—Delta-sigma modulation, excess loop delay,
single-amplifier biquad, quantizer. more demanding as the feedback DAC now directly loads
the preceding integrator stage. In [2], the modulator adopts a
I. I NTRODUCTION hybrid loop filter topology that consists of active-RC, gm-C,
and passive RC networks to implement a fifth-order modulator.

D ELTA-SIGMA modulators (DSMs) have been a popular

analog-to-digital converter (ADC) architecture in various
applications, such as in sensor interfaces and wireless systems.
The integration function realized by the passive network leads
to additional parasitic poles and weakens the noise-shaping
characteristic of the modulator.
For high-resolution and wide-bandwidth applications, the To reduce the number of active amplifiers used in a modula-
continuous-time delta-sigma modulator (CTDSM) is a good tor, several works exploited the single-amplifier biquad (SAB)
candidate for realizing the ADC. Comparing to a discrete-time topology to realize the loop filter [3]–[7]. By incorporating
delta-sigma modulator (DTDSM), the CTDSM is favored proper passive device networks, the SAB can realize a higher
owing to its relaxed integrator design requirement and inherent order transfer function with only one amplifier, which poten-
antialiasing filtering characteristic. Still, to achieve a good SNR tially reduces the modulator power consumption. However, the
performance (e.g., > 11 bits) with a wide signal bandwidth SAB architecture inherently comes with fewer virtual ground
(∼ 10 MHz), the modulator usually employs a high-order nodes; its design flexibility in realizing a given transfer function
loop filter, a multibit quantizer, and needs to operate at a is more restricted. In addition, implementing the feedforward
high sampling frequency. Optimization of the loop filter and path and excess-loop-delay (ELD) compensation in a SAB-
quantizer from system to circuit design is crucial in designing based modulator becomes more difficult. Although these tasks
a low-power CTDSM. may be accomplished by introducing an additional summing
Manuscript received May 18, 2015; revised December 01, 2015; accepted amplifier, this extra amplifier diminishes the benefit of the SAB
February 07, 2016. This paper was approved by Associate Editor Andrea topology. To avoid the power consumption penalty of an active
Baschirotto. This work was supported in part by NTU, in part by Intel-NTU summing amplifier, passive summers can be adopted. However,
Connected Context Computing Center (ICCC), in part by Intel Corporation,
and in part by the Ministry of Science and Technology (MOST), Taiwan. the signal swing at the loop filter output usually contains the
C.-H. Weng, T.-A. Wei, and T.-H. Lin are with the Department of Electrical majority of the input signal. Large signal swing complicates the
Engineering, Graduate Institute of Electronics Engineering, National Taiwan design of the preceding-stage op-amp and feedback DAC in the
University, Taipei 106, Taiwan (e-mail: thlin@ntu.edu.tw). passive summer approach.
E. Alpman and C.-T. Fu are with Intel, Hillsboro, OR 97124 USA.
Color versions of one or more of the figures in this paper are available online The other important building block in a low-power CTDSM
at http://ieeexplore.ieee.org. is the quantizer, which is typically a multibit implementation in
Digital Object Identifier 10.1109/JSSC.2016.2532345 a wide-bandwidth high-performance system. The conventional
0018-9200 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 1. Architecture of the initial feedforward/feedback hybrid third-order

CTDSM.
Fig. 2. Third-order feedforward/feedback hybrid CTDSM implemented with
three integrators [26].
flash-type quantizer can operate at a high sampling frequency.
However, both the hardware and the power consumption grow

exponentially with the resolution. Several solutions are pro- C = a2 a3 fb + a1 a2 b1 f2 · e−td + a2 a3 b3 fb · e−td
posed to address this issue, such as successive-approximation- 
+a2 a3 b1 b2 f2 fb · e−td /T 2
register (SAR) quantizer [12], [13], two-step quantizer [15],  
VCO-based quantizer [8]–[11], and time-to-digital converter D = a1 a2 a3 b1 +2a2 a23 b1 b2 fb +a1 a2 a3 b1 f1 fb ·e−td/T 3 .
(TDC) [14]. Considering the data-weighed-averaging (DWA) (1)
function among all types of quantizers, the VCO-based quan-
tizer can achieve barrel-shifting operation with simple digital In (1), td is the delay contributed by the loop filter and
hardware and low latency since the ring oscillator can provide quantizer. The notch frequency is adjustable by tuning the coef-
integration and modulus functions on a phase-domain signal. ficients of second and third integrators, and local feedback
In this work, several architecture and circuit techniques are path (fb ).
proposed to design a low-power CTDSM. In the loop filter, the For the third-order CTDSM shown in Fig. 1, the loop filter is
SAB technique is applied. The proposed SAB-based loop filter usually realized with three integrators; one active-RC integrator
incorporates ELD compensation and proper feedforward paths attains a first-order integration function and the other two inte-
to realize the desired transfer function. In the quantizer, a multi- grators with a feedback resistor realize the resonator function.
bit time-domain quantizer operating in a barrel-shifting manner All signal components corresponding to first-, second-, and
is proposed, which effectively realizes a DWA-embedded TDC. third-integration paths (called s−1 , s−2 , s−3 terms hereafter)
This paper is organized as follows. Section II presents the mod- and ELD compensation signals are summed up in the last-stage
ulator architecture and system-level design of the proposed integrator and then fed to the input of the quantizer. Fig. 2 illus-
SAB-based loop filter. Section III describes circuit imple- trates a CTDSM implementation example that employs three
mentation details. Section IV provides measurement results. integrators to realize the hybrid feedforward and feedback loop
Section V gives conclusion for the implemented work. filter [26]. This design adopts a local feedforward path (via
RFF ) to replace one of DACs; meanwhile, the DAC2 path is
kept to implement the s−1 and ELD compensation terms. In
II. SAB-BASED L OOP F ILTER short, to implement all these design attributes, three individual
integrators are employed.
A. Modulator Architecture
To reduce the number of op-amps used in the modulator,
Fig. 1 shows the initial system-level block diagram of instead of the direct three-integrator implementation, the pro-
the CTDSM design. This modulator targets a bandwidth of posed loop filter adopts the SAB topology with a twin-T filter
8.5 MHz with an SNDR around 70 dB and it employs a third- to realize the resonator function. While the advantage of reduc-
order, single-loop DSM with a 3 bit quantizer. The loop filter ing one op-amp is apparent, there are several major design
adopts a hybrid feedforward and feedback topology. The feed- issues in a SAB-based loop filter. First, one less op-amp implies
forward paths f1 and f2 can facilitate smaller internal swings, one less virtual ground node available for signal summing.
which helps to lower the hardware design requirements of asso- Most prior SAB-based loop filters still mandate either a pas-
ciated integrators. Instead of using a single feedforward path f1 sive summer [3]–[5] or an active summing amplifier [6] for
to realize the whole s−1 term in the transfer function, the feed- signal summation (i.e., summing of signals from paths f1 ,
back path b2 contributes to partial s−1 term that enables a better f2 , b3 , and third-integrator output). A passive summer usually
system stability. The purpose of b3 path is to realize the ELD leads to signal attenuation, while an active summing amplifier
compensation. The local feedback path fb along with the sec- takes extra power. Either active or passive summer implemen-
ond and third integrators implements a resonator, which further tation compromises the advantages of adopting the SAB-based
optimizes the in-band quantization noise. The noise transfer modulator.
function of the system shown in Fig. 1 can be described by the Second, considering the transfer function of a twin-T fil-
following equations: ter (from the input of the twin-T filter to its output) of an
 3  SAB resonator, the coefficients of the s−1 and s−2 terms are
Vo s + ωn2 s a2 a3 f b tightly coupled and cannot be determined independently [3],
NTF (s) = = ; ω2 = ;
e As3 + Bs2 + Cs + D n T2 which leads to severe constraint in designing and optimizing
A = (b3 · e−td + 1); B = (a3 b1 b2 + a1 b1 f1 ) · e−td /T the loop filter. One further drawback relating to the previous
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WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER 3

Node A DAC2
C2 C3 RE

R3 Partial s–1 &

Vo,op1 RX Ry
C1 ELD path
CX VLP
R2
V i R1 Dout
OP1 OP2
s–1,s–2 and s–3 terms
DAC1

Fig. 4. Proposed realization of the SAB-based third-order CTDSM with a 3 bit

quantizer.

Fig. 3. (a) System-level view focusing on the second- and third-stage inte-
grators with associated feedforward/feedback and ELD compensation signals; Fig. 5. Simulated voltage swings at node A (of Fig. 4) with different values of
(b) corresponding SAB implementation with the twin-T filter. C2 /C3 .

Finally, the overall third-order CTDSM is shown in Fig. 4. It

two issues is that the ELD compensation design becomes more is composed of a first-order integrator followed by the proposed
challenging. The feedback network of the twin-T filter is dif- SAB-based resonator, which embeds the ELD compensation.
ferent from that of a single active-RC integrator. The technique The proposed CTDSM adopts a multibit time-domain quan-
of reusing the virtual ground node of the last-stage integrator tizer, which is consisted of a voltage-to-time converter (VTC)
to realize ELD compensation is no longer feasible in the SAB- and a circular TDC (CRTDC). The time-domain quantizer will
based topology [17], [22]. In other words, an additional summer be described in Section III-C.
seems indispensable for the ELD compensation.
To address the aforementioned issues, a new twin-T topology
B. Design Considerations
for SAB, shown in Fig. 3, is proposed in this work. In Fig. 3(a),
the system-level view focusing on the second- and third-stage To transform the architecture of Fig. 1 into circuit-level
integrators with associated feedforward/feedback and ELD implementation shown in Fig. 4, several design considerations
compensation signals is shown, while Fig. 3(b) depicts the cor- must be carefully evaluated. Considering the input stage of the
responding SAB implementation with the twin-T filter. In the modulator, the first feedback DAC (DAC1 ) and the input resis-
proposed realization, an additional resistor RE in series with tors (R1 ) typically set the thermal noise floor of the modulator.
C3 creates a proportional path, which realizes the f1 path with- Therefore, they are designed to meet the noise requirement.
out an explicit summer. As mentioned previously, lacking one In the subsequent SAB-based resonator, the DAC2 signal is
virtual ground node in the SAB-based topology leads to diffi- injected into a node between C2 and C3 (node A), which is
culty in injecting feedback DAC current to complete the ELD not a virtual ground node. The signal swing at this node affects
compensation loop. In this design, the ELD compensation is the current accuracy of DAC2 , which introduces nonlinearity to
realized by injecting the feedback signal into an intermediate the modulator. Therefore, the magnitude of signal swing at this
node between capacitors C2 and C3 (node A of Fig. 3) to gen- node should be carefully optimized for a given linearity require-
erate the desired compensation term. In this proposed scheme, ment. Here, the ratio between C2 and C3 is taken as a design
benefitting from the filtering capability of the RC network, the parameter. The voltage swing at node A is examined by vary-
signal fluctuation at node A is considerably smaller than that at ing the C2 /C3 value and is plotted in Fig. 5. As the value of
the loop filter output. Therefore, the DAC2 design requirement C2 /C3 increases, the voltage swing at node A decreases, which
is relaxed. Comparing to prior SAB-based modulators [3]–[7], relaxes the design requirement of DAC2 . In the proposed SAB-
this design does not use any active or passive summer circuit based loop filter, the value of C3 is first determined by the value
to sum all feedforward and feedback signals. Another implicit of s−2 term; next, the chosen C2 /C3 value determines C2 and
benefit of this proposed twin-T filter is that the proposed injec- Cx . Considering the voltage swing at node A and total capacitor
tion path also provides an additional design freedom to realize a area, the value of C2 /C3 is chosen as 2 in this design. The RC
fast s−1 feedback path, which helps to improve the overall loop network formed by components Rx , Ry , C2 , and C3 determines
stability. the notch frequency ωn (= 1/ Rx Ry C2 C3 ). The resistor RE ,
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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 6. Fast path realized by DAC2 helps to boost loop filter gain at high frequency and extend the bandwidth.

which is in series with C3 , serves to accomplish the ELD com- op-amps (modeled with an infinite GBW); 2) conventional two-
pensation (path b3 in Fig. 1), and attains partial coefficient for integrator resonator with practical op-amps (modeled with a
the s−1 term with the DAC2 current. finite gain bandwidth, GBW = 2 × fs ); and 3) the proposed
In most prior SAB-based CTDSMs, the loop filter usually SAB-based resonator with a practical op-amp (modeled with a
adopts the multiple feedforward topology to reduce internal finite GBW = 2 × fs ). The adopted op-amp model is consisted
swing and lower design complexity on feedback paths [3]–[7]. of voltage control current source, single pole implemented with
However, two feedback paths are still required to implement the resistor and capacitor, and ideal output buffer. Among these
desired transfer function. One feedback path goes through the three cases, case (1) represents the ideal design. These res-
whole loop filter and the other one is for ELD compensation. In onators are all designed to place a notch at 6.5 MHz in the
a multiple feedforward modulator, the s−1 term usually suffers overall modulator NTF.
from longer phase delay comparing to that of a multiple feed- Fig. 7 shows the three cases simulated for different types of
back modulator. The excess phase shift of the s−1 term mainly resonators and Fig. 8 plots the magnitude and phase responses
comes from two sources; one is the finite GBW of the first for the corresponding simulation results. Fig. 8(a) shows that
integrator and the other is the summing operation ahead of the the quality factor of the peaking (corresponding to notch in the
quantizer. The prolonged phase shift of the s−1 term degrades modulator NTF) in the SAB-based resonator is slightly lower
the stability of the modulator. To mitigate this effect, the op- than that attained by the two-op-amp resonators. A lower qual-
amp located in this critical path has to consume more power in ity factor may lead to a worse notch performance. However, in
order to minimize the phase. In [20], this issue is alleviated by a practical circuit-level design considering device noise, the in-
adopting a feedback path that goes through the last-stage inte- band noise is usually dominated by the circuit noise, instead
grator to realize the s−1 term to minimize the parasitic phase of the quantization noise. Therefore, the design requirement
shift. on quality factor of the notch is less crucial. Also observed in
The same principle is applied in this work, where a fast s−1 Fig. 8(a), compared to the two-integrator resonator with a finite
term is realized by injecting the feedback signal via DAC2 . GBW, the SAB-based resonator exhibits a less steep roll-off
Since the DAC2 path only experiences the delay of op-amp2 , at higher frequencies, which implies that it has a wider band-
this DAC2 path partially realizes a fast s−1 term with less width. Note that the gain response of the SAB-based resonator
propagation delay and mitigates the roll-off rate of the loop is close to that of the ideal resonator (adopting op-amps with
filter gain response. The benefit of the proposed topology infinite GBW). Benefited from only single op-amp used in a
can be observed from Fig. 6, where the gain responses of SAB-based resonator, the latency of the signal flows is reduced
loop filter transfer function H(s) with and without DAC2 are and wider unity gain bandwidth can be achieved.
compared. The transfer functions of H(s) without DAC2 is In terms of phase response behaviors, Fig. 8 shows the plots
defined as VLP (s)/Vb1 (s), while H(s) with DAC2 is defined of simulated phase for the three resonator cases. The SAB-
as VLP (s)/Vb1 (s) + VLP (s)/Vb2 (s). As seen from Fig. 6, with based topology induces less phase shift compared to that of the
the fast path realized by DAC2 , the gain response of H(s) rolls practical conventional two-integrator architecture, and is again
off at a slower rate than that of the H(s) without DAC2 path. behaving similar to the ideal case. This is mainly attributed to
This implies that the proposed loop filter can use an op-amp the shorter path delay as only one op-amp is used in the res-
designed with a relaxed GBW since the proposed SAB-based onator. In short, the attribute of wider resonator bandwidth may
modulator with the assistance of DAC2 path is more tolerant to relax the op-amp design requirement for a given design target.
delay. Next, we evaluate the overall modulators. Two cases, shown
in Fig. 9(a), a conventional third-order CTDSM and the pro-
posed SAB-based CTDSM, are studied. The conventional
C. Comparison
three-integrator CTDSM (from Fig. 2) is designed first, and
In order to evaluate the resonator behavior realized with then the SAB-based modulator (from Fig. 4) is derived by
the proposed SAB-based topology, we compare the proposed following the design guideline discussed in Section II-A. In
SAB-based resonator to that implemented with a conventional both cases, op-amps with the same finite GBW(= 2 × fs ) are
two-active-RC-integrator architecture. Three resonator cases utilized in the system simulation. The simulated magnitude
are studied: 1) conventional two-integrator resonator with ideal responses of the loop filter (H(s)) and STF are shown in
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WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER 5

Fig. 7. Three cases for comparison with two resonators: (a) conventional resonator; (b) SAB-based resonator. Case 1: resonator (a) with OPideal (60 dB dc gain
and infinite GBW); Case 2: resonator (a) with OPmodel : (60 dB dc gain and 2 × fs finite GBW); Case 3: resonator (b) with OPmodel (60 dB dc gain and
2 × fs finite GBW).

Fig. 8. Comparison of (a) magnitude responses and (b) phase responses for three resonator cases.

Fig. 9(b) and(c), respectively. In both the conventional archi- consisted of OP2 and DAC2 . Therefore, this design has lower
tecture and proposed loop filter, the dominating term of system signal peaking effect than that of the multiple-feedforward
stability, first-order term, is achieved with feedback DAC2 with topology. Although the feedforward term contributed by RE
RE and only goes though the last-stage op-amp. Therefore, still results in an elevated STF peaking than that of the multiple-
the loop filter and STF frequency responses of the SAB-based feedback topology, the same feedforward path achieved by RE
CTDSM are similar to those of the conventional three-op-amp helps to lower the signal swing of OP1 and reduce the num-
modulator. The similarity between two modulators in both plots ber of DACs required to realize the entire modulator including
validates the design of transforming the original modulator into the ELD compensation. Overall, the proposed hybrid modulator
the proposed one. achieves a good compromise among STF peaking, magnitude
In short, in a conventional three-integrator CTDSM, the of internal swing, and hardware complexity on feedback paths.
design of the intermediate integrator stage, although relatively
relaxed compared to those of the first- and last-stage integra-
tor, still demands an op-amp GBW of at least larger than fs /2 III. C IRCUIT I MPLEMENTATION
[26], [28]. This integrator still consumes a notable amount
of power. With the SAB-based resonator, a high-order loop A. Architecture of the Proposed Modulator
filter is achieved with fewer active circuits. Using fewer cir- Fig. 10 shows the detailed block diagram of the imple-
cuits not only lessens the latency contributed by the loop filter mented CTDSM. It features a SAB-based third-order modulator
but also relaxes the GBW design requirement on the circuits with a 3 bit CRTDC [21]. Benefited from the proposed ELD-
along the signal path. Furthermore, the proposed SAB architec- embedded SAB topology, only two op-amps are needed to real-
ture can achieve the resonator function and ELD compensation ize the third-order modulator. For the quantization operation, a
concurrently with only single op-amp where these two func- time-domain architecture is adopted; a VTC first converts the
tions are usually implemented with separate circuit blocks in a loop filter output (VLP ) to a pulse signal, then the CRTDC dig-
conventional SAB-based resonator. itizes the pulse signal to digital codes. Meanwhile, the CRTDC
Considering the STF peaking in proposed SAB-based work shuffles these output codes in a barrel-shifting manner, which
[shown in the right of Fig. 9(a)], with the assistance of feedback helps to suppress the nonlinearity due to mismatch of DAC
path DAC2 , part of the s−1 term goes through the inner loop unit cells. To compensate for PVT variations, the loop filter
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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Gm2 M7 M8
M11 M12

Vbiasp M5 M6 Vbiasp
Von,opa RC CC CC RC V –Gmf
op,opa
VCMFB
M3 M4
Gm1 Vbiasp Vi,opa Vo,opa
Gm1 –Gm2
Vin,opa M1 M2 Vip,opa
Vip,opa Vin,opa
Gmf
VB
M9 M10
Rbias Rbias

Fig. 11. Left: circuit schematic of the operational amplifier; right: its equivalent
model.

stage, instead of the conventional cascode topology, the com-

pound transistor pairs (M1 /M3 and M2 /M4 ) are adopted. The
body voltages of M3 /M4 and M5 /M6 are biased at a separate
dc voltage Vbiasp to reduce their threshold voltages and assist
M1 /M2 and M7 /M8 pairs operating in the saturation region
[24]. This pseudocascode topology achieves a better dc gain
without consuming large overdrive voltage. The bias voltage
Vbiasp is generated by a simple replica biasing circuit.
For the high-speed path, transistors M9 and M10 serve as
the input pair where the input signals (Vin,opa /Vip,opa ) are ac-
coupled to the gate terminals. This feedforward path provides
additional trans-conductance at high frequency which extends
the amplifier bandwidth. Fig. 11 also shows the equivalent
model of this dual-path amplifier. Gm1 is formed by the com-
pound transistor pairs M1 /M3 and M2 /M4 ; Gm2 is composed
of transistors M11 and M12 ; Gmf is realized by transistors M9
and M10 .
In the proposed CTDSM, both op-amps used in the first-
Fig. 9. Comparison of frequency responses of the proposed SAB-based and
conventional third-order modulators. (a) Two modulator topologies under com- stage integrator and the subsequent SAB-filter adopt the same
parison. (b) Plots of loop filter (H(s)) frequency responses. (c) Plots of STF amplifier topology. The dc gains of both amplifiers are close to
frequency responses. 60 dB. The GBW of the first and second integrators are 750 and
890 MHz, respectively, and power consumed by the first and
second integrators are 0.665 and 0.95 mW, respectively. In this
design, the delay of the second integrator dominates the phase
of the first-order term (s−1 ), and a wider unity gain bandwidth
is necessary for the second integrator considering the stability
of the modulator. The GBW values are chosen to be sufficiently
high to ensure that the modulator works properly even at worst
corners.

Fig. 10. Block diagrams of the implemented CTDSM. C. Time-Based Quantizer—VTC and CRTDC
A conventional multibit voltage quantizer is comprised of
coefficients are made programmable by adjusting the capacitor multiple comparators. The design of these comparators entails
of the first-stage integrator and feedback currents of DAC1 and efforts in optimization of power consumption and several non-
DAC2 . To avoid undesired parasitic terms induced by inserting idealities, such as mismatch and offset voltage. The offset
additional switches into the twin-T network, the compensation voltage mismatch among comparators is known to cause modu-
mechanism is not implemented in the SAB-based resonator. lator nonlinearity and degrade the SNDR [4]. Furthermore, the
resilience of modulator to nonideality of the quantizer becomes
weaker in low-OSR designs.
In this design, to avoid the aforementioned issues in a multi-
B. Operational Amplifier bit quantizer, a time-based quantizer architecture is adopted
The op-amp adopted in this work is shown in Fig. 11. A two- [14]. The proposed overall time-based quantizer is composed
stage architecture, which is composed of a high-gain path and of two parts: a VTC and a CRTDC. The VTC converts the
a high-speed path, is employed [13], [23]. For the inner input output voltage of the loop filter into a pulse signal; next, the
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WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER 7

Fig. 13. Schematic of the CRTDC.

with simulation (and measurement presented in Section IV).

This design approach not only reduces the quantizer power
consumption but also relaxes the design effort on the prior
stage.
Fig. 12. VTC circuit consisted of ramp generator and comparator. Considering the PVT variations, the characteristics of delay
elements of TDC and ramp generator also vary; these effec-
tively change the quantizer gain. With the 3 bit time-domain
CRTDC digitizes the pulse signal generated by the VTC into quantizer and 8 dB out-of-band gain adopted in this design, a
digital codes which represent the loop filter output. ±10% gain variation of the quantizer leads to less than 1.4 dB
Fig. 12 depicts the circuit schematic of the VTC; it consists change in the SQNR. Despite the small degradation, the vari-
of two comparators and a ramp generator. In Fig. 12, VLP is ation in the effective quantizer gain is mitigated in this work
the loop filter output; Vref is a reference voltage that is deter- by adjusting the value of Cramp shown in Fig. 12 with 4 bit
mined by the lowest voltage of the loop filter output. Vramp is a external control.
triangular-shaped ramp signal that is generated by a ramp gen- To further lower power dissipation, current-gating technique
erator circuit. As also illustrated in Fig. 12, by comparing VLP is employed in the VTC. Since the comparison operation
and Vref with Vramp via the two comparators, two time-domain only occupies a fraction of a clock cycle, powering down the
edge signals Vpulse+ and Vpulse− are generated, respectively. comparator temporarily in the unused time interval is possi-
These two edges then constitute a pulsewidth that is propor- ble. However, turning off the whole comparator would lower
tional to the voltage difference between VLP and Vref . In effect, the operation speed of the VTC. In this design, only the most
the VTC acts as a pulsewidth modulation (PWM) circuit that power-hungry part of the comparator, which is the input inverter
converts the VLP signal into a pulsewidth signal. stage with the active load, is turned off during the inactive
To ensure that the VTC operates as designed, the ramp period. In Fig. 12, the gating transistor M7 serves to discon-
generator demands some design considerations. In [14], the nect partial branches (M1 − M6 ) of the comparator from the
conversion from an analog signal to a pulse signal occupies supply voltage when CLK = 0 (CLKB = 1).
nearly a full clock period due to excessive quantization lev- Following the VTC, the CRTDC circuit digitizes the
els; therefore, the ramp signal must also be valid for the full pulsewidth signal formed by the edges of Vpulse+ and Vpulse− .
clock cycle. A switched-current integrator is adopted to realize Fig. 13 shows the CRTDC circuit which replaces the conven-
the ramp generator, where the tail current of the integrator and tional flash-type quantizer. The Vernier TDC-based configura-
the load capacitor (Cramp ) determines the slope of the ramp tion is adopted with a time resolution of 75 ps. However, in
signal. As the ramp signal must be valid for the whole clock contrast to a conventional Vernier TDC, the delay cells of the
cycle, the ramp generator adopts the class-A architecture, which proposed CRTDC are connected in a circular manner, as illus-
is less power efficient. Furthermore, to maintain a stable input trated in Fig. 13. Furthermore, the input of each delay cell can
to VTC during one clock period, a sample-and-hold (S/H) cir- serve as a signal entry point by adding a multiplexer to each
cuit is required before the comparator. Both issues lead to larger delay cell input. As a pulse signal travel through the CRTDC,
circuit latency and higher power consumption. the end point of the present pulse signal can be easily identi-
In this work, the ramp generator design is based on a single- fied by detecting the transition of output codes from 1 to 0. The
ended two-stage operational amplifier. The outer stage of the subsequent incoming pulse signal would then be injected to the
proposed ramp generator is a class-AB stage that generates a input of next delay cell to start another conversion operation.
linear ramp signal efficiently. Instead of using a whole clock One important advantage of the proposed CRTDC is that
period for the analog-to-pulse-signal conversion, only a por- both the mismatches among multiple DAC cells and those
tion of the ramp signal (Vramp ) is adopted for comparison. of multiple TDC delay cells are mitigated due to this barrel-
Therefore, the linearity of Vramp only needs to be ensured dur- shifting operation. In effect, the CRTDC implements an
ing a narrow period. Furthermore, for low-power consideration, inherent data-weighted averaging (DWA) algorithm with little
the frontend S/H circuit is eliminated. (The design robustness hardware overhead. Furthermore, with this inherent-DWA oper-
of the modulator without S/H circuit is verified by applying ation, the latency associated with the DWA algorithm is elimi-
two out-of-band interferences to the modulator in testing, and nated and the timing constraint on the CRTDC is considerably
is demonstrated in Section IV.) Considering the OSR (∼ 17.6) relaxed. Comparing to a VCO-based quantizer, the CRTDC
in this modulator, the performance loss due to eliminating S/H can realize the quantization and DWA functions concurrently
circuit is negligible. This has been verified in system analysis without the assistance of the explicitly preceding ring oscillator.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 14. DAC1 circuit for the input stage and DAC driver.

Fig. 17. Output spectrum with the (a) DWA function disabled and (b) DWA
function enabled by configuring the TDC as a CRTDC.

IV. E XPERIMENTAL R ESULTS

Fig. 15. Chip micrograph.
The CTDSM incorporating the proposed SAB-based loop
filter and DWA-embedded CRTDC is fabricated in a 90 nm
CMOS process. Fig. 15 shows the chip photo of the imple-
mented modulator. The active part of the proposed design
occupies an area of 0.2 mm × 0.6 mm. The modulator is mostly
operated from a 1.2 V supply, except the input-stage feed-
back DAC which is supplied from a 1.4 V voltage for noise
and linearity consideration, as described in Section III-D. Total
power dissipation of the modulator is 4.3 mW. Fig. 16 shows
Fig. 16. Pie chart of the power consumption distribution.
the power breakdown of the modulator. The most power con-
suming circuits are op-amp2 , which is used in the SAB-based
resonator, and the quantizer (including VTC and TDC). In this
design, the op-amp2 plays a key role in facilitating both the
D. DAC Circuits
ELD compensation path (s0 term) and s−1 term, which largely
The noise performance of the DAC feeding back to the input determines the modulator stability. Therefore, the op-amp2 is
stage is crucial, as this noise source is not shaped by the mod- designed with a higher GBW compared to that of op-amp1 .
ulator. Fig. 14 depicts the DAC circuit schematic. For linearity On the quantizer, two techniques DWA-embedded CRTDC and
and noise considerations, the cascode topology is adopted to supply-gated VTC are realized to facilitate low-power opera-
implement the current cell. The DAC is supplied from a 1.4 V tion. However, converting an analog signal to a pulse signal at
supply voltage to allow additional headroom to accommodate a high operating speed of 300 MHz still consumes considerable
the degeneration resistor for suppressing the thermal noise amount of power.
contributed by the tail current. Two off-chip capacitors (Cext For observing the SNDR and SNR performance, a 2 MHz
shown in Fig. 14) are added to filter the thermal noise from single-tone input signal with a maximum input voltage of
the bias current. The mismatch among the DAC unit cells is 1.6 Vpp-diff (−4 dBFS) is applied to the modulator. The mea-
solved by the DWA function inherent in the CRTDC (described sured output spectrum is shown in Fig. 17. Fig. 17(a) and
in Section III-C). However, the fast-switching DWA operation (b) shows the output spectra with the inherent-DWA func-
would still induce unwanted current spike at the drain node of tion disabled (the TDC is configured as a conventional Vernier
the tail current and result in signal-dependent harmonic tones. TDC by breaking the circular connection) and enabled (as a
To mitigate this effect, a DAC driver is inserted between the CRTDC), respectively. The output spectra show that both the
quantizer output and inputs of DAC cells to control the crossing in-band noise floor and harmonic tones are improved when the
point of the DAC control signals (in this case, a low-crossing inherent-DWA function is activated with the CRTDC topology.
signal) and minimize the current spike energy. The associated With an 8.5 MHz signal bandwidth, the maximum SNDR is
waveforms are also illustrated in Fig. 14. 67.2 dB. Fig. 18 illustrates the measured plot of the two-tone
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER 9

Fig. 18. Measured output spectrum with two-tone inputs.

Fig. 20. Measured out-of-band linearity (a) with two out-of-band tones at 11.5
and 21 MHz and (b) with two out-of-band tones at 20 and 42 MHz.

Fig. 19. Measured STF: (a) frequency span from 800 kHz to 150 MHz and
(b) close-up plot showing a maximum peaking of 6.3 dB.

test, where the frequencies of the two sinusoidal input tones are
located at 1.5 and 2 MHz. With −8 dBFS two-tone input sig- Fig. 21. SNR/SNDR versus normalized input signal level.
nals, the measured third-order intermodulation distortion (IM3)
is 71 dB below the two tones. The DWA operation results in
signal-dependent switching activities and induces second-order into the modulator to observe the in-band noise floor and the
harmonic tones [4]. In the measured result of Fig. 17(b), the in- out-of-band linearity. As shown in Fig. 20(a), the second-order
band noise is mainly dominated by the second-order harmonic intermodulation tone located at 9.5 MHz is −69 dBFS and the
tone and it may be caused by the interaction between the off- third-order intermodulation tone at 2 MHz is −86 dBFS. The
set voltage of op-amp and spiking current induced by frequent noise floor remains at a level similar to that of Fig. 17(b). To test
switching of DAC cells with the DWA function. the immunity to blocker signals at even higher frequencies, two
With the hybrid feedforward and feedback topology, the input signals of 20 and 42 MHz with −11 dBFS [tones A and B
modulator exhibits some peaking in the STF. This is observed in in Fig. 20(b)] are applied to the modulator. Fig. 20(b) shows that
measurement shown in Fig. 19. The STF is measured by sweep- the measured output spectrum and the third intermodulation
ing the input signal frequency from 800 kHz to 150 MHz. The tone at 2 MHz is −75.5 dBFS. As these intermodulation levels
measured STF with a frequency span up to 150 MHz is plot- are low and the noise floor remains similar to that without high-
ted in Fig. 19(a); a close-up plot up to 40 MHz is shown in frequency interferers, the performance loss due to eliminating
Fig. 19(b). The maximum peaking is 6.3 dB at 21 MHz and the S/H circuit is insignificant.
close to the value (∼ 7 dB) predicted by the behavior model. Fig. 21 shows the measured SNR and SNDR versus the
In the proposed time-domain quantizer, the S/H circuit, normalized input amplitudes. The modulator achieves 73 dB
which is typically required before the VTC, is eliminated for dynamic range (DR) in 8.5 MHz signal bandwidth, and the peak
low-power consideration. To test the robustness of this design SNR and peak SNDR are 69.3 and 67.2 dB, respectively.
approach, two out-of-band signals at 11.5 and 21 MHz with Table I summarizes the measured chip performance and com-
−11 dBFS amplitude [tones A and B in Fig. 20(a)] are injected pares with other CTDSM designs targeting at similar signal
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON

FoM = Power/(2 × Bandwidth × 2((Peak SNDR-1.76)/6.02) ).

Conv.: loop filter implemented with active-RC integrators.
TD: time-domain quantizer.
BG*: circuit block for DAC linearization is implemented with digitally estimated auxiliary DAC and background operation.
FG*: circuit block for DAC linearization is implemented with post lookup table and foreground operation.

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[12] M. Ranjbar, A. Mehrabi, O. Oliaei, and F. Carrez, “A 3.1 mW continuous- Tzu-An Wei was born in Taipei, Taiwan, in 1987.
time ΔΣ modulator with 5-bit successive approximation quantizer for He received the B.S. degree from the National
WCDMA,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1479–1491, Cheng Kung University, Tainan, Taiwan, in 2011,
Aug. 2010. and the M.S. degree from the National Taiwan
[13] H.-C. Tsai, C.-L. Lo, C.-Y. Ho, and Y.-H. Lin, “A 64-fJ/conv.-step University, Taipei, Taiwan, in 2014, both in electronic
continuous-time ΣΔ modulator in 40-nm CMOS using asynchronous engineering. His thesis focused on the design
SAR quantizer and digital ΔΣ truncator,” IEEE J. Solid-State Circuits, and implementation of low power continuous-time
vol. 48, no. 11, pp. 2637–2648, Nov. 2013. delta-sigma modulator in wireless communication
[14] V. Dhanasekaran et al., “A 20 MHz BW 68 dB DR CT ΔΣ ADC based receivers.
on a multi-bit time-domain quantizer and feedback element,” in IEEE In 2014, he joined MediaTek Inc., Hsinchu,
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, Taiwan, where he is involved in mixed-signal cir-
pp. 174–175. cuits for wireless receivers. His research interests include wide-bandwidth
[15] O. Rajaee et al., “A 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline continuous-time delta-sigma ADC in cellular system.
ADC,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009,
pp. 74–75.
[16] M. S.-W. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asyn- Erkan Alpman (M’09) received the B.Sc. and M.Sc.
chronous ADC in 0.13-µm CMOS,” IEEE J. Solid-State Circuits, vol. 41, degrees in electrical and electronics engineering from
no. 12, pp. 2669–2680, Dec. 2006. Middle East Technical University, Ankara, Turkey, in
[17] M. Vadipour et al., “A 2.1 mW/3.2 mW delay-compensated GSM/ 2003 and 2005, respectively, and the Ph.D. degree in
WCDMA sigma-delta analog-digital converter,” in IEEE Symp. VLSI electrical and computer engineering from Carnegie
Circuits Dig. Tech. Papers, Jun. 2008, pp. 180–181. Mellon University, Pittsburgh, PA, USA, in 2009.
[18] M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns, and Y. Manoli, Since 2009, he has been an Analog Engineer/
“A comparative study on excess-loop-delay compensation techniques for Research Scientist with Intel Labs, Hillsboro, OR,
continuous-time sigma-delta modulators,” IEEE Trans. Circuits Syst. I, USA, working on analog and mixed signal circuits
Reg. Papers, vol. 55, no. 11, pp. 3480–3487, Dec. 2008. and architectures for wired/wireless transceivers in
[19] M. Ranjbar and O. Oliaei, “A multibit dual-feedback CT ΔΣ modulator scaled CMOS processes.
with lowpass signal transfer function,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 58, no. 9, pp. 2083–2095, Sep. 2011. Chang-Tsung Fu received the M.S and Ph.D.
[20] W. Yang et al., “A 100 mW 10-MHz BW CT SD modulator with 87 dB degrees in electrical engineering from the National
DR and 91 dBc IMD,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Chiao Tung University, Hsinchu, Taiwan, in 2001 and
Dig. Tech. Papers, Feb. 2008, pp. 498–499. 2009, respectively.
[21] C.-C. Lin, C.-H. Weng, T.-A. Wei, Y.-Y. Lin, and T.-H. Lin, “A In 2008, he joined Intel Labs, Hillsboro, OR, USA,
TDC-based two-step quantizer with swapper technique for a multibit as a Research Scientist and has dedicated on criti-
continuous-time delta-sigma modulator,” IEEE Trans. Circuits Syst. II, cal component and circuitry path finding on CMOS
Exp. Briefs, vol. 61, no. 2, pp. 75–79, Feb. 2014. RF/analog circuits, RF SoC integration, and design
[22] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and methodology. In 2015, he joined Intel Radio Product
E. Romani, “A 20 mW 640 MHz CMOS continuous-time ADC with Development Group, focused on connectivity for
20 MHz signal bandwidth, 80 dB dynamic range and 12 bit ENOB,” IEEE applications including Internet of Things. He cur-
J. Solid-State Circuits, vol. 41, no. 12, pp. 2641–2649, Dec. 2006. rently holds 8 issued and pending patents and has authored or coauthored
[23] P. Shettigar and S. Pavan, “Design techniques for wideband single-bit 16 papers in first-tier IEEE conferences or journals. His research works
continuous-time modulators with FIR feedback DACs,” IEEE J. Solid- include broadband noise matching theory, CMOS T/R switches, and high-
State Circuits, vol. 47, no. 12, pp. 2865–2879, Dec. 2012. linearity LNA. His research interests include RF/microwave component design,
[24] M. Taherzadeh-Sani and A. A. Hamoui, “A 1-V process-insensitive RF/analog circuit design, and wireless transceiver system.
current-scalable two-stage opamp with enhanced DC gain and settling
behavior in 65-nm digital CMOS,” IEEE J. Solid-State Circuits, vol. 46,
no. 3, pp. 660–668, Mar. 2011. Tsung-Hsien Lin (M’03–SM’09) received the B.S.
[25] S. Yan and E. Sanchez-Sinencio, “A continuous-time ΣΔ modulator with degree in electronics engineering from the National
88-dB dynamic range and 1.1-MHz signal bandwidth,” IEEE J. Solid- Chiao-Tung University, Hsinchu, Taiwan, and the
State Circuits, vol. 39, no. 1, pp. 75–86, Jan. 2004. M.S. and Ph.D. degrees in electrical engineering from
[26] J. G. Kauffman, P. Witte, J. Becker, and M. Ortmanns, “An 8.5 mW the University of California, Los Angeles, CA, USA,
continuous-time ΣΔ modulator with 25 MHz bandwidth using digital in 1997 and 2001, respectively.
background DAC linearization to achieve 63.5 dB SNDR and 81 dB In 2000, he joined Broadcom Corporation, Irvine,
SFDR,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2869–2881, Mar. CA, USA, as a Senior Staff Scientist, where
2011. he was involved in wireless transceiver develop-
[27] P. Witte, J. G. Kauffman, J. Becker, Y. Manoli, and M. Ortmanns, “A ments. In 2004, he joined the Graduate Institute
72 dB DR CT ΔΣ modulator using digitally estimated, auxiliary DAC of Electronics Engineering and the Department of
linearization achieving 88 fJ/conv in a 25 MHz BW,” in IEEE Int. Solid- Electrical Engineering, National Taiwan University, Taipei, Taiwan, where he
State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 154–155. is currently a Professor. His research interests include the design of wireless
[28] Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, and P.-C. Chiu, “A 28 fJ/conv- transceivers, clock and frequency generation systems, delta-sigma modulators,
step CT ΔΣ modulator with 78 dB DR and 18 MHz BW in 28 nm CMOS and transducer interface circuits.
using a highly digital multibit quantizer,” in IEEE Int. Solid-State Circuits Dr. Lin served on the IEEE Asian Solid-State Circuit Conference (A-SSCC)
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 268–269. Technical Program Committee (TPC) from 2005 to 2011 and was the TPC Vice-
Chair for 2011 A-SSCC. He was a Guest Editor for the IEEE J OURNAL OF
Chan-Hsiang Weng received the B.S. degree from S OLID -S TATE C IRCUITS (JSSC) in 2012 and was an Associate Editor for the
the National Central University, Taoyuan, Taiwan, same journal from 2013 to 2015. He has been serving the ISSCC International
and the M.S. and Ph.D. degrees from the National Technical Program Committee (ITPC) since 2010, and is in the ISSCC Student
Taiwan University, Taipei, Taiwan, in 2005, 2008, and Research Preview (SRP) Committee since 2012. He was the recipient of the
2015, respectively, all in electrical engineering. Best Presentation Award for his paper presented at the 2007 IEEE VLSI-DAT
From 2008 to 2011, he was a Mixed-Signal Design Symposium, and the Best Paper Award at the same Symposium in 2015. He was
Engineer with Airoha Corp., Hsinchu, Taiwan, dur- also the recipient of the Teaching Excellence Award from the National Taiwan
ing which time he was involved in the development University in 2007, 2008, and 2014, and Exceptional Teaching Excellence
of wireless for FM, BT, and audio applications. In Award in 2009.
the summer 2013, he was an Intern with Intel Labs,
Portland, OR, USA. He is currently with Mediatek
Corp., Hsinchu, Taiwan, where he has been engaged in the design of mixed-
signal integrated circuits for wireless communications. His research interests
include data converters, temperature sensors, and mixed-signal circuit designs.
Dr. Weng was the recipient of the Intel-NTU Center Fellowship in 2014 and
2015 and the Best Paper Award for the 2015 IEEE VLSI-DAT Symposium.