Design and Implementation of

VLSI Systems
Lecture 08
Thuan Nguyen
Faculty of Electronics and Telecommunications,
University of Science, VNU HCMUS
Spring 2011
1
1 Static CMOS

2 Ratioed Circuits

3 Dynamic Circuits

4 Pass-transistor Circuits

2
1 Static CMOS

2 Ratioed Circuits

3 Dynamic Circuits

4 Pass-transistor Circuits

3
COMPOUND GATES

 Logical Effort of compound gates

unit inverter AOI21 AOI22 Complex AOI

YA Y  A BC Y  A BC D Y  A B  C  D E

D
A A E
Y
B B A
A Y Y Y
C C B
D C

A 4 B 4 A 4 B 4 B 6
2 C 4 C 4 D 4 C 6 A 3
A Y Y Y
1 A 2 A 2 C 2 D 6 E 6
C 1 Y
B 2 B 2 D 2 E 2 A 2
D 2 B 2 C 2

gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3

p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3
gC = 5/3 gC = 6/3 gC = 8/3
p = 7/3 gD = 6/3 gD = 8/3
4
p = 12/3 gE = 8/3
p = 16/3
EXAMPLE
 A multiplexer has a maximum input capacitance of 16
units on each input. It must drive a load of 160 units.
Estimate the delay of the two designs below.
H = 160 / 16 = 10 B = 1 N = 2

D0 D0
S S
Y Y
D1
D1
S S
P  22 4 P  4 1  5
G  (4 / 3) (4 / 3)  16 / 9 G  (6 / 3) (1)  2
F  GBH  160 / 9 F  GBH  20
fˆ  N F  4.2 fˆ  N F  4.5
D  Nfˆ  P  12.4 D  Nfˆ  P  14 5
EXAMPLE

 Annotate your designs with transistor sizes that

achieve this delay.

8 8
8 10 10
8 25 25 10 10 24
Y Y
25 6 6 12
8 8 25 6 6
8
8
16 160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36

6
INPUT ARRIVAL TIME

 Arrival time of A and B when getting to NAND2 gate

may be different
 A would come sooner than B if Circuit A was less
delay than Circuit B

2 2 Y
Circuit A
A 2
B 2
Circuit B

7
INNER & OUTER INPUTS

 Inner input is closest to output (A)

 Outer input is closest to suply rail (B)

2 2 Y
A 2 6C

B 2x 2C

 If input arrival time is known

 Connect earliest input to outer terminal
 Connect latest input to inner terminal

8
PERFECT SYMMETRIC GATES

 Inputs can be made perfectly symmetric

 Delay of a perfect symmetric gate is identical for all
inputs

2 2
Y
A 1 1
B 1 1

9
ASYMMETRIC GATES
 Asymmetric gates favor one input over another
 Suppose input A of a NAND gate is most critical. This
NAND gate can be modified to favor input A
 Use smaller transistor on A (less capacitance)
 Increase size of noncritical input
 So total resistance is same A
Y
reset

 gA = 10/9
2 2
 gB = 2 Y
A 4/3
 gtotal = gA + gB = 28/9
reset 4

 Asymmetric gate approaches g = 1 on critical input

 But total logical effort goes up 10
SKEWED INVERTER

𝛽𝑛
o = 1: un-skewed inv
𝛽𝑝
𝛽𝑛
o > 1: HI-skewed inv
𝛽𝑝
𝛽𝑛
o < 1: LO-skewed inv
𝛽𝑝

Transfer characteristics of
skewed inverter

11
SKEWED GATES

 Skewed gates favor one transition edge over

another
 Ex: suppose rising output of inverter is most critical
 Downsize noncritical nMOS transistor
HI-skew unskewed inverter unskewed inverter
inverter (equal rise resistance) (equal fall resistance)

2 2 1
A Y A Y A Y
1/2 1 1/2

 Calculate logical effort by comparing to unskewed

inverter with same effective resistance on that
edge.
 gu = 2.5 / 3 = 5/6
 gd = 2.5 / 1.5 = 5/3 12
HI- AND LO-SKEW

 Def: Logical effort of a skewed gate for a particular

transition is the ratio of the input capacitance of that
gate to the input capacitance of an un-skewed
inverter delivering the same output current for the
same transition.

 Skewed gates reduce size of noncritical transistors

 HI-skew gates favor rising output (small nMOS)
 LO-skew gates favor falling output (small pMOS)

 Logical effort is smaller for favored direction

 But larger for the other direction

13
 CATALOG OF SKEWED GATES
Inverter NAND2 NOR2

2 2 B 4
Y
2 A 4
A 2
unskewed A Y Y
1 gu = 1 B 2 gu = 4/3 1 1 gu = 5/3
gd = 1 gd = 4/3 gd = 5/3
gavg = 1 gavg = 4/3 gavg = 5/3

2 2 B 4
Y
2 A 4
A 1
HI-skew A Y Y
1/2 gu = 5/6 B 1 gu = 1 1/2 1/2 gu = 3/2
gd = 5/3 gd = 2 gd = 3
gavg = 5/4 gavg = 3/2 gavg = 9/4
1 1 B 2
Y
1 A 2
A 2
LO-skew A Y Y
1 gu = 4/3 B 2 gu = 2 1 1 gu =2
gd = 2/3 gd = 1 gd =14
1
gavg = 1 gavg = 3/2 gavg = 3/2
BEST P/N RATIO

 P/N ratio giving lowest average delay is the square

root of the ratio that gives equal rise and fall delays
 You will prove this as a homework

15
PROPERTIES OF STATIC CMOS GATES

 High noise margins

 In ideal condition (no leakage current), static power

consumption is zero

 Comparable rise and fall times (under the appropriate

scaling conditions)

16
CIRCUIT FAMILIES
 The delay of a logic gate:
C: load capacitance
𝐶
t ∝ ∆𝑉 I: output current
𝐼
∆𝑉: output voltage swing

 nMOS provides more current than pMOS for the same size
and capacitance
 Static CMOS requires both nMOS and pMOS on each input.
 All the node voltages in static CMOS must transition between
0 and VDD  propagation delay + power consumption.

 Circuit families
17
1 Static CMOS

2 Ratioed Circuits

3 Dynamic Circuits

4 Pass-transistor Circuits

18
INTRODUCTION

 Ratioed gate consists of a pulldown network and some

pullup device called the static load.

 When pulldown network is OFF, the

static load pulls output to 1

 When pulldown network turns ON, it

fights the static load to pull output to 0

 The static load must be weak enough

that the output pulls down to an
acceptable 0 19
PSEUDO-NMOS

20
 PSEUDO-NMOS GATES

 Design for unit current on output to

Y
compare with unit inverter.
inputs
 pMOS fights nMOS f

Inverter NAND2 NOR2

gu = 4/3 gu = 8/3 gu = 4/3

gd = 4/9 2/3 g = 8/9 gd = 4/9
gavg = 8/9 Y gd = 16/9 gavg = 8/9
2/3 avg 2/3
pu = 6/3 A 8/3 pu = 10/3
Y Y pu = 10/3
A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9
pavg = 12/9 pavg = 20/9 pavg = 20/9
21
PSEUDO-NMOS DELAY

 Ex: Design a k-input AND gate using pseudo-

nMOS. Estimate the delay driving a capacitor of H

Pseudo-nMOS
In1 1
Y
 G = 1 * 8/9 = 8/9 H
Ink 1
 F = GBH = 8H/9

 P = 1 + (4+8k)/9 = (8k+13)/9

N=2
4 2 H 8k  13
 D = NF1/N + P = 
3 9

22
PSEUDO-NMOS POWER

 Pseudo-nMOS draws power whenever Y = 0

 Called static power P = IDDVDD
 A few mA / gate * 1M gates would be a problem
 Explains why pseudo-nMOS went extinct

 Use pseudo-nMOS sparingly for wide NORs

 Turn off pMOS when not in use

en
Y
A B C
23
PSEUDO-NMOS SUMMARY

 Pseudo-nMOS uses a always-ON pMOS transistor as

the static load to fight nMOS network

 The transfer function depends on the ratio of the

strength of the pull-down to the pull-up => Make pMOS
about ¼ effective strength of pulldown network

 Pseudo-nMOS dissipates power continually in certain

states and have poorer noise margins than static
CMOS circuits.

 Pseudo-nMOS is used only in very limited 24

circumstances
1 Static CMOS

2 Ratioed Circuits

3 Dynamic Circuits

4 Pass-transistor Circuits

25
DYNAMIC LOGIC

 Dynamic gates uses a clocked pMOS pullup

 Two modes: precharge and evaluate

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

 Precharge Evaluate Precharge

26
THE FOOT

 What if pulldown network is ON during precharge?

 Use series evaluation transistor to prevent fight.

 
precharge transistor
 Y Y
Y inputs inputs
A f f

foot
footed unfooted

27
 LOGICAL EFFORT

Inverter NAND2 NOR2

 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3

 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3

28
DYNAMIC LOGIC CHARACTERISTIC

 N+2 transistors for N-input function

– Better than 2N transistors for static CMOS
– Comparable to N+1 for ratioed circuit

 Low logical effort and parasitic delay

– Better than static CMOS

 No static power dissipation

– Better than ratioed circuit

 However, Dynamic Logic must solve many

29
challenges as shown in the next slides
MONOTONICITY

 Dynamic gates require monotonically rising

inputs during evaluation
 00 
 01
 11 A
 But not 1  0

violates monotonicity
during evaluation
A

 Precharge Evaluate Precharge

Y
30

Output should rise but does not

 MONOTONICITY

 Dynamic gates produce monotonically falling

outputs during evaluation. This output is Illegal to
drive to drive another dynamic gate (assuming both
gates are using same clock)!

A=1

  Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot
31
DOMINO LOGIC
 Monotonicity problem can be
solved by placing a static CMOS
inverter between dynamic gates

 HI-Skew inverter is usually prefered

 Monotonically falling output

become monotonically rising signal

 Precharge occurs in parallel, but

evaluation occurs sequentially

32
DOMINO COMPOUND GATE
 Other CMOS gates such as NANDs or NORs can
be used in place of the inverter to perform logic

S0 S1 S2 S3
D0 D1 D2 D3
Y
H


S4 S5 S6 S7
D4 D5 D6 D7 33
LEAKAGE
 Dynamic node floats high during evaluation
 Transistors are leaky (IOFF  0)
 Dynamic value will leak away over time
 Formerly miliseconds, now nanoseconds

 Use keeper to hold dynamic node

 Must be weak enough not to fight evaluation

weak keeper
 1 k
X
H Y
A 2
2 34
CHARGE SHARING

 Dynamic gates suffer from charge sharing



Y A
A x CY
Y
B=0 Cx Charge sharing noise

CY
Vx  VY  VDD
Cx  CY
35
SECONDARY PRECHARGE

 Solution: add secondary precharge transistors

 Typically need to precharge every other node

 Big load capacitance CY helps as well

secondary
 precharge
Y transistor
A x
B

36
NOISE SENSITIVITY

 Dynamic gates are very sensitive to noise

 Inputs: VIH  Vtn
 Outputs: floating output susceptible noise

 Noise sources
 Capacitive crosstalk
 Charge sharing
 Power supply noise
 Feedthrough noise
 And more!

37
POWER

 Domino gates have high activity factors

 Output evaluates and precharges
 If output probability = 0.5, a = 0.5
 Output rises and falls on half the cycles

 Clocked transistors have a = 1

 Leads to very high power consumption

38
DYNAMIC CIRCUIT SUMMARY

 Domino logic is attractive for high-speed circuits

 1.3 – 2x faster than static CMOS
 But many challenges:
 Monotonicity, leakage, charge sharing, noise

 Widely used in high-performance microprocessors

in 1990s when speed was king

 Largely displaced by static CMOS now that power

is the limiter

 Still used in memories for area efficiency 39

1 Static CMOS

2 Ratioed Circuits

3 Dynamic Circuits

4 Pass-transistor Circuits

40
PASS TRANSISTOR CIRCUITS

 Use pass transistors like switches to do logic

 Inputs drive diffusion terminals as well as gates

 CMOS + Transmission Gates:

 2-input multiplexer
 Gates should be restoring

S S

A A

S Y S Y

B B

S S
41
LEAP

 LEAn integration with Pass transistors

 Get rid of pMOS transistors
 Use weak pMOS feedback to pull fully high
 Ratio constraint

S
A
S L Y
B

42
CPL

 Complementary Pass-transistor Logic

 Dual-rail form of pass transistor logic
 Avoids need for ratioed feedback
 Optional cross-coupling for rail-to-rail swing

S
A
S L Y
B
S
A
S L Y
B

43
PASS TRANSISTOR SUMMARY

 Researchers investigated pass transistor logic for

general purpose applications in the 1990’s
 Benefits over static CMOS were small or negative
 No longer generally used

 However, pass transistors still have a niche in

special circuits such as memories where they offer
small size and the threshold drops can be managed

44
CMOS CIRCUIT STYLES - SUMMARY

45
Q&A

46