Design and Implementation of

VLSI Systems
Lecture 05

Ref: Neil H.E. Weste, David Money Harris; CMOS VLSI Design: A Circuit and Systems Perspective 4th
WHERE ARE WE?

CMOS LOGIC Combination and sequential circuits

are made up from CMOS

CMOS FAB TECHNOLOGY Fabricattion of a CMOS circuit

Layout of a CMOS circuit

CMOS CIRCUITRY LAYOUT How large is it? How costly is it?

MOS TRANSISTOR THEORY I-V and C-V Characteristics of a MOS

CMOS ANALYSIS DELAY How fast is a CMOS circuit?

How much power a CMOS circuit

CMOS ANALYSIS POWER
consump? 2
CONTENT

1 Inverter Transient Response

2 RC Delay Model

3 Linear Delay Model

3
CONTENT

1 Inverter Transient Response

2 RC Delay Model

3 Linear Delay Model

4
INVERTER DRIVING INVERTER

5
HOW CURRENT FLOW?

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 DELAY OF INVERTER X1

 What if there was no  There is capacitor at node B

capacitor at node B ? actually …

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DELAY OF INVERTER X1 (CONT)
 tpdr: rising propagation delay
 Max time: From input to rising output crossing VDD/2
 tpdf: falling propagation delay
 Max time: From input to falling output crossing VDD/2
 tpd: average propagation delay. tpd = (tpdr + tpdf)/2

 tcdr: rising contamination (best-case) delay

 Min time: From input to rising output crossing VDD/2
 tcdf: falling contamination (best-case) delay
 Min time: From input to falling output crossing VDD/2
 tcd: average contamination delay. tcd = (tcdr + tcdf)/2

 tr: rise time

 From output crossing 0.2 VDD to 0.8 VDD
 tf: fall time 8
 From output crossing 0.8 VDD to 0.2 VDD
 DELAY OF INVERTER X1 (CONT)

 We want to calculate tpdf and tpdr

of inverter X1.

 Capacitor Cgp1, Cgn1, Csbp1,

Csbn1, Csbp2, Csbn2, Cdbp2, Cdbn2
are irrelevant of the delay

 Other capacitors can be

combined into a single capacitor
Cout connected to GND.

 Cout = Cdbn1 + Cdbp1 + Cwire +

Cgn2 + Cgp2
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DELAY OF INVERTER X1 (CONT)

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 DELAY OF INVERTER X1 (CONT)

 Solving the differential equation

by hand is too hard.
 SPICE simulator solves the
equation numerically (It uses
more accurate I-V, C-V models
too)

 We would like to be able to easily estimate delay:

+ Not as accurate as simulation + But easier to ask “What if?”
 Note that:
+ βp = βn => tpdf = tpdr
+ tpdf and tpdr increases with Cout and decreases with 11

the driver current

CONTENT

1 Inverter Transient Response

2 RC Delay Model

3 Linear Delay Model

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1ST ORDER RC DELAY

13
tdelay = RCln2 => We say the delay is RC for short
NTH ORDER RC DELAY (ELMORE DELAY)

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 UNIT TRANSISTOR MODEL
 Unit MOS transistor is a transistor with minimum length
(L) and minimum width (W) in a fabrication process

 Unit nMOS is equivalent to an  Unit pMOS is equivalent to an

circuit of: circuit of:
+ Ideal switch + Ideal switch
+ Capacitance C + Capacitance C
+ Effective Resistance R + Effective Resistance 2R

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 GENERIC TRANSISTOR MODEL

 nMOS transistor whose width  pMOS transistor whose width

is k-time wider than unit is k-time wider than unit
nMOS is equivalent to an pMOS is equivalent to an
circuit of: circuit of:
+ Ideal switch + Ideal switch
+ Capacitance kC + Capacitance kC
+ Effective Resistance R/k + Effective Resistance 2R/k
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s 16
s
d
DELAY OF UNIT INVERTER

 Estimate tpdf

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tpdf = 6RC
DELAY OF UNIT INVERTER

 Estimate tpdf

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tpdf = 6RC
DELAY OF UNIT INVERTER (CONT)

 Estimate tpdr

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tpdr = 6RC
DELAY OF UNIT INVERTER (CONT)

 Estimate tpdr

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tpdr = 6RC
MOS TRANSISTORS IN SERIES
 Diffusion regions of series transistors can be merged
together to reduce diffusion capacitors

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EXAMPLE: 3-INPUT NAND
 Sketch a 3-input NAND with transistor widths chosen to achieve
effective rise and fall resistances equal to a unit inverter (R).
 This is a good common practise to have equal rising and falling
delay

2 2 2

3
3

3
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EXAMPLE: 3-INPUT NAND CAPS
 Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
9C
3 3C
5C 3C
3C
3
5C 3C
3C
3
5C 3C
3C
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 EXAMPLE: 3-INPUT NAND DELAY

 Estimate tpdr tpdf tcdr and tcdf of 3-input NAND driving h identical gates.
 Fan-out of this gate is h
 Fan-in of this gate is 3

h copies

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 EXAMPLE: 3-INPUT NAND DELAY (CONT)

 tpdr happens when A, B, C change their states from (1,1,1) to (1,1,0)

 tpdr = ((9 + 5h)C)(R) + (3C)(R) + (3C)(R)

= (15 + 5h)RC 25
 EXAMPLE: 3-INPUT NAND DELAY (CONT)

 tpdf happens when A, B, C change their states from (1,1,0) to (1,1,1)

 tpdf = (3C)(R/3) + (3C)(R/3 + R/3) + ((9 + 5h)C)(R/3+ R/3+ R/3)

= (12 + 5h)RC 26
 EXAMPLE: 3-INPUT NAND DELAY (CONT)

 tcdr happens when A, B, C change their states from (1,1,1) to (0,0,0)

 tcdr = (3 + (5/3)h)RC
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 EXAMPLE: 3-INPUT NAND DELAY (CONT)

 tcdf happens when A, B, C change their states from (0,1,1) to (1,1,1)

 tcdf = (9 + 5h)RC
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 EXAMPLE: 3-INPUT NAND DELAY (CONT)

 tpdr tpdf tcdr and tcdf all consists of two components:

 Parasitic delay caused by parasitic capacitor in

diffusion region source and drain. This delay is
independent of the transistor width

 Effort delay caused by driving external load

capacitance. This delay reduced when the transistor
width increase
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CONTENT

1 Inverter Transient Response

2 RC Delay Model

3 Linear Delay Model

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 INTRODUCTION
 Chip designers face a bewildering array of choices
 What is the best circuit topology for a function?
 How many stages of logic give least delay?
???
 How wide should the transistors be?

 Consider a design consists of 3 stages

 Delay = delaygate1 + delaygate2 + delaygate3
 Increase transistor width of gate2 certainly reduces
delaygate2 but also increases delaygate1. Is it a correct
choice?

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Gate 1 Gate 2 Gate 3
NORMALIZED DELAY OF A GATE

 The normalized delay of a gate can be expressed as

d = f + p = gh + p (in unit of t)
 f: effort delay (a.k.a. stage effort)
 g: logical effort
 Measures relative ability of gate to deliver current
 g  1 for inverter
 h: electrical effort = Cout / Cin
 Ratio of output to input capacitance
 Sometimes called fanout
 p: parasitic delay
 Represents delay of gate driving no load
 Set by internal parasitic capacitance 32
 t: constant for a fabrication process, t = 3RC
LOGICAL EFFORT

 Logical effort is the ratio of the input capacitance of a

gate to the input capacitance of an inverter delivering the
same output current.
 Measure from delay vs. fanout plots

 Or estimate by counting transistor widths

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PARASITIC DELAY

 Parasitic delay of a gate is the delay of the gate when it

drives zero load.
 It can be estimated with RC delay models

 Or counting only diffusion capacitance on the output

node for roughly estimation

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CATALOG OF GATES
 Logical effort of common gates

Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8

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CATALOG OF GATES
 Parasitic delay of common gates
 In multiples of pinv (1)

Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
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EXAMPLE: RING OSCILLATOR

 Estimate the frequency of an N-stage ring oscillator

Logical Effort: g=1

Electrical Effort: h = 1
Parasitic Delay: p = 1
Stage Delay: d=2
Frequency: fosc = 1/(2*N*d) = 1/4N
In 65 nm process, t = 3ps => 31-stage ring oscillator 37

has frequency of ~ 1/(4 × 31 × 3 ps) = 2.7 GHz

EXAMPLE: FO4 INVERTER

 Estimate the delay of a fanout-of-4 (FO4) inverter

d

Logical Effort: g=1

Electrical Effort: h=4
Parasitic Delay: p=1
Stage Delay: d=5
In 65 nm process, t = 3ps => delay of a fanout-of-4 38

(FO4) inverter is 5 x 3ps = 15ps

MULTISTAGE LOGIC NETWORKS

 Logical effort generalizes to multistage networks

 Path Logical Effort G gi 
Cout-path
 Path Electrical Effort H
Cin-path
 Path Effort F   f i   gi hi

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z 39
MULTISTAGE LOGIC NETWORKS

 Logical effort generalizes to multistage networks

 Path Logical Effort G  gi
Cout  path
 Path Electrical Effort H
Cin  path
 Path Effort F   f i   gi hi

 Can we write F = GH?

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PATHS THAT BRANCH

 No! Consider paths that branch:

G =1 15
90
H = 90 / 5 = 18 5
GH = 18
15
g1 =1 90
g2 =1
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = f1f2 = g1h1g2h2 = 36 = 2GH 41
BRANCHING EFFORT

 Introduce branching effort

 Accounts for branching between stages in path
Con path  Coff path
b
Con path
B   bi
Note:

 Now we compute the path effort

 h  BHi

 F = GBH

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MULTISTAGE DELAYS

 Path Effort Delay DF   f i

 Path Parasitic Delay P   pi

 Path Delay D   d i  DF  P

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DESIGNING FAST CIRCUITS

D   d i  DF  P
 Delay is smallest when each stage bears same effort

fˆ  gi hi  F
1
N

 Thus minimum delay of N stage path is

1
D  NF  P N

 This is a key result of logical effort

 Find fastest possible delay
 Doesn’t require calculating gate sizes
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GATE SIZES

 How wide should the gates be for least delay?

fˆ  gh  g CCoutin
gi Couti
 Cini 
fˆ
 Working backward, apply capacitance transformation to
find input capacitance of each gate given load it drives.
 Check work by verifying input cap spec is met.

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EXAMPLE

 Select gate sizes for least delay from A to B

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EXAMPLE (CONT)

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ  3 F  5
Parasitic Delay P=2+3+2=7 47

Delay D = 3*5 + 7 = 22
EXAMPLE (CONT)
 Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

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EXAMPLE (CONT)
 Verification
d1 = f1 + p1 = g1h1 + p1 = (4/3) × (10 + 10 + 10)/8 + 2 = 7
d2 = f2 + p2 = g2h2 + p2 = (5/3) × (15 + 15)/10 + 3 = 8
d3 = f3 + p3 = g3h3 + p3 = (5/3) × 45/15 + 2 = 7
=> path delay is 7 + 8 + 7 = 22
In 65 nm process, t = 3ps => path delay is 22 x 3ps = 66ps

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BEST NUMBER OF STAGES
 How many stages should a path use?
 Minimizing number of stages is not always fastest
 Example: drive 64-bit datapath with unit inverter
Initial Driver 1 1 1 1

8 4 2.8
D = NF1/N+P
= N(64)1/N + N 16 8

23

Datapath Load 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3 50
Fastest
BEST NUMBER OF STAGES (CONT)
 Consider a path
 F is the path effort
 𝑁 is the best number of stages
 ρ is the best stage effort,

=> The path achieves

least delay by using ρ
in the range of 2.4 to 6
(ρ = 4 is a convenient
choice)

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METHOD OF LOGICAL EFFORT

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NOTATION OF LOGICAL EFFORT

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LIMITS OF LOGICAL EFFORT

 Chicken and egg problem

 Need path to compute G
 But don’t know number of stages without G

 Simplistic delay model

 Neglects input rise time effects
 Interconnect
 Iteration required in designs with wire
 Maximum speed only
 Not minimum area/power for constrained delay

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SUMMARY
 Logical effort is useful for thinking of delay in
circuits
 Numeric logical effort characterizes gates
 NANDs are faster than NORs in CMOS
 Paths are fastest when effort delays are ~4
 Path delay is weakly sensitive to stages, sizes
 But using fewer stages doesn’t mean faster paths
 Delay of path is about log4F FO4 inverter delays
 Inverters and NAND2 best for driving large caps
 Provides language for discussing fast circuits
 But requires practice to master
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