Q.

Write at least six difference between RISC and CISC

RISC CISC
Columns are difficult columns are easy
emphasis on hardware emphasis on software
the register is less complexity in compiler
use allot of microprogramming instruction set with formats less
addressing modes more than CISC Less addressing modes
multiple instruction formats and size. register more

Q. Illustrate what do you mean by Interrupt. Write its main purpose. Discuss hardware interrupt, Software
interrupt and priority interrupt. Explain how interrupts are prioritized.

Interrupt  It alerts the processor of interrupt and act as request to processor.

 Interrupt has highest priority for software and hardware events.
Purpose of Interrupt  Main purpose of interrupt is to increase efficiency of processor.
 Processor is faster as compared to external devices therefore a lot of time is
wasted matching their speeds.
hardware interrupt  when any external device or hardware send signal for processor it's hardware
Interrupt.
 These are of two types:
1. Maskable
2. Non-Maskable
Software interrupt  Caused by internal system
 These are of two types:
1. Normal interrupt
2. Exception
priority interrupt It's used to decide the priority of interrupt causing devices. This priority is then used
by processor to respond to interrupts.
how are interrupts  Interrupt are prioritized using Daisy currently being excepted.
prioritized?  All interrupt generating devises are serially connected.

Q. Illustrate Virtual memory and its working details.

is an area of a computer system's secondary memory storage space (such as a hard disk) which acts as if it
were a part of the system's RAM or primary memory. Ideally, the data needed to run applications is stored in
RAM, where they can be accessed quickly by the CPU.
Q. Interpret Logical address with an example. Illustrate the purpose of Page table and sketch a diagram to
show the Page table connection with the Logical and Physical address.

Logical addresses

are generated by the CPU for the pages of the processes

therefore they are generally used by the processes.

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 Page Table:
is a data structure used by the virtual memory system to store the mapping between logical addresses and
physical addresses.

Q. Evaluate the Translation Lookaside Buffer (TLB).

It's a memory buffer used to reduce the time it takes to reach a user's memory location.
It is a part of the chip memory management unit. TLB stores recent virtual memory translations into physical.
Q. Write the mnemonics to multiply the two numbers. First assign the value 25H and 32H into registers.
Then write mnemonics to find the multiplication

MVI C,25H Load value 25 in register C

MVI E,32H Load value 32 in register E
MVI D 00 Assigns 00 to 0
LXI H 0000 Assigns 00 to H and 00 to L
DAD D Adds HL and DE and assigns the result to HL
DCR C Decrements C by 1
JNZ 200A Jumps program counter to 200A if Zero flag = 0
SHLD 3050 Stores value of H at memory location 3051 and L at 3050
HLT Stops executing the program

Q. Write the difference between direct and register indirect addressing.

DIRECT ADDRESSING MODE INDIRECT ADDRESSING MODE

Address field contains the effective address of Address field contains reference of effective address
operand
Requires only one memory reference Requires two memory references
Fast addressing Slower than direct addressing mode
No further classification Further classified into two categories
No further calculation is required to perform the Require further calculation to find the effective
operation address

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 Q. What do you understand by XOR gate. Discuss it briefly.

• The XOR (exclusive-OR) gate acts in the same way as the logical "either/or." The output is "true" if
either, but not both, of the inputs are "true." The output is "false" if both inputs are "false" or if both
inputs are "true."

Define RS Latch. And explain.

The RS latch is the basic memory element consists of two cross-coupled NOR gates. It has two input signals, S set
signal and R reset signal. It also has two outputs Q and Q'; and two states, a set state when Q = 1 and a reset state
when Q = 0 (Q' = 1)

Draw the truth table for the given circuit.

Q. What do you understand by DDR SDRAM.

DDR SDRAM stands for Double Data Rate Synchronous Dynamic RAM. It can theoretically improve memory clock speed
to at least 200 MHz*. It activates output on both the rising and falling edge of the system clock rather than on just the
rising edge, potentially doubling output.
Q. Race Around condition in JK flip flop.
if J=K=1, and if CLK=1 for a long period of time, then Q output will toggle if CLK is high, which makes the
output of the flip-flop unstable or uncertain

What are in the general-purpose registers and Segment registers. Briefly describe them.

Ans: General-purpose registers are EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP and in the EFLAGS register. The
segment registers are CS, DS, SS, ES, FS, and GS.
AL, BL, CL and DL are eight-bit, general purpose registers where data is stored.
Define the term MAR, Program Counter (PC) & the Instruction Register (IR)
Memory Address Registers (MAR): holds the address of location into which the word is to be stored by CPU
The PC: is the register that contains the address of the next instruction to be fetched.

The IR: is the register that holds the loaded instruction for execution.

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 Data bus: The data lines provide a path for moving data among system modules. These lines, collectively,
are called the data bus. The data bus may consist of 32, 64, 128, or even more separate lines, the number
of lines being referred to as the width of the data bus.
Latches A latch is a memory element whose excitation signals control the state of the device. A latch has two stages
set and reset. Set stage sets the output to 1. Reset stage set the output to 0

L3 cache: Level 3 or L3 cache is specialized memory that works together with L1 and L2 cache to improve
computer performance.
What is the difference between DRAM and SRAM?

DRA SRA
M M
Slow Fast
Capacit Circ
ors uit
Need to refresh every MS No need to refresh
Cheaper Expensive
Define Addressing mode? Discuss immediate and indirect addressing mode using diagram.

An addressing mode specifies how to calculate the effective memory address of an

operand by using information held in registers and/or constants contained within a
machine instruction or elsewhere
1. Immediate
2. Indirect

Immediate addressing: The operand is given explicitly as the instruction, meaning operand is part of the
instruction.
• Operand is an immediate (constant) value.
• Immediate values are encoded directly into the instruction.
• No memory access is required.
• Fast addressing mode.
• Examples:
• ADD 5 meaning add 5 to contents of accumulator, here 5 is an operand

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 Indirect Addressing: Memory cell pointed to by Address field contains the address of (pointer to) the
operand.

Multiple memory accesses to find operand, Hence slower

Write COMAND for the given instructions

JAE : Jump if above or equal C=0

JG : Jump if greater Z=0 and S=0

Q. Write the command for data input from I/O port 07 to AL and Data output to I/O port 07 from AL

IN and OUT transfer data between an I/O device and the microprocessor's accumulator (AL, AX or EAX).
• IN Read from a port
• OUT Write to a port
• IN 07 Data input from I/O port 07 to AL.
• OUT 01 Data output to I/O port 07 from AL.

Analyze Branch instruction with an example

A branch instruction, also called a jump instruction, has as one of its operands address of the next instruction to be
executed. Most often, the instruction is a conditional branch instruction if a certain condition is met. Otherwise, the
next instruction in sequence is executed. A branch instruction in which the branch is always taken is an unconditional
branch.

BRP X Branch to location X if result is positive.

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 Q. Analyze the instruction 3
# Mnemonics Meaning
1 MOV AL,15 Copy 15 into AL
2 MOV BL,[15] Copy RAM [15] into BL
3 MOV [15], CL Copy CL into RAM [15]
4 DIV DL, AL DL / AL
5 MUL CL,03 CL * 3
6 BRZ X Branch instruction, Branch to location X if result is zero.
7 BRN X Branch to location X if result is negative
8 Branch to location X if overflow occurs.
BRO X
9 Branch to location X if result is positive.
BRP X
10 CMP AL,BL Set 'Z' flag if AL = BL. Set 'S' flag if AL < BL.

Q. Draw Diagram
Design logic gate for X, Y and Z for this formula ? 6

Draw a Circuit Diagram corresponding to the following Boolean expression.

, A̅ ( �̅ + �̅)
(���) + � (�̅ + �̅ ), ( �̅ + �̅) ( �̅ + �̅ ) �̅

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 Draw K map and solve the equation and then draw circuit 6

Y = A̅ B C̅ + A̅ B̅ C + A B̅ C̅ + A̅ B̅ C̅
Y = A̅ B̅ C̅ + A̅ B C̅ + A̅ B̅
Y = A̅ B + A B + A B̅
Draw the truth table for Carry A.B + A.C + B.C and Sum

INPUT OUTPUT

Carry Sum
A B C
A.B+A.C+B.C

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Q. Analyze Diagram
Identify the tracks, Sectors, intersect or gap and inter track gap on the magnetic disk? 2

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 Find the value into Decimal Number System – 1
(2C)16 , (4D)16 , (6A)16 .

2x16+12 =44, 4x16+13 =77, 6x16+10 =106

Represent into Binary– 1

(CC)16 , (ED)16 , (FA)16
11001100, 11101101, 11111010

Convert into Hexadecimal – 2

(34)10 , (24)10 , (21)10

22, 18, 15

Find sum using 8 bit binary – 2

-3 and 5 , -4 and 2, - 6 and 3

+15
-20
--------------------
-128+64+32+16+8+0+2+1
00001111
11111011 = -5
11101011
1

Find the sum in the hexadecimal system – 2

4E – 2F, 5C-8D, 5B + 9C

4E
- 2F
-----------------
- FF 15 15
2F 2 15 = 13 0 = D0

4 14 ¿ 14∧4+ 13=17−16=1=11 E
13 0

Convert into Hexadecimal format

(101101.11)2, (101111.011)2, (111101.01)2

0010 = 2 1101=D .1100=C (2D.C), 0010 =2 1111=F .0110 = 6 (2F.6), 0011=3 1101=D .0100 =4 (3D.4)

Find the designation of Max term A̅ + B̅ + C, �+ B̅ + C, A̅ +B + C̅

Á + B́+C=6 , A + B́+C=4 , Á+ B+ Ć=5

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