AD9912

1 GSPS Direct Digital
Synthesizer with 14-Bit DAC

AD9912
FEATURES APPLICATIONS
1 GSPS internal clock speed (up to 400 MHz output directly) Agile LO frequency synthesis
Integrated 1 GSPS 14-bit DAC Low jitter, fine tune clock generation
48-bit frequency tuning word with 4 μHz resolution Test and measurement equipment
Differential HSTL comparator Wireless base stations and controllers
Flexible system clock input accepts either crystal or external Secure communications
reference clock Fast frequency hopping
On-chip low noise PLL REFCLK multiplier
2 SpurKiller channels GENERAL DESCRIPTION
Low jitter clock doubler for frequencies up to 750 MHz The AD9912 is a direct digital synthesizer (DDS) that features
Single-ended CMOS comparator; frequencies of <150 MHz an integrated 14-bit digital-to-analog converter (DAC). The
Programmable output divider for CMOS output AD9912 features a 48-bit frequency tuning word (FTW) that
Serial I/O control can synthesize frequencies in step sizes no larger than 4 μHz.
Excellent dynamic performance Absolute frequency accuracy can be achieved by adjusting the
Software controlled power-down DAC system clock.
Available in two 64-lead LFCSP packages
Residual phase noise @ 250 MHz The AD9912 also features an integrated system clock phase-
10 Hz offset: −113 dBc/Hz locked loop (PLL) that allows for system clock inputs as low
1 kHz offset: −133 dBc/Hz as 25 MHz.
100 kHz offset: −153 dBc/Hz The AD9912 operates over an industrial temperature range,
40 MHz offset: −161 dBc/Hz spanning −40°C to +85°C.
BASIC BLOCK DIAGRAM

AD9912
DAC_OUT
STARTUP
S1 TO S4 CONFIGURATION
LOGIC
DIRECT FILTER
FDBK_IN
DIGITAL
SYNTHESIS
CORE
CLOCK OUT
DIGITAL SERIAL PORT,
INTERFACE OUTPUT
I/O LOGIC
DRIVERS OUT_CMOS
SYSTEM CLOCK
MULTIPLIER
06763-001
Figure 1.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD9912
TABLE OF CONTENTS
Features .............................................................................................. 1 Default Output Frequency on Power-Up ................................ 25
Applications ....................................................................................... 1 Power Supply Partitioning............................................................. 26
General Description ......................................................................... 1 3.3 V Supplies.............................................................................. 26
Basic Block Diagram ........................................................................ 1 1.8 V Supplies.............................................................................. 26
Revision History ............................................................................... 3 Serial Control Port ......................................................................... 27
Specifications..................................................................................... 4 Serial Control Port Pin Descriptions ....................................... 27
DC Specifications ......................................................................... 4 Operation of Serial Control Port .............................................. 27
AC Specifications.......................................................................... 6 The Instruction Word (16 Bits) ................................................ 28
Absolute Maximum Ratings............................................................ 8 MSB/LSB First Transfers ........................................................... 28
Thermal Resistance ...................................................................... 8 I/O Register Map ............................................................................ 31
ESD Caution .................................................................................. 8 I/O Register Descriptions .............................................................. 33
Pin Configuration and Function Descriptions ............................. 9 Serial Port Configuration (Register 0x0000 to
Typical Performance Characteristics ........................................... 11 Register 0x0005) ......................................................................... 33
Input/Output Termination Recommendations .......................... 16 Power-Down and Reset (Register 0x0010 to

Register 0x0013) ......................................................................... 33
Theory of Operation ...................................................................... 17
System Clock (Register 0x0020 to Register 0x0022) ............. 34
Overview...................................................................................... 17
CMOS Output Divider (S-Divider) (Register 0x0100 to
Direct Digital Synthesizer (DDS) ............................................. 17 Register 0x0106) ......................................................................... 35
Digital-to-Analog (DAC) Output ............................................ 18 Frequency Tuning Word (Register 0x01A0 to
Reconstruction Filter ................................................................. 18 Register 0x01AD) ....................................................................... 35
FDBK_IN Inputs ........................................................................ 19 Doubler and Output Drivers (Register 0x0200 to
SYSCLK Inputs ........................................................................... 20 Register 0x0201) ......................................................................... 37
Output Clock Drivers and 2× Frequency Multiplier ............. 22 Calibration (User-Accessible Trim) (Register 0x0400 to
Register 0x0410) ......................................................................... 37
Harmonic Spur Reduction ........................................................ 22
Harmonic Spur Reduction (Register 0x0500 to
Thermal Performance .................................................................... 24 Register 0x0509) ......................................................................... 37
Power-Up ......................................................................................... 25 Outline Dimensions ....................................................................... 39
Power-On Reset .......................................................................... 25 Ordering Guide .......................................................................... 39
Rev. F | Page 2 of 40
AD9912
REVISION HISTORY
6/10—Rev. E to Rev. F 7/09—Rev. B to Rev. C
Changed Default Value of Register 0x003 to 0x19 (Table 12).....31 Changes to Logic Outputs Parameter, Table 1 .............................. 3
Changes to AVDD (Pin 25, Pin 26, Pin 29, and Pin 30) ............ 25
5/10—Rev. D to Rev. E 6/09—Rev. A to Rev. B
Deleted 64-Lead LFCSP (CP-64-1) .................................. Universal Changes to Figure 40 and Direct Digital Synthesizer Section .. 17
Changes to SYSCLK PLL Enabled/ Maximum Input Rate of System Changes to Figure 48 ...................................................................... 22
Clock PFD, Table 2 ............................................................................... 6 Changes to Table 11 ........................................................................ 30
Updated Outline Dimensions ........................................................39 Changes to Table 22 and Table 23 ................................................. 34
Changes to Ordering Guide ...........................................................39
1/08—Rev. 0 to Rev. A
11/09—Rev. C to Rev. D Changes to Table 1 ............................................................................ 3
Added 64-Lead LFCSP (CP-64-7).................................... Universal Changes to Table 2 ............................................................................ 5
Changes to Serial Port Timing Specifications and Changes to Table 4 ............................................................................ 8
Propagation Delay Parameters ........................................................ 6 Changes to Typical Performance Characteristics ....................... 10
Added Exposed Paddle Notation to Figure 2 ................................ 8 Changes to Functional Description Section ................................ 19
Changes to Power Supply Partitioning Section ...........................25 Changes to Single-Ended CMOS Output Section ...................... 21
Change to Serial Control Port Section .........................................26 Changes to Harmonic Spur Reduction Section .......................... 21
Changes to Figure 52 ......................................................................28 Changes to Power Supply Partitioning Section........................... 25
Added Exposed Paddle Notation to Outline Dimensions .........38
Changes to Ordering Guide ...........................................................39 10/07—Revision 0: Initial Version
AD9912
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, AVSS = 0 V, DVSS = 0 V, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
DVDD_I/O (Pin 1) 3.135 3.30 3.465 V
DVDD (Pin 3, Pin 5, Pin 7) 1.71 1.80 1.89 V
AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49) 3.135 3.30 3.465 V
AVDD3 (Pin 37) 1.71 3.30 3.465 V Pin 37 is typically 3.3 V but can be set to 1.8 V
AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29, 1.71 1.80 1.89 V
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)
SUPPLY CURRENT See also the Total Power Dissipation
specifications
IAVDD3 (Pin 37) 8 9.6 mA CMOS output driver at 3.3 V, 50 MHz, with
5 pF load
IAVDD3 (Pin 46, Pin 47, Pin 49) 26 31 mA DAC output current source, fS = 1 GSPS
IAVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29, 113 136 mA Aggregate analog supply, with system
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45) clock PLL, HSTL output driver, and S-divider
enabled
IAVDD (Pin 53) 40 48 mA DAC power supply
IDVDD (Pin 3, Pin 5, Pin 7) 205 246 mA Digital core (SpurKiller off )
IDVDD_I/O (Pin 1, Pin 14 1 ) 2 3 mA Digital I/O (varies dynamically)
LOGIC INPUTS (Except Pin 32) Pin 9, Pin 10, Pin 54, Pin 55, Pin 58 to Pin 61,
Pin 63, Pin 64
Input High Voltage (VIH) 2.0 DVDD_I/O V
Input Low Voltage (VIL) DVSS 0.8 V
Input Current (IINH, IINL) ±60 ±200 μA At VIN = 0 V and VIN = DVDD_I/O
Maximum Input Capacitance (CIN) 3 pF
CLKMODESEL (Pin 32) LOGIC INPUT Pin 32 only
Input High Voltage (VIH) 1.4 AVDD V
Input Low Voltage (VIL) AVSS 0.4 V
Input Current (IINH, IINL) −18 −50 μA At VIN = 0 V and VIN = AVDD
Maximum Input Capacitance (CIN) 3 pF
LOGIC OUTPUTS Pin 62 and the following bidirectional pins:
Pin 9, Pin 10, Pin 54, Pin 55, Pin 63
Output High Voltage (VOH) 2.7 DVDD_I/O V IOH = 1 mA
Output Low Voltage (VOL) DVSS 0.4 V IOL = 1 mA
FDBK_IN INPUT Pin 40, Pin 41
Input Capacitance 3 pF
Input Resistance 18 22 26 kΩ Differential
Differential Input Voltage Swing 225 mV p-p Equivalent to 112.5 mV swing on each leg;
must be ac-coupled
AD9912
SYSTEM CLOCK INPUT System clock inputs should always be ac-
coupled (both single-ended and differential)
SYSCLK PLL Bypassed
Input Capacitance 1.5 pF Single-ended, each pin
Input Resistance 2.4 2.6 2.9 kΩ Differential
Internally Generated DC Bias Voltage 2 0.93 1.17 1.38 V
Differential Input Voltage Swing 632 mV p-p Equivalent to 316 mV swing on each leg
SYSCLK PLL Enabled
Input Capacitance 3 pF Single-ended, each pin
Input Resistance 2.4 2.6 2.9 kΩ Differential
Internally Generated DC Bias Voltage2 0.93 1.17 1.38 V
Differential Input Voltage Swing 632 mV p-p Equivalent to 316 mV swing on each leg
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance 9 100 Ω 25 MHz, 3.2 mm × 2.5 mm AT cut
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing 1080 1280 1480 mV Output driver static, see Figure 27 for
output swing vs. frequency
Common-Mode Output Voltage2 0.7 0.88 1.06 V
CMOS Output Driver Output driver static, see Figure 28 and
Figure 29 for output swing vs. frequency
Output Voltage High (VOH) 2.7 V IOH = 1 mA, Pin 37 = 3.3 V
Output Voltage Low (VOL) 0.4 V IOL = 1 mA, Pin 37 = 3.3 V
Output Voltage High (VOH) 1.4 V IOH = 1 mA, Pin 37 = 1.8 V
Output Voltage Low (VOL) 0.4 V IOL = 1 mA, Pin 37 = 1.8 V
TOTAL POWER DISSIPATION
DDS Only 637 765 mW Power-on default, except SYSCLK PLL by-
passed and CMOS driver off; SYSCLK = 1 GHz;
HSTL driver off; spur reduction off; fOUT =
200 MHz
DDS with Spur Reduction On 686 823 mW Same as “DDS Only” case, except both spur
reduction channels on
DDS with HSTL Driver Enabled 657 788 mW Same as “DDS Only” case, except HSTL driver
enabled
DDS with CMOS Driver Enabled 729 875 mW Same as “DDS Only” case, except CMOS
driver and S-divider enabled and at 3.3 V;
CMOS fOUT = 50 MHz (S-divider = 4)
DDS with HSTL and CMOS Drivers Enabled 747 897 mW Same as “DDS Only” case, except both HSTL
and CMOS drivers enabled; S-divider
enabled and set to 4; CMOS fOUT = 50 MHz
DDS with SYSCLK PLL Enabled 648 777 mW Same as “DDS Only” case, except 25 MHz on
SYCLK input and PLL multiplier = 40
Power-Down Mode 13 16 mW Using either the power-down and enable
register or the PWRDOWN pin
1
Pin 14 is in the AVDD3 group, but it is recommended that Pin 14 be tied to Pin 1.
2
AVSS = 0 V.
AD9912
AC SPECIFICATIONS
fS = 1 GHz, DAC RSET = 10 kΩ, unless otherwise noted. Power supply pins within the range specified in the DC Specifications section.
Table 2.
FDBK_IN INPUT Pin 40, Pin 41
Input Frequency Range 10 400 MHz
Minimum Differential Input Level 225 mV p-p −12 dBm into 50 Ω; must be ac-coupled
40 V/μs
SYSTEM CLOCK INPUT Pin 27, Pin 28
SYSCLK PLL Bypassed
Input Frequency Range 250 1000 MHz Maximum fOUT is 0.4 × fSYSCLK
Duty Cycle 45 55 %
Minimum Differential Input Level 632 mV p-p Equivalent to 316 mV swing on each leg
SYSCLK PLL Enabled
VCO Frequency Range, Low Band 700 810 MHz When in the range, use the low VCO band exclusively
VCO Frequency Range, Auto Band 810 900 MHz When in the range, use the VCO auto band select
VCO Frequency Range, High Band 900 1000 MHz When in the range, use the high VCO band exclusively
Maximum Input Rate of System 200 MHz
Clock PFD
Without SYSCLK PLL Doubler
Multiplication Range 4 66 Integer multiples of 2, maximum PFD rate and system clock
frequency must be met
With SYSCLK PLL Doubler
Multiplication Range 8 132 Integer multiples of 8
Input Duty Cycle 50 % Deviating from 50% duty cycle may adversely affect
spurious performance
Crystal Resonator with SYSCLK PLL
Enabled
Crystal Resonator Frequency Range 10 50 MHz AT cut, fundamental mode resonator
Maximum Crystal Motional Resistance 100 Ω See the SYSCLK Inputs section for recommendations
CLOCK DRIVERS
HSTL Output Driver
Frequency Range 20 725 MHz See Figure 27 for maximum toggle rate
Duty Cycle 48 52 %
Rise Time/Fall Time (20% to 80%) 115 165 ps 100 Ω termination across OUT/OUTB, 2 pF load
Jitter (12 kHz to 20 MHz) 1.5 ps fOUT = 155.52 MHz, 50 MHz system clock input (see Figure 12
through Figure 14 for test conditions)
HSTL Output Driver with 2× Multiplier
Frequency Range 400 725 MHz
Duty Cycle 45 55 %
Rise Time/Fall Time (20% to 80%) 115 165 ps 100 Ω termination across OUT/OUTB, 2 pF load
Subharmonic Spur Level −35 dBc Without correction
Jitter (12 kHz to 20 MHz) 1.6 ps fOUT = 622.08 MHz, 50 MHz system clock input (see Figure 15
for test conditions)
CMOS Output Driver
(AVDD3/Pin 37) @ 3.3 V
Frequency Range 0.008 150 MHz See Figure 29 for maximum toggle rate; the S-divider
should be used for low frequencies because the FDBK_IN
minimum frequency is 10 MHz
Duty Cycle 45 55 65 % With 20 pF load and up to 150 MHz
Rise Time/Fall Time (20% to 80%) 3 4.6 ns With 20 pF load
AD9912
CMOS Output Driver
(AVDD3/Pin 37) @ 1.8 V
Frequency Range 0.008 40 MHz See Figure 28 for maximum toggle rate
Duty Cycle 45 55 65 % With 20 pF load and up to 40 MHz
Rise Time/Fall Time (20% to 80%) 5 6.8 ns With 20 pF load
DAC OUTPUT CHARACTERISTICS
DCO Frequency Range (1st Nyquist Zone) 0 450 MHz DAC lower limit is 0 Hz; however, the minimum slew rate
for FDBK_IN dictates the lower limit if using CMOS or HSTL
outputs
Output Resistance 50 Ω Single-ended (each pin internally terminated to AVSS)
Output Capacitance 5 pF
Full-Scale Output Current 20 31.7 mA Range depends on DAC RSET resistor
Gain Error −10 +10 % FS
Output Offset 0.6 μA
Voltage Compliance Range AVSS − +0.5 AVSS + V Outputs connected to a transformer whose center tap is
0.50 0.50 grounded
Wideband SFDR See the Typical Performance Characteristics section
20.1 MHz Output −79 dBc 0 MHz to 500 MHz
Narrow-Band SFDR See the Typical Performance Characteristics section
20.1 MHz Output −95 dBc ±250 kHz
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down 15 μs
Time Required to Leave Power-Down 18 μs
Reset Assert to High-Z Time 60 ns Time from rising edge of RESET to high-Z on the S1, S2, S3,
for S1 to S4 Configuration Pins S4 configuration pins
SERIAL PORT TIMING SPECIFICATIONS
SCLK Clock Rate (1/tCLK ) 25 50 MHz Refer to Figure 56 for all write-related serial port parameters;
maximum SCLK rate for readback is governed by tDV
SCLK Pulse Width High, tHIGH 8 ns
SCLK Pulse Width Low, tLOW 8 ns
SDO/SDIO to SCLK Setup Time, tDS 1.93 ns
SDO/SDIO to SCLK Hold Time, tDH 1.9 ns
SCLK Falling Edge to Valid Data on 11 ns Refer to Figure 54
SDIO/SDO, tDV
CSB to SCLK Setup Time, tS 1.34 ns
CSB to SCLK Hold Time, tH −0.4 ns
CSB Minimum Pulse Width High, tPWH 3 ns
IO_UPDATE Pin Setup Time tCLK sec tCLK = period of SCLK in Hz
(from SCLK Rising Edge of the Final Bit)
IO_UPDATE Pin Hold Time tCLK sec tCLK = period of SCLK in Hz
PROPAGATION DELAY
FDBK_IN to HSTL Output Driver 2.8 ns
FDBK_IN to HSTL Output Driver with 2× 7.3 ns
Frequency Multiplier Enabled
FDBK_IN to CMOS Output Driver 8.0 ns S-divider bypassed
FDBK_IN Through S-Divider to CMOS 8.6 ns
Output Driver
Frequency Tuning Word Update: 60/fS ns fS = system clock frequency in GHz
IO_UPDATE Pin Rising Edge to DAC
Output
AD9912
ABSOLUTE MAXIMUM RATINGS

Table 3.
THERMAL RESISTANCE
Parameter Rating
Analog Supply Voltage (AVDD) 2V θJA is specified for the worst-case conditions, that is, a device
Digital Supply Voltage (DVDD) 2V soldered in a circuit board for surface-mount packages.
Digital I/O Supply Voltage 3.6 V Table 4. Thermal Resistance
(DVDD_I/O)
Package Type θJA θJB θJC Unit
DAC Supply Voltage (AVDD3 Pins) 3.6 V
64-Lead LFCSP 25.2 13.9 1.7 °C/W typical
Maximum Digital Input Voltage −0.5 V to DVDD_I/O + 0.5 V
Storage Temperature −65°C to +150°C Note that the exposed pad on the bottom of package must be
Operating Temperature Range −40°C to +85°C soldered to ground to achieve the specified thermal performance.
Lead Temperature 300°C See the Typical Performance Characteristics section for more
(Soldering, 10 sec) information.
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings ESD CAUTION
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD9912
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IO_UPDATE
PWRDOWN
DAC_OUTB
DAC_OUT
RESET
AVDD3
AVDD
SCLK
DVSS
DVSS
AVSS
SDIO
SDO
CSB
S4
S3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DVDD_I/O 1 PIN 1 48 DAC_RSET
DVSS 2 INDICATOR 47 AVDD3
DVDD 3 46 AVDD3
DVSS 4 45 AVDD
DVDD 5 44 AVDD
DVSS 6 43 AVSS
DVDD 7 42 AVDD
DVSS 8
AD9912 41 FDBK_IN
S1 9 TOP VIEW 40 FDBK_INB
S2 10 (Not to Scale) 39 AVSS
AVDD 11 38 OUT_CMOS
NC 12 37 AVDD3
NC 13 36 AVDD
AVDD3 14 35 OUT
NC 15 34 OUTB
NC 16 33 AVSS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLKMODESEL
LOOP_FILTER
SYSCLK
NC
NC
AVDD
NC
NC
NC
AVDD
AVDD
AVDD
AVDD
SYSCLKB
AVDD
AVDD
NOTES
06763-002
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions

Input/
Pin No. Output Pin Type Mnemonic Description
1 I Power DVDD_I/O I/O Digital Supply.
2, 4, 6, 8 I Power DVSS Digital Ground. Connect to ground.
3, 5, 7 I Power DVDD Digital Supply.
9, 10, 54, 55 I/O 3.3 V CMOS S1, S2, S3, S4 Start-Up Configuration Pins. These pins are configured under program
control and do not have internal pull-up/pull-down resistors.
11, 19, 23 to 26, I Power AVDD Analog Supply. Connect to a nominal 1.8 V supply.
29, 30, 36, 42, 44,
45, 53
12, 13, 15, 16, 17, NC No Connect. These unused pins can be left unconnected.
18, 20, 21, 22
14, 46, 47, 49 I Power AVDD3 Analog Supply. Connect to a nominal 3.3 V supply.
27 I Differential SYSCLK System Clock Input. The system clock input has internal dc biasing and
input should always be ac-coupled, except when using a crystal. Single-ended
1.8 V CMOS can also be used, but it may introduce a spur caused by an input
duty cycle that is not 50%. When using a crystal, tie the CLKMODESEL pin
to AVSS, and connect crystal directly to this pin and Pin 28.
28 I Differential SYSCLKB Complementary System Clock. Complementary signal to the input
input provided on Pin 27. Use a 0.01 μF capacitor to ground on this pin if the
signal provided on Pin 27 is single-ended.
31 O LOOP_FILTER System Clock Multiplier Loop Filter. When using the frequency multiplier to
drive the system clock, an external loop filter must be constructed and
attached to this pin. This pin should be pulled down to ground with 1 kΩ
resistor when the system clock PLL is bypassed. See Figure 46 for a diagram
of the system clock PLL loop filter.
AD9912
Input/
Pin No. Output Pin Type Mnemonic Description
32 I 1.8 V CMOS CLKMODESEL Clock Mode Select. Set to GND when connecting a crystal to the system
clock input (Pin 27 and Pin 28). Pull up to 1.8 V when using either an
oscillator or an external clock source. This pin can be left unconnected
when the system clock PLL is bypassed. (See the SYSCLK Inputs section for
details on the use of this pin.)
33, 39, 43, 52 O GND AVSS Analog Ground. Connect to ground.
34 O 1.8 V HSTL OUTB Complementary HSTL Output. See the Specifications and Primary 1.8 V
Differential HSTL Driver sections for details.
35 O 1.8 V HSTL OUT HSTL Output. See the Specifications and Primary 1.8 V Differential HSTL
Driver sections for details.
37 I Power AVDD3 Analog Supply for CMOS Output Driver. This pin is normally 3.3 V but can
be 1.8 V. This pin should be powered even if the CMOS driver is not used.
See the Power Supply Partitioning section for power supply partitioning.
38 O 3.3 V CMOS OUT_CMOS CMOS Output. See the Specifications section and the Output Clock Drivers
and 2× Frequency Multiplier section. This pin is 1.8 V CMOS if Pin 37 is set
to 1.8 V.
40 I Differential FDBK_INB Complementary Feedback Input. When using the HSTL and CMOS outputs,
input this pin is connected to the filtered DAC_OUTB output. This internally
biased input is typically ac-coupled, and when configured as such, can
accept any differential signal whose single-ended swing is at least 400 mV.
41 I Differential FDBK_IN Feedback Input. In standard operating mode, this pin is connected to the
input filtered DAC_OUT output.
48 O Current set DAC_RSET DAC Output Current Setting Resistor. Connect a resistor (usually 10 kΩ)
resistor from this pin to GND. See the Digital-To-Analog (DAC) Output section.
50 O Differential DAC_OUT DAC Output. This signal should be filtered and sent back on-chip through
output the FDBK_IN input. This pin has an internal 50 Ω pull-down resistor.
51 O Differential DAC_OUTB Complementary DAC Output. This signal should be filtered and sent back
output on-chip through the FDBK_INB input. This pin has an internal 50 Ω pull-
down resistor.
56, 57 Power DVSS Digital Ground. Connect to ground.
58 I 3.3 V CMOS PWRDOWN Power-Down. When this active high pin is asserted, the device becomes
inactive and enters the full power-down state. This pin has an internal
50 kΩ pull-down resistor.
59 I 3.3 V CMOS RESET Chip Reset. When this active high pin is asserted, the chip goes into reset.
Note that on power-up, a 10 μs reset pulse is internally generated when
the power supplies reach a threshold and stabilize. This pin should be
grounded with a 10 kΩ resistor if not used.
60 I 3.3 V CMOS IO_UPDATE I/O Update. A logic transition from 0 to 1 on this pin transfers data from the
I/O port registers to the control registers (see the Write section). This pin
has an internal 50 kΩ pull-down resistor.
61 I 3.3 V CMOS CSB Chip Select. Active low. When programming a device, this pin must be held
low. In systems where more than one AD9912 is present, this pin enables
individual programming of each AD9912. This pin has an internal 100 kΩ
pull-up resistor.
62 O 3.3 V CMOS SDO Serial Data Output. When the device is in 3-wire mode, data is read on this
pin. There is no internal pull-up/pull-down resistor on this pin.
63 I/O 3.3 V CMOS SDIO Serial Data Input/Output. When the device is in 3-wire mode, data is
written via this pin. In 2-wire mode, data reads and writes both occur on
this pin. There is no internal pull-up/pull-down resistor on this pin.
64 I 3.3 V CMOS SCLK Serial Programming Clock. Data clock for serial programming. This pin has
an internal 50 kΩ pull-down resistor.
Exposed Die Pad O GND EPAD Analog Ground. The exposed die pad on the bottom of the package
provides the analog ground for the part; this exposed pad must be
connected to ground for proper operation.
AD9912
TYPICAL PERFORMANCE CHARACTERISTICS

AVDD, AVDD3, and DVDD at nominal supply voltage; DAC RSET = 10 kΩ, unless otherwise noted. See Figure 26 for 1 GHz reference
phase noise used for generating these plots.
–50 10
CARRIER: 98.6MHz
0
SFDR: –67dBc
–55 FREQ. SPAN: 500MHz
–10
RESOLUTION BW: 3kHz
–20 VIDEO BW: 10kHz
SIGNAL POWER (dBm)

–60
–30
SFDR (dBc)
–40
–65
–50
–60
–70
–70
+25°C –80
–75 –40°C
+85°C –90
–80 06763-003 –100
06763-006
0 100 200 300 400 500 0 100 200 300 400 500
OUTPUT FREQUENCY (MHz) FREQUENCY (MHz)
Figure 3. Wideband SFDR vs. Output Frequency at −40°C, +25°C, and +85°C, Figure 6. Wideband SFDR at 98.6 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed) SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
–50 10
CARRIER: 201.1MHz
0
SFDR: –61dBc
–55 FREQ. SPAN: 500MHz
–10
RESOLUTION BW: 3kHz
–20 VIDEO BW: 10kHz
SIGNAL POWER (dBm)
–60
–30
SFDR (dBc)
–40
–65
–50
–60
–70
–70
HIGH VDD
–75 –80
NORMAL VDD
LOW VDD –90
–80 –100
06763-004
06763-007
0 100 200 300 400 500 0 100 200 300 400 500
OUTPUT FREQUENCY (MHz) FREQUENCY (MHz)
Figure 4. Variation of Wideband SFDR vs. Frequency over DAC Power Supply Figure 7. Wideband SFDR at 201.1 MHz,
Voltage, SYSCLK = 1 GHz (SYSCLK PLL Bypassed) SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
10 10
CARRIER: 20.1MHz CARRIER: 398.7MHz
0 0
SFDR: –79dBc SFDR: –59dBc
FREQ. SPAN: 500MHz FREQ. SPAN: 500MHz
–10 –10
RESOLUTION BW: 3kHz RESOLUTION BW: 3kHz
–20 VIDEO BW: 10kHz –20 VIDEO BW: 10kHz
SIGNAL POWER (dBm)
SIGNAL POWER (dBm)
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
06763-005
06763-008
0 100 200 300 400 500 0 100 200 300 400 500
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 5. Wideband SFDR at 20.1 MHz, Figure 8. Wideband SFDR at 398.7 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed) SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
AD9912
10 –80
CARRIER: 20.1MHz RMS JITTER (100Hz TO 40MHz):
0 SFDR: –95dBc 99MHz: 413fs
FREQ. SPAN: 500kHz –90
399MHz: 222fs
–10
RESOLUTION BW: 300Hz
–20 VIDEO BW: 1kHz –100
PHASE NOISE (dBc/Hz)

SIGNAL POWER (dBm)
–30
–110
–40
–50 –120
–60
–130
–70
399MHz
–80 –140
–90
–150
–100 99MHz
–110 –160
06763-009
06763-012
19.85 19.95 20.05 20.15 20.25 20.35 100 1k 10k 100k 1M 10M 100M
FREQUENCY (MHz) FREQUENCY OFFSET (Hz)
Figure 9. Narrow-Band SFDR at 20.1 MHz, Figure 12. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed) SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
10 –80
CARRIER: 201.1MHz RMS JITTER (12kHz TO 20MHz):
0 SFDR: –91dBc 99MHz: 0.98ps
399MHz: 0.99ps
–10
SIGNAL POWER (dBm)
–30
–110
–40
–50 –120
–60
–130 399MHz
–70
–80 –140
–90 99MHz
–150
–100
–110 –160
06763-010
06763-013
200.85 200.95 201.05 201.15 201.25 201.35 10 100 1k 10k 100k 1M 10M 100M
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed) SYSCLK = 1 GHz (SYSCLK PLL Driven by Rohde & Schwarz SMA100 Signal
Generator at 83.33 MHz )
10 –80
CARRIER: 398.7MHz RMS JITTER (12kHz TO 20MHz):
0 SFDR: –86dBc 99MHz: 1.41ps
–10 399MHz: 1.46ps
SIGNAL POWER (dBm)
–30
–110
–40
–50 –120
–60
–130
–70 399MHz
–80 –140
–90 99MHz
–150
–100
–110 –160
06763-011
06763-014
398.45 398.55 398.65 398.75 398.85 398.95 10 100 1k 10k 100k 1M 10M 100M
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed) SYSCLK = 1 GHz (SYSCLK PLL Driven by Rohde & Schwarz SMA100 Signal
Generator at 25 MHz )
AD9912
–100 800
RMS JITTER (100Hz TO 100MHz): TOTAL
600MHz: 585fs 3.3V
800MHz: 406fs 700
1.8V
–110
POWER DISSIPATION (mW)

600
500
–120
800MHz
400
–130 300
600MHz
200
–140
100
–150 0
06763-015
06763-018
100 1k 10k 100k 1M 10M 100M 250 375 500 625 750 875 1000
FREQUENCY OFFSET (Hz) SYSTEM CLOCK FREQUENCY (MHz)
Figure 15. Absolute Phase Noise Using HSTL Driver, Figure 18. Power Dissipation vs. System Clock Frequency
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed), (SYSCLK PLL Bypassed), fOUT = fSYSCLK/5, HSTL Driver On, CMOS Driver On,
HSTL Output Doubler Enabled SpurKiller Off
–110 800
RMS JITTER (100Hz TO 20MHz):
150MHz: 308fs
50MHz: 737fs 700
–120
POWER DISSIPATION (mW)

600
500
–130
400
–140 TOTAL
300 3.3V
150MHz 1.8V
200
–150 50MHz
100
10MHz
–160 0
06763-016
06763-019
100 1k 10k 100k 1M 10M 100M 0 100 200 300 400
FREQUENCY OFFSET (Hz) OUTPUT FREQUENCY (MHz)
Figure 16. Absolute Phase Noise Using CMOS Driver at 3.3 V, Figure 19. Power Dissipation vs. Output Frequency
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed) SYSCLK = 1 GHz (SYSCLK PLL Bypassed), HSTL Driver On,
DDS Run at 200 MSPS for 10 MHz Plot CMOS Driver On, SpurKiller Off
–110 10
RMS JITTER (100Hz TO 20MHz): CARRIER: 399MHz
50MHz: 790fs 0 SFDR W/O SPURKILLER: –63.7dBc
SFDR WITH SPURKILLER: –69.3dBc
–10 FREQUENCY SPAN:
–120 500MHz
RESOLUTION BW: 3kHz
–20
SIGNAL POWER (dBm)
VIDEO BW: 30kHz

–30
–130
–40
–50 THESE TWO SPURS

ELIMINATED WITH
–140 SPURKILLER
–60
50MHz –70
–150 –80
10MHz –90
–160 –100
06763-020
06763-017
100 1k 10k 100k 1M 10M 100M 0 100 200 300 400 500
FREQUENCY OFFSET (Hz) FREQUENCY (MHz)
Figure 17. Absolute Phase Noise Using CMOS Driver at 1.8 V, Figure 20. SFDR Comparison With and Without SpurKiller,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed) SYSCLK = 1 GHz, fOUT = 400 MHz
AD9912
–115 –115
RMS JITTER (100Hz TO 20MHz): RMS JITTER (100Hz TO 100MHz): 83fs
50MHz: 62fs
200MHz: 37fs
–125 –125
400MHz: 31fs

–135 –135
–145 –145
–155 –155
400MHz
–165 200MHz –165
50MHz
–175 –175
06763-051
06763-054
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz) FREQUENCY OFFSET (Hz)
Figure 21. Absolute Phase Noise of Unfiltered DAC Output, Figure 24. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 258.3 MHz,
fOUT = 50 MHz, 200 MHz, and 400 MHz, SYSCLK Driven by SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
–115 –115
RMS JITTER (100Hz TO 20MHz): 69fs RMS JITTER (100Hz TO 100MHz): 82fs
–125 –125

–135 –135
–145 –145
–155 –155
–165 –165
–175
06763-055
–175
06763-052
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
Figure 22. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz, Figure 25. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 311.6 MHz,
SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed) SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
–115 –110
RMS JITTER (100Hz TO 40MHz): 61fs RMS JITTER (100Hz TO 100MHz): 22fs
–125 –120
–135 –130
–145 –140
–155 –150
–165 –160
–170
06763-056
–175
06763-053
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
Figure 23. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 171 MHz, Figure 26. Absolute Phase Noise of 1 GHz Reference Used for Performance
SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed) Plots; Wenzel Components Used: 100 MHz Oscillator, LNBA-13-24 Amp,
LNOM 100-5 Multiplier, LNDD 500-14 Diode Doubler
AD9912
650 0.6
0.4
600
0.2
AMPLITUDE (mV)
AMPLITUDE (V)
550 0
FREQUENCY = 600MHz
–0.2 tRISE (20%→80%) = 104ps
tFALL (80%→20%) = 107ps
500 V p-p = 1.17V DIFF.
NOM SKEW 25°C, 1.8V SUPPLY –0.4 DUTY CYCLE = 50%
WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY)
–0.6
06763-024
450
06763-021
0 200 400 600 800 0 0.5 1.0 1.5 2.0 2.5
FREQUENCY (MHz) TIME (ns)
Figure 27. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs. Figure 30. Typical HSTL Output Waveform, Nominal Conditions,
Toggle Rate (100 Ω Across Differential Pair) DC-Coupled, Differential Probe Across 100 Ω load
2.5 1.8
1.6
2.0 1.4
1.2
AMPLITUDE (V)
1.5 AMPLITUDE (V) 1.0
0.8
1.0 0.6 FREQUENCY = 20MHz

tRISE (20%→80%) = 5.5ns
0.4
tFALL (80%→20%) = 5.9ns
0.5 NOM SKEW 25°C, 1.8V SUPPLY (20pF) V p-p = 1.8V
0.2
WORST CASE (SLOW SKEW 90°C, DUTY CYCLE = 53%
1.7V SUPPLY (20pF)) 0
0 –0.2
06763-022
06763-025
0 10 20 30 40 0 20 40 60 80 100
Figure 28. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate Figure 31. Typical CMOS Output Driver Waveform (@ 1.8 V),
(AVDD3 = 1.8 V) with 20 pF Load Nominal Conditions, Estimated Capacitance = 5 pF
3.5
3.3
3.0
2.8
2.5
2.3
AMPLITUDE (V)
AMPLITUDE (V)
2.0
1.8
1.5 FREQUENCY = 40MHz

1.3
NOM SKEW 25°C, 1.8V SUPPLY (20pF) tRISE (20%→80%) = 2.25ns
WORST CASE (SLOW SKEW 90°C, tFALL (80%→20%) = 2.6ns
1.0 0.8
3.0V SUPPLY (20pF)) V p-p = 3.3V
DUTY CYCLE = 52%
0.5 0.3
06763-026
0 –0.2
06763-023
0 50 100 150 0 10 20 30 40 50
Figure 29. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate Figure 32. CMOS Output Driver Waveform (@ 3.3 V),
(AVDD3 = 3.3 V) with 20 pF Load Nominal Conditions, Estimated Capacitance = 5 pF
AD9912
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
0.01µF 0.1µF
AD9912 DOWNSTREAM CLOCK AD9912

1.8V DEVICE SOURCE SELF-BIASING
100Ω 100Ω
HSTL (HIGH-Z) WITH DIFF. SYSCLK
OUTPUT OUTPUT INPUT
0.01µF 0.1µF
06763-027
06763-030
Figure 33. AC-Coupled HSTL Output Driver Figure 36. SYSCLK Differential Input, Non-Xtal
0.01µF
50Ω
AD9912 DOWNSTREAM CLOCK SOURCE AD9912
1.8V DEVICE WITH SELF-BIASING
HSTL AVDD/2 (HIGH-Z) SINGLE-ENDED SYSCLK
OUTPUT 1.8V CMOS INPUT
50Ω OUTPUT 0.01µF
06763-028
06763-049
Figure 34. DC-Coupled HSTL Output Driver Figure 37. SYSCLK Single-Ended Input, Non-Xtal
10pF*
0.1µF
AD9912
SELF-BIASING
SYSCLK
INPUT 100Ω AD9912
(OPTIONAL) SELF-BIASING
(CRYSTAL
10pF* FDBK INPUT
MODE)
0.1µF
06763-050
06763-029
*REFER TO CRYSTAL
DATA SHEET.
Figure 35. SYSCLK Input, Xtal Figure 38. FDBK_IN Input
AD9912
THEORY OF OPERATION
OUT_CMOS
OUT
2× OUTB
÷S
FDBK_IN
FDBK_INB
DIGITAL SYNTHESIS CORE

FREQUENCY
TUNING WORD
DAC_OUT
EXTERNAL
CONTROL ANALOG
DDS/DAC DAC_OUTB
LOGIC LOW-PASS
FILTER
LOW NOISE EXTERNAL

CLOCK LOOP
CONFIGURATION MULTIPLIER
LOGIC FILTER
AMP
SYSCLK PORT
06763-031
S1 TO S4 DIGITAL SYSCLK SYSCLKB
INTERFACE
Figure 39. Detailed Block Diagram
OVERVIEW The output circuitry includes HSTL and CMOS output buffers,
The AD9912 is a high performance, low noise, 14-bit DDS as well as a frequency doubler for applications that need
clock synthesizer with integrated comparators for applications frequencies above the Nyquist level of the DDS.
desiring an agile, finely tuned square or sinusoidal output signal. The AD9912 also offers preprogrammed frequency profiles that
A digitally controlled oscillator (DCO) is implemented using a allow the user to generate frequencies without programming
direct digital synthesizer (DDS) with an integrated output DAC, the part. The individual functional blocks are described in the
clocked by the system clock. following sections.
A bypassable PLL-based frequency multiplier is present, DIRECT DIGITAL SYNTHESIZER (DDS)
enabling use of an inexpensive, low frequency source for the The frequency of the sinusoid generated by the DDS is
system clock. For best jitter performance, the system clock PLL determined by a frequency tuning word (FTW), which is a
should be bypassed, and a low noise, high frequency system digital (that is, numeric) value. Unlike an analog sinusoidal
clock should be provided directly. Sampling theory sets an upper generator, a DDS uses digital building blocks and operates as
bound for the DDS output frequency at 50% of fS (where fS is a sampled system. Thus, it requires a sampling clock (fS) that
the DAC sample rate), but a practical limitation of 40% of serves as the fundamental timing source of the DDS. The
fS is generally recommended to allow for the selectivity of the accumulator behaves as a modulo-248 counter with a program-
required off-chip reconstruction filter. mable step size that is determined by the frequency tuning word
The output signal from the reconstruction filter can be fed back (FTW). A block diagram of the DDS is shown in Figure 40.
to the AD9912 to be processed through the output circuitry.
AD9912
DAC I-SET DAC_RSET
PHASE
48-BIT ACCUMULATOR REGISTERS
OFFSET
AND LOGIC
48 14
FREQUENCY 48 48 19 19 ANGLE TO 14 DAC_OUT

DAC
TUNING WORD D Q AMPLITUDE
CONVERSION (14-BIT)
(FTW) DAC_OUTB
06763-032
fS
Figure 40. DDS Block Diagram
The input to the DDS is a 48-bit FTW that provides the accu- is internally connected to a virtual voltage reference of 1.2 V
mulator with a seed value. On each cycle of fS, the accumulator nominal, so the reference current can be calculated by
adds the value of the FTW to the running total of its output. 1 .2
For example, given an FTW = 5, the accumulator increments I DAC _ REF =
R DAC _ REF
the count by 5 sec on each fS cycle. Over time, the accumulator
reaches the upper end of its capacity (248 in this case) and then Note that the recommended value of IDAC_REF is 120 μA, which
rolls over, retaining the excess. The average rate at which the leads to a recommended value for RDAC_REF of 10 kΩ.
accumulator rolls over establishes the frequency of the output The scale factor consists of a 10-bit binary number (FSC)
sinusoid. The following equation defines the average rollover programmed into the DAC full-scale current register in the
rate of the accumulator and establishes the output frequency I/O register map. The full-scale DAC output current (IDAC_FS)
(fDDS) of the DDS: is given by
⎛ FTW ⎞ ⎛ 192 FSC ⎞
f DDS = ⎜ 48 ⎟ f S I DAC _ FS = I DAC _ REF ⎜ 72 +
⎝ 2 ⎠ ⎟
⎝ 1024 ⎠
Solving this equation for FTW yields Using the recommended value of RDAC_REF, the full-scale DAC
⎡ ⎛f ⎞⎤ output current can be set with 10-bit granularity over a range of
FTW = round ⎢2 48 ⎜ DDS ⎟⎥ approximately 8.6 mA to 31.7 mA. 20 mA is the default value.
⎢⎣ ⎜⎝ f S ⎟⎥
⎠⎦ AVDD3
49
For example, given that fS = 1 GHz and fDDS = 19.44 MHz, then
FTW = 5,471,873,547,255 (0x04FA05143BF7). IFS/2
IFS
IFS/2
The relative phase of the sinusoid can be controlled numerically,

as well. This is accomplished using the phase offset function of CURRENT CURRENT
SWITCH
the DDS (a programmable 14-bit value (Δphase); see the I/O SWITCH
CONTROL
SWITCH
ARRAY ARRAY
Register Map section). The resulting phase offset, ΔΦ (radians),
IFS/2 + ICODE IFS/2 – ICODE
is given by CODE
⎛ Δphase ⎞ DAC_OUT 50 51 DAC_OUTB

ΔΦ = 2π⎜ 14 ⎟
⎝ 2 ⎠ INTERNAL INTERNAL
50Ω 50Ω
06763-033
DIGITAL-TO-ANALOG (DAC) OUTPUT 52
AVSS
The output of the digital core of the DDS is a time series of
Figure 41. DAC Output
numbers representing a sinusoidal waveform. This series is
translated to an analog signal by means of a digital-to-analog RECONSTRUCTION FILTER
converter (DAC). The origin of the output clock signal produced by the AD9912
The DAC outputs its signal to two pins driven by a balanced is the combined DDS and DAC. The DAC output signal appears
current source architecture (see the DAC output diagram in as a sinusoid sampled at fS. The frequency of the sinusoid is
Figure 41). The peak output current derives from a combination determined by the frequency tuning word (FTW) that appears
of two factors. The first is a reference current (IDAC_REF) that is at the input to the DDS. The DAC output is typically passed
established at the DAC_RSET pin, and the second is a scale through an external reconstruction filter that serves to remove
factor that is programmed into the I/O register map. the artifacts of the sampling process and other spurs outside the
The value of IDAC_REF is set by connecting a resistor (RDAC_REF) filter bandwidth. If desired, the signal can then be brought back
between the DAC_RSET pin and ground. The DAC_RSET pin on-chip to be converted to a square wave that is routed internally
to the output clock driver or the 2× DLL multiplier.
AD9912
MAGNITUDE
(dB)
IMAGE 0 IMAGE 1 IMAGE 2 IMAGE 3 IMAGE 4
0
–20
PRIMARY FILTER
–40 SIGNAL RESPONSE SIN(x)/x
–60 ENVELOPE
–80 SPURS
–100 f
06763-034
fs/2 fs 3fs/2 2fs 5fs/2
BASE BAND
Figure 42. DAC Spectrum vs. Reconstruction Filter Response
Because the DAC constitutes a sampled system, its output must FDBK_IN INPUTS
be filtered so that the analog waveform accurately represents the The FDBK_IN pins serve as the input to the comparators and
digital samples supplied to the DAC input. The unfiltered DAC output drivers of the AD9912. Typically, these pins are used to
output contains the (typically) desired baseband signal, which receive the signal generated by the DDS after it has been band-
extends from dc to the Nyquist frequency (fS/2). It also contains limited by the external reconstruction filter.
images of the baseband signal that theoretically extend to infinity.
Notice that the odd images (shown in Figure 42) are mirror A diagram of the FDBK_IN input pins is provided in Figure 43,
images of the baseband signal. Furthermore, the entire DAC which includes some of the internal components used to bias
output spectrum is affected by a sin(x)/x response, which is the input circuitry. Note that the FDBK_IN input pins are
caused by the sample-and-hold nature of the DAC output signal. internally biased to a dc level of ~1 V. Care should be taken to
ensure that any external connections do not disturb the dc bias
For applications using the fundamental frequency of the DAC because this may significantly degrade performance.
output, the response of the reconstruction filter should preserve
FDBK_IN
the baseband signal (Image 0), while completely rejecting all TO S-DIVIDER
~1pF 15kΩ AND CLOCK
other images. However, a practical filter implementation OUTPUT SECTION
AVSS
typically exhibits a relatively flat pass band that covers the
~1pF 15kΩ
desired output frequency plus 20%, rolls off as steeply as
possible, and then maintains significant (though not complete) FDBK_INB
+
rejection of the remaining images. Depending on how close
06763-035
~1V ~2pF
unwanted spurs are to the desired signal, a third-, fifth-, or
AVSS
seventh-order elliptic low-pass filter is common.
Figure 43. Differential FDBK_IN Inputs
Some applications operate off an image above the Nyquist
frequency, and those applications use a band-pass filter instead
of a low-pass filter.
The design of the reconstruction filter has a significant impact
on the overall signal performance. Therefore, good filter design
and implementation techniques are important for obtaining the
best possible jitter results.
AD9912
SYSCLK INPUTS Note that although these crystals meet the preceding criteria
Functional Description according to their data sheets, Analog Devices, Inc., does not
guarantee their operation with the AD9912, nor does Analog
An external time base connects to the AD9912 at the SYSCLK
Devices endorse one supplier of crystals over another.
pins to generate the internal high frequency system clock (fS).
When the SYSCLK PLL multiplier path is disabled, the AD9912
The SYSCLK inputs can be operated in one of the following
must be driven by a high frequency signal source (250 MHz to
three modes:
1 GHz). The signal thus applied to the SYSCLK input pins becomes
• SYSCLK PLL bypassed the internal DAC sampling clock (fS) after passing through an
• SYSCLK PLL enabled with input signal generated externally internal buffer.
• Crystal resonator with SYSCLK PLL enabled It is important to note that when bypassing the system clock
A functional diagram of the system clock generator is shown in PLL, the LOOP_FILTER pin (Pin 31) should be pulled down to
Figure 44. the analog ground with a 1 kΩ resistor.
The SYSCLK PLL multiplier path is enabled by a Logic 0 (default) SYSCLK PLL Doubler
in the PD SYSCLK PLL bit (Register 0x0010, Bit 4) of the I/O The SYSCLK PLL multiplier path offers an optional SYSCLK
register map. The SYSCLK PLL multiplier can be driven from PLL doubler. This block comes before the SYSCLK PLL
the SYSCLK input pins by one of two means, depending on the multiplier and acts as a frequency doubler by generating a pulse
logic level applied to the 1.8 V CMOS CLKMODESEL pin. on each edge of the SYSCLK input signal. The SYSCLK PLL
When CLKMODESEL = 0, a crystal can be connected directly multiplier locks to the falling edges of this regenerated signal.
across the SYSCLK pins. When CLKMODESEL = 1, the The impetus for doubling the frequency at the input of the
maintaining amp is disabled, and an external frequency source SYSCLK PLL multiplier is that an improvement in overall phase
(such as an oscillator or signal generator) can be connected noise performance can be realized. The main drawback is that
directly to the SYSCLK input pins. Note that CLKMODESEL = 1 the doubler output is not a rectangular pulse with a constant
does not disable the system clock PLL. duty cycle even for a perfectly symmetric SYSCLK input signal.
The maintaining amp on the AD9912 SYSCLK pins is intended This results in a subharmonic appearing at the same frequency
for 25 MHz, 3.2 mm × 2.5 mm AT cut fundamental mode crystals as the SYSCLK input signal, and the magnitude of the subharmonic
with a maximum motional resistance of 100 Ω. The following can be quite large. When employing the doubler, care must be
crystals, listed in alphabetical order, meet these criteria (as of taken to ensure that the loop bandwidth of the SYSCLK PLL
the revision date of this data sheet): multiplier adequately suppresses the subharmonic.
• AVX/Kyocera CX3225SB The benefit offered by the doubler depends on the magnitude
• ECS ECX-32 of the subharmonic, the loop bandwidth of the SYSCLK PLL
• Epson/Toyocom TSX-3225 multiplier, and the overall phase noise requirements of the
• Fox FX3225BS specific application. In many applications, the AD9912 clock
• NDK NX3225SA output is applied to the input of another PLL, and the subhar-
monic is often suppressed by the relatively narrow bandwidth of
the downstream PLL.
Note that generally, the benefits of the SYSCLK PLL doubler are
realized for SYSCLK input frequencies of 25 MHz and above.
PD SYSCLK PLL BIPOLAR EDGE DETECTOR
(I/O REGISTER BIT) (I/O REGISTER BIT)
SYSCLK PLL BYPASSED
SYSCLK 2 WITH EXTERNAL DRIVE

2 1
2
SYSCLKB 0
2 2
1 1 1 2 DAC
0 SYSCLK SAMPLE
2
SYSCLK 0 2 0 PLL 0 CLOCK
PLL 1 MULTIPLIER
ENABLED
BIPOLAR
WITH CRYSTAL
EDGE
RESONATOR
DETECTOR
CLKMODESEL
06763-036
LOOP_FILTER
Figure 44. System Clock Generator Block Diagram
AD9912
EXTERNAL
SYSCLK PLL Multiplier LOOP FILTER
When the SYSCLK PLL multiplier path is employed, the AVDD
FERRITE R1
frequency applied to the SYSCLK input pins must be limited so BEAD C2
as not to exceed the maximum input frequency of the SYSCLK C1
PLL phase detector. A block diagram of the SYSCLK generator
appears in Figure 45. 29 26 31
LOOP_FILTER
SYSCLK PLL MULTIPLIER

~2pF
ICP CHARGE
VCO
(125µA, 250µA, 375µA) PUMP
06763-038
KVCO AD9912
2 (HIGH/LOW RANGE)
Figure 46. External Loop Filter for SYSCLK PLL
FROM PHASE DAC
SYSCLK FREQUENCY CHARGE SAMPLE
VCO
INPUT DETECTOR PUMP CLOCK Table 6. Recommended Loop Filter Values for a Nominal
1GHz
~2pF 1.5 MHz SYSCLK PLL Loop Bandwidth
Multiplier R1 Series C1 Shunt C2
<8 390 Ω 1 nF 82 pF
÷N ÷2
10 470 Ω 820 pF 56 pF
(N = 2 TO 33)
06763-037 20 1 kΩ 390 pF 27 pF
LOOP_FILTER 40 (default) 2.2 kΩ 180 pF 10 pF
Figure 45. Block Diagram of the SYSCLK PLL 60 2.7 kΩ 120 pF 5 pF
The SYSCLK PLL multiplier has a 1 GHz VCO at its core.
A phase/frequency detector (PFD) and charge pump provide
Detail of SYSCLK Differential Inputs
the steering signal to the VCO in typical PLL fashion. The PFD A diagram of the SYSCLK input pins is provided in Figure 47.
operates on the falling edge transitions of the input signal, which Included are details of the internal components used to bias the
means that the loop locks on the negative edges of the reference input circuitry. These components have a direct effect on the
signal. The charge pump gain is controlled via the I/O register static levels at the SYSCLK input pins. This information is
map by selecting one of three possible constant current sources intended to aid in determining how best to interface to the
ranging from 125 μA to 375 μA in 125 μA steps. The center device for a given application.
frequency of the VCO is also adjustable via the I/O register map CRYSTAL RESONATOR WITH
and provides high/low gain selection. The feedback path from MUX SYSCLK PLL ENABLED
VCO to PFD consists of a fixed divide-by-2 prescaler followed SYSCLK AMP INTERNAL
CLOCK
by a programmable divide-by-N block, where 2 ≤ N ≤ 33. This
SYSCLKB
limits the overall divider range to any even integer from 4 to 66,
inclusive. The value of N is programmed via the I/O register map SYSCLK PLL ENABLED
via a 5-bit word that spans a range of 0 to 31, but the internal
INTERNAL
logic automatically adds a bias of 2 to the value entered, extending ~3pF 1kΩ CLOCK
the range to 33. Care should be taken when choosing these VSS
values so as not to exceed the maximum input frequency of the ~3pF 1kΩ
SYSCLK PLL phase detector or SYSCLK PLL doubler. These

+
values can be found in the AC Specifications section.
~1V ~2pF
External Loop Filter (SYSCLK PLL) VSS
The loop bandwidth of the SYSCLK PLL multiplier can be

SYSCLK PLL BYPASSED
adjusted by means of three external components as shown in
Figure 46. The nominal gain of the VCO is 800 MHz/V. The ~1.5pF 500Ω
INTERNAL
CLOCK
recommended component values (shown in Table 6) establish VSS
a loop bandwidth of approximately 1.6 MHz with the charge ~1.5pF 500Ω
pump current set to 250 μA. The default case is N = 40, and
it assumes a 25 MHz SYSCLK input frequency and generates +
~1V ~2pF
an internal DAC sampling frequency (fS) of 1 GHz.
06763-039
VSS
Figure 47. Differential SYSCLK Inputs
AD9912
Note that the SYSCLK PLL bypassed and SYSCLK PLL enabled If the CMOS output divider is bypassed, the HSTL and CMOS
input paths are internally biased to a dc level of ~1 V. Care should drivers are the same frequency as the signal presented at the
be taken to ensure that any external connections do not disturb FDBK_IN pins. When using the CMOS output in this configu-
the dc bias because this may significantly degrade performance. ration, the DDS output frequency should be in the range of
Generally, it is recommended that the SYSCLK inputs be 30 MHz to 150 MHz. At low output frequencies (<30 MHz), the
ac-coupled, except when using a crystal resonator. low slew rate of the DAC results in a higher noise floor. This can
be remedied by running the DDS at 100 MHz or greater and
OUTPUT CLOCK DRIVERS AND 2× FREQUENCY
using the CMOS divider. At an output frequency of 50 MHz,
MULTIPLIER
the best technique depends on the user’s application. Running
There are two output drivers provided by the AD9912. The the DDS at 200 MHz, and using a CMOS divider of 4, results in
primary output driver supports differential 1.8 V HSTL output a lower noise floor, but at the expense of close-in phase noise.
levels, while the secondary supports either 1.8 V or 3.3 V CMOS
At frequencies greater than 150 MHz, the HSTL output should
levels, depending on whether Pin 37 is driven at 1.8 V or 3.3 V.
be used.
The primary differential driver nominally provides an output
voltage with 100 Ω load applied differentially. The source
CMOS Output Divider (S-Divider)
impedance of the driver is approximately 100 Ω for most of The CMOS output divider is 16 bits cascaded with an additional
the output clock period; during transition between levels, the divide-by-two. The divider is therefore capable of integer division
source impedance reaches a maximum of about 500 Ω. The from 1 to 65,535 (index of 1) or from 2 to 131,070 (index of 2).
driver is designed to support output frequencies of up to and The divider is programmed via the I/O register map to trigger
beyond the OC-12 network rate of 622.08 MHz. on either the rising (default) or falling edge of the feedback
signal.
The output clock can also be powered down by a control bit in
the I/O register map. The CMOS output divider is an integer divider capable of
handling frequencies well above the Nyquist limit of the DDS.
Primary 1.8 V Differential HSTL Driver
The S-divider/2 bit (Register 0x0106, Bit 0) must be set when
The DDS produces a sinusoidal clock signal that is sampled at FDBK_IN is greater than 400 MHz.
the system clock rate. This DDS output signal is routed off chip
Note that the actual output divider values equal the value stored
where it is passed through an analog filter and brought back on
in the output divider register minus one. Therefore, to have an
chip for buffering and, if necessary, frequency doubling. Where
output divider of one, the user writes zeros to the output divider
possible, for the best jitter performance, it is recommended that
register.
the frequency doubler be bypassed.
The 1.8 V HSTL output should be ac-coupled, with 100 Ω termi- HARMONIC SPUR REDUCTION
nation at the destination. The driver design has low jitter injection The most significant spurious signals produced by the DDS are
for frequencies in the range of 50 MHz to 750 MHz. Refer to the harmonically related to the desired output frequency of the DDS.
AC Specifications section for the exact frequency limits. The source of these harmonic spurs can usually be traced to the
2× Frequency Multiplier DAC, and the spur level is in the −60 dBc range. This ratio
represents a level that is about 10 bits below the full-scale
The AD9912 can be configured (via the I/O register map) with output of the DAC (10 bits down is 2−10, or 1/1024).
an internal 2× delay-locked loop (DLL) multiplier at the input
of the primary clock driver. The extra octave of frequency gain Such a spur can be reduced by combining the original signal
allows the AD9912 to provide output clock frequencies that with a replica of the spur, but offset in phase by 180°. This idea
exceed the range available from the DDS alone. These settings is the foundation of the technique used to reduce harmonic
are found in Register 0x0010 and Register 0x0200. spurs in the AD9912. Because the DAC has 14-bit resolution,
a −60 dBc spur can be synthesized using only the lower 4 bits of
The input to the DLL consists of the filtered DDS output signal the DAC full-scale range. That is, the 4 LSBs can create an output
after it has been squared up by an integrated clock receiver level that is approximately 60 dB below the full-scale level of the
circuit. The DLL can accept input frequencies in the range of DAC (commensurate with a −60 dBc spur). This fact gives rise
200 MHz to 400 MHz. to a means of digitally reducing harmonic spurs or their aliased
Single-Ended CMOS Output images in the DAC output spectrum by digitally adding a sinusoid
In addition to the high-speed differential output clock driver, at the input of the DAC with a similar magnitude as the offending
the AD9912 provides an independent, single-ended output, spur, but shifted in phase to produce destructive interference.
CMOS clock driver that is very good for frequencies up to
150 MHz. The signal path for the CMOS clock driver can either
include or bypass the CMOS output divider.
AD9912
Although the worst spurs tend to be harmonic in origin, the fact The procedure for tuning the spur reduction is as follows:
that the DAC is part of a sampled system results in the possibility 1. Determine which offending harmonic spur to reduce and
of spurs appearing in the output spectrum that are not harmoni- its amplitude. Enter that harmonic number into Bit 0 to
cally related to the fundamental. For example, if the DAC is Bit 3 of Register 0x0500/Register 0x0505.
sampled at 1 GHz and generates an output sinusoid of 170 MHz,
the fifth harmonic would normally be at 850 MHz. However, 2. Turn off the fundamental by setting Bit 7 of Register 0x0013
because of the sampling process, this spur appears at 150 MHz, and enable the SpurKiller channel by setting Bit 7 of
only 20 MHz away from the fundamental. Therefore, when Register 0x0500/Register 0x0505.
attempting to reduce DAC spurs it is important to know the 3. Adjust the amplitude of the SpurKiller channel so that it
actual location of the harmonic spur in the DAC output matches the amplitude of the offending spur.
spectrum based on the DAC sample rate so that its harmonic 4. Turn the fundamental on by clearing Bit 7 of Register 0x0013.
number can be reduced.
5. Adjust the phase of the SpurKiller channel so that
The mechanics of performing harmonic spur reduction is shown maximum interference is achieved.
in Figure 48. It essentially consists of two additional DDS cores
operating in parallel with the original DDS. This enables the user Note that the SpurKiller setting is sensitive to the loading of the
to reduce two different harmonic spurs from the second to the DAC output pins, and that a DDS reset is required if a SpurKiller
15th with nine bits of phase offset control (±π) and eight bits of channel is turned off. The DDS can be reset by setting Bit 0 of
amplitude control. Register 0x0012, and resetting the part is not necessary.
The dynamic range of the cancellation signal is further aug- The performance improvement offered by this technique varies
mented by a gain bit associated with each channel. When this widely and depends on the conditions used. Given this extreme
bit is set, the magnitude of the cancellation signal is doubled by variability, it is impossible to define a meaningful specification
employing a 1-bit left-shift of the data. However, the shift to guarantee SpurKiller performance. Current data indicate that
operation reduces the granularity of the cancellation signal a 6 dB to 8 dB improvement is possible for a given output
magnitude. The full-scale amplitude of a cancellation spur is frequency using a common setting over process, temperature,
approximately −60 dBc when the gain bit is a Logic 0 and and voltage. There are frequencies, however, where a common
approximately −54 dBc when the gain bit is a Logic 1. setting can result in much greater improvement. Manually
adjusting the SpurKiller settings on individual parts can result
in more than 30 dB of spurious performance improvement.
DDS
DDS
PHASE
SPUR
OFFSET DAC I-SET DAC_RSET
48-BIT ACCUMULATOR CANCELLATION
REGISTERS
48 ENABLE
14 AND LOGIC
48-BIT ANGLE TO
FREQUENCY 14 48 19 19 14
D Q AMPLITUDE 0 14 DAC DAC_OUT
TURNING WORD CONVERSION
(FTW) 1 (14-BIT)
DAC_OUTB
SYSCLK
2-CHANNEL
4 HARMONIC HEADROOM
CH1 HARMONIC NUMBER
FREQUENCY CORRECTION
GENERATOR
9
CH1 CANCELLATION PHASE OFFSET
0
CH1 SHIFT 1
4
CH2 HARMONIC NUMBER
CH1 GAIN
9 0
CH2 CANCELLATION PHASE OFFSET
CH2 SHIFT 1
8 CH2 GAIN
CH1 CANCELLATION MAGNITUDE
8
06763-040
CH2 CANCELLATION MAGNITUDE

HARMONIC SPUR CANCELLATION
Figure 48. Spur Reduction Circuit Diagram
AD9912
THERMAL PERFORMANCE
Table 7. Thermal Parameters
Symbol Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board Value Unit
θJA Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air) 25.2 °C/W
θJMA Junction-to-ambient thermal resistance, 1.0 m/sec air flow per JEDEC JESD51-6 (moving air) 22.0 °C/W
θJMA Junction-to-ambient thermal resistance, 2.0 m/sec air flow per JEDEC JESD51-6 (moving air) 19.8 °C/W
θJB Junction-to-board thermal resistance, 1.0 m/sec air flow per JEDEC JESD51-8 (moving air) 13.9 °C/W
θJC Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 1.7 °C/W
ΨJT Junction-to-top-of-package characterization parameter, 0 m/sec air flow per JEDEC JESD51-2 (still air) 0.1 °C/W
The AD9912 is specified for a case temperature (TCASE). To Values of θJA are provided for package comparison and PCB
ensure that TCASE is not exceeded, an airflow source can be used. design considerations. θJA can be used for a first-order
Use the following equation to determine the junction tempera- approximation of TJ by the equation
ture on the application PCB: TJ = TA + (θJA × PD)
TJ = TCASE + (ΨJT × PD) where TA is the ambient temperature (°C).
where: Values of θJC are provided for package comparison and PCB
TJ is the junction temperature (°C). design considerations when an external heat sink is required.
TCASE is the case temperature (°C) measured by customer at top Values of θJB are provided for package comparison and PCB
center of package. design considerations.
ΨJT is the value from Table 7.
PD is the power dissipation (see the Total Power Dissipation The values in Table 7 apply to both 64-lead package options.
section in the Specifications section).
AD9912
POWER-UP
POWER-ON RESET The DDS output frequency listed in Table 8 assumes that
On initial power-up, the AD9912 internally generates a 75 ns the internal DAC sampling frequency (fS) is 1 GHz. These
RESET pulse. The pulse is initiated when both of the following frequencies scale 1:1 with fS, meaning that other start-up
two conditions are met: frequencies are available by varying the SYSCLK frequency.
At startup, the internal frequency multiplier defaults to 40×
• The 3.3 V supply is greater than 2.35 V ± 0.1 V.
when the Xtal/PLL mode is selected via the status pins.
• The 1.8 V supply is greater than 1.4 V ± 0.05 V.
Less than 1 ns after RESET goes high, the S1 to S4 configuration Table 8. Default Power-Up Frequency Options for 1 GHz
pins go high impedance and remain high impedance until System Clock
RESET is deactivated. This allows strapping and configuration Status Pin SYSCLK Output Frequency
during RESET. S4 S3 S2 S1 Input Mode (MHz)
0 0 0 0 Xtal/PLL 0
Because of this reset sequence, external power supply sequenc-
0 0 0 1 Xtal/PLL 38.87939
ing is not critical.
0 0 1 0 Xtal/PLL 51.83411
DEFAULT OUTPUT FREQUENCY ON POWER-UP 0 0 1 1 Xtal/PLL 61.43188
The four status pins (S1 to S4) are used to define the output 0 1 0 0 Xtal/PLL 77.75879
frequency of the DDS at power-up even though the I/O registers 0 1 0 1 Xtal/PLL 92.14783
have not yet been programmed. At power-up, internal logic 0 1 1 0 Xtal/PLL 122.87903
initiates a reset pulse of about 10 ns. During this time, S1 to S4 0 1 1 1 Xtal/PLL 155.51758
briefly function as input pins and can be driven externally. Any 1 0 0 0 Direct 0
logic levels thus applied are transferred to a 4-bit register on the 1 0 0 1 Direct 38.87939
falling edge of the internally initiated pulse. The same behavior 1 0 1 0 Direct 51.83411
occurs when the RESET pin is asserted manually. 1 0 1 1 Direct 61.43188
1 1 0 0 Direct 77.75879
Setting up S1 to S4 for default DDS startup is accomplished by
1 1 0 1 Direct 92.14783
connecting a resistor to each pin (either pull-up or pull-down)
1 1 1 0 Direct 122.87903
to produce the desired bit pattern, yielding 16 possible states
1 1 1 1 Direct 155.51758
that are used both to address an internal 8 × 16 ROM and to
select the SYSCLK mode (see Table 8). The ROM contains eight
16-bit DDS frequency tuning words (FTWs), one of which is
selected by the state of the S1 to S3 pins. The selected FTW is
transferred to the FTW0 register in the I/O register map
without the need for an I/O update. This ensures that the DDS
generates the selected frequency even if the I/O registers have
not been programmed. The state of the S4 pin selects whether
the internal system clock is generated by means of the internal
SYSCLK PLL multiplier or not (see the SYSCLK Inputs section
for details).
AD9912
POWER SUPPLY PARTITIONING

The AD9912 features multiple power supplies, and their power 1.8 V SUPPLIES
consumption varies with its configuration. This section covers DVDD (Pin 3, Pin 5, and Pin 7)
which power supplies can be grouped together and how the
These pins should be grouped together and isolated from the
power consumption of each block varies with frequency.
1.8 V AVDD supplies. For most applications, a ferrite bead
The numbers quoted here are for comparison only. Refer to the provides sufficient isolation, but a separate regulator may be
Specifications section for exact numbers. With each group, use necessary for applications demanding the highest performance.
bypass capacitors of 1 μF in parallel with a 10 μF. The current consumption of this group increases from about
The recommendations here are for typical applications, and for 160 mA at a system clock of 700 MHz to about 205 mA at a
these applications, there are four groups of power supplies: system clock of 1 GHz. There is also a slight (~5%) increase as
3.3 V digital, 3.3 V analog, 1.8 V digital, and 1.8 V analog. fOUT increases from 50 MHz to 400 MHz.
Applications demanding the highest performance may require AVDD (Pin 11, Pin 19, Pin 23, Pin 24, Pin 36, Pin 42,
additional power supply isolation. Pin 44, and Pin 45)
Important: All power supply pins must receive power regardless These pins can be grouped together and should be isolated from
of whether that block is used. other 1.8 V supplies. A separate regulator is recommended. At
a minimum, a ferrite bead should be used for isolation.
3.3 V SUPPLIES
AVDD (Pin 53)
DVDD_I/O (Pin 1) and AVDD3 (Pin 14)
This 1.8 V supply consumes about 40 mA. The supply can be
Although one of these pins is analog and the other is digital,
run off the same regulator as the 1.8 V AVDD group, with a
these two 3.3 V supplies can be grouped together. The power
ferrite bead to isolate Pin 53 from the rest of the 1.8 V AVDD
consumption on Pin 1 varies dynamically with serial port
group. However, for applications demanding the highest
activity.
performance, a separate regulator is recommended.
AVDD3 (Pin 37)
AVDD (Pin 25, Pin 26, Pin 29, and Pin 30)
This is the CMOS driver supply. It can be either 1.8 V or 3.3 V,
These system clock PLL power pins should be grouped together
and its power consumption is a function of the output frequency
and isolated from other 1.8 V AVDD supplies.
and loading of OUT_CMOS (Pin 38).
At a minimum, it is recommended that Pin 25 and Pin 30 be
If the CMOS driver is used at 3.3 V, this supply should be
tied together and isolated from the aggregate AVDD 1.8 V
isolated from other 3.3 V supplies with a ferrite bead to avoid
supply with a ferrite bead. Likewise, Pin 26 and Pin 29 can also
a spur at the output frequency. If the HSTL driver is not used,
be tied together, with a ferrite bead isolating them from the same
AVDD3 (Pin 37) can be connected (using a ferrite bead) to
aggregate 1.8 V supply. The loop filter for the system clock PLL
AVDD3 (Pin 46, Pin 47, and Pin 49). If the HSTL driver is used,
should directly connect to Pin 26 and Pin 29 (see Figure 46).
connect AVDD3 (Pin 37) to Pin 1 and Pin 14, using a ferrite bead.
Applications demanding the highest performance may need to
If the CMOS driver is used at 1.8 V, AVDD3 (Pin 37) can be
have these four pins powered by their on their own LDO.
connected to AVDD (Pin 36).
If the system clock PLL is bypassed, the loop filter pin (Pin 31)
If the CMOS driver is not used, AVDD3 (Pin 37) can be tied
should be pulled down to analog ground using a 1 kΩ resistor.
directly to the 1.8 V AVDD (Pin 36) and the CMOS driver
Pin 25, Pin 26, Pin 29, and Pin 30 should be included in the large
powered down using Register 0x0010.
1.8 V AVDD power supply group. In this mode, isolation of these
AVDD3 (Pin 46, Pin 47, and Pin 49) pins is not critical, and these pins consume almost no power.
These are 3.3 V DAC power supplies that typically consume
about 25 mA. At a minimum, a ferrite bead should be used to
isolate these from other 3.3 V supplies, with a separate regulator
being ideal.
AD9912
SERIAL CONTROL PORT

The AD9912 serial control port is a flexible, synchronous, serial go high on byte boundaries only and can go high during either
communications port that allows an easy interface with many part (instruction or data) of the transfer. During this period, the
industry-standard microcontrollers and microprocessors. Single serial control port state machine enters a wait state until all data
or multiple byte transfers are supported, as well as MSB first or has been sent. If the system controller decides to abort the transfer
LSB first transfer formats. The AD9912 serial control port can before all of the data is sent, the state machine must be reset by
be configured for a single bidirectional I/O pin (SDIO only) or either completing the remaining transfer or by returning the CSB
for two unidirectional I/O pins (SDIO and SDO). low for at least one complete SCLK cycle (but fewer than eight
Note that all serial port operations (such as the frequency SCLK cycles). Raising the CSB on a nonbyte boundary terminates
tuning word update) depend on the presence of the DAC the serial transfer and flushes the buffer.
system clock. In the streaming mode ([W1:W0] = 11), any number of data
bytes can be transferred in a continuous stream. The register
SERIAL CONTROL PORT PIN DESCRIPTIONS
address is automatically incremented or decremented (see the
SCLK (serial clock) is the serial shift clock. This pin is an input. MSB/LSB First Transfers section). CSB must be raised at the end
SCLK is used to synchronize serial control port reads and writes. of the last byte to be transferred, thereby ending the stream mode.
Write data bits are registered on the rising edge of this clock,
and read data bits are registered on the falling edge. This pin Communication Cycle—Instruction Plus Data
has an internal pull-down resistor. There are two parts to a communication cycle with the AD9912.
The first writes a 16-bit instruction word into the AD9912, coin-
SDIO (serial data input/output) is a dual-purpose pin and
cident with the first 16 SCLK rising edges. The instruction word
acts as input only or input/output. The AD9912 defaults to
provides the AD9912 serial control port with information
bidirectional pins for I/O. Alternatively, SDIO can be used
regarding the data transfer, which is the second part of the
as a unidirectional I/O pin by writing to the SDO active bit
communication cycle. The instruction word defines whether
(Register 0x0000, Bit 0 = 1). In this case, SDIO is the input,
the upcoming data transfer is a read or a write, the number of
and SDO is the output.
bytes in the data transfer, and the starting register address for
SDO (serial data out) is used only in the unidirectional I/O mode the first byte of the data transfer.
(Register 0x0000, Bit 0 = 1) as a separate output pin for reading
Write
back data. Bidirectional I/O mode (using SDIO as both input
and output) is active by default (SDO active bit: Register 0x0000, If the instruction word is for a write operation (I15 = 0), the
Bit 0 = 0). second part is the transfer of data into the serial control port
buffer of the AD9912. The length of the transfer (1, 2, or 3 bytes,
CSB (chip select bar) is an active low control that gates the read
or streaming mode) is indicated by two bits ([W1:W0]) in the
and write cycles. When CSB is high, SDO and SDIO are in a high
instruction byte. The length of the transfer indicated by [W1:W0]
impedance state. This pin is internally pulled up by a 100 kΩ
does not include the 2-byte instruction. CSB can be raised after
resistor to 3.3 V. It should not be left floating. See the Operation
each sequence of eight bits to stall the bus (except after the last
of Serial Control Port section on the use of the CSB in a
byte, where it ends the cycle). When the bus is stalled, the serial
communication cycle.
transfer resumes when CSB is lowered. Stalling on nonbyte
SCLK (PIN 64) boundaries resets the serial control port.
AD9912
SDIO (PIN 63)
SDO (PIN 62)
SERIAL There are three types of registers on the AD9912: buffered, live,
06763-041
CONTROL
CSB (PIN 61) PORT and read only. Buffered (also referred to as mirrored) registers
require an I/O update to transfer the new values from a
Figure 49. Serial Control Port
temporary buffer on the chip to the actual register and are
OPERATION OF SERIAL CONTROL PORT marked with an M in the Type column of the register map.
Framing a Communication Cycle with CSB Toggling the IO_UPDATE pin or writing a 1 to the register
update bit (Register 0x0005, Bit 0) causes the update to occur.
A communication cycle (a write or a read operation) is gated by
Because any number of bytes of data can be changed before
the CSB line. CSB must be brought low to initiate a communica-
issuing an update command, the update simultaneously enables
tion cycle.
all register changes that have occurred since any previous update.
CSB stall high is supported in modes where three or fewer bytes Live registers do not require I/O update; they update immediately
of data (plus the instruction data) are transferred ([W1:W0] after being written. Read-only registers ignore write commands
must be set to 00, 01, or 10; see Table 9). In these modes, CSB and are marked RO in the Type column of the register map. An
can temporarily return high on any byte boundary, allowing AC in this column indicates that the register is autoclearing.
time for the system controller to process the next byte. CSB can
AD9912
Read Bits[A12:A0] select the address within the register map that is
If the instruction word is for a read operation (I15 = 1), the next written to or read from during the data transfer portion of the
N × 8 SCLK cycles clock out the data from the address specified communications cycle. The AD9912 uses all of the 13-bit
in the instruction word, where N is 1, 2, 3, or 4, as determined address space. For multibyte transfers, this address is the
by [W1:W0]. In this case, 4 is used for streaming mode where starting byte address.
four or more words are transferred per read. The data readback Table 9. Byte Transfer Count
is valid on the falling edge of SCLK.
Bytes to Transfer
The default mode of the AD9912 serial control port is bidirec- W1 W0 (Excluding the 2-Byte Instruction)
tional mode, and the data readback appears on the SDIO pin. It 0 0 1
is possible to set the AD9912 to unidirectional mode by writing 0 1 2
to the SDO active bit (Register 0x0000, Bit 0 = 1), and in that 1 0 3
mode, the requested data appears on the SDO pin. 1 1 Streaming mode
By default, a read request reads the register value that is cur-
rently in use by the AD9912. However, setting Register 0x0004,
MSB/LSB FIRST TRANSFERS
Bit 0 = 1 causes the buffered registers to be read instead. The The AD9912 instruction word and byte data can be MSB first or
buffered registers are the ones that take effect during the next LSB first. The default for the AD9912 is MSB first. The LSB first
I/O update. mode can be enabled by writing a 1 to the LSB first bit in the
serial configuration register and then issuing an I/O update.
Immediately after the LSB first bit is set, all serial control port
CONTROL REGISTERS
REGISTER BUFFERS
SCLK
operations are changed to LSB first order.
SDIO When MSB first mode is active, the instruction and data bytes
SDO
UPDATE must be written from MSB to LSB. Multibyte data transfers in
CSB REGISTERS
SERIAL
MSB first format start with an instruction byte that includes the
06763-042
TOGGLE
CONTROL
IO_UPDATE
AD9912 register address of the most significant data byte. Subsequent
PORT CORE
PIN data bytes must follow in order from high address to low address.
Figure 50. Relationship Between Serial Control Port Register Buffers and In MSB first mode, the serial control port internal address
Control Registers of the AD9912
generator decrements for each data byte of the multibyte
The AD9912 uses Register 0x0000 to Register 0x0509. Although transfer cycle.
the AD9912 serial control port allows both 8-bit and 16-bit
When LSB first = 1 (LSB first), the instruction and data bytes
instructions, the 8-bit instruction mode provides access to five
must be written from LSB to MSB. Multibyte data transfers in
address bits (A4 to A0) only, which restricts its use to Address
LSB first format start with an instruction byte that includes the
Space 0x00 to Address Space 0x31. The AD9912 defaults to 16-bit
register address of the least significant data byte followed by
instruction mode on power-up, and the 8-bit instruction mode
multiple data bytes. The serial control port internal byte address
is not supported.
generator increments for each byte of the multibyte transfer cycle.
THE INSTRUCTION WORD (16 BITS) The AD9912 serial control port register address decrements from
The MSB of the instruction word is R/W, which indicates the register address just written toward 0x0000 for multibyte
whether the instruction is a read or a write. The next two bits, I/O operations if the MSB first mode is active (default). If the
[W1:W0], are the transfer length in bytes. The final 13 bits are LSB first mode is active, the serial control port register address
the address ([A12:A0]) at which to begin the read or write increments from the address just written toward 0x1FFF for
operation. multibyte I/O operations.
For a write, the instruction word is followed by the number of Unused addresses are not skipped during multibyte I/O operations.
bytes of data indicated by Bits[W1:W0], which is interpreted The user should write the default value to a reserved register and
according to Table 9. should write only zeros to unmapped registers. Note that it is
more efficient to issue a new write command than to write the
default value to more than two consecutive reserved (or
unmapped) registers.
AD9912
Table 10. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB LSB
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
CSB
SCLK DON'T CARE DON'T CARE
SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE
06763-043
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA
Figure 51. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
CS
SCLK
DON'T CARE DON'T CARE
SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
06763-057
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA DON'T
CARE
Figure 52. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
tDS tHI
tS tCLK tH
tDH
CSB tLO
SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE
06763-045
Figure 53. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CSB
SCLK
tDV
06763-046
SDIO
SDO DATA BIT N DATA BIT N – 1
Figure 54. Timing Diagram for Serial Control Port Register Read
CSB
SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE

06763-047
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA
Figure 55. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
AD9912
tS tH
CSB
tCLK
tHIGH tLOW
tDS
SCLK
tDH
06763-048
SDIO BIT N BIT N + 1
Figure 56. Serial Control Port Timing—Write
Table 11. Definitions of Terms Used in Serial Control Port Timing Diagrams
Parameter Description
tCLK Period of SCLK
tDV Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO)
tDS Setup time between data and rising edge of SCLK
tDH Hold time between data and rising edge of SCLK
tS Setup time between CSB and SCLK
tH Hold time between CSB and SCLK
tHI Minimum period that SCLK should be in a logic high state
tLO Minimum period that SCLK should be in a logic low state
AD9912
I/O REGISTER MAP

All address and bit locations that are left blank in Table 12 are unused.
Table 12.
Addr Default
(Hex) Type 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex)
Serial port configuration and part identification
0x0000 Serial SDO LSB first Soft Long Long Soft reset LSB first SDO 0x18
config. active (buffered) reset instruction instruction (buffered) active
0x0001 Reserved 0x00
0x0002 RO Part ID Part ID 0x02
0x0003 RO 0x19
0x0004 Serial Read buffer 0x00
options register
0x0005 AC Register 0x00
update
Power-down and reset
0x0010 Power- PD HSTL Enable Enable PD Full PD Digital PD 0xC0 or
down and driver CMOS output SYSCLK 0xD0
enable driver doubler PLL
0x0012 M, AC Reset DDS reset 0x00
0x0013 M PD fund S-div/2 S-divider 0x00
DDS reset reset
System clock
0x0020 N-divider N-divider, Bits[4:0] 0x12
0x0022 PLL VCO auto 2× refer- VCO range Charge pump current, 0x04
parameters range ence Bits[1:0]
CMOS output divider (S-divider)
to
0x0103
0x0104 S-divider S-divider, Bits[15:0] 0x00
and LSB: Register 0x0104
0x0105
0x0106 Falling S-divider/2 0x01
edge
triggered
Frequency tuning word
0x01A0 Reserved 0x00
to
0x01A5
0x01A6 M FTW0 FTW0, Bits[47:0] 0x00
0x01A7 M (frequency LSB: Register 0x01A6 0x00
tuning
0x01A8 M 0x00
word)
0x01A9 M 0x00
0x01AA M Start-up
cond.
0x01AB M Start-up
cond.
0x01AC M Phase DDS phase word, Bits[7:0] 0x00
0x01AD M DDS phase word, Bits[13:8] 0x00
Doubler and output drivers
0x0200 HSTL driver OPOL HSTL output doubler, 0x05
(polarity) Bits[1:0]
0x0201 CMOS driver CMOS mux 0x00
AD9912
Addr Default
(Hex) Type 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex)
Calibration (user-accessible trim)
to
0x040A
0x040B DAC full- DAC full-scale current, Bits[7:0] 0xFF
0x040C scale DAC full-scale current, 0x01
current Bits[9:8]
0x040D Reserved 0x00
0x040E Reserved 0x10
0x040F Reserved 0x00
and
0x0410
Harmonic spur reduction
0x0500 M Spur A HSR-A Amplitude Spur A harmonic, Bits[3:0] 0x00
enable gain × 2
0x0501 M Spur A magnitude, Bits[7:0] 0x00
0x0503 M Spur A phase, Bits[7:0] 0x00
0x0504 M Spur A 0x00
phase, Bit 8
0x0505 M Spur B HSR-B Amplitude Spur B harmonic, Bits[3:0] 0x00
enable gain × 2
0x0506 M Spur B magnitude, Bits[7:0] 0x00
0x0508 M Spur B phase, Bits[7:0] 0x00
0x0509 M Spur B 0x00
phase, Bit 8
1
Types of registers: M = mirrored (also called buffered). This type of register needs an I/O update for the new value to take effect; RO = read-only; AC = autoclear.
AD9912
I/O REGISTER DESCRIPTIONS

SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)
Register 0x0000—Serial Port Configuration
Table 13.
Bits Bit Name Description
[7:4] These bits are the mirror image of Bits[3:0].
3 Long instruction Read-only; the AD9912 supports only long instructions.
2 Soft reset Resets register map, except for Register 0x0000. Setting this bit forces a soft reset, meaning that S1 to
S4 are not tristated, nor is their state read when this bit is cleared. The AD9912 assumes the values of
S1 to S4 that were present during the last hard reset. This bit is not self-clearing, and all other registers
are restored to their default values after a soft reset.
1 LSB first Sets bit order for serial port.
1 = LSB first.
0 = MSB first. I/O update must occur for the MSB first to take effect.
0 SDO active Enables SDO pin.
1 = SDO pin enabled (4-wire serial port mode).
0 = 3-wire mode.
Register 0x0001—Reserved
Register 0x0002 and Register 0x0003—Part ID (Read-Only)
Register 0x0004—Serial Options

Table 14.
0 Read buffer register For buffered registers, serial port readback reads from actual (active) registers instead of the buffer.
1 = reads the buffered values that take effect during the next I/O update.
0 = reads values that are currently in effect.
Register 0x0005—Serial Options (Self Clearing)

Table 15.
0 Register update Software access to the register update pin function. Writing a 1 to this bit is identical to performing
an I/O update.
POWER-DOWN AND RESET (REGISTER 0x0010 TO REGISTER 0x0013)

Register 0x0010—Power-Down and Enable
Power-up default is defined by the start-up pins.
Table 16.
7 PD HSTL driver Powers down HSTL output driver.
1 = HSTL driver powered down.
6 Enable CMOS driver Powers up CMOS output driver.
1 = CMOS driver on.
5 Enable output doubler Powers up output clock generator doubler. Output doubler must still be enabled in Register 0x0200.
4 PD SYSCLK PLL System clock multiplier power-down.
1 = system clock multiplier powered down.
If the S4 pin is tied high at power-up or reset, this bit is set, and the default value for Register 0x0010
is D0, not C0.
1 Full PD Setting this bit is identical to activating the PD pin and puts all blocks (except serial port) into power-
down mode. SYSCLK is turned off.
0 Digital PD Removes clock from most of digital section; leave serial port usable. In contrast to full PD, setting this
bit does not debias inputs, allowing for quick wake-up.
AD9912
Register 0x0012—Reset (Autoclearing)
To reset the entire chip, the user can use the (non-autoclearing) soft reset bit in Register 0x0000.
Table 17.
0 DDS reset Reset of the direct digital synthesis block. Reset of this block is very seldom needed.
Register 0x0013—Reset (Continued) (Not Autoclearing)

Table 18.
7 PD fund DDS Setting this bit powers down the DDS fundamental output but not the spurs. It is used during tuning
of the SpurKiller circuit.
3 S-div/2 reset Asynchronous reset for S prescaler.
1 S-divider reset Synchronous (to S-divider prescaler output) reset for integer divider.
SYSTEM CLOCK (REGISTER 0x0020 TO REGISTER 0x0022)

Register 0x0020—N-Divider
Table 19.
[4:0] N-divider These bits set the feedback divider for system clock PLL. There is a fixed divide-by-2 preceding this
block, as well as an offset of 2 added to this value. Therefore, setting this register to 00000 translates to
an overall feedback divider ratio of 4. See Figure 45.
Register 0x0022—PLL Parameters
Table 20.
7 VCO auto range Automatic VCO range selection. Enabling this bit allows Bit 2 of this register to be set automatically.
[6:4] Reserved Reserved.
3 2× reference Enables a frequency doubler prior to the SYSCLK PLL and can be useful in reducing jitter induced by
the SYSCLK PLL. See Figure 44.
2 VCO range Selects low range or high range VCO.
0 = low range (700 MHz to 810 MHz).
1 = high range (900 MHz to 1000 MHz). For system clock settings between 810 MHz and 900 MHz, use
the VCO auto range (Bit 7) to set the correct VCO range automatically.
[1:0] Charge pump current Charge pump current.
00 = 250 μA.
01 = 375 μA.
10 = off.
11= 125 μA.
AD9912
CMOS OUTPUT DIVIDER (S-DIVIDER) (REGISTER 0x0100 TO REGISTER 0x0106)

Register 0x0100 to Register 0x0103—Reserved
Register 0x0104—S-Divider
Table 21.
[7:0] S-divider CMOS output divider. Divide ratio = 1 − 65,536. If the desired S-divider setting is greater than 65,536,
or if the signal on FDBK_IN is greater than 400 MHz, then Bit 0 in Register 0x0106 must be set. Note that
the actual S-divider is the value in this register plus 1; so to have an S-divider of 1, Register 0x0104 and
Register 0x0105 must both be 0x00. Register 0x0104 is the least significant byte.
Register 0x0105—S-Divider (Continued)

Table 22.
[15:8] S-divider CMOS output divider. Divide ratio = 1 − 65,536. If the desired S-divider setting is greater than 65,536,
or if the signal on FDBK_IN is greater than 400 MHz, then Bit 0 in Register 0x0106 must be set. Note that
the actual S-divider is the value in this register plus 1; so to have an S-divider of 1, Register 0x0104 and
Register 0x0105 must both be 0x00. Register 0x104 is the least significant byte.
Register 0x0106—S-Divider (Continued)

Table 23.
7 Falling edge triggered Setting this bit inverts the reference clock before S-divider.
0 S-divider/2 Setting this bit enables an additional /2 prescaler. See the CMOS Output Divider (S-Divider) section.
If the desired S-divider setting is greater than 65,536, or if the signal on FDBK_IN is greater than 400 MHz,
this bit must be set.
FREQUENCY TUNING WORD (REGISTER 0x01A0 TO REGISTER 0x01AD)

Register 0x01A0 to Register 0x01A5—Reserved
Register 0x01A6—FTW0 (Frequency Tuning Word)
Table 24.
[7:0] FTW0 These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte
of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW
results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)

Table 25.

Table 26.
AD9912
Table 27.
of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant
byte of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to
the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)

Table 28.
Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)

Table 29.
Register 0x01AC—Phase
Table 30.
[7:0] DDS phase word Allows the user to vary the phase of the DDS output. See the Direct Digital Synthesizer section.
Register 0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary
phase discontinuity may occur as the phase passes through 45° intervals.
Register 0x01AD—Phase (Continued)

Table 31.
[13:8] DDS phase word Allows the user to vary the phase of the DDS output. See the Direct Digital Synthesizer section.
Register 0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary
phase discontinuity may occur as the phase passes through 45° intervals.
AD9912
DOUBLER AND OUTPUT DRIVERS (REGISTER 0x0200 TO REGISTER 0x0201)

Register 0x0200—HSTL Driver
Table 32.
4 OPOL Output polarity. Setting this bit inverts the HSTL driver output polarity.
[1:0] HSTL output doubler HSTL output doubler.
01 = doubler disabled.
10 = doubler enabled. When using doubler, Bit 5 in Register 0x0010 must also be set to 1.
Register 0x0201—CMOS Driver

Table 33.
0 CMOS mux This bit allows the user to select whether the CMOS driver output is divided by the S-divider.
0 = S-divider input sent to CMOS driver.
1 = S-divider output sent to CMOS driver. See Figure 39.
CALIBRATION (USER-ACCESSIBLE TRIM) (REGISTER 0x0400 TO REGISTER 0x0410)

Register 0x0400 to Register 0x040A—Reserved
Register 0x040B—DAC Full-Scale Current
Table 34.
[7:0] DAC full-scale current DAC full-scale current, Bits[7:0]. See the Digital-to-Analog (DAC) Output section.
Register 0x040C—DAC Full-Scale Current (Continued)

Table 35.
[9:8] DAC full-scale current DAC full-scale current, Bits[9:8]. See Register 0x040B.
Register 0x040D to Register 0x0410—Reserved
HARMONIC SPUR REDUCTION (REGISTER 0x0500 TO REGISTER 0x0509)

See the Harmonic Spur Reduction section.
Register 0x0500—Spur A
Table 36.
7 HSR-A enable Harmonic Spur Reduction A enable.
6 Amplitude gain × 2 Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.
[3:0] Spur A harmonic Spur A Harmonic 1 to Spur A Harmonic 15. Allows user to choose which harmonic to eliminate.
Register 0x0501—Spur A (Continued)

Table 37.
[7:0] Spur A magnitude Linear multiplier for Spur A magnitude.
AD9912
Table 38.
[7:0] Spur A phase Linear offset for Spur B phase.

Table 39.
[8] Spur A phase Linear offset for Spur A phase.
Register 0x0505—Spur B
Table 40.
7 HSR-B enable Harmonic Spur Reduction B enable.
6 Amplitude gain × 2 Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.
[3:0] Spur B harmonic Spur B Harmonic 1 to Spur B Harmonic 15. Allows user to choose which harmonic to eliminate.
Register 0x0506—Spur B (Continued)

Table 41.
[7:0] Spur B magnitude Linear multiplier for Spur B magnitude.

Table 42.
[7:0] Spur B phase Linear offset for Spur B phase.

Table 43.
8 Spur B phase Linear offset for Spur B phase.
AD9912
OUTLINE DIMENSIONS
9.10
9.00 SQ 0.60 MAX
8.90 0.60
MAX PIN 1
49 64 INDICATOR
48 1
PIN 1
INDICATOR
8.85 0.50 EXPOSED 5.36

8.75 SQ BSC PAD
5.21 SQ
8.65 5.06
0.50
0.40 33 16
32 17
0.30
BOTTOM VIEW 0.25 MIN
TOP VIEW
7.50 REF
12° MAX 0.80 MAX
1.00
0.65 TYP FOR PROPER CONNECTION OF
0.85
0.05 MAX THE EXPOSED PAD, REFER TO
0.80 THE PIN CONFIGURATION AND
0.02 NOM
FUNCTION DESCRIPTIONS
SEATING 0.30 SECTION OF THIS DATA SHEET.
PLANE 0.20 REF
0.23
0.18
062209-A
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 57. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD9912ABCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-7
AD9912ABCPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-7
AD9912A/PCBZ Evaluation Board
1
Z = RoHS Compliant Part.
AD9912
NOTES
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06763-0-6/10(F)

AD9912

Uploaded by

Copyright:

Available Formats

AD9912

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

AD9912

Uploaded by

Copyright:

Available Formats

1 GSPS Direct Digital

Synthesizer with 14-Bit DAC

BASIC BLOCK DIAGRAM

Input/Output Termination Recommendations .......................... 16 Power-Down and Reset (Register 0x0010 to

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

SIGNAL POWER (dBm)

–80 06763-003 –100

SIGNAL POWER (dBm)

PHASE NOISE (dBc/Hz)

PHASE NOISE (dBc/Hz)

POWER DISSIPATION (mW)

POWER DISSIPATION (mW)

VIDEO BW: 30kHz

–50 THESE TWO SPURS

PHASE NOISE (dBc/Hz)

–165 200MHz –165

PHASE NOISE (dBc/Hz)

1.5 AMPLITUDE (V) 1.0

1.0 0.6 FREQUENCY = 20MHz

1.5 FREQUENCY = 40MHz

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

AD9912 DOWNSTREAM CLOCK AD9912

Figure 35. SYSCLK Input, Xtal Figure 38. FDBK_IN Input

DIGITAL SYNTHESIS CORE

LOW NOISE EXTERNAL

Figure 39. Detailed Block Diagram

FREQUENCY 48 48 19 19 ANGLE TO 14 DAC_OUT

The relative phase of the sinusoid can be controlled numerically,

⎛ Δphase ⎞ DAC_OUT 50 51 DAC_OUTB

DIGITAL-TO-ANALOG (DAC) OUTPUT 52

Figure 42. DAC Spectrum vs. Reconstruction Filter Response

SYSCLK PLL BYPASSED

SYSCLK 2 WITH EXTERNAL DRIVE

Figure 44. System Clock Generator Block Diagram

SYSCLK PLL MULTIPLIER

SYSCLK PLL phase detector or SYSCLK PLL doubler. These

The loop bandwidth of the SYSCLK PLL multiplier can be

Figure 47. Differential SYSCLK Inputs

CH2 CANCELLATION MAGNITUDE

Figure 48. Spur Reduction Circuit Diagram

POWER SUPPLY PARTITIONING

SERIAL CONTROL PORT

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE

DON'T CARE DON'T CARE

SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

Figure 56. Serial Control Port Timing—Write

I/O REGISTER MAP

I/O REGISTER DESCRIPTIONS