RF1K49093

Data Sheet August 1999 File Number

3969.5

2.5A, 12V, 0.130 Ohm, Logic Level, Dual P-Channel LittleFET Power MOSFET
This Dual P-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This product achieves full rated conduction at a gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA49093.

Features
2.5A, 12V rDS(ON) = 0.130 Temperature Compensating PSPICE Model On-Resistance vs Gate Drive Voltage Curves Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards

Symbol
BRAND RF1K49093
S1 (1) G1 (2) D1 (8) D1 (7)

Ordering Information
PART NUMBER RF1K49093 PACKAGE MS-012AA

NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4909396.

D2 (6) D2 (5) S2 (3) G2 (4)

Packaging
JEDEC MS-012AA

BRANDING DASH

5 1 2 3 4

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. LittleFET is a trademark of Intersil Corporation. PSPICE is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999

RF1K49093
Absolute Maximum Ratings
TA = 25oC Unless Otherwise Specied RF1K49093 -12 -12 10 2.5 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260 UNITS V V V A

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k, Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse width = 5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation TA = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg

W W/oC oC
oC oC

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 1. TJ = 25oC to 125oC. TA = 25oC, Unless Otherwise Specied SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 13) VGS = VDS, ID = 250A, (Figure 12) VDS = -12V, VGS = 0V VGS = 10V ID = 2.5A, VGS = -5V, (Figure 9, 11) VDD = -6V, ID 2.5A, RL = 2.40, VGS = -5V, RGS = 25 (Figure 10) TA = 25oC TA = 150oC MIN -12 -1 VGS = 0V to -10V VGS = 0V to -5V VGS = 0V to -1V VDD = -9.6V, ID = 2.5A, RL = 3.84 (Figure 15) Pulse width = 1s Device mounted on FR-4 material TYP 25 65 40 45 19 10 0.8 775 550 150 MAX -2 -1 -50 100 0.130 115 110 24 14 1.1 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W

Electrical Specications
PARAMETER

Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current

Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at -5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction-to-Ambient

IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(-5) Qg(TH) CISS COSS CRSS RJA

VDS = -10V, VGS = 0V, f = 1MHz (Figure 14)

Source to Drain Diode Ratings and Specications

PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = -2.5A ISD = -2.5A, dISD/dt = -100A/s MIN TYP MAX -1.25 55 UNITS V ns

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RF1K49093 Typical Performance Curves

1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 ID, DRAIN CURRENT (A) -3.0 -2.5 -2.0 -1.5

0.6 0.4

-1.0 -0.5 0 25

0.2 0.0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150

50

75 100 125 TA, AMBIENT TEMPERATURE (oC)

150

FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE

10

ZJA, NORMALIZED THERMAL IMPEDANCE

DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM

0.1

t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103

SINGLE PULSE 0.01 10-3 10-2

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-100

VDSS MAX = -12V ID, DRAIN CURRENT (A) -10 5ms 10ms -1 100ms 1s -0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -0.01 -0.1 -1 -10 DC

IDM, PEAK CURRENT CAPABILITY (A)

TJ = MAX RATED, TA = 25oC

-200 -100 VGS = -10V

FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I

= I25

150 - TA 125 TA = 25oC

-10

VGS = -5V

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 10-5 10-4 10-3 10-2 10-1 100 101

-100

VDS, DRAIN TO SOURCE VOLTAGE (V)

t, PULSE WIDTH (s)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

FIGURE 5. PEAK CURRENT CAPABILITY

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RF1K49093 Typical Performance Curves

-20 IAS, AVALANCHE CURRENT (A)

(Continued)
-25 VGS = -10V

STARTING TJ = 25oC

ID, DRAIN CURRENT (A)

-10

-20

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = -5V

-15 VGS = -4.5V -10 VGS = -4V -5 VGS = -3V

STARTING TJ = 150oC

If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] -1 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100

-1 -2 -3 -4 VDS, DRAIN TO SOURCE VOLTAGE (V)

-5

NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS

-25 ID(ON), ON-STATE DRAIN CURRENT (A) VDD = -6V -20 25oC -15 rDS(ON) , ON-STATE RESISTANCE (m) -55oC 150oC

500 ID = -1.5A 400 ID = -2.5A 300

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -10V ID = -6.0A

-10

200

ID = -0.5A

-5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0.0 -1.5 -3.0 -4.5 -6.0 VGS, GATE TO SOURCE VOLTAGE (V) -7.5

100

0 -2.5

-3.0

-3.5

-4.0

-4.5

-5.0

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 8. TRANSFER CHARACTERISTICS

FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT

120 100 SWITCHING TIME (ns) 80 60 tD(OFF) 40 tD(ON) 20 0 tr NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = -6V, ID = -2.5A, RL= 2.40

2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -5V, ID = -2.5A 1.5

tf

1.0

0.5

10 20 30 40 RGS, GATE TO SOURCE RESISTANCE ()

50

0 -80

-40

40

80

120

160

TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. SWITCHING TIME AS A FUNCTION OF GATE RESISTANCE

FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

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RF1K49093 Typical Performance Curves

2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = -250A

(Continued)
2.0 ID = -250A 1.5

THRESHOLD VOLTAGE

NORMALIZED GATE

1.5

1.0

1.0

0.5

0.5

0.0 -80

-40

0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)

160

0.0 -80

-40

0 40 80 120 TJ , JUNCTION TEMPERATURE (oC)

160

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE

1200

FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

-12 VDS , DRAIN-SOURCE VOLTAGE (V) VDD = BVDSS -9 -5.00 VGS , GATE-SOURCE VOLTAGE (V) VDD = BVDSS -3.75

C, CAPACITANCE (pF)

900 CISS COSS 600

VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD

-6

0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 3.84 IG(REF) = -0.5mA VGS = -5V

-2.50

-3

-1.25

300 CRSS 0

0 0 -2 -4 -6 -8 -10

0.00

VDS, DRAIN TO SOURCE VOLTAGE (V)

20 --------------------I G ( ACT ) NOTE:

I G ( REF )

t, TIME (s)

80 --------------------I G ( ACT )

I G ( REF )

Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT

Test Circuits and Waveforms

VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0

VDD VDD

0V VGS

DUT tP IAS 0.01

IAS tP BVDSS VDS

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT

FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

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RF1K49093 Test Circuits and Waveforms

(Continued)

tON td(ON) tr 0 RL 10%

tOFF td(OFF) tf 10%

DUT VGS RG

VDD
+

VDS VGS 0

90%

90%

10% 50% PULSE WIDTH 90% 50%

FIGURE 18. SWITCHING TIME TEST CIRCUIT

FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

CURRENT REGULATOR

-VDS (ISOLATED SUPPLY) Qg(TH) VDS

DUT 12V BATTERY 0.2F 50k 0.3F

0 VGS= -1V

D G 0 Ig(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR 0 Ig(REF) DUT VDD

-VGS Qg(-5)

VGS= -5V

VGS= -10V

Qg(TOT)

FIGURE 20. GATE CHARGE TEST CIRCUIT

FIGURE 21. GATE CHARGE WAVEFORMS

Soldering Precautions
The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device.

3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided.

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RF1K49093 PSPICE Electrical Model

SUBCKT RF1K49093 2 1 3; CA 12 8 8.75e-10 CB 15 14 8.65e-10 CIN 6 8 7.65e-10 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 5 DPLCAPMOD
-

rev 10/24/94
DPLCAP 10 5 LDRAIN 2 DRAIN

RDRAIN

EBREAK 5 11 17 18 -23.75 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9

ESG + EVTO LGATE RGATE + 18 8 9 20

6 8 - VTO + 6

+ 16 EBREAK MOS2 11 DBREAK 17 18 -

DBODY

GATE 1

21 MOS1

RIN

CIN 8 RSOURCE 7 LSOURCE 3 SOURCE

S1A 12 13 8 S1B CA EGS 14 13

S2A 15 S2B 13 CB + 6 8 EDS + 5 8 14 IT RBREAK 17 18 RVTO 19 VBAT +

MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 7.36e-3 RGATE 9 20 6.1 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 4.56e-2 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.558

.MODEL DBDMOD D (IS = 3.0e-13 RS = 4.4e-2 TRS1 = 1.0e-3 TRS2 = -7.37e-6 CJO = 1.27e-9 TT = 2.2e-8) .MODEL DBKMOD D (RS = 7.84e-2 TRS1 = -4.27e-3 TRS2 = 5.77e-5) .MODEL DPLCAPMOD D (CJO = 2.85e-10 IS = 1e-30 N = 10) .MODEL MOSMOD PMOS (VTO = -2.1423 KP = 9.206 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.61e-4 TC2 = -1.09e-6) .MODEL RDSMOD RES (TC1 = 2.10e-3 TC2 = 6.99e-6) .MODEL RVTOMOD RES (TC1 = -1.82e-3 TC2 = 1.47e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.47 VOFF= 3.47) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.47 VOFF= 5.47) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.05 VOFF= -3.95) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.95 VOFF= 1.05) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.

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