Data Sheet No.

PD60240

IRS20124(S)PbF
Digital Audio Driver with Discrete Deadtime and Protection
Features Product Summary
• 200 V high voltage ratings deliver up to 1000 W
VSUPPLY 200 V max.
output power in Class D audio amplifier
applications IO+/- 1 A / 1.2 A typ.
• Integrated deadtime generation and bi-directional
over-current sensing simplify design Selectable Deadtime
• Programmable compensated preset deadtime for 15 ns, 25 ns, 35 ns, 45 ns typ.
improved THD performances over temperature
Prop Delay Time 60 ns typ.
• High noise immunity
• Shutdown function protects devices from overload Bi-Directional Over-
conditions Current Sensing
• Operates up to 1 MHz
• 3.3 V/5 V logic compatible input Package
• RoHS compliant

14-Lead SOIC

Typical Application Diagram

<20 V
<200 V

IN IN NC
OCSET 1 NC
<20 V DT/SD VB
OCSET 2 HO

OC OC VS

COM NC

LO VCC
SD
IRS20124

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 IRS20124S(PbF)

Description
The IRS20124 is a high voltage, high speed power MOSFET driver with internal deadtime and shutdown
functions specially designed for Class D audio amplifier applications.

The internal dead time generation block provides accurate gate switch timing and enables tight deadtime
settings for better THD performances.

In order to maximize other audio performance characteristics, all switching times are designed for immunity
from external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logic
inputs are compatible with LSTTL output or standard CMOS down to 3.0 V without speed degradation. The
output drivers feature high current buffers capable of sourcing 1.0 A and sinking 1.2 A. Internal delays are
optimized to achieve minimal deadtime variations. Proprietary HVIC and latch immune CMOS technologies
guarantee operation down to Vs= –4 V, providing outstanding capabilities of latch and surge immunities with
rugged monolithic construction.

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. All currents are defined positive into any lead. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

VB High-side floating supply voltage -0.3 220
Vs High-side floating supply voltage VB-20 VB+0.3
VHO High-side floating output voltage Vs-0.3 VB+0.3
VCC Low-side fixed supply voltage -0.3 20
VLO Low-side output voltage -0.3 Vcc+0.3 V
VIN Input voltage -0.3 Vcc+0.3
VOC OC pin input voltage -0.3 Vcc+0.3
VOCSET1 OCSET1 pin input voltage -0.3 Vcc+0.3
VOCSET2 OCSET2 pin input voltage -0.3 Vcc+0.3
dVs/dt Allowable Vs voltage slew rate - 50 V/ns
PD Maximum power dissipation - 1.25 W
RthJA Thermal resistance, junction to ambient - 100 °C/W
TJ Junction temperature - 150
TS Storage temperature -55 150 °C
TL Lead temperature (soldering, 10 seconds) - 300

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 IRS20124S(PbF)

Recommended Operating Conditions

For proper operation, the device should be used within the recommended conditions. The Vs and COM
offset ratings are tested with all supplies biased at a 15 V differential.

Symbol Definition Min. Max. Units

VB High-side floating supply absolute voltage Vs+10 Vs+18
VS High-side floating supply offset voltage Note 1 200
VHO High-side floating output voltage Vs VB
VCC Low-side fixed supply voltage 10 18
VLO Low-side output voltage 0 VCC V
VIN Logic input voltage 0 VCC
VOC OC pin input voltage 0 VCC
VOCSET1 OCSET1 pin input voltage 0 VCC
VOCSET2 OCSET2 pin input voltage 0 VCC
TA Ambient Temperature -40 125 °C

Note 1: Logic operational for VS equal to -8 V to 200 V. Logic state held for VS equal to -8 V to -VBS.

Dynamic Electrical Characteristics

VBIAS (VCC, VBS) = 15 V, CL = 1n F and TA = 25 °C unless otherwise specified. Fig. 2 shows the timing definitions.

Symbol Definition Min. Typ. Max. Units Test Conditions

ton High & low-side turn-on propagation delay — 60 80 VS=0 V
toff High & low-side turn-off propagation delay — 60 80 VS=200 V
tr Turn-on rise time — 25 40
tf Turn-off fall time — 15 35
tsd Shutdown propagation delay — 140 200
OCSET1=3.22 V
toc Propagation delay time from Vs>Vsoc+ to OC — 280 —
OCSET2=1.20 V
twoc min OC pulse width — 100 — ns
toc filt OC input filter time — 200 —
Deadtime: LO turn-off to HO turn-on (DTLO-HO)
DT1 0 15 40 VDT>VDT1
& HO turn-off to LO turn-on (DTHO-LO)
Deadtime: LO turn-off to HO turn-on (DTLO-HO)
DT2 5 25 50 VDT1>VDT> VDT2
& HO turn-off to LO turn-on (DTHO-LO)
Deadtime: LO turn-off to HO turn-on (DTLO-HO)
DT3 10 35 60 VDT2>VDT>VDT3
& HO turn-off to LO turn-on (DTHO-LO)
Deadtime: LO turn-off to HO turn-on (DTLO-HO)
DT4 15 45 70 VDT3>VDT>VDT4
& HO turn-off to LO turn-on (DTHO-LO)VDT= VDT4

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 IRS20124S(PbF)

Static Electrical Characteristics

VBIAS (VCC , VBS) = 15 V and TA = 25 °C unless otherwise specified.

Symbol Definition Min. Typ. Max. Units Test Conditions

VIH Logic high input voltage 2.5 — — Vcc=10 V -20 V
VIL Logic low input voltage — — 1.2
VOH High level output voltage, VBIAS – VO — — 1.2
Io=0 A
VOL Low level output voltage, VO — — 0.1
V
UVCC+ Vcc supply UVLO positive threshold 8.3 9.0 9.7
UVCC- Vcc supply UVLO negative threshold 7.5 8.2 8.9
UVBS+ High-side well UVLO positive threshold 8.3 9.0 9.7
UVBS- High-side well UVLO negative threshold 7.5 8.2 8.9
IQBS High-side quiescent current — — 1
mA
IQCC Low-side quiescent current — — 4 VDT=Vcc
ILK High-to-low-side leakage current — — 50 VB=VS =200 V
IIN+ Logic “1” input bias current — 3 10 µA VIN=3.3 V
IIN- Logic “0” input bias current — 0 1.0 VIN=0V
Io+ Output high short circuit current (source) — 1.0 — Vo=0 V, PW<10 µs
A
Io- Output low short circuit current (sink) — 1.2 — Vo=15 V, PW<10 µs
VDT1 DT mode select threshold 1 0.8(Vcc) 0.89(Vcc) 0.97(Vcc)
VDT2 DT mode select threshold 2 0.51(Vcc) 0.57(Vcc) 0.63(Vcc)
VDT3 DT mode select threshold 3 0.32(Vcc) 0.36(Vcc) 0.40(Vcc)
VDT4 DT mode select threshold 4 0.21(Vcc) 0.23(Vcc) 0.25(Vcc)
V
OCSET1=3.22 V
VSOC+ OC threshold in Vs 0.75 1.0 1.25
OCSET2=1.20 V
OCSET1=3.22 V
VSOC- OC threshold in Vs -1.25 -1.0 -0.75
OCSET2=1.20 V

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 IRS20124S(PbF)

Lead Definitions
Symbol Description
VCC Low-side logic supply voltage
VB High-side floating supply
HO High-side output
VS High-side floating supply return
IN Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
DT/SD Input for programmable deadtime, referenced to COM. shutdown LO and HO when tied to COM
COM Low-side supply return
LO Low-side output
OC Over-current output (negative logic)
OC SET1 Input for setting negative over current threshold
OC SET2 Input for setting positive over current threshold

1 IN NC 14
2 OCSET1 NC 13
3 DT/SD VB 12
4 OCSET2 HO 11
5 OC VS 10
6 COM NC 9
7 LO VCC 8

IR20124S 14 Lead SOIC (narrow body)

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 IRS20124S(PbF)

Block Diagram

VB
UV
DETECT UV
Q
LEVEL
S
SHIFTER
R
HO
DEAD
IN TIME SD

VS
CURRENT
SENSING

DT/SD
Vcc
UV
DETECT

LO

DELAY
COM
OCSET2
OCSET1
OC

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IN 50% 50%

ton(L)
toff(L)
toff(H)
ton(H)
90%
LO

10%

DTHO- LO DTLO- HO

90%
HO

10%

Figure 1. Switching Time Waveform Definitions

DT/SD

VSD

HO
LO
90%

TSD
Figure 2. Shutdown Waveform Definitions

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LO
COM

toc filt VS
VSoc+
VS COM
Vsoct VSoc-
COM

HIGH OC

OC tdoc
COM
twoc

Figure 3. OC Input FilterTime Definitions Figure 4. OC Waveform Definitions

IN NC

OCSET1 NC
DT/SD VB
OCSET2 HO
__ 15V
10k OC VS
Vsoc+
COM NC
Vsoc-
LO VCC
15V

OC

Vsoc+
VS COM
Vsoc-

OC

Figure 5. OC Waveform Definitions

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 IRS20124S(PbF)

200 200

160 160
Turn-On Delay Time (ns)

Turn-On Delay Time (ns)

120 120

80 80

40 40

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature ( C) o
V BIAS Supply Voltage (V)

Figure 6A. Turn-On Tim e Figure 6B. Turn-On Tim e

vs. Tem perature vs. Supply Voltage

0
150 150

0
120 120
Turn-Off Time (ns)

Max.
Turn-Off Time (ns)

Max.
0
90 90

60
0 60
Typ.
Typ.
30
0 30

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20

Temperature (oC) VBIAS Supply Voltage (V)

Figure 7A. Turn-Off Time Figure 7B. Turn-Off Time

vs. Temperature vs. Supply Voltage

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60 60

Turn-On Rise Time (ns)

Turn-On Rise Time (ns)

50 50

40 40

30 30

20 20

10 10
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature ( oC) V BIAS Supply Voltage (V)

Fiure 8A. Turn-On Rise Tim e Figure 8B. Turn-On Rise Tim e
vs.Tem perature vs. Supply Voltage

50 50
Turn-Off Fall Time (ns)

Turn-Off Fall Time (ns)

40 40

30 30

20 20

10 10

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature ( C)o
V BIAS Supply Voltage (V)

Figure 9A. Turn-Off Fall Tim e Figure 9B. Turn-Off Fall Tim e
vs. Tem perature vs. Supply Voltage

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 IRS20124S(PbF)

5 5

4 4

Input Voltage (V)

Input Voltage (V)

3 3

Min. 2
2
Min.

1 1
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20

Temperature (oC) V CC Supply Voltage (V)

Figure 10A. Logic "1" Input Voltage Figure 10B. Logic "1" Input Voltage
vs. Tem perature vs. Supply Voltage

4 4

3 3
Input Voltage (V)

Input Voltage (V)

2 2

Max. Max.

1 1

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20

Temperatre ( C)o V CC Supply Voltage (V)

Figure 11A. Logic "0" Input Voltage Figure 11B. Logic "0" Input Voltage
vs. Temperature vs. Supply Voltage

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4 4

High Level Output Voltage (V)

High Level Output Voltage (V)

3
3
Max.
2
2
1 Max.
1
0

-1 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20

Temperature (oC) V CC Supply Voltage (V)

Figure 12A. High Level Output Figure 12B. High Level Output
vs. Temperature vs. Supply Voltage

0.25 0.25
Low Level Output Voltage (V)

Low Level Output Voltage (V)

0.20 0.20

0.15 0.15
Max. Max.
0.10 0.10

0.05 0.05

0.00 0.00
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature ( C)
o
VCC Supply Voltage (V)
Figure 13A. Low Level Output Figure 13B. Low Level Output
vs.Temperature vs. Supply Voltage

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300 110

Offset Supply Leakage Current (µA)

Offset Supply Leakage Current (µA)

250 90

200 70
Max.
150 50

100 30
Max. Typ.
50 10

0 -10
-50 -25 0 25 50 75 100 125 50 80 110 140 170 200
Temperature ( oC) V B Boost Voltage (V)

Figure 14A. Offset Supply Leakage Figure 14B. Offset Supply Leakage
Current vs. Temperature V B= 200 V Current vs. Supply Voltage

2.5 3
V BS Supply Current (µA )

V BS Supply Current (µA)

2.0 2

1.5 2

1.0 1

0.5 1

0.0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20

Temperature (oC) V BS Supply Voltage (V)

Figure 15A. V BS Supply Current Figure 15B. V BS Supply Current

vs. Tem perature vs. Supply Voltage

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10 10

V cc Supply Current (µΑ)

V cc Supply Current (µA)

8 8

6 6
Max. Max.
4 4

2 2

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20

Temperature (oC) V CC Supply Voltage (V)

Figure 16B. V CC Supply Current

Figure 16A. V CC Supply Current vs. Supply Voltage
vs. Temperature

30 30
Logic "1" Input Current (µA)

Logic "1" Input Current (µA)

24 24

18 18

12 12

6 6

0
0
-50 -25 0 25 50 75 100 125
10 12 14 16 18 20
Temperature (oC)
V CC Supply Voltage (V)

Figure 17A. Logic "1" Input Current Figure 17B. Logic "1" Input Current
vs. Tem perature vs. Supply Voltage

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 IRS20124S(PbF)

6 6

Logic "0" Input Bias C urrent (µA)

Lo gic "0" Input Bias Current (µA)

5 Max 5 Max

4 4

3 3

2 2

1 1

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (°C) Supply Voltage (V)
Figure 18A. Logic "0" Input Bias Current Figure 18B. Logic "0" Input Bias Current
vs. Temperature vs. Voltage

11 11
V cc Supply Cur rent (µΑ )
V cc Supply Cur rent (µΑ)

10 10
Max.
Max.
9 9
Typ. Typ.
8 8
Min.

7 7 Min.

6 6
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature ( C)
o
Temperature ( C)
o

Figure 19. V CC Undervoltage Threshold (+) Figure 20. V CC Undervoltage Threshold (-)
vs. Temperature vs. Temperature

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 IRS20124S(PbF)

11 11

VBS Supply Current (µA)

VBS Supply Current (µA)

10 10

9 9

8 8

7 7

6 6
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Temperature (oC) Temperature ( C)

o

Figure 21. V BS Undervoltage Threshold (+) Figure 22. V BS Undervoltage Threshold (-)
vs. Tem perature vs. Tem perature

1.5 1.5
Output Source Current (Α)

Output Sink Current (Α)

1.3 1.3

1.1 1.1

0.9 0.9
Typ.
Typ.
0.7 0.7

0.5 0.5
10 12 14 16 18 20 10 12 14 16 18 20
V BIAS Supply Voltage (V) VBIAS Supply Voltage (V)

Figure 23. Output Source Current Figure 24. Output Sink Current
vs. Supply Voltage vs. Supply Voltage

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 IRS20124S(PbF)

-5 16
VS Offset Supply Voltage (V)

Typ. Max.
-7 15

-9 14

VDT1 (V)
Typ.
-11 13
Min.
-13 12

-15 11
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
V BS Floting Supply Voltage (V) Temperature ( C)
o

Figure 25. Maximum V S Negative Offset Figure 26. DT Mode Select Threshold (1)
vs. Supply Voltage vs. Temperature

11 8

10 Max. 7
Max.
9 6
VDT2 (V)

VDT3 (V)

Typ.
Typ.
8 5
Min. Min.
7 4

6 3
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature ( C)
o
Temperature ( C)
o

Figure 27. DT Mode Select Threshold (2) Figure 28. DT Mode Select Threshold (3)
vs. Temperature vs. Temperature

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 IRS20124S(PbF)

4.5 60

4.0 52

3.5 44
VDT4 (V)

DTLO-HO (ns)
3.0 36
Typ.
2.5 28

2.0 20
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Temperature ( C)
o Temperature ( C)
o

Figure 29. DT Mode Select Threshold (4) Figure 30. DT LO Turn-Off to HO TurnOon (3)
vs. Tem perature vs. Tem perature

2.0 -0.3

Max.
1.6 -0.6
Negative OC TH (V)
Positive OC TH (V)

Max.
1.2 -0.9
Typ.
Typ.
0.8 -1.2
Min. Min.
0.4 -1.5

0.0 -1.8
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature ( oC) Temperature ( C)
o

Figure 31. Positive OC Threshold(+) in V S Figure 32. Negative OC Threshold(-) in V S

vs. Tem perature vs. Temperature

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 IRS20124S(PbF)

65 65

55 55

Temperature (oC)
Temperature (oC)

140v
70v
45 140V
45 0v
70V
35 0V 35

25 25

15 15
1 10 100 1000 1 10 100 1000
Frequency (kHz) Frequency (kHz)

Figure 33
32.. IRS20124S vs. Frequency (IRFBC20) Figure 34
33.. IRS20124S vs. Frequency (IRFBC30)
Rgate=33 Ω , VCC=12 V Rgate=22 Ω , V CC=12 V

65 75
140V

55 65 70V
140V
Temperature (oC)

Temperature (oC)

0V
70V 55
45 0V

45
35
35
25 25

15 15
1 10 100 1000 1 10 100 1000
Frequency (kHz) Frequency (kHz)
Figure 334.
5. IRS20124S vs. Frequency (IRFBC40) Figure 335.
6. IRS20124S vs. Frequency (IRFPE50)
Rgate=15 Ω , V CC=12 V Rgate=10 Ω , V CC=12 V

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 IRS20124S(PbF)

Functional description
90%
Programmable Dead-time
Effective dead-time
HO (or LO)
The IRS20124 has an internal deadtime generation 10%
block to reduce the number of external components
in the output stage of a Class D audio amplifier.
Selectable deadtime through the DT/SD pin volt- tf
age is an easy and reliable function, which re-
quires only two external resistors. The deadtime
generation block is also designed to provide a LO (or HO) Dead-
constant deadtime interval, independent of Vcc time
fluctuations. Since the timings are critical to the 10%
audio performance of a Class D audio amplifier,
the unique internal deadtime generation block is
Effective Deadtime
designed to be immune to noise on the DT/SD
pin and the Vcc pin. Noise-free programmable
deadtime function is available by selecting
deadtime from four preset values, which are opti- A longer deadtime period is required for a MOSFET
mized and compensated. with a larger gate charge value because of the
longer tf. A shorter effective deadtime setting is
How to Determine Optimal Deadtime always beneficial to achieve better linearity in the
Class D switching stage. However, the likelihood
Please note that the effective deadtime in an actual of shoot-through current increases with narrower
application differs from the deadtime specified in deadtime settings in mass production. Negative
this datasheet due to finite fall time, tf. The values of effective deadtime may cause excessive
deadtime value in this datasheet is defined as the heat dissipation in the MOSFETs, potentially
time period from the starting point of turn-off on leading to their serious damage. To calculate the
one side of the switching stage to the starting optimal deadtime in a given application, the fall
point of turn-on on the other side as shown in Fig. time (tf)for both output voltages, HO and LO, in
5. The fall time of MOSFET gate voltage must be the actual circuit needs to be measured. In
subtracted from the deadtime value in the addition, the effective deadtime can also vary with
datasheet to determine the effective dead time of temperature and device parameter variations.
a Class D audio amplifier. Therefore, a minimum effective deadtime of 10 ns
is recommended to avoid shoot-through current
(Effective deadtime) over the range of operating temperatures and
= (Deadtime in datasheet) – (fall time, tf) supply voltages.

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 IRS20124S(PbF)

DT/SD pin

DT/SD pin provides two functions: 1) setting dead- Deadtime R1 R2 DT/SD

time and 2) shutdown. The IRS20124 determines mode (Ω) (Ω) (V)
its operation mode based on the voltage applied DT1 <10k Open 1.00 (Vcc)
to the DT/SD pin. An internal comparator DT2 3.3k 8.2k 0.71 (Vcc)
translates which mode is being used by comparing DT3 5.6k 4.7k 0.46 (Vcc)
internal reference voltages. Threshold voltages for DT4 8.2k 3.3k 0.29 (Vcc)
each mode are set internally by a resistive voltage
Table 1. Suggested Resistor Values for Deadtime
divider off Vcc, negating the need of using a precise Settings
absolute voltage to set the mode.

Shutdown
Operational Mode
Since IRS20124 has internal deadtime generation,
independent inputs for HO and LO are no longer
15nS provided. Shutdown mode is the only way to turn
off both MOSFETs simultaneously to protect them
25nS
Dead-time from over current conditions. If the DT/SD pin de-
35nS tects an input voltage below the threshold, VDT4,
the IRS20124 will output 0 V at both HO and LO
45nS
outputs, forcing the switching output node to go
Shutdown
VDT
into a high impedance state.
0.23xVcc 0.36xVcc 0.57xVcc 0.89xVcc Vcc

Over Current Sensing

Deadtime Settings vs VDT Voltage

In order to protect the power MOSFET, IRS20124

has a feature to detect over-current conditions,
Design Example
which can occur when speaker wires are shorted
together. The over-current shutdown feature can
Table 1 shows suggested values of resistance for
be configured by combining the current sensing
setting the deadtime. Resistors with up to 5%
function with the shutdown mode via the DT/SD pin.
tolerance can be
IRS20124
used if these
listed values are >0.5mA Load Current Direction in Class D Audio
Vcc
followed. Application
R1
DT/SD In a Class D audio amplifier, the direction of the
R2 load current alternates according to the audio in-
COM put signal. An over current condition can therefore
happen during either a positive current cycle or a
External Resistor
negative current cycle. It should be noted that

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 IRS20124S(PbF)

each MOSFET carries a part of the load current IRS20124 measures the current during the period
in an audio cycle. Bi-directional current sensing when the low side MOSFET is turned on. Under
offers over current detection capabilities in both normal operating conditions, Vs voltage for the low
cases by monitoring only the low side MOSFET. side switch is well within the trip threshold bound-
aries, VSOC- and VSOC+. In the case of Fig. 9(b) which
demonstrates the amplifier sourcing too much cur-
rent to the load, the Vs node is found below the trip
Load Current
level, VSOC-. In Fig. 9(c) with opposite current direc-
tion, the amplifier sinks too much current from the
load, positioning Vs well above trip level, VSOC+.
0
Once the voltage in Vs exceeds the preset thresh-
old, the OC pin pulls down to COM to detect an
over-current condition.

Direction in MOSFET Current and Load Current Since the switching waveform usually contains
over/under shoot and associated oscillatory arti-
facts on their transient edges, a 200 ns blanking
interval is inserted in the Vs voltage sensing block
Bi-Directional Current Sensing
at the instant the low side switch is engaged.
Because of this blanking interval, the OC function
IRS20124 has an over-current detection function
will be unable to detect over current conditions if
utilizing RDS(ON) of the low side switch as a current
the low side ON duration less than 200 ns.
sensing shunt resistor. Due to the proprietary HVIC
process, the IRS20124 is able to sense negative
LO
as well as positive current flow, enabling bi-direc- Vs +
tional load current sensing without the need for OC SET1 -
OC
any additional external passive components. OR
AND

OCSET2 +
-
vs

~
~ ~
~ ~
~ ~
~ ~ ~
~ ~ ~
~ ~
~ ~
~ ~
~ ~
~

Vsoc+
Simplified Functional Block Diagram of
COM Bi-Directional Current Sensing
Vsoc-
The bi-directional current sensing block has an
(a ) Normal Operation (b ) Over- Current in (c ) Over- Current in internal V level shifter feeding the signal to the
Condition Positive Load Current Negative Load Current
comparator. OCSET1 sets the threshold, and is
given a trip level at VSOC+, which is OCSET1 -V. In
Vs Waveform in Over-Current Condition the same way, for a given OCSET2, VSOC- is set at
OCSET2 -V.

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 IRS20124S(PbF)

in the negative load current direction, the sensing

>0.5mA voltage at the Vs node is limited by the body di-
Vcc
ode of the low side MOSFET as explained later.
R3
OCSET1 Design Example
R4
This example demonstrates how to use the exter-
OCSET2 nal resistor network to set ITRIP+ and ITRIP- to be
R5 ±11 A, using a MOSFET that has RDS(ON) =60 µΩ.

COM
VISET1 = VTH+ + 2.21 V = ITRIP+ x RDS(ON) + 2.21 V =
11 x 60 µΩ +2.21 V = 2.87 V
External Resistor Network to Set OC Threshold VISET2 = VTH- + 2.21 V = ITRIP- x RDS(ON) + 2.21 V =
(−11) V 60 µΩ +2.21 V = 1.55 V

How to set OC Threshold The total resistance of resistor network is based

on the voltage at the Vcc and required bias cur-
rent in this resistor network.
The positive and negative trip thresholds for bi-
directional current sensing are set by the voltages
Rtotal =R3 + R4 + R5 = Vcc / Ibias
at OCSET1 and OCSET2.
= 12 V / 1 µΑ = 12 k Ω

The trip threshold voltages, VSOC+ and VSOC+, are The expected voltage across R3 is Vcc- VISET1
determined by the required trip current levels, ITRIP+ = 12 V - 2.87 V=9.13 V. Similarly, the voltages
ITRIP-, and RDS(ON) in the low side MOSFET. across R4 is VSOC+ - VSOC- = 2.87 V - 1.55 V
Since the sensed voltage of Vs is shifted up by =1.32 V, and the voltage across R5 is VISET2= 1.55
2.21 V internally and compared with the voltages V respectively.
fed to the OCSET1 and OCSET2 pins, the required
value of OCSET1 with respect to COM is R3 =9.13 V/ Ibias = 9.13 kΩ
R4 =1.32 V/ Ibias = 1.32 kΩ
VOCSET1 = VSOC+ + 2.21 V = I x RDS(ON) + 2.21 V R5 =1.55 V/ Ibias = 1.55 kΩ

The same relation holds between OCSET2 and VSOC-, Choose R3= 9.09 kΩ R4=1.33 kΩ, R5=1.54 kΩ
from E-96 series.
VOCSET2 = VSOC- + 2.21 V = I x RDS(ON) + 2.21 V Consequently, actual threshold levels are
VSOC+ =2.88 V gives ITRIP+ = 11.2 A
In general, RDS(ON) has a positive temperature co- VSOC- =1.55 V gives ITRIP- = -11.0 A
efficient that needs to be considered when the
threshold level is being set. Please also note that, Resisters with 1% tolerances are recommended.

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 IRS20124S(PbF)

OC Output Signal
VS - COM
The OC pin is a 20 V open drain output. The OC
pin is pulled down to ground when an over current
condition is detected. A single external pull-up
resistor can be shared by multiple IRS20124 OC
pins to form the ORing logic. In order for a micro-
processor to read the OC signal, this information
is buffered with a mono stable multi vibrator to

}
ensure 100 ns minimum pulse width. ID
0
Because of unpredictable logic status of the OC
pin, the OC signal should be ignored during power
up/down.

Limitation from Body Diode in MOSFET

When a Class D stage outputs a positive current, OCSET2 should be

Body Diode Clamp set in this region
flowing from the Class D amp to the load, the body
diode of the MOSFET will turn on when the drain Body Diode in MOSFET Clamps vs Voltage
to source voltage of the MOSFET become larger
than the diode forward drop voltage. In such a
case, the sensing voltage at the Vs pin of the
IRS20124 is clamped by the body diode. This
means that the effective RDS(ON) is now much lower
than expected from RDS(ON) of the MOSFET, and
the Vs node my not able to reach the threshold
to turn the OC output on before the MOSFET fails. For further application information for gate driver
Therefore, the region where body diode clamping IC please refer to AN-978 and DT98-2a. For fur-
takes a place should be avoided when setting VSOC- ther application information for class D applica-
. tion, please refer to AN-1070 and AN-1071.

www.irf.com 24
 IRS20124S(PbF)

Case Outline

01-6019
14 Lead SOIC (narrow body) 01-3063 00 (MS-012AB)

www.irf.com 25
 IRS20124S(PbF)
LOAD ED TA PE FEED DIRECTION
Tape & Reel
14-Lead SOIC B A H

F C

N OT E : CO NTROLLING
D IMENSION IN MM E

C A R R I E R T A P E D IM E N S I O N F O R 1 4 S O IC N
M etr ic Im p erial
Co d e M in M ax M in M ax
A 7 .9 0 8.1 0 0. 31 1 0 .3 18
B 3 .9 0 4.1 0 0. 15 3 0 .1 61
C 15 .7 0 1 6. 30 0. 61 8 0 .6 41
D 7 .4 0 7.6 0 0. 29 1 0 .2 99
E 6 .4 0 6.6 0 0. 25 2 0 .2 60
F 9 .4 0 9.6 0 0. 37 0 0 .3 78
G 1 .5 0 n/ a 0. 05 9 n/ a
H 1 .5 0 1.6 0 0. 05 9 0 .0 62

B
C
A
E

R E E L D IM E N S I O N S F O R 1 4 SO IC N
M etr ic Im p erial
Co d e M in M ax M in M ax
A 32 9. 60 3 30 .2 5 1 2 .9 76 13 .0 0 1
B 20 .9 5 2 1. 45 0. 82 4 0 .8 44
C 12 .8 0 1 3. 20 0. 50 3 0 .5 19
D 1 .9 5 2.4 5 0. 76 7 0 .0 96
E 98 .0 0 1 02 .0 0 3. 85 8 4 .0 15
F n /a 2 2. 40 n /a 0 .8 81
G 18 .5 0 2 1. 10 0. 72 8 0 .8 30
H 16 .4 0 1 8. 40 0. 64 5 0 .7 24

www.irf.com 26
 IRS20124S(PbF)

LEADFREE PART MARKING INFORMATION

Part number IRSxxxxx

Date code YWW? IR logo

Pin 1 ?XXXX
Identifier
Lot Code
? MARKING CODE (Prod mode - 4 digit SPN code)
P Lead Free Released
Non-Lead Free
Released
Assembly site code
Per SCOP 200-002

ORDER INFORMATION
14-Lead SOIC IRS20124SPbF
14-Lead SOIC Tape & Reel IRS20124STRPbF

SO-14 package is MSL2 qualified.

This product has been designed and qualified for the industrial level.
Qualification standards can be found at IR's Web Site http://www.irf.com
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel:(310) 252-7105
Data and specifications subject to change without notice. 12/4/2006

www.irf.com 27
Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Infineon:
IRS20124SPBF IRS20124STRPBF