d i l a luS Implementduuol

uact,, and
and toto co Pcate
the signs and the magnitudes of the numbers. Usually.
ually, an algorithCOmpat
contain a number of procedural steps which are dependenorithn
nt
previous steps. A convenient method for presenting algorithmo on
ns is a results t
The computational steps are specified in the flowchart insiddlowch flowcha
boxes. The decision steps are indicated inside diamond-shanoa
which two or more alternate paths emerge.
rectangalfroam
-shaped boxes
In this chapter we develop the various arithmetic algorithma
the procedure implementing them with digital hardware. Ne
for
addition, subtraction, multiplication, and division for the following tconsiden
data: type
1. Fixed-point binary data in signed-magnitude representation
2. Fixed-point binary data in signed-2's complement representation
3. Floating-point binary data
4. Binary-coded decimal (BCD) data

10-2 Addition and Subtraction

As stated in Sec. 3-3, there are three ways of representing negative fixed-pom
binary numbers: signed-magnitude, signed-1's complement, or signed
ation
complement. Most computers use the signed-2's complement representate
per
when performing arithmetic operations with integers. For floating-pointop
mar

ations, most computers use the signed-magnitude representation for ther

s for
tissa. In this section we develop the addition and subtraction algornth
ted
data represented in signed-magnitude and again for data represer
signed-2's complement.
It is realize that the adopted representation for neg
important to
and
beforeana
numbers refers to the representation of numbers in the registers
 SECTION 10-2 Addition and Subtraction 335
after the
execution of the arithmetic
ment arithmetic operation. It does not mean that comple
may not be used in an intermediate
step. For example, it s
convenient to employ
complement arithmetic when performingAs subtracton
a
operation with numbers in
initial minuend and signed-magnitude representation. the long
as
subtrahend, as well as the final difference, are in signea
magnitude form the fact that complements have been used in an
step does not alter the fact that the representation is in intermediate
signed-magnitude.
Addition and Subtraction with Signed-Magnitude Data
The representation of numbers in signed-magnitude is familiar because it is
used in everyday arithmetic calculations. The procedure for adding or subtract
ing two signed binary numbers with paper and pencil is simple and straight
forward. A review of this procedure will be helpful for deriving the hardware

algorithm. two numbers When the

by A and B.
We designate the magnitude of the different
we find that there are eight
signed numbers are added or subtracted,
the sign of the numbers and the opera-
conditions to consider, depending on Table 10-1.
column of
conditions are listed in the first
tion performed. These to be performed with
columns in the table show the actual operation
The other needed to prevent a negative
of the numbers. The last column is
the magnitude numbers are subtracted,
the result
magnitude words, when two equal
z e r o . In other
-0.
should be +0 not subtraction are derived from the table
algorithms for addition and should be used for
The words inside parentheses
follows (the
and c a n be stated
as
identical
the subtraction algorithm):
signs of A and B
are
when the
algorithm: of A to the result.
When
Addition (subtraction) attach the sign
addition the two magnitudes and the magnitudes and
(different), add
compare
(subtractiom) of A and B are
d i t t e r e n t (identical),

algorithm the signs

Numbers
Subtraction of Signed-Magnitude
Addition and
TABLE 10-1
Subtract Magnitudes
When A = B
Add When A < B
When A >B
Magnitudes

Operation +(A - B)
+(A +B) -(B A )
+(A B ) +(A B )
(+A) + (+B) +(B A )
-(A-B)
(+A) +(-B)
-(B A ) +(A B )
+ (+B) -(A + B) +(A B )
)
(-A) + (-B)
(+B) +(A + B) +(A B )
+(B-A)
(+A) (-B) -(A + B) -

B)
-(A
(+A) -
(-A) (+B)
(-4)-(-B)
CHAPTER TEN Computer Aritlhmetic

the larger. Choose the sign ae

subtract the smaller number from
of the sign of Aif he result t
be the same as A if A > B or the complement A
two magnitudes are subtract
equal, B from A and nake the sign of theB.f th
B.
positive. resu
The two algorithms are similar except for the sign comparicn.
procedure to be followed for identical signs in the addition algorithmhe
same as for different signs in the subtraction algorithm, and vice wthe
versa.

Hardware Implementation
To implement the two arithmetic operations with hardware, it is first necese
that the two numbers be stored in registers. LetA and B be two registersth
hold the magnitudes of the numbers, and A, and B, be two fip-tlops that hol
the corresponding signs. The result of the operation may be transíerred tba
third register: however, a saving is achieved if the result is transferred into
and A. Thus A and A, together form an accumulator register.
Consider now the hardware implementation of the algorithms above.
First, a parallel-adder is needed to perform the microoperation A + B. Second,
a comparator circuit is needed to establish if A> B, A = B, or A << B. Third,
two parallel-subtractor circuits are needed to perform the microoperations
A B and B - A. The sign relationship can be determined from anexclusive
OR gate with A, and B, as inputs.
and fwo
This procedure requires a magnitude comparator, an adder,
subtractors. However, a different procedure can be found that requires ks
equipment. First, we know that subtraction can be accomplished by meanso
and add. Second, the result of a comparison can be determined
complement
from the end carry after the subtraction. Careful investigation of the altern
tives reveals that the use of 2's complement for subtraction and comparis
an efficient procedure that requires only an adder and a complementer the

Figure 10-1 shows a block diagram of the hardware for implemen

addition and subtraction operations. It consists of registers A ana Daento
flip-flops A, and B,. Subtraction is done by adding A to the 2's compied 0
B. The output carry is transferred to flip-flop E, where it can be verlot
determine the relative magnitudes of the two numbers. The ada heA register

AVF holds the overflow bit when A and B are added. The the

flip-flop
provides other microoperations that may be needed when we sP
sequence of steps in the algorithm. (sum)

output of the adder is applied to the input of the A

The addition of A
gister. adder.
Theh The
comple
estate
dementer
oh
plus B is done through the parallel "the com
ateof

the
incr
provides an output of B or the complement of B depending on rtes and
mode control M. The complementer consists of ex exclusive-OR gates Chap 4

in
adder consists of full-adder shown in Fig. *M 0
parallel circuits as
outputo
The M signal is also applied to the input carry of the adder. viht
output of B is transferred to the adder, the input carry is 0, ar
 SECTION 10-2 Addition and Subtraction 337
B register

4VF Complementer M (Mode control)

Output
carry Parallel adder
Input carry

A register

Figure 10-1 Hardware for

signed-magnitude addition and subtraction.
the adder is
equal to the sum A + B. When M 1, the 1's =
is
applied the adder, the input carry is 1, and
to
S
of Bcomplement
plus the 2's complement of B, whichoutput
is equal to A =
A + B + 1. This
is equivalent to the subtrac-
tion A B.

Hardware Algorithm
The flowchart for the hardware
algorithm is presented in Fig. 10-2. The two
signs A, and B, are compared by an excusive-OR gate. If the output of the gate
is 0, the signs are identical; if it is 1, the
signs are different. For an add operation,
identical signs dictate that the magnitudes be added. Fora subtract operation,
different signs dictate that the magnitudes be added. The magnitudes are
added with a microoperation EA-A + B, where EA is a register that com-
bines E and A. The carry in E atter the addition constitutes an overflow if it is
equal to 1. The value of E is transferred intothe add-overflow flip-flop AVF.
The two magnitudes are subtracted if the signs are different for an add
operation or identical for a subtract operation. The magnitudes are subtracted

by adding A to the 2's complement ot B. No overtlow can occur if the numbers

are subtracted so AVF is
cleared to 0. A 1 in E indicates that A 2 B and the
If this number is zero, the sign A, must be
number in A is the correct result.
zero. A 0 in E indicates that A < B. For this
made positive to avoid a negative
of the value in A. This operation
case it is necessary
to take the 2's complement
A - A +1. However, we assume that
one microoperation
can be done with so the
for microoperations complement and increment,
COmplement
tncrement
and the A register has circuits In other
microoperations. of paths
2's complement is obtained
from
these twosame as the
of the result is the sign of A, so no change
the flowchart, the sign the sign ofthe result is the comple-
However, when A <B,
in A, is required. to complement A, to obtain
sign of A. It is then necessary
ment of the original
338 CHAPTER TEN Computer Arithmetic

Subtract operation Add operation

Minuend in A
Subtrahend in B
Augend in A
Addend in B

= 0 =1
A,DB, 0
A,®B,
A, B, A, B,
4,+B A,-
EA-A +B+1 EA A +B
AVF+0

0 AVF-E
A <B AB

#0

A-A +I|
4,+A,

END
(result is in A and
A,)
Figure 10-2 Flowchart for add and subtract operations.

the correct sign. The final in

result is found in register A and its Sig
value in AVF
provides an overflow indication. The final value ot E

Addition and Subtraction with

Complement Data Signed-2's ithanit

The signed-2's
metic algorithmscomplement
for
representation of
tog inn numbers Sec.
3-3 Th
addition and subtraction are introduced
binarynu
are
summarized here for easy reference. The. o f a Signbitisl
represents the sign bit: 0 for positive and 1 fornegative. If the resen
entire number is represented in 2's complementform. Thus +33 is rep
as 0010 SECTION 10-2 Addition and Subtraction
as 100001 and -33 as 339
00100001, and vice 11011111. Note that 011111
versa. 11011111 is the 2's complement of
The addition
of two
adding the numbers with numbers in signed-2'
compie
number. A the sign bits ned-2'ss complement form consists of
complement
carry-out of the sign-bit treated the same
same as
as the other bits of the
the otner
consists of first
taking the 2's position is discarded. The
it to the
minuend. subtractlo
complement of the subtrahend and then adu6
When two
numbers of
n digits
each are added and the sum
digits, we say that an overflow
occupiesn t 1
of two
signed-2's complement occurred.
can be detected
The effect of an overflow
numbers is discussed in Sec. 3-3. An
on the
sunm
by
the two carries areinspecting the last two carries out of the addition.overt
when the output ofapplied
to an exclusive-OR when
gate, the overflow 1s detectea
the gate is
The equal to 1.
register configuration for the
Fig. 10-3. This is the same configurationhardware implementation is shown in
as in Fig. 10-1
are not except that the sign bits
separated from the rest of the registers. We name the A
(accumulator) and the B register BR. The leftmost bit in AC and BRregister
AC

the sign bits of the numbers. The two represent

sign bits are added subtracted
with the other bits in the
or
together
complementer and parallel adder. The overflow
flip-flop V is set to 1 if there is an overflow. The output carry in this case is
discarded.
The algorithm for adding and subtracting two binary numbers in signed-
2's complement representation is shown in the flowchart of Fig. 10-4. The sum
is obtained by adding the contents of AC and BR (including their sign bits). The
overflow bit V is set to 1 if the exclusive-OR of the last two carries is 1, and it
is cleared to 0 otherwise. The subtraction operation is accomplished by adding
of BR. Taking the 2's complement of
the content of AC to the 2's complement
number to negative, and vice versa.
BR has the effect of changing positive
a
this operation because the two numbers
An overflow must be checked during
The programmer must realize that if an
added could have the
same sign.
erroneous result in the AC register.
will be an
overflow occurs, there

complement addition
and subtraction.
Figure 10-3 Hardware for signed-2's

BR register

Complementer and
parallel adder

Overflow

AC register
340 CHAPTER TEN
Computer Arithmetic
Subtract
Add

Minuend in AC
Subtrahend in BR Augend in AC
Addend in BR

AC-AC+ BR + 1
Voverflow AC-AC+ BR
V-overflow

END
END
Figure10-4 Algorithm for
complement representation. adding and
subtracting numbers in
signed-2

Comparing this algorithm with its

note that it is
are
much signed-magnitude
maintained in simpler to add and subtract counterpart.
numbers if negative
signed-2's complement
computers adopt this
over representation.
representation For this number
the more reason mo
familiar
signed-magnitude
10-3 Multiplication Algorithms
Multiplication of two
sentation is done withfixed-point binary numbers in
add paper and pencil by a
operations. This process is best
signed-magnitude
process of successive shiftrepe
illustrated with a
and
numerical example.
23 10111 Multiplicand
19 x 10011 Multiplier
10111
10111
00000 +
00000
10111
437 110110101 Product
The process consists
icant bit first. If of
the looking
at
successive
otherwise, zeros are multiplier bit is a 1, thebits of the multiplier,
ltiplier, leastsignik
ed
lines are shifted one copied down. The multiplicand is
numbers copied down copesie
position to the left from
down

numbers are added and

their sum forms the previous number.nt, r
the
the
product.
 The
sign of the SECTION 10-3
and Multiplication Algorithms 341
multiplier.
unlike, If
the sign of theyproduct
are
is
alike, determined
the the sign of from the signs of
tne ve, 1fIfItiplicand
product is negative. the product isis positive.
posinve they are are
Hardware
When Implementation
multiplication for
is
change the process implemented
add
Si gned-Magni
in
slightly. First, insteaddigital
ital
tu de
a
Data
simultaneously of computer,
nputer, it is convenient
co
it is to
convenient to many binary numbers providing registers t
it is as

numbers and provide an there are bits

adder for the assummation bi in the inlier
multiplier,
ond, instead of successively accumulate the partial of only two binary
shifted to the shifting the
multiplicand to products a regiser Sec-
in
right, which results in the left, the partial
product
multiplicand in the required relative leaving the partial 1s
bit of the positions. Third, when the product aand
tne
multiplier is 0, there is no need
since it will not alter to corresponding
add all zeros to the
its value. partial product
The hardware for
10-1 plus two more multiplication
consists of the equipment
shownA inandFigB
are shown in
registers. These registers together with registers
Fig. 10-5. The multiplier is stored in the Q register and its sign
in Qs. The
sequence counter SC is initially set to a number
of bits in the multiplier. The eounter is decremented 1equal
to the number
by after forming
eachis
partial product. When the content of the counter reaches zero, the product
formed and the process stops.
Initially, the multiplicand is in register B and the multiplier in Q. The sum
of A andB forms a partial product which is transferred to the EA register. Both
to the right. This shift will be denoted
partial product and multiplier are shifted
the shift depicted in Fig. 10-5. The
by the statement shr EAQ to designate right
10-5 Hardware for multiply operation.
Figure

Sequence counter (SCC)

B register

Complementer and
parallel adder
(rightmost bit)
On

Q register

A register
342 CHAPTER TEN Computer Arithmetic

least significant bit of A is shifted into

bit from E is shifted into the most
onificant posi
the most significant
position
significant position of A, and of Q,
0 ise the
E. After the shift, one bit of the partial product is shifted into ohiftedi
multiplier bits one position to the right. In this manner, the rig
in register Q, designated by Qn, will hold the bit of the multi rightm pushing the
ost fip-top
be inspected next. Itiplier, which m
Hardware Algorithm
Figure 10-6 is a flowchart of thehardware multiply algorithm. Initial.
multiplicand is in B and the multiplier inQ. Their corresponding signs
B, and Q, respectively. The signs
are compared, and both A and o
Figure 106 Flowchart for multiply operation.

Multiply operation

Multiplicand in B
Multiplier in Q

A,0,B,
0,-0,0B,
A0, E+0
SCn- 1

EAA+B

shr EAQ
SC+SC

0 0

END
(product is in AQ)
 SECTION
e correspond to the sign of the Multiplication Algorithms 343
10.3

stored in product since

counter SCregisters
is set to
A and
Q. Registers A double-length a
pro
be
are
assuming here number equal to the
a and E are
cleared ana encee se

unit that has that operands number of bits of tne We

t words of n bits.
are
transferred
Since an operand mustregisters
to
fro
one bit ot the word will be
of n - 1 be
occupied by the sign and the storea
eion.
bits. magnitude oconsist
wu
After the initialization, the low-order
it is a
f 1, the
multiplicand in B
bit of the multiplier in .
1S teste
If it is
a 0, is added to the present partial
nothing done. Register EAQ is then shifted once product int r
form the new
is
partial product. The sequence counter is to tri
its new value
checked. If it is not equal decremented by i arnu
to
new
partial product is formed. The processzero, the process is 0.repeatedthat
anaa
stops when SC Note the
=

partial product formed in A is shifted into one bit at a

time and eventualy
replaces the multiplier. The final product isQavailable in both A and Q, with A
holding the most
significant
bits and Q holding the least
The previous numerical example is repeated in Table 10-2 to clarify the significant bits.
hardware multiplication process. The procedure follows the steps outlined in
the flowchart.

Booth Multiplication Algorithm

Booth algorithm gives a procedure for multiplying binary integersin signed-2s
complement representation. It operates on the fact that strings of O's in the
a string of l's in the
multiplier require no addition but just shifting, and
treated as 2*1 2. For
be
multiplier from bit weight 2 to weight 2"
-

can
has a string of 1's from 2 to 2
example, the binary number 001110 (+14)

for Binary Multiplier

TABLE 10-2 Numerical Example

E A Q SC
Multiplicand B
=
10111

0 00000 10011 101

Multiplier in Q
10111
Qn =1; add B 10111
First partial product 01011 11001 100
0
Shift right EAQ 10111
On =1; add B 1 00010
Second partial product 10001 01100 011
0
Shift right EAQ 01000 10110 010
0
right EAQ 00100 01011 001
Qn= 0; shift 0
shift right EAQ 10111
On 0;
=

add B 0 11011
O. 1; 000
=

01101 10101
Fifth partial product 00
Shift right EAQ
=
0110110101

Final product in AQ
344 CHAPTER TEN Computer Arithmetic

(k 3, mn =
The number can be represented as 2*1_.
1). =
MM X 14, where M is tha- 22
+12
2 14. Therefore, the multiplication
14 the multiplier, can be done as M X 2"- M x 2. Thus th
-2=1
plicand
obtained by shifting the binary multiplicand M four
our times times product
to cany
the let
subtracting M shifted left once.
As in all multiplication schemes, Booth algorithm requires.
of the multiplier bits and shifting of the partial product. Prior to tho
the multiplicand may be added to the partial product, subtracte
partial product, or left unchanged according to the following rules

1. The multiplicand is subtracted from the partial product upon en

ing the first least significant 1 in a string of 1's in the encounter
2. The multiplicand is added to the partial product upon
multiplier.
encounterine .
first 0 (provided that there was a previous 1) in a string of 0's in
th
multiplier.
3. The partial product does not change when the multiplier bit is identi
to the previous multiplier bit.

Thealgorithm works for positive or negative multipliers in 2s come

ment representation. This is because a negative multiplier ends with a string
of 1's and the last operation will be a subtraction of the
appropriate weigh
For example, a multiplier equal to -14 is represented in 2's complement a
110010 and is treated as -2 + 22 2 = -14.
The hardware implementation of Booth the
algorithm requires regsE
configuration shown in Fig. 10-7. This is similar to Fig. 10-5 except that tnesp
bits are not separated from the rest of the
registers. To show this dittern
we rename
registers A, B, andQ, as AC, BR, and QR, respectively. Q
nates the least significant bit of the
multiplier in register QR. An extra uy
Qn+1 is appended to QR to facilitate a double bit inspection ot
The flowchart for Booth the nm
algorithm is shown in Fig. 10-8. AC and the dyr
Figure 10-7 Hardware for Booth algorithm.
BR register
Sequence counter (SC)

Complementer and
parallel adder

On

AC register
OR register
 SECTION 10.3 Multiplication Algorithms 345

Multiply

Multiplicand in BR
Multiplier in QR

AC
en+10
SC

01
10
Q,n+1

00
= 11 AC-AC+ + BR

AC AC +BR+1

ashr (AC & QR)

SCSC-1

=0
SC
#0

END

complemene

multiplication
of signed-2's
for
algorithm
Booth
10-8
Figure
numbers
 CPU Organisation
Memory Address Register (MAR): Used to provide address of of memorymemory location
where data is to be retricved or to which data is to be stored.
from
The contents of PC is modified cither aftcr fctching an instruction or by a bran
instruction. MAR and DR plays important roles in
ransier of data betwcen O
memory. In thecomputersystems which use system bus,MAR is directlyV PU andsSkithe
address bus, while DR is dircctly connected to data bus. DR is also
among scveral other registers.
used toto conne
inted
intercange data

Arithmetic Logic
Unit (ALU)

Data Procesting
Unit

Accumulator

To/from
main memory
or Input/Output
HR (AC)
Con
the
Device

Program Instruction
Counter(PC) Register TR)

Program
Control
Unit
Control
Unit

Figure 1: Basic Structure of CPU

So, we have a simple basic the
How to make this CPU whích can
perform various computational tasks
instructional style. simple structure more
In the next section powerful in terms of processing easily.
more powerful. we will
discuss how the simpleefficiency and
structure can be made

2.3 AN
ADVANCED STRUCTURE
Let us have few
made more additional features in the
powerful. Some of these simple structure of the CPU such that it
aspects are: can be
Provide additional
accumulator by a setregisters for storing
of registers. Theseoperands and addresses, thus,
registers which are registers can be used as replacing a sing
A Set of these generalmulti-purpose nature (e.g. can store either
in general purpose
of these registers is to registers may be temed as a operands
register file. One of
or
addresses
address. The IBM S/360-370the operands which are needed for calculationtheofkey funcuo
store

microprocessor, some special computers had this general memory

are address register organisation. In
so
of 8usea. registers
data An example of such case is Motorola namely index register, base regis
registers along with a 68020
microprocessor which have
Increase the capabilities of ALU matching set of 8 address
a

capabilities for performing circuits. For example, most registers.

capability with only little addition and microprocessor have
32
fixed point numbers extra
circuitry subtraction
on on fixed point numbers. naY
ThisS
numbers a also.
However cant sed for
substantial increase for
implementin multiplication and divisiono
Include special register to
Tegister which
of
circuitry needed.
is
ating arithmetic on
floating point
gives facilitate
information about conditional jumps within
various a
conditions such program.
as the A
sign ofStauus
tne sult,
i
 uon Irom

ztin or by a bra
data between nch or skip whether the result
Ris CPU and is

vecution, ofcan be used.zero,Thisarithmetic overllow, etc. in the

directdy nd the
o used to connected to execution a branch sSatus register can
instruction. checkedpreceding
be
for Lypicalinstruction Reglster Organi
erchange data lnclude special registers for
transfer of control
suborograms intcrrupis. nc such register between different subroutines
or
condition for and Micro-Oper

oram Status Word) which uscd in or

Ths PSW can record the stores program countersIBM and
360/370 series is called PSW
exccution
r a call to subroutine this PSW status of the
is storcd in
various condition flags.
program. On occurrence
when the execution of this a
specific arca in the
of
interrupt
main memory for controlling program is to be resumed. memory and is restored
Data Processing a special arca in the
transfer of Many
control. This is a computers use a stack in the
Unit main
memory and a register calledvery flexible approach. It
she top of the stack. The stack is a LIFO stack
found to be very usciul for (Last In First Out) data pointer (SP) points to
implementing structure. It has been
Provisions for execution of more than oneprogram transfcr of conurol, very efficientdy.
are not discussed at instruction
present but will be taken up for simultaneously. These provisions
discussion of Block 4 of
Considering the
requirements, let us have a more
enhanced view of the CPU.
this course.
the detailed view of the CPU.
Figure 2 give

General
Purpose Arithmetic
Logic
Register Set Unit ALU
Data
Processing
Programn
Control
Unit

Unit Buffer Register

for Data Status
Register
Data **************

Address

Control

al tasks easily. -*** *---.--

fficiency and Buffer Register Instruction
cture can be made for Address Kegister

Programn
Control
Unit

Program
Counter
hat it can be Logic for
Stack Address generation Control UnitE
Pointer
lacing a single
urpose Figure 2: CPU with general register organ1sation
raddresses.
e key function The general purpose registers can be in general 8-16. ALU performs operation on the data
of memory stored in these general purpose registers and also stores results in these registers only. There
ion. In some are few special-purpose address registers. Two of these are Program Counter (PC) and Stack
register, ec. Pointer (SP). The status register stores the key characteristics or conditions of the result of
ch have a set the last ALLU operation. A special simple arithmetic logic unit can be attached as an address
generation logic performing the simple fixed point computations. The inputs to the control
unit are from the instruction register which contains the operation code of the instruction to
r have be executed and from status register which help in generating proper control signals on
This branch operation. The system bus plays the role of communication media. Please note the
ivision on direction of arrows on address bus. There are several inermediate buffer registers also which
point help in intermediate
storage of infomation. In this organisation of CPU parallelism can be
implemented within the ALU operation or through the overlapped operations of data
processing and program control unit.
atus
the result,
 True False o f re
Ho
2.4 REGISTER ORGANISATION cha
Com
me
n the previous subsection, we have given some
CPU must have. Let hints to the types of Registers a reg
The
us take a more
internal processor general view on register organisation in moderm day exe
memory of a CPU is served by its this seCion.
among various computers is the difference in their registers. One of the key difference
large while some has smaller sets. register sets. Some computers have very Reg
set can be But on the whole, from a user's reg
classified under two basic point of view the register
categories. whE
Programmer Visible Registers: These add
registers can be used by machine or
assembly language programmers to minimize is s
the references to main
Status Control and memory. wh
Registers: These registers can not be used by the
but are used to control
the CPU or the execution of a programmers Co
Different vendors has used some program. Co
of these
stick to these definitions registers interchangeably, therefore you should not har
rigidly. Yet this
register sets of machine. Therefore, let us categorisation will help in better understanding of ovE
discuss more about these
categories. tes
2.4.1 col
Programmer Visible Registers In
These registers can be accessed using machine In
of
programmer visible registers. language. In general we encounter four types ins
General Purpose Registers On
Data Registers wh
cal
Address Registers Th
Condition Codes Registers prc
prc
The general
purpose registers are used for various
general purpose register can contain functions desired by the
2.
operand for any operation code of an operand or can be used for calculationprocessor.
of address
Atuue
towards dedicated instruction. But trends in of Fo
operations. In someregisters, today's machines show drift
for example. some in
machines there is a distinct registers may be dedicated to
registers. separation between data and floating
address
point prc
Co
(The data registers are used for
are not used for only storing intermediate Al
calculation of address of the results or data. These data registers pr
An address register may be a operand.
34 general purpose register, but some
COC
be:
are also
used in several machines.
Examples of dedicated addressdedicated address registers
registers can be
oncnts. In the
llowed by the Segment Pointer
Uscd to point out a
ithmctic
this Block. Index Register These are uscd for segment of memory. Register Organis
Suck Pointer (when index addressing scheme. and Micro-Operi

programmer visible stack

several issucs related to programmer
There arc sevcral addressing is used.)
Do we use general
visible registers. Some of the issues are
purpose registerS or dedicated register in a
Dns the number of registers machine?
efect the design of an
instruction of a
executed .sltin case of specialised
register the number of bits needed for computer?
Wed as here we need to specity
reuulisation does not allow much only few registers out of register specific details are
a set of
flexibility
tion to this problem, yet the trends are in favourto the registers. However, this
programmer.
of use of Although there is no
best
eneral ther issue related to the register set
specialised registers.
data and address regstrs to De provideddesign is the number of
general purpose
The number of registersalso or
in
ect the instruction design as he number of a micro-processor. registers
registers
in an instruction to Specity a register reference. In determines the number of bits needed
number of registers in a CPU is the range 8 to 32.general, it has been found that
optimum
then more memory reference perininstruction on an
In case
registers fall below the range
average will be needed, as some of the
intermediate result then have to be stored in the memory. On the other hand, if the number
registers go above 32, then there is no
of
However, in some appreciable reduction in memory
computers hundreds of registers are used. These references.
characterisúcs. Reduced Instruction Set Computers (RISC) exhibit systems have special
computers are discussed in Block 4 of this course. What is the this property. RISSC
importance of
having
memory references? As the time required for memory reference is more than that of a less

dern day register reference, therefore, the increased number of memory references results in slower
tion. execution of a program.

ifference Register Length: Another important characteristic related to registers is the length of a
ve very register. Nomally, the length of a register is dependen. on its use. For example, a register
register which is used to calculate address must be long enough to hold the maximum possible
address. Similarly, the length of data register should be long enough to hold the data type it
is supposed to hold. In certain cases two consecutive registers may be used to hold data
whose length is double of the register length.

ammers Condition code registers may only be partially available to the programmers. These register
contains condition codes which are also known as flags. These fags are set by the CPU
hardware while performing anoperation. For taample, an addition operation may set the
ld not overflow flag or on a division by 0 the overflow flag can be set etc. These codes may be
ng of tested by a program for a typical conditional branch operation. The condition codes are
collected in one or more registers. RISC machines have several set of conditional code bits.
In these machines an instruction specifies the set of condition codes which is to be used.
Independent sets of sondition code enable the provisions of having parallelism within the
instruction execution unit.
types
One of the key operation which is needed with the programmer uaable registers happens
when a subroutine call is issued. On a subroutine call all the registers either are saved by the
call statement itself and restored on encountering a retum statement from thesubroutne.
This operation in most machines is automatic yet in certain machines this is done by the
programmers. Similarly while writing interrupt service routine you need to save some or all
programmer usable registers.

2:4.2 Status and Control Registers

true These registers can not be used
For control of various operations several registers are used.
in data manipulations, however, the content of some of these registers
can be used by the
rift programmer. Some of the control register for a von Neumann machine
can be the Program
nt
Counter (PC), Memory Address Register (MAR) and Data Register (DR).
of which be
Almost all the CPUs, as discussed earlier, have status register, apart is calledmay
condition
be formed by condition codes
visible. Aregister which may
ers programmer or condition codes
in such a register may
COde register. Some of the commonly used flags
be: