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System Verilog

System Verilog is summarized as follows: 1. System Verilog is an extension of Verilog that supports object-oriented programming features like classes, inheritance, and polymorphism. It also supports new features like arrays, associative arrays, queues, randomization, and assertions. 2. The document outlines various data types, arrays, tasks and functions, object-oriented features, randomization, constraints, threads and more. It also describes stratified event scheduling and new features like modports, clocking blocks, and interfaces. 3. Key array types include fixed size arrays, dynamic arrays, multi-dimensional arrays, associative arrays, queues, and strings. The document provides examples and syntax for declaring

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0% found this document useful (0 votes)
392 views

System Verilog

System Verilog is summarized as follows: 1. System Verilog is an extension of Verilog that supports object-oriented programming features like classes, inheritance, and polymorphism. It also supports new features like arrays, associative arrays, queues, randomization, and assertions. 2. The document outlines various data types, arrays, tasks and functions, object-oriented features, randomization, constraints, threads and more. It also describes stratified event scheduling and new features like modports, clocking blocks, and interfaces. 3. Key array types include fixed size arrays, dynamic arrays, multi-dimensional arrays, associative arrays, queues, and strings. The document provides examples and syntax for declaring

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jagadeesh
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© © All Rights Reserved
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SYSTEM VERILOG

CONTENTS

• WHY SYSTEM VERILOG?

• DIFFERENCE B/W VERILOG & SYSTEM VERILOG

• DATA TYPES

• STRATIFIED EVENT SCHEDULER

• ARRAYS

• Fixed size Array


• Dynamic Array
• Multi Dimensional Array
• Associative Array
• Queue
• String
• Array Methods
• TASKS & FUNCTIONS

• OOPS

• Class

• Object

• Inheritance

• Polymorphism

• $Cast

• ABSTRACTION (OR) VIRTUAL CLASS

• CONSTRUCTOR - NEW() KEYWORD


• SUPER KEYWORD

• SUPER.NEW() KEYWORD

• THIS KEYWORD

• EXTERN KEYWORD

• SHALLOW COPY

• DEEP COPY

• MAILBOX

• RANDOMIZATION

• rand & randc


• CONSTRAINTS
• Distribution Constraints
• Inline Constraints
• Conditional Constraints
• Soft Constraints
• Solve Before Constraints
• THREADS (FORK_JOIN , FORK_JOIN_ANY, FORK_JOIN_NONE)
• SEMAPHORE
• MODPORTS
• CLOCKING BLOCKS , PROGRAM BLOCKS
• INPUT AND OUTPUT SKEW
• INTERFACE and VIRTUAL INTERFACE
• CODE COVERAGE
• FUNCTIONAL COVEARGE
• TB ARCHITECTURE
• ASSERTIONS (or) CHECKERS
DATA TYPES IN SYSTEM VERILOG

2-State and 4-State Data types:-


In System Verilog, there are following data types:
• 2-State data type (0,1)
• 4-State data type(0,1,X,Z)

2-state data type:-


2-state data type can have values as 0 or 1. Below are the 2-state datatypes.

bit 0,1 1-bit unsigned

byte (0-7) 8-bit Signed


Short_int (0-15) 16-bit Signed

int (0-31) 32-bit Signed

Long_int (0-63) 64-bit Signed


4-State data type:-

• 4-state data type can have values out of 0,1, X, Z.


• Below are the 4-state datatypes.

logic 1-bit

Integer 32-bit

Time 64-bit
Enum Datatype:- (list of values)
• An Enumerated data type defines a set of named values.

• Example 1: enum { red, green, blue, yellow, white }


• The actual values are defaulted to integers starting at 0 and then increase.
• So in this example by default variable will get the default value of 0,1,2,3,4.

• Example 2: enum { red=0, green, blue=4, yellow, white=10 }


• Here I have set red=0, blue=4, white=10.
• A name without a value is automatically assigned an increment of the value of the previous name.
• So green and yellow automatically assigned to the increment value of 1,5.

• NOTE:-If an automatically incremented value is assigned elsewhere in the same enumeration, this
shall be a syntax error.
• Example 3: enum { red=0, green, blue=4, yellow, white=5 }
Code of Enum:

module enums;
enum{red=0,green=1,yellow=2,blue=3,pink=4}clr; initial
begin
clr=clr.first();
$display("display the first clr=%0s",clr);
clr=clr.last();
$display("display the last clr=%0s",clr);
clr=clr.next();
$display("display the next clr=%0s",clr);
clr=clr.prev();
$display("display the prev clr=%0s",clr);
end endmodule
Typedef Data Type:-
• Typedef allows users to create their own names for type definition that they will use
frequently in their code.
• Typedefs can be very convenient when building up complicated array definitions.
• By using typedef we can define any data type.
• By using typedef we can declare outside of the module , with the help of handle we can
access inside the module.
• Syntax of typedef:
• typedef enum;
• typedef bit;
• typedef int
Code of Typedef:

typedef enum{red=0,green=1,yellow=2,blue=3,pink=4}colours;
module sv;
colours clr;
initial begin
clr=clr.first();
$display("display the first clr=%0s",clr);
clr=clr.last();
$display("display the last clr=%0s",clr);
clr=clr.next();
$display("display the next clr=%0s",clr);
clr=clr.prev();
$display("display the prev clr=%0s",clr);
end
endmodule
Struct Data Types:- static
• Collection of variables of different data types.
• It is fixed data type.
• Memory allocations can be done at compilation time.
Sample code of Struct:
module sv;
struct packed{ int addr;
bit data;
byte arun; }pkt;
initial
begin
pkt='{1,2,3};
$display("pkt=%0d",pkt);
$display("addr=%0d,data=%0d,arun=%0d",pkt.addr,pkt.data,pkt.arun); end
endmodule
DATA SIGNED/U SIZE STATE COMPATIBILITY SYNTAX
TYPES NSIGNED (IN
BITS
)
reg Unsigned 1 4 SV/V Reg <variable_name>;
wire Unsigned 1 4 SV/V Wire <variable_name>;
logic Unsigned 1 4 SV Logic <variable_name>;
integer Signed 32 4 SV/V Integer <variable_name>;
real Signed 64 4 SV/V real <variable_name>;
realtime Unsigned 64 4 SV/V realtime <variable_name>;
time Unsigned 64 4 SV/V time <variable_name>;
int Signed 32 2 SV Int <variable_name>;
bit Unsigned 1 2 SV bit <variable_name>;
byte signed 8 2 SV byte <variable_name>;
shortint Signed 16 2 S shortint <variable_name>;
longint Signed 64 2 SV longint <variable_name>;
STRATIFIED EVENT QUEUE
Detailed:
Stratified event scheduler:
System Verilog (ARRAYS)
SYSTEM VERILOG - ARRAYS

ARRAYS:
An array is collection of variables of same type, and accessed using the
same name plus one or more indices.

Types of Arrays :
• Fixed Size Arrays
• Packed and Un-packed Arrays
• Dynamic Array
• Associative Array
• Queues
• String

Note: We have some array methods also.

int array1 [6];            //fixed size single dimension array


int array2 [5:0];          //fixed size single dimension array
int array3 [3:0][2:0];     //fixed size multi dimension array
bit [7:0] array4[2:0];     //unpacked array declaration
bit [2:0][7:0] array5;     //packed array declaration
bit [2:0][7:0] array6 [3]; //mixed packed and unpacked array
In system Verilog we have following type arrays:-

• Fixed Size Array:


In fixed size array, array size will be constant throughout the simulation, Once the
array is declared no need to create it. By default, the array will be initialized with value ‘0’.
• Single dimensional array
Syntax : int array1 [6]; int
array2 [5:0];
• Multidimensional array are also known as an array of arrays.

Two dimensional array


Syntax : int arr [2][3];
This array has total 2*3=6 elements.

Three dimensional array:


Syntax : int array1 [2:0][3:0]; 12 elements
array assignment

array1 = '{0,1,2,3,4,5};

array2 = '{0,1,2,3,4,5};

array3 = '{ '{0,1,2,3},'{4,5,6,7},'{8,9,10,11}};

Fixed Size Array Example


This example shows array declaration and array manipulation using for and foreach loop.
module fixedsize_array;

  //declaration of array’s

int array1[6];               //single dimension array

  int array2[5:0];             //single dimension array

  int array3[2:0][3:0];        //multi dimension array

  int array4[4:0];

  initial begin

    //array initialization

    array1 = '{0,1,2,3,4,5};

    array2 = '{0,1,2,3,4,5};
    array3 = '{'{0,1,2,3},'{4,5,6,7},'{8,9,10,11}};

    //displaying array elements

    $display("-------displaying array1-------");

    foreach(array1[i]) $display("\t array1[%0d] = %0d",i,array1[i]);

    $display("-------displaying array2-------");

    for(int i=0;i<6;i++) $display("\t array2[%0d] = %0d",i,array2[i]);

    $display("-------displaying array3-------");

    foreach(array3[i,j]) $display("\t array3[%0d][%0d] = %0d",i,j,array3[i]


[j]);
    $display("-------displaying uninitialized array4-------");

    for(int i=0;i<5;i++) $display("\t array4[%0d] = %0d",i,array4[i]);

  end

endmodule

Simulator Output:

-------displaying array1-------
array1[0] = 0
array1[1] = 1
array1[2] = 2
array1[3] = 3
array1[4] = 4
array1[5] = 5
-------displaying array2-------
array2[0] = 5
array2[1] = 4
array2[2] = 3
array2[3] = 2
array2[4] = 1
array2[5] = 0
-------displaying array3-------
array3[2][3] = 0
array3[2][2] = 1
array3[2][1] = 2
array3[2][0] = 3
array3[1][3] = 4
array3[1][2] = 5
array3[1][1] = 6
array3[1][0] = 7
array3[0][3] = 8
array3[0][2] = 9
array3[0][1] = 10
array3[0][0] = 11
-------displaying uninitialized array4-------
array4[0] = 0
array4[1] = 0
array4[2] = 0
array4[3] = 0
array4[4] = 0
Packed and Unpacked Arrays:

The term packed array is used to refer to the dimensions declared before the data identifier name

The term unpacked array is used to refer to the dimensions declared after the data identifier name

bit [7:0] temp_var; // packed array of bit types

bit temp_var [7:0]; // unpacked array of real types

Packed array:-
• Packed arrays can be of single bit data types like reg, logic, bit.
• Dimensions declared before the data identifier name.
Syntax: logic[15:0] arr;
• Packed arrays are fixed sized , single or multidimensional array.
• Packed array is guaranteed to be represented as a contiguous set of bits.
• Syntax : bit [2:0][7:0] array1;
• The below example shows storing packed array as a contiguous set of bits.
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

UnPacked array

Unpacked arrays can be of any data type.


Unpacked arrays shall be declared by specifying the element ranges after the identifier name.
An unpacked array may or may not be so represented as a contiguous set of bits.

Example bit [7:0] array4[2:0];


Dynamic Array :

• A dynamic array is unpacked array whose size can be set or changed at runtime.
• During the runtime we can increase size and decrease the size.
• Dynamic array can be represented as [ ]; Syntax :
int array_1 [ ];
• Array creation : array_1 = new [10];

• data_type array_name [ ];

• data_type is the data type of the array elements.


• Methods : new[ ]    –> allocates the storage.
size( )    –> returns the current size of a dynamic array.
delete( ) –> empties the array, resulting in a zero-sized array.

//declaration
bit [7:0] d_array1[ ];

int d_array2[ ];

//memory allocation

d_array1 = new[4]; //dynamic array of 4 elements

d_array2 = new[6]; //dynamic array of 6 elements

//array initialization

d_array1 = {0,1,2,3};

foreach(d_array2[j]) d_array2[j] = j;
//Change the length of the array after declaration/initialization

d_array1 = new[10]; //dynamic array of 10 elements

In the above syntax, d_array1 will get allotted with 10 new memory locations and old values of d_array1 will get deleted. old values of d_array1
elements can be retained by extending the current array by using the below syntax.

//Allocate 6 new elements and retain values of 4 elements.

d_array1 = new[10](d_array1);

c
//delete array

d_array1.delete;

array_name.delete() method will delete the array.

Dynamic Array Declaration, Allocation and Initialization.

module dynamic_array;

//dynamic array declaration

bit [7:0] d_array1[];

int d_array2[];

initial begin

$display("Before Memory Allocation");


$display("\tSize of d_array1 %0d",d_array1.size());

$display("\tSize of d_array2 %0d",d_array2.size());

//memory allocation

d_array1 = new[4];

d_array2 = new[6];

$display("After Memory Allocation");

$display("\tSize of d_array1 %0d",d_array1.size());

$display("\tSize of d_array2 %0d",d_array2.size());

//array initialization
d_array1 = {0,1,2,3};

foreach(d_array2[j]) d_array2[j] = j;

$display("--- d_array1 Values are ---");

foreach(d_array1[i]) $display("\td_aaray1[%0d] = %0d",i, d_array1[i]);

$display("---------------------------------");

$display("--- d_array2 Values are ---");

foreach(d_array2[i]) $display("\td_aaray2[%0d] = %0d",i, d_array2[i]);

$display("---------------------------------");

end
endmodule

Simulator Output:

Before Memory Allocation

Size of d_array1 0

Size of d_array2 0

After Memory Allocation

Size of d_array1 4

Size of d_array2 6

--- d_array1 Values are ---

d_aaray1[0] = 0

d_aaray1[1] = 1
d_aaray1[2] = 2

d_aaray1[3] = 3

---------------------------------

--- d_array2 Values are ---

d_aaray2[0] = 0

d_aaray2[1] = 1

d_aaray2[2] = 2

d_aaray2[3] = 3

d_aaray2[4] = 4

d_aaray2[5] = 5

---------------------------------

Dynamic Array delete method


module dynamic_array;

//dynamic array declaration

bit [7:0] d_array1[];

int d_array2[];

initial begin

//memory allocation

d_array1 = new[2];

d_array2 = new[3];

//array initialization
d_array1 = {2,3};

foreach(d_array2[j]) d_array2[j] = j;

$display("--- d_array1 Values are ---");

foreach(d_array1[i]) $display("\td_aaray1[%0d] = %0d",i, d_array1[i]);

$display("---------------------------------");

$display("--- d_array2 Values are ---");

foreach(d_array2[i]) $display("\td_aaray2[%0d] = %0d",i, d_array2[i]);

$display("---------------------------------");

//delete array
d_array1.delete;

d_array2.delete;

$display("After Array Delete");

$display("\tSize of d_array1 %0d",d_array1.size());

$display("\tSize of d_array2 %0d",d_array2.size());

end

endmodule

Simulator Output:

--- d_array1 Values are ---

d_aaray1[0] = 2
d_aaray1[1] = 3

---------------------------------

--- d_array2 Values are ---

d_aaray2[0] = 0

d_aaray2[1] = 1

d_aaray2[2] = 2

---------------------------------

After Array Delete

Size of d_array1 0

Size of d_array2 0

The below example shows the increasing dynamic array size by overriding and retaining old values.
module dynamic_array;

//dynamic array declaration

bit [7:0] d_array1[];

int d_array2[];

initial begin

//memory allocation

d_array1 = new[2];

d_array2 = new[3];

//array initialization
d_array1 = {2,3};

foreach(d_array2[j]) d_array2[j] = j;

$display("----- d_array1 Values are -----");

foreach(d_array1[i]) $display("\td_aaray1[%0d] = %0d",i, d_array1[i]);

$display("----- d_array2 Values are -----");

foreach(d_array2[i]) $display("\td_aaray2[%0d] = %0d",i, d_array2[i]);

//Increasing the size by overriding the old values

d_array1 = new[4]; //Create dynamic array of 4 elements

$display("Size of Array d_array1 %0d",d_array1.size());


$display("----- d_array1 Values are -----");

foreach(d_array1[i]) $display("\td_aaray1[%0d] = %0d",i, d_array1[i]);

//Increasing the size by retaining the old values

d_array2 = new[5](d_array2); //Create dynamic array of 5 elements, retaining old values

$display("Size of Array d_array2 %0d",d_array2.size());

$display("----- d_array2 Values are -----");

foreach(d_array2[i]) $display("\td_aaray2[%0d] = %0d",i, d_array2[i]);

end

endmodule

Simulator Output:
----- d_array1 Values are -----

d_aaray1[0] = 2

d_aaray1[1] = 3

----- d_array2 Values are -----

d_aaray2[0] = 0

d_aaray2[1] = 1

d_aaray2[2] = 2

Size of Array d_array1 4

----- d_array1 Values are -----

d_aaray1[0] = 0

d_aaray1[1] = 0

d_aaray1[2] = 0
d_aaray1[3] = 0

Size of Array d_array2 5

----- d_array2 Values are -----

d_aaray2[0] = 0

d_aaray2[1] = 1

d_aaray2[2] = 2

d_aaray2[3] = 0

d_aaray2[4] = 0
Sample code for Dynamic array:

module sv;
int array_1[];
initial
begin
$display("display the size of the array_1=%0d",array_1.size());
array_1=new[10];
$display("display the size of the array_1=%0d",array_1.size());
array_1=new[50](array_1);
$display("display the size of the array_1=%0d",array_1.size());
array_1.delete();
$display("display the size of the array_1=%0d",array_1.size());
end
endmodule
Unpacked Array:-

• Unpacked arrays can be of any data type.


• Unpacked arrays shall be declared by specifying the element ranges after the identifier
name.
• An unpacked array may or may not be so presented as a contiguous set of bits.
• Syntax : bit array2[2:0];

• Below diagram shows storing unpacked array as a non-contiguous set of bits.

7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Associative Array:-

• Associative array has non-continuous elements.


• Associative array can be represented as [*] , * indicates index values.
• Index values can be either integers(1,2,3) or strings(a,b,c).
• For large memory storing we are using associative array.
• Associative arrays allocate the storage only when it is used, unless like in the dynamic array we need to allocate
memory before using it.
• When the size of a collection is unknown or the data space is sparse, an associative array is a better option.
• Dynamic arrays are useful for contiguous collections of variables whose number changes dynamically.

Syntax:
int array_1[*] //associative array of integer (unspecified index).
Array Declaration

data_type array_name [ index_type ];

where:
data_type – data type of the array elements.
array_name – name of the associative array.
index_type – data-type to be used as an index, or *.
* indicates the array is indexed by any integral expression of arbitrary size.

int a_array1[*] ;            // associative array of integer (unspecified index)


bit [31:0] a_array2[string]; // associative array of 32-bit, indexed by string
ev_array [myClass];          //associative array of event,indexed by class
Associative array methods are:-

• num(), returns the number of entries in the associative array


• first(var), assigns the value of first index to the variable var
• last(var), assigns the value of last index to the variable var
• next(var), assigns the value of next index to the variable var
• perv(var), assigns the value of previous index to the variable var
• delete(index), removes the entry at the specified index.exa_array.delete(index)
• exists(index) returns 1 if an element exists at the specified index else returns 0

Example-1 : Associative Array Declaration, num(), first() and last() method’s.


module associative_array;
//array declaration
int a_array[*];
int index;
initial begin
//allocating array and assigning value to it
repeat(3) begin
a_array[index] = index*2;
index=index+4;
end

//num() –Associative array method


$display("\tNumber of entries in a_array is %0d",a_array.num());
$display("--- Associative array a_array entries and Values are ---");
foreach(a_array[i]) $display("\ta_array[%0d] \t = %0d",i,a_array[i]);
$display("--------------------------------------------------------");

//first()-Associative array method


a_array.first(index);
$display("\First entry is \t a_array[%0d] = %0d",index,a_array[index]);

//last()-Associative array method


a_array.last(index);
$display("\Last entry is \t a_array[%0d] = %0d",index,a_array[index]);
end
endmodule
Simulator Output:
Number of entries in a_array is 3
--- Associative array a_array entries and Values are ---
a_array[0] = 0
a_array[4] = 8
a_array[8] = 16
--------------------------------------------------------
First entry is a_array[0] = 0
Last entry is a_array[8] = 16

exists(), prev() and last() method’s


Example-2 : Associative Array – exists(), prev() and last() method’s.
module associative_array;
//array declaration
int a_array[*];
int index;

initial begin
//allocating array and assigning value to it
repeat(3) begin
a_array[index] = index*2;
index=index+4;
end
//exists()-Associative array method
if(a_array.exists(8))
$display("Index 8 exists in a_array");
else
$display("Index 8 doesnt exists in a_array");

//last()-Associative array method


a_array.last(index);
$display("Last entry is a_array[%0d] = %0d",index,a_array[index]);

//prev()-Associative array method


a_array.prev(index);
$display("entry is a_array[%0d] = %0d",index,a_array[index]);

//next()-Associative array method


a_array.next(index);
$display("entry is a_array[%0d] = %0d",index,a_array[index]);
end
endmodule
Simulator Output:
Index 8 exists in a_array
Last entry is a_array[8] = 16
entry is a_array[4] = 8
entry is a_array[8] = 16
bit and string index type
Example-3: Associative Array – bit and string index type.
module associative_array;
//array declaration
int a_array1[bit [7:0]]; //index type is bit [7:0] and entry type is int
bit a_array2[string] ; //index type is string and entry type is bit

initial begin
//allocating array and assigning value to it
a_array1[5] = 10;
a_array1[8] = 20;

a_array2["GOOD_PKT"] = 1;
a_array2["BAD_PKT"] = 0;

foreach(a_array1[index])
$display("a_array1[%0d] = %0d",index,a_array1[index]);
foreach(a_array2[index])
$display("a_array2[%0s] = %0d",index,a_array2[index]);
end
endmodule
Simulator Output:
a_array1[5] = 10
a_array1[8] = 20
a_array2[BAD_PKT] = 0
a_array2[GOOD_PKT] = 1

Deleting complete Assoc Array


Example-4: Deleting complete Associative Array
Calling array.delete() method will delete the complete array, which leads to the deletion of all the entries of an array.
module associative_array;
//array declaration
int a_array[*];
int index;

initial begin
//allocating array and assigning value to it
repeat(3) begin
a_array[index] = index*2;
index=index+4;
end

$display("[Before-Delete] Associative array size is %0d",a_array.size());


a_array.delete();
$display("[After -Delete] Associative array size is %0d",a_array.size());
end
endmodule
Simulator Output:
[Before-Delete] Associative array size is 3
[After -Delete] Associative array size is 0
code of Associative array using(int):
module assoc;
$display("display the first index array_1=%0d",index,array_1[index]);
int array_1[*];
array_1.last(index);
int index;
$display("display the last index array_1=%0d",index,array_1[index]);
initial
array_1.prev(index);
begin
$display("display the prev index array_1=%0d",index,array_1[index]);
$display("number of entries array_1=%0d",array_1.num());
array_1.next(index);
array_1[1]=500;
array_1[2]=700; $display("display the next index array_1=%0d",index,array_1[index]);

array_1[3]=300; if(array_1.exists(2))

array_1[4]=200; $display("index 2 is exists in array_1");


array_1[5]=900; else
array_1[6]=1000; $display("index 2 is not exists in array_1");
$display("number of entries array_1=%0d",array_1.num()); if (array_1.exists(7))
foreach(array_1[i]) $display("index 7 is exists in array_1");
$display("number of entries array_1[%0s]=%0d",i,array_1[i]); else
array_1.first(index);
$display("index 7 is not exists in array_1");
end
endmodule
code of Associative array using(string):

module assoc; array_1.first(index);


int array_1[*]; $display("display the first index array_1=%0d",index,array_1[index]);
int index; array_1.last(index);
initial $display("display the last index array_1=%0d",index,array_1[index]);
begin array_1.prev(index);
$display("number of entries array_1=%0d",array_1.num()); $display("display the prev index array_1=%0d",index,array_1[index]);
array_1["A"]=500; if(array_1.exists(2))
array_1["B"]=700; $display("index 2 is exists in array_1");
array_1["C"]=300; else
array_1["D"]=200; $display("index 2 is not exists in array_1");
array_1["C"]=900; if(array_1.exists(7))
array_1["E"]=1000; $display("index 7 is exists in array_1");
$display("number of entries array_1=%0d",array_1.num()); else
foreach(array_1[i]) $display("index 7 is not exists in array_1");
$display("number of entries array_1[%0s]=%0d",i,array_1[i]); end
endmodule
Queues:-
• Queues can be represented as $.
• In queue 0 represents the first, and $ representing the last entries.
• Queue supports adding and removing elements anywhere.
A queue is a variable-size, ordered collection of homogeneous elements.

• like a dynamic array, queues can grow and shrink


• Queues are declared using the same syntax as unpacked arrays, but specifying $ as the array size. In queue 0 represents the
first, and $ representing the last entries.
• Queue has flexible memory.
• Queue has variable sizing.
• Queue has 2 types:
Bounded ---- If size is mentioned.
Unbounded ---- If size is not mentioned.
• Syntax:
• int queue_1 [$];
• example:-
• int queue_1[$]; //queue of bits (Unbounded queue)
• byte queue2[$:255]; //queue of byte (bounded queue with 256 entries)
Queue Declaration
data_type queue_name[$];
where:
data_type     – data type of the queue elements.
queue_name – name of the queue.
Queue Declaration Example
bit queue_1[$]; // queue of bits (unbound queue)
int queue_2[$]; // queue of int
byte queue_3[$:255]; // queue of byte (bounded queue with 256 entries)
string queue_4[$]; // queue of strings

Queue Initialization
queue_1 = {0,1,2,3};
queue_4 = {“Red”,"Blue”,"Green”};
Unbounded Queue

SystemVerilog queue
Bounded Queue

SystemVerilog Bounded queue


Queue Methods:-

• size() returns the number of items in the queue


• insert() inserts the given item at the specified index position
• delete() deletes the item at the specified index position
• push_front() inserts the given element at the front of the queue
• push_back() inserts the given element at the end of the queue
• pop_front() removes and returns the first element of the queue
• pop_back() removes and returns the last element of the queue
Unbounded Queue Declaration, Initialization, Size, Insert and Delete Method
This example shows the declaration and usage Queue methods.
module queues_array;
//declaration
bit [31:0] queue_1[$]; //unbounded queue
string queue_2[$];
initial begin
//Queue Initialization:
queue_1 = {0,1,2,3};
queue_2 = {"Red","Blue","Green"};
//Size-Method
$display("----- Queue_1 size is %0d -----",queue_1.size());
foreach(queue_1[i]) $display("\tqueue_1[%0d] = %0d",i,queue_1[i]);
$display("----- Queue_2 size is %0d -----",queue_2.size());
foreach(queue_2[i]) $display("\tqueue_2[%0d] = %0s",i,queue_2[i]);
//Insert-Method
queue_2.insert(1,"Orange");
$display("----- Queue_2 size after inserting Orange is %0d -----",queue_2.size());
foreach(queue_2[i]) $display("\tqueue_2[%0d] = %0s",i,queue_2[i]);
//Delete Method
queue_2.delete(3);
$display("----- Queue_2 size after Delete is %0d -----",queue_2.size());
foreach(queue_2[i])$display("\tqueue_2[%0d] = %0s",i,queue_2[i]);
end

endmodule
Simulator Output:
----- Queue_1 size is 4 -----
queue_1[0] = 0
queue_1[1] = 1
queue_1[2] = 2
queue_1[3] = 3
----- Queue_2 size is 3 -----
queue_2[0] = Red
queue_2[1] = Blue
queue_2[2] = Green
----- Queue_2 size after inserting Orange is 4 -----
queue_2[0] = Red
queue_2[1] = Orange
queue_2[2] = Blue
queue_2[3] = Green
----- Queue_2 size after Delete is 3 -----
queue_2[0] = Red
queue_2[1] = Orange
queue_2[2] = Blue

example ;
module queues_array;
//declaration
bit [31:0] queue_1[$];
int lvar;
initial begin
//Queue Initialization:
queue_1 = {0,1,2,3};
//Size-Method
$display("\tQueue_1 size is %0d",queue_1.size());
//Push_front Method
queue_1.push_front(22);
$display("\tQueue_1 size after push_front is %0d",queue_1.size());
//Push_back Method
queue_1.push_back(44);
$display("\tQueue_1 size after push_back is %0d",queue_1.size());

//Pop_front Method
lvar = queue_1.pop_front();
$display("\tQueue_1 pop_front value is %0d",lvar);

//Pop_back Method
lvar = queue_1.pop_back();
$display("\tQueue_1 pop_back value is %0d",lvar);
end
endmodule
Simulator Output:
Queue_1 size is 4
Queue_1 size after push_front is 5
Queue_1 size after push_back is 6
Queue_1 pop_front value is 22
Queue_1 pop_back value is 44

Bounded queue declaration and accessing


The number of entries of the bounded queue is limited, push_back to the bounded queue (after the queue full condition) will not impact any
changes to the queue.  push_front to the bounded queue (after the queue full condition) will delete the last entry from queue and stores a new entry
in the 0th index of the queue.

module queues_array;
//declaration
int queue[$:2];
int index;
int temp_var;
initial begin
//Queue Initialization:
queue = {7,3,1};
$display("Queue elements are,");
$display("\tqueue = %p",queue);
queue.push_back(10);
$display("After push_back Queue elements are,");
$display("\tqueue = %p",queue);
queue.push_front(10);
$display("After push_front Queue elements are,");
$display("\tqueue = %p",queue);
end
endmodule
Simulator Output:
Queue elements are,
queue = '{7, 3, 1}
After push_back Queue elements are,
queue = '{7, 3, 1}
After push_front Queue elements are,
queue = '{10, 7, 3}

Accessing random element of queue


In the below example, random queue entry will be accessed by using index. Unlike pop_front/pop_back option queue entry will not get deleted on
accessing with an index of the queue.
module queues_array;
//declaration
int queue[$];
int index;
int temp_var;
initial begin
//Queue Initialization:
queue = {7,3,1,0,8};
$display("----- Queue elements with index -----");
foreach(queue[i])
$display("\tqueue[%0d] = %0d",i,queue[i]);
$display("-------------------------------------\n");
$display("Before Queue size is %0d",queue.size());
repeat(2) begin //{
index = $urandom_range(0,4); //index of queue is from 0 to 4
temp_var = queue[index];
$display("Value of Index %0d in Queue is %0d",index,temp_var);
end //}
$display("After Queue size is %0d",queue.size());
end
endmodule
Simulator Output:
----- Queue elements with index -----
queue[0] = 7
queue[1] = 3
queue[2] = 1
queue[3] = 0
queue[4] = 8
-------------------------------------
Before Queue size is 5
Value of Index 3 in Queue is 0
Value of Index 0 in Queue is 7
After Queue size is 5

Deleting random element of queue with index


Calling queue.delete(index) method will delete the entry stored with ‘index’.
module queues;
//declaration
int queue[$];
int index;
int temp_var;
initial begin
//Queue Initialization:
queue = {7,3,1,0,8};
$display("Queue entries are %p",queue);
$display("Before Queue size is %0d",queue.size());
index = $urandom_range(0,4); //index of queue is from 0 to 4
$display("Index %0d is deleted",index);
queue.delete(index);
$display("After Queue size is %0d",queue.size());
$display("Queue entries are %p",queue);
$display("\nQueue entries are %p",queue);
$display("Before Queue size is %0d",queue.size());
index = $urandom_range(0,3); //index of queue is from 0 to 4
$display("Index %0d is deleted",index);
queue.delete(index);
$display("After Queue size is %0d",queue.size());
$display("Queue entries are %p",queue);
end
endmodule
Simulator Output:
Queue entries are '{7, 3, 1, 0, 8}
Before Queue size is 5
Index 3 is deleted
After Queue size is 4
Queue entries are '{7, 3, 1, 8}

Queue entries are '{7, 3, 1, 8}


Before Queue size is 4
Index 0 is deleted
After Queue size is 3
Queue entries are '{3, 1, 8}

Deleting complete queue


Calling queue.delete() method will delete the complete queue, which leads to the deletion of all the entries of the queue.
module qu_delete;
//queue declaration
int qu[$];
initial begin

qu.push_back(2);
qu.push_back(13);
qu.push_back(5);
qu.push_back(65);
$display("[Before-Delete] Queue size is %0d",qu.size());
qu.delete();
$display("[After -Delete] Queue size is %0d",qu.size());
end
endmodule
Simulator Output:
[Before-Delete] Queue size is 4
[After -Delete] Queue size is 0
code of queue:
queue_1.pop_back();
module sv; $display("size of the queue(pop_back) is
int queue_1[$]; queue_1=%0d",queue_1.size());
initial
begin
$display("size of the queue is queue_1=%0d",queue_1.size()); queue_1=%0d",queue_1.size());
queue_1= {1,2,3,4,5,7,8,10};
foreach(queue_1[i])

$display("size of the queue(size) is


queue_1[%0d]=%0d",i,queue_1[i]);
queue_1.push_front(100);
$display("size of the queue(push_front) is
queue_1=%0d",queue_1.size());
queue_1.push_back(200);
$display("size of the queue(push_back) is
queue_1=%0d",queue_1.size());
queue_1.pop_front();
$display("size of the queue(pop_front) is
queue_1.insert(1,766);
$display("size of the queue(insert) is
queue_1=%0d",queue_1.size());

foreach(queue_1[i])
$display("size of the queue(size after all methods)
is queue_1[%0d]=%0d",i,queue_1[i]);

queue_1.delete();
$display("size of the queue(delete) is
queue_1=%0d",queue_1.size());
end endmodule
STRING :

• String is a group of characters.


• String should be with in the double quotes(“”).
• We can put & get characters in the string. Syntax:
String s1 = “SemiConducTors”;
• String Methods:
tolower()
toupper() putc()
getc()
substr()
len()
STRING code:

module sv; $display("display the s2=%0s",s2.toupper());


string s1="semiconductors"; $display("display the s1=%0s",s1.getc(5));
string s2="samsung"; $display("display the s2=%0s",s2.getc(6));
initial $display("display the s1=%0d",s1.len());
begin $display("display the s2=%0d",s2.len());
$display("display the s1=%0s",s1); s1.putc(1,"A");
$display("display the s2=%0s",s2); $display("display the s1=%0s",s1);
$display("display the s2=%0s",s1.tolower()); end endmodule
$display("display the s2=%0s",s1.toupper());
$display("display the s2=%0s",s2.tolower());
System Verilog (OOPS)
OOPS Terminology

• OOPS(Object Oriented Programming).


• Class – It is used for creating variables & methods.
• Object – an instance of a class is known as object.
• Handle – a pointer to an object.
• Class is user defined data type. That can be used to encapsulate data(property) and
tasks/functions(methods) which operate on the data.

Syntax :
class driver ;
…..
endclass
Object Creation :
Syntax for Object Creation:

Ex1: packet pkt1; <= creating handle


pkt1=new(); (or)
packet pkt1= new(); <= creating handle and object

this Keyword:
• this keyword shows the local and global variable difference.
• Local variable means inside the module,
• Global variable means outside the module.
• By using this keyword we can access outside module variables.
INHERITANCE

Child class can access the parent class properties with the help of child class handle.
Child class inherits all the properties and methods of parent class by using child class handle.

Code Of Inheritance:
module sv;
class parent; parent p;
int addr; int child c;
data; initial
function void display(); begin
$display ("i am in parent "); c=new();
endfunction c.display();
endclass c.addr=20;
c.data=90;
class child extends parent; c.data1=100;
int data1; c.addr1=200;
int addr1;
function void display(); $display("addr=%0d,data=%0d,data1=%0d,addr1=
$display("i am in child"); %0d",c.addr,c.data,c.data1,c.addr1); end
endfunction endmodule
endclass
Super keyword:

• By using super keyword we can access parent class properties.


• With in the function we are using super keyword.

Code of Super keyword:


module sv;
• class parent;
parent p;
virtual function void display();
child c;
$display ("i am in parent ");
initial
endfunction
begin
endclass
p=new();
c=new();
class child extends parent;
p=c;
function void display();
c.display();
$display("i am in child");
end
super.display(); endfunction
endmodule
endclass
POLYMORPHISM:

• Poly means many and morphism means changes.


• In Polymorphism, parent class properties are assigned to child class.
• We assign parent = child.
• When ever we are assigning parent = child, it show child class properties.
• While parent = child , parent class must contain virtual methods.
• Using super keyword in child class we can access the parent class properties.
• Disadvantage of Polymorphism is we cannot assign child class properties to parent class.
• Using $cast, we can assign child class properties to the parent class.
Code of Polymorphism:

class parent; module polymorphism;


virtual function void display(); parent p;
$display ("i am in parent "); child c;
endfunction initial
endclass begin
p=new();
class child extends parent;
c=new(); p=c;
function void display();
c.display();
$display("i am in child");
end
endfunction
endmodule
endclass
$cast:
In polymorphism we are assigning parent = child but there is no possibility to assign child=parent, but by using $cast we can
perform child = parent also which is illegal.

class parent; module polymorphism;

virtual function void display(); initial

$display ("i am in parent "); begin

endfunction parent p = new();


child c = new();
endclass
child c_1;

class child extends parent; p=c;

function void display(); $cast (c_1,p);


super.display(); c_1.display();
end
$display("i am in child");
endmodule
endfunction
endclass
Abstract Class:

• A class is called abstract class if virtual keyword is used before a class.


• An abstract class cannot be instantiated, it can only be derived and can be used in
module inside initial begin block.
• Without deriving if we use abstract class directly in to module initial begin block, it
will give compilation error.

• Syntax :
virtual class parent;
Code of Abstract class:

virtual class parent; function


void display();
$display("Iam in parent");
endfunction
endclass

class child extends parent;


endclass
module sv;
parent p;
child c;
initial
begin
c=new();
c.display();
end
endmodule
Shallow Copy:

• Only properties parent class are copied , but not object of subclass.
• Shallow copy creates a separate memory only for the properties of the class but not the subclass object.

class packet; pkt_2.addr=20;


bit [31:0]addr,data1,data2; pkt_2.data1=30;
task display_name(); pkt_2.data2=50;
$display($time,"addr=%0d, data1=%0d, data2=%0d",addr,data1,data2); endtask pkt_1.display_name();
endclass packet pkt_2.display_name();
pkt_1; packet pkt_1.addr=10;
pkt_2; initial pkt_1.data1=20;
begin pkt_1.data2=30; pkt_2 =
pkt_1=new(); pkt_1;
pkt_1.display_name(); pkt_2.display_name();
//pkt_2.display_name(); pkt_1.display_name();
end
endmodule
Deep Copy:

• Both Data & Objects of parent class are copied.


• .copy() method is used to perform deep_copy.
pt1=new();
class simple;
pt2=new();
int a,b;
pt2=pt1.copy();
function simple copy();
$display("a=%d,b=%d",pt1.a,pt1.b);
copy=new(); copy.a=2;
$display("a=%d,b=%d",pt2.a,pt2.b);
copy.b=4;
pt1.a=5;
endfunction
pt1.b=7;
endclass module
$display("a=%d,b=%d",pt1.a,pt1.b);
main(); simple
pt1,pt2; $display("a=%d,b=%d",pt2.a,pt2.b);
end
initial begin
endmodule
Randomization:

• System Verilog randomization provides a built-in method randomize. The randomize() method generates random
values for all the active random variables of an object.

• Variables declared with the rand keyword will get random values on the object.randomize()
method call.

• On calling randomize(), pre_randomize() and post_randomize() functions will get called


before and after the randomize call respectively.

• Users can override the pre_randomize() and post_randomize() functions.


• If we declare a rand method i.e., rand &randc we need to use .randomize() method also.
rand and randc

• rand : In the declared list of values , when we use rand keyword , it generates repeated values.

• randc: random cyclic it means values are not repeated until one cycle completes.

• Value will repeated only after all the values have been assigned at least once.
• constraint_modes:
• Constraint_mode(1) --- It will enable the constraint.
• Constraint_mode(0) --- It will disable the constraint.

• rand_modes:
• rand_mode(1) ----- It will enable the randomization.
• rand_mode(0) ----- It will disable the randomization.
Code of Randomization:

class parent; rand


bit[7:0] a;
endclass
module sv;
parent p;
initial begin
p=new();
repeat(10)
begin
p.randomize();
$display("a=%0d",p.a);
end
end
endmodule
Constraints

• Constraints are declared with in the class.


• In class after randomization only, constraints are possible.
• Constraints are limited to particular value.
• Control the values getting assigned on randomization, this can be achieved by writing constraints.

Syntax :
constraint constraint_name{a=5;}
Types of Constraints:

• Inline constraint

• Inside constraint

• Distributional constraint

• Conditional constraints

• Solve before constraint

• Soft constraint
• inline constraints: used to introduce an additional constraint represented as
randomize() with;

• Inside Operator:
• During randomization , it might require to randomize the variable with in the range of values.
• Values with in the inside block can be variable, constant or range.

Syntax:
Constraint addr {data inside {1,3,[5:10],12,[13:15]};}
In the above example 1,3 are set of values and [13:15] represents range.
Inline example:

class packet;
rand bit [3:0] addr;
rand bit [3:0] data;

constraint data_range { data > 0; data < 10; }


endclass

module inline_constr;
initial begin
packet pkt; pkt
= new();
repeat(2) begin
pkt.randomize() with { addr == 8;};
$display("\taddr = %0d data = %0d",pkt.addr,pkt.data);
end
end
endmodule
Inside operator:

class packet;
rand bit [3:0] addr;
rand bit [3:0] wr; rand
bit [3:0] rd;
constraint addr_1_range { addr inside {[wr:rd]}; } // We can add values also with in the
range.
endclass

module constr_inside;
initial begin
packet pkt; pkt
= new();
repeat(3) begin
pkt.randomize();
$display("wr = %0d,rd = %0d",pkt.wr,pkt.rd);
$display("addr = %0d",pkt.addr); end
end
endmodule
Distribution constraints:

• Controls
the values on randomization.
• Repetition of the same value on randomization can be controlled by weighted distribution.
• There are 2 types of operators in distribution constraints.
1) := for each declared range, assigns weight to every value.
Syntax: [101:200] := 200
In the above example from 101 , 102, …,200 … each value gets a weight of
200.
Constraint c1 {a.dist { [101:200] };}
2) :/ assigns weight to whole value. Syntax:
[101:200] :/ 200
In the above example each item gets a weight of 2.
• By default the weight is 1.
Conditional Constraint:

• The implication operator can be used to declaring conditional relations between two variables.
Syntax:
Constraint identifier {expression ->{constraint_set};}
Implication Operator:

If else : if else block allows conditional executions of constraints. If the expression is true, all the constraints in the first
constraint/constraint-block must be satisfied, otherwise all the constraints in the optional else constraint/constraint-block must
be satisfied.
Syntax:
{if (exp) {constraint_set {else constraint_set}};}
Example:
constraint address_range { if(addr == "true") data < 8;
else
data > 8;
}
Soft Constraint:

• To override the constraint we use the soft keyword, any conflict between class constraint leads to a randomization
failure, from this it is clear that it is not possible to override the class constraint by inline constraint.

class packet; repeat(4) begin


rand bit [3:0] data; pkt.randomize() with { data < 6;};
constraint addr_range { soft data > 6; } $display("data = %0d",pkt.data);
endclass end
module soft_constr; initial end
begin packet pkt; endmodule
pkt = new();
Solve before constraints:

• solve before constraints are used to force the constraint block to specify the
order of constraint solving.

Example: module inline;


initial
class packet; begin packet
rand bit; pkt; pkt =
rand bit [3:0]b; new();
constraint ab {solve a before b;} repeat(10)
constraint a_b {(a ==1) -> (b==0);} pkt.randomize();
endclass $display(“value of a = %0d, b = %0d”,
pkt.a , pkt.b);
end
end
endmodule
Unique Constraint:

• Unique values to set of variables or unique elements to an array can be generated by using Unique
Constraint.

Syntax:
module sv; packet
class packet;
pkt; initial begin
rand bit [31:0] array[10];
pkt = new();
constraint array_c {unique {array}; pkt.randomize();
foreach(array[i]) array[i] < 10;} pkt.display();
function display(); end endmodule
$display("array = %p",array);
endfunction
endclass
Keypoints of Constraints:

• Constraints are declared with in the class.


• Constraints are possible only after randomization.
• Constraint overriding is possible only by declaring the same name in another constraint also.
• Syntax: constraint c1 { a = 10;}
constraint c1 { a = 20;}
• Constraint Conflict:
Syntax: constraint c1 {a >10 ;}
constraint c2 {a <10 ;}
In the above example , as we have declared the same variable name , randomization cannot choose what
constraint has to be randomized. So in this case constraint conflict occurs.
THREADS:

There are 3 types of threads:


•fork_join : Fork-Join will start all the processes inside it parallel and wait for the completion of all the processes.
Example :
module sv;
Initial
begin
fork
begin
#10 $display($time,"i am cat");
end
begin
#20 $display($time,"i am fat");
end
begin
#30 $display($time,"i am dog");
end
join
#40 $display($time,"i am rat");
end
endmodule
• fork_join_any : Fork-Join_any will be unblocked after the completion of any of the Processes.
Example :

module sv;
initial begin
fork
begin
#10 $display($time,"i am cat"); end
begin
#20 $display($time,"i am fat");
end
begin
#30 $display($time,"i am dog");
end
join_any
#40 $display($time,"i am rat");
end
endmodule
fork_join_none : fork-join_none means it will not join the threads.
Example :
module sv;
initial begin
fork
begin
#10 $display($time,"i am cat");
end
begin
#20 $display($time,"i am fat");
end
begin
#30 $display($time,"i am dog");
end
join_none
#40 $display($time,"i am rat");
end
endmodule
MAILBOX :

• A mailbox is a Inter Process communication mechanism between two components (i.e., generator
& driver) , (monitor & Scoreboard) in system Verilog.

• In generator we are using put() method , to place some data and using get() method we can
retrieve the data in driver.

• Mailbox has 2 types depends up on type:

• Generic mailbox (all data types)


• Parameterized mailbox (particular data type)
Mailbox has 2 types depends on size:
• Bounded mailbox (size is mentioned)
• Unbounded mailbox (size is not mentioned)
There are 2 methods of mailbox:
• put(); , get(); , peek() Blocking methods
• tryput(), tryget(); , trypeek(); Non_blocking methods

Syntax:

mailbox # (transaction) gen2drv;


Semaphore:

• Semaphore is a System Verilog built-in class, used for access control to shared resources, and for basic
synchronization and mutual exclusion purpose.
• A semaphore is like a bucket with number of keys.
• By using semaphore we can put the keys and get the keys to access any files.

Semaphore methods:
• Semaphore is a built-in class that provides the following methods,
• new(); Create a semaphore with a specified number of keys.
• get(); Obtain one or more keys from the bucket.
• put(); Return one or more keys into the bucket.
• try_get(); Try to obtain one or more keys without blocking.
• try_put(); To return one or more keys without blocking.
Semaphore code:

module semaphore_ex;
semaphore sema; initial task automatic display();

begin sema=new(4); sema.get(3); //getting '4' keys from sema


fork
display(); $display($time,"Current Simulation Time"); #20;
display();
sema.put(4); //putting '4' keys to sema
join
endtask
end
endmodule
Interface:

• The interface is used to connect the design and testbench.

Without interface With interface

Interface syntax:
interface mem_intf;
logic clk;
logic [7:0]addr;
logic wr_rd;
endinterface
Virtual Interface:

• An interface is a named as group of signals.


• Virtual Interface is Bi-directional.
• In interface we are declaring input , output signals by using logic data type.
• Virtual Interface is dynamic in nature, we can change virtual interface during the run_time.
• Virtual Interface contains Modports & Clocking blocks.
• Virtual interface point outs the physical interface which is present in the sv_library or
uvm_library.
• An interface can have parameters, constants, variables, functions, and tasks.
Modports:

• Modports provides the direction to the module ports i.e. ,they specify the inputs & outputs to
the module.

Syntax:

interface intf;
logic a;
logic b;
modport driver (input a , output b); // modport declaration
modport monitor (input a, input b);
endinterface
Clocking Blocks:

• Clocking blocks are used for synchronizing purpose.


• Clocking blocks used to avoid the race conditions between testbench & design.
• Clocking blocks provides input & output skew.
• By using clocking blocks testbench will drive the stimulus to the DUT at the right time. blocks are used in
• Clocking Virtual Interface.
Syntax of clocking block:
clocking cb@(posedge clk); default
input #1 output #2; input
from_dut;
output to_dut;
endclocking
Input and Output Skew:

• Input skew: TB samples DUT outputs before the clock edge


• Outp
• ut skew: TB drives the DUT inputs at the clock edge.
coverage :

• Coverage is used to measure tested and untested portions of the design. Coverage is

defined as the percentage of verification objectives that have been met. types of coverage metrics,

• There are two

• Code Coverage

• Functional Coverage
Code Coverage :

• Code coverage measures how much of the “design Code” is covered.

• The simulator tool will automatically extract the code coverage from the design code.

Types of Code Coverage :

1. Line Coverage

2. Statement Coverage

3. Toggle /Transition Coverage

4. FSM Coverage

5. Branch / Conditional Coverage

6. Block / Expression Coverage

7. Path Coverage
1. Line Coverage : Conveys the number of lines covered in the design.

Syntax: input a;

output b;

2. Statement Coverage : Conveys the number of statements covered.

Syntax: y = a+b;

x = b+c;

3. Toggle / Transition Coverage : It covers the toggle i.e., 0-1 or 1-0 conditions.

4. FSM Coverage : It covers the states of a Finite machine i.e., melay and moore states.

5. Branch / Conditional Coverage : Branch covers if – else , do – while , priority – if coverages.

6. Block Coverage: Covers all the begin – end , always blocks.


7. Path Coverage : Covers true & false paths.
Functional coverage :

• Functional coverage is a user-defined metric that measures how much of the design specifications or how many features
have been covered in verification of the design.

• Functional coverage is user-defines implemented at environment side.

• In the functional coverage we have covergroups

coverpoints , bins ,

cross coverage.
Cover group:

covergroup cg @(posedge clk) c1 :


coverpoint addr {
bins[ ] = {[100 : 200]};
bins[5] = {[300 : 500]};
}
c2 : coverpoint data {
bins [ ] = {[10:50]};
bins [2] = {[60:90]};
}
c1 *c2 :
cross c1,c2;
endgroup
• Once covergroup is created we need to create a handle for that. Syntax: cg cg_inst;
• Once covergroup is instantiated we need to assign memory for that.
Syntax: cg_inst = new();
• Once memory is assigned we need to sample the covergroup.
• cg_inst.sample ();
Defining cover points

• A covergroup can contain one or more coverage points. A coverage point can be an integral variable or an integral
expression. Each coverage point is associated with “bin”. On each sample clock simulator will increment the associated
bin value.

• The bins will automatically be created or can be explicitly defined.

Automatic Bins or Implicit Bins:

• An automatically single bin will be created for each value of the coverpoint variable range. These are called
automatic, or implicit, bins.

• For an “n” bit integral coverpoint variable, a 2^n number of automatic bins will get created.

• Syntax : 1) bins [ ] = {[0:10]}; // Here 11 bins are created for 11 values.

2) bins [5] = {[0:10]} ; 5 bins are created for 11 values.


Explicit bins :

• “bins” keyword is used to declare the bins explicitly to a variable.

• A separate bin is created for each value in the given range of variable or a single/multiple bins for the range of values.

• Bins are explicitly declared within curly braces { } along with the bins keyword followed by bin name and variable

value/range, immediately after the coverpoint identifier.

• Syntax : c1: coverpoint addr { bins b1 = {0,2,7};}


Transition bins

• The transition of coverage point can be covered by specifying the sequence,

• value1 => value2

• It represents transition of coverage point value from value1 to value2.

• sequence can be single value or range,

• value1 => value2 => value3 ….

• range_list_1 => range_list_2

Syntax: c1: coverpoint addr { bins b1 = (10=>20=>30);}


illegal and ignore bins:

Ignore bins: Ignore bins are excluded from the coverage if you declare , the bin as ignore it will give

the fatal error. It is not included in the coverage , but simulator will give the coverage list which are
ignored.

Syntax : - c1: coverpoint addr{ ignore_bins b1= {5 , 10 , 15};}

illegal bins: illegal_bins are not added in the coverage , it is excluded from the coverage , if we declare illegal bin , simulator throws

the run time error.

Syntax: - c1:coverpoint addr{ illegal_bins b1={7,70,77};}


Coverage options

at_least :

auto_bin_max :

cross_auto_bin_max :

eg

covergroup cg @(posedge clk);

c1: coverpoint addr { option.auto_bin_max = 128;}

c2: coverpoint wr_rd { option.atleast = 2;}

c1Xc2: cross c1, c2 { option.cross_auto_bin_max = 128;} endgroup : cg


Important Topics of Coverage:

Scenario 1:
When Code Coverage is 90% & Functional coverage is 100% ?
• When code is covered till 90% remaining 10% is not covered due to missing of some blocks,
statements, toggle conditions , lines or FSM states etc.,

Scenario 2:
When Functional Coverage is 90% & Code Coverage is 100%?
• When code is Covered 100% ,but if functional coverage is less compared to code coverage because of some
features are missing, even though if we cover all features we cannot expect 100% coverage.

Scenario 3:
Refinement File : When Functional Coverage is 98% , remaining 2% can be achieved by refinement file. Refinement File can be collected
from RTL designer.
Assertions / Checkers:

• Assertion is a property , that the design should operate and which is always true.
• These are used to monitor the internal signals.
• To check the proper assertion quality, stimulus must be driven.

There are 2 types of assertions in System Verilog:


1) Immediate Assertions :
• Immediate Assertions can be written only inside procedural block and will be active only inside
procedural block.
• Error message occurs when assertions fails.
2) Concurrent Assertions :
• By using Concurrent assertions we can express complex designs also very simple.
• Can be used in procedural block , module, interface .
• Can be used with both static and Dynamic verification.
Built –in functions of Assertions :

• $rose( ) : useful for edge triggered properties.


• Syntax: $rose (expr) : Change in transition of a signal and it must be 1.

• $fell( ) : Change in transition of a signal and it must be 0.


• Syntax : $fell (expr)

• $past( ): Returns the value of A from a previous evaluation cycle.


• Syntax : $past (A , N)

• $stable( ) : Checks for the previous cycle.

• $countones( ) : Returns the number of 1’s in an expression , any value other than one will be ignored.
• Syntax : $countones (expr)

• $isunknown( ) : Returns a boolean true if any bit in expression is x or z.


• Syntax: $isunknown (expr)

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