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Program Name and Code: CO3I Academic Year : 2018-2019

Course Name and Code: DIGITAL TECHNIQUES Semester : Third

A STUDY ON
“LOGIC GATES USING TRANSISTORS”

MICRO PROJECT REPORT

Submitted in Nov 2018 by the group of 03students
Sr. Roll No Enrollment Seat No
Full name of Student
No (Sem-III) No (Sem-II)
1
2
3

Under the Guidance of

[ your guide name ]
in
Three Years Diploma Program in Engineering & Technology of Maharashtra
State Board of Technical Education, Mumbai (Autonomous)
ISO 9001:2008 (ISO/IEC-27001:2013)
at

[ your college name ]

1
 MAHARASHTRA STATE BOARD OF TECHNICAL
EDUCATION, MUMBAI

Certificate
This is to certify that Mr. /Ms.

Roll No: of Third Semester of Diploma

Program in Engineering & Technology at [ your college nname ] , has completed the

Micro Project satisfactorily in Subject Digital Techniques in the academic year2018-

2019 as per the MSBTE prescribed curriculum of I Scheme.

Place:Pune EnrollmentNo:

Date: / /2018 Exam. SeatNo:

ProjectGuide Head ofthe Department Principal

Seal of Institute

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 Index

Sr. No Title Page No

1 Introduction 4-5

2 Abstract 6-8

3 Main content 9-13

4 Diagrams 9-13

5 Requirements 14

6 Model photo 15

7 Conclusion 16

6 References 17

7 Weekly Work / Progress Report 18

8 Evaluation Sheet 19

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 INTRODUTION
TO
“LOGIC GATES USING TRANSISTORS”

Basic Gates
This is an active graphic. Click on any of the gates for further information.

Negative Logic Gates

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The reason for which the computers are capable of performing complex operation is due to the
interconnection of these logic gates. Logic gates are implemented by using transistors, diodes, relays, optics
and molecules or even by several mechanical elements. Due to this reason logic gates can also be considered
as electronic circuits. The logic gates can be build up in a wide variety forms such as large-scale integrated
circuits (LSI), very large-scale integrated circuits (VLSI) and also in small-scale integrated circuits (SSI).
Here the inputs and output of all the gates of integrated devices can be accessible and also the external
connections are made available to them just like discrete logic gates.

Inputs and outputs of logic gates are in two levels termed as HIGH and LOW, or TRUE and FALSE, or ON
and OFF, or simply 1 and 0. A table which list out the combination of input variables and the corresponding
output variables is termed as “TRUTH TABLE”. It explains how the logic circuit output responds to various
combinations of logic levels at the inputs. Here we are following level logic, in which the voltage levels are
represented as logic 1 and logic 0. Level logic is of two types such as positive logic or negative logic. In the
positive logic system, higher of the two voltage levels are represented as 1 and lower of the two voltage levels
are represented as 0. But in the negative logic system, higher of the two voltage levels are represented as 0
and lower of the two voltage levels are represented as 1. While considering the transistor-transistor logic
(TTL), the lower state is assumed to be zero volts (0V) and the higher state is considered as five volts positive
(+5V).For the purpose of this class, we will consider transistors to be the basic building blocks of computer
hardware.A transistor is an electronic device that has three ends: a source, a sink, and a gate. The figure below
shows three individual transistors (circa 1960s). Today's technology allows us to pack up to 1 million
transistors per square millimeter (circa 2006). An Intel processor measuring less than a square inch has well
over 1.5 billion transistors on it (circa 2007) . 

Figure 1: Picture of individual transistors (courtesy of Wikipedia).

More conveniently, transistors are depicted using the picture below.

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 ABSTRACT

Transistor AND Gate

The use of transistorsfor the construction of

logic gates depends upon their utility as
fast switches. When the base-emitter diode is turned
on enough to be driven into saturation, the collector
voltage with respect to the emitter may be near zero
and can be used to construct gates for the TTL logic
family. For the AND logic, the transistors are in
series and both transistors must be in the conducting
state to drive the output high

Transistor OR Gate

The use of transistorsfor the construction of logic gates depends upon their

utility as fast switches. When the base-emitter diode is turned on enough to
be driven into saturation, the collector voltage with respect to the emitter may
be near zero and can be used to construct gates for the TTL logic family. For
the OR logic, the transistors are in parallel and the output is driven high if
either of the transistors is conducting.

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 Transistor NAND Gate

The use of transistorsfor the construction of logic gates depends upon their

utility as fast switches. When the base-emitter diode is turned on enough to
be driven into saturation, the collector voltage with respect to the emitter
may be near zero and can be used to construct gates for the TTL logic
family. For the NAND logic, the transistors are in series, but the output is
above them. The output is high unless both A and B inputs are high, in
which case the output is taken down close to ground potential.

Transistor NOR Gate

The use of transistorsfor the construction of logic gates depends upon their

utility as fast switches. When the base-emitter diode is turned on enough to
be driven into saturation, the collector voltage with respect to the emitter
may be near zero and can be used to construct gates for the TTL logic
family. For the NOR logic, the transistors are in parallel with the output
above them so that if either or both of the inputs are high, the output is
driven low.

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 Transistor NOR Gate

The use of transistorsfor the construction of logic gates depends upon their

utility as fast switches. When the base-emitter diode is turned on enough to
be driven into saturation, the collector voltage with respect to the emitter
may be near zero and can be used to construct gates for the TTL logic
family. In this alternative way to achieve NOR logic, only one transistor is
used with the two inputs tied to its base through resistors. If either or both
of the inputs is high, the output is driven low.

TTL Logic Family

The transistor-transistor-logic (TTL) family was developed in the use of transistor switches for
logical operations and defines the binary values as

0 V to 0.8 V = logic 0
2 V to 5 V = logic 1
TTL is the largest family of digital ICs, but the CMOS family is growing rapidly. They are
inexpensive, but draw a lot of power and must be supplied with +5 volts. Individual gates may
draw 3 to 4 mA.

The low power Schottky versions of TTL chips draw only 20% of the power, but are more
expensive. Part numbers for these chips have LS in the middle of them.

CMOS Logic Family

The complementary metal oxide semiconductor family (CMOS) has equivalents to most of the
TTL chips. CMOS chips are much lower in power requirements (drawing about 1 mA) and
operate with a wide range of supply voltages (typically 3 to 18 volts). The CMOS model number
will have a C in the middle of it, e.g., the 74C04 is the CMOS equivalent to the TTL 7404. A
bigh drawback is extreme sensitivity to static electricity - they must be carefully protected from
static discharges.

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  CONTENT
AND GATE
An AND gate requires two or more inputs and produce only one output. The AND gate
produces an output of logic 1 state when each of the inputs are at logic 1 state and also
produces an output of logic 0 state even if any of its inputs are at logic 0 state. The symbol for
AND operation is ‘.’, or we use no symbol for representing. If the inputs are of X and Y, then
the output can be expressed as Z=XY. The AND gate is so named because, if 0 is called
“false” and 1 is called “true,” the gate performs in the same way as the logical “and” operator.
The AND gate is also named as all or nothing gate. The logic symbols and truth tables of two-
input and three-input AND gates are given below.

2 Input AND Gate – Truth Table

3 Input AND Gate – Truth Table

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 2-Input Transistor AND Gate

In the case of transistor AND gate, When the inputs X, Y = 0V or when X=0V and Y= +5V or
when X=+5V and Y=0V, both the transistors Q1 and Q2 are at OFF state. At the same time,
Transistor Q3 gets enough base drive from the supply through Resistor R3 and so transistor
Q3 will be ON. Thereby the output voltage Z= V ce(sat) corresponds to 0V. When both the inputs
are equal to +5V, the transistors Q1 and Q2 will be ON and therefore the voltage at the
collector of transistor Q1 will drop. Due to this the transistor Q3 doesn’t get enough base
drive and turns OFF. As a result no current flows through the collector resistor of Q3 and ,
thereby no voltage drop across it. So the final output voltage corresponds to +5V. The truth
table for this gate circuit is shown below:

Discrete AND Gate Truth Table

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 OR GATE

Similar to AND gate, an OR gate may also have two or more inputs but produce only one
output. The OR gate produces an output of logic 1 state even if any of its inputs is in logic 1
state and also produces an output of logic 0 state if any of its inputs is in logic 0 state. The
symbol for OR operation is ‘+’.  If the inputs are of X and Y, then the output can be
represented as Z=X+Y. An OR gate may also be defined as a device whose output is 1, even if
one of its input is 1. OR gate is also called as any or all gate. It is also called as an inclusive
OR gate because it consists of the condition of ‘both the inputs can be present’.  The logic
symbols and truth table for two-input and three-input OR gates are given below.

2 Input OR Gate – Truth Table

3 Input OR Gate – Truth Table

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 2-Input Transistor OR Gate

In the case of transistor OR gate, when the inputs X=0V and Y = 0V both the transistors Q1
and Q2 are at OFF state. At the same time, Transistor Q3 gets enough base drive from the
supply +5V through Resistor R3 and so transistor Q3 will be ON. Thereby the output voltage
Z= Vce(sat) corresponds to 0V. When either the inputs X and Y or both the inputs are equal to
+5V, then the corresponding transistors either Q1 or Q2 will be ON or both the transistors Q1
and Q2 will be ON and therefore the voltage at the collector of transistor Q1 is
VCE(sat) corresponds to 0V. Due to this reason the transistor Q3 doesn’t forward bias the base-
emitter junction and turns OFF. So the final output voltage corresponds to +5V (logic 1 state).
The truth table for this gate circuit is shown below:

Discrete OR Gate Truth Table

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 NOT GATE

The NOT gate is also called as an inverter, simply because it changes the input to its opposite.
The NOT gate is having only one input and one corresponding output. It is a device whose
output is always the compliment of the given input. That means, the NOT gate produces an
output of logic 1 state when the input is of logic 0 state and also produce the output of logic 0
state when the input is of logic 1 state. The NOT operation is denoted by ’-‘(bar). When the
input variable to the NOT gate is represented by ‘X’ and the output is represented by ‘Z’. In
the NOT operation it can be read as ‘Z is equal to X bar’. The logic symbol and truth table are
given below:

NOT Gate – Truth Table

Discrete NOT gate may be realized by using transistors. The inputs represented as X may be
either 0V or +5V correspondingly. The output is represented by Z. When the input X = 0V,
then the transistor Q1 will be reverse biased and therefore it remains OFF. As a result no
current flows through the resistor and thereby there will not be any voltage drop across the
resistor. As a result, the output voltage Z corresponds to +5V. When the input X= +5V,
transistor Q1 is ON and the output voltage Z=V  ce(sat) corresponds to 0V. The truth table for the

NOT gate is given below:

Transistor Inverter NOT Gate – Truth Table

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 REQUIREMENTS:

TOOLS QUANTITY
I. Logic gates (AND,OR,NOT)
II. Transistors (5)
III. Battery (1)
IV. PCB Board (2)
V. Soldering Machine (1)
VI. Resistors (9)
VII. LEDs (3)
VIII. Switch keys (5)

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PROJECT PHOTO COPY:

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 CONCLUSION

We converted the previous diagrams we made into circuits that were composed mainly of
NAND and NOR gates and followed the same procedure. In the first circuit or in the F1, it is
in the Sum o Products form (SOP) and therefore can be easily implemented using NAND
gates. Thus, we constructed its equivalent circuit using NAND gates only. Then, in the second
circuit or in the F2, it can be easily seen that it is in Product of Sums form (POS) and therefore
it can be easily implemented using NOR gates, Hence, we constructed once again
another circuit using NOR gates only but the exact equivalent of theF2.We have constructed
another series of possible answer for each combination so as to serve as a guide to the values
were going to measure. We then measured the corresponding output voltages for each of the
combinations and compared it with our computed or expected values. The results were exactly
the same as what we obtained from the first procedure .After the experiment, we can now say
that using Universal gates we can implement any gate like AND,OR and NOT, or any
combination of these basic gates and obtained the same output. Also we have proved its most
important advantage compared to circuits using basic gates, and that is it minimizes thelogic
ICs being used. Therefore NAND and NOR gates really deserves their title as the Universal
gates.

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 REFERENCES

I. http://hyperphysics.phyastr.gsu.edu/hbase/Electronic/
trangate.html#c1
II. http://www.circuitstoday.com/logic-gates
III. https://www.cs.bu.edu/~best/courses/modules/
Transistors2Gates/
IV. https://www.scribd.com/doc/81284251/Discussion-an-
Conclusion-Logic-Lab

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 Weekly Work / Progress Report

Week Duration Sign of

No. Date Work or activity Performed the Guide
in hours

1 22/12/2018 Two hour

2 29/12/2018 Two hour

3 05/01/2018 Two hour

4 12/01/2018 Two hour

5 19/01/2018 Two hour

6 02/02/2018 Two hour

7 16/02/2018 Two hour

8 16/03/2018 Two hour

9 23/03/2018 Two hour

Name of Project Guide: Ms. SHEETAL DHATRAK

Lecturer in Digital Techniques.
1734- Trinity Polytechnic Pune.

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 Evaluation Sheet for the Micro Project

Academic Year: 2018-19

Program: Computer Engg. Name of Faculty: Sheetal Dhatrak
Course: DTE Course Code: Semester: III
Title of The Project: FOUR BIT ADDER

COs Addressed by the Micro Project:

A. Communicate effectively by avoiding barriers in various formal and informal situations.
B. Communicate skillfully using non-verbal methods of communication.
C. Give presentations by using audio-visual aids.
Major Learning Outcomes achieved by students by doing the project:

(a) Practical Outcomes: 1) Project skills upgraded

(b) digital electronics used
1) Prepare and make seminar presentation.
2) Prepare and Participate in projects related to digilat techniques.
3) Prepare the points for computer presentation for the given topic.
4) Make effective computer presentations.
(c) Outcomes in Affective Domain:
a) Follow safety practices
b) Maitain cleanliness.
c) Demonstrate working as a leader /a team member.
d) Follow ethics.
Comments/Suggestions about team work/leadership/inter-personal communication (if any)

……………………………………………………………………………………………
Marks out of 6 for Marks out of 4for
Roll performance in performance in Total out of
Student Name
No. group activity (D5 oral/presentation 10
Col.8) (D5 Col.9)
7
8
9

Name & Signature of Faculty

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