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3 EMC in Space: The James Webb Space Telescope

By Martin Rowe, Senior Technical Editor, EE Times & EDN

8 Design PCBs for EMI, part 1: How signals move

By Kenneth Wyatt, Contributing Writer, president and principal 25 The connector is often the EMI problem
consultant of Wyatt Technical Services By Eric Bogatin, Contributing Writer

13 Design PCBs for EMI, part 2: Basic stack-up

By Kenneth Wyatt, Contributing Writer, president and principal
28 Characterize DC-DC converter EMI with near-field probes
By Kenneth Wyatt, Contributing Writer

33
consultant of Wyatt Technical Services

18 Design PCBs for EMI, part 3: Partitioning and routing

By Kenneth Wyatt, Contributing Writer, president and principal
How to improve EMC in a PFC circuit for electric vehicles
By Karl Wallinger, Applications Engineer, Integrated Power
Management, and By Ankur VERMA, Applications Engineer, Signal
consultant of Wyatt Technical Services Chain Texas Instruments

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EMC in Space:
The James Webb Space Telescope
By Martin Rowe, Contributing Writer

T
esting for EMC on a spacecraft isn’t unlike testing for terrestrial
equipment except for the fact that spacecrafts live in a different
electromagnetic environment.
Here on Earth, every piece of electronic equipment must contend
with its electromagnetic environment. Systems such as nearby
equipment, broadcast signals, and the like mean that you either
need to test in a shielded enclosure or find some remote area.
Your equipment must play nice with everything around it. In space,
however, many of these sources of outside interference aren’t present.
When putting a satellite into space, do you need to perform the same
emissions and susceptibility tests as you would for an earthbound
system?

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 Figure 1: The
James Webb Space
That’s the question that EMC engineers
Telescope will
at NASA face. EMC standards, which NASA replace the aging
uses as a basis for EMC testing, were written Hubble Space
Telescope.
with an emphasis on earthbound equipment. (Source: NASA)
In space, the primary sources of interference
are systems on the same spacecraft. John
McCloskey, chief EMC engineer at NASA’s
Goddard Space Flight Center (GSFC), has
spent the bulk of his career testing the
James Webb Space Telescope (JWST), the
replacement for the Hubble Space Telescope.
JWST is expected to launch in 2021 from
French Guiana atop an Ariane 5 rocket.
The JWST (Figure 1) will have a mirror
consisting of hexagon-shaped reflective
panels that will unfold once in orbit. A sun
shield, about the size of a tennis court, McCloskey and others are responsible for with the satellite’s receivers. There is,
will enable the telescope to operate at ensuring that the JWST’s electronic systems however, no specific EMI standard for
the cryogenic temperatures required to don’t interfere with the satellite’s radio spacecraft. NASA EMC engineers use limits
achieve the necessary sensitivity. Behind the receivers, nor with each other. and test procedures based on MIL-STD-
telescope’s primary mirror assembly is the Because satellites spend their operational 461G. If spacecraft radio receivers don’t get
Integrated Science Instrument Module (ISIM), lifetimes in space, it’s the on-board systems hit with the full electromagnetic spectrum
which includes four science instruments. that have the greatest potential to interfere in space, do you need to test for emissions

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 Figure 2: NASA
outside those frequencies used by the engineers at Goddard
receivers on the platform? McCloskey says Space Flight Center
performed EMI tests
no, so why spend money for unnecessary
on the JWST using
testing? If JWST’s radio receivers aren’t in a chamber inside a
use prior to deployment in space, then there clean room.
(Source: NASA)
should be no reason to test for radiated
emissions and susceptibility outside the
frequencies of the intentional receivers.
Tests for interference among the JWST’s
subsystems focus on crosstalk from cables.
“You must, of course, test for emissions
levels within the RF bands of the intentional
receivers,” said McCloskey. “But emissions
outside those receiver bands are generally
not a significant factor.”
Another issue arises as to whether
emissions testing should be performed at wherein each “box” is tested separately. instrument level.
the integrated instrument or spacecraft level Testing at the unit level lets engineers McCloskey prefers to perform unit tests in
versus testing at the unit level. Testing at diagnose and fix any potential problems which each unit operates in a configuration
the integrated instrument or spacecraft level when they are much less costly to address that brings out the highest emissions.
requires more people. McCloskey estimates than at higher levels of integration. “We want to make each unit an emissions
daily testing costs to be at Figure 2 shows the EMC team at GSFC, culprit,” he said. “That might require two
least 10 times higher than at the unit level, where engineers test the unit level and or three tests for the highest emissions

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at different frequencies.” EMC engineers Table 1: JWST
radiated emissions
consult with designers to find those
frequencies and
conditions. Such conditions might, for
antennas.
example, occur when the main computer
sends commands to a motor or when it’s
sending significant amounts of data. “It’s
OK to have test-only modes such as those
for moving motors or states of high data Unit-level emissions tests are performed instruments at those frequencies.1
intensity to get worst-case conditions.” with several EMI antennas that cover EMC in space isn’t all about emissions
JWST unit-level testing for radiated different frequency ranges, all at 1 m from interfering with radios. Non-RF devices
emissions covered the frequency range the EUT. Table 1 lists those antennas. such as computers and scientific
of the S-band receiver: 2.0898521 GHz Like any other electronic device, the units in instruments must properly operate with
to 2.0916521 GHz. In addition, tests the JWST must pass radiated susceptibility the spacecraft. Conducted emissions
were needed to ensure that the JWST tests, which are more time-consuming and susceptibility tests let engineers test
electronics that must operate during the that emissions tests. Because all JWST how units and systems can interfere with
launch sequence wouldn’t interfere with equipment was tested to 18 GHz at unit level, each other. Crosstalk among cables can
the UHF uplink from mission control to the it was sufficient to test the ISIM to only 8 GHz cause signals to couple into unintended
Launch Vehicle Command Destruct receiver once integrated to the instrument level. systems. Here, the problem is common-
— 420 MHz to 480 MHz at 35 dBµV/m. JWST also has no intentional transmitters mode current, which McCloskey measures
Outside of that band, testing was still operating below 1 GHz. Nevertheless, with current probes. For susceptibility tests,
performed to ensure that units would not engineers chose to test down to 30 MHz engineers inject common-mode current
interfere with each other and that cables so that they could characterize sensitivity and look for errors that it might cause.2
and enclosures were properly constructed. of the detector systems in the science Engineers also look for worst-case

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situations between offenders and sensitive From an EMC perspective, space places
cables. In such situations, distance matters. unique conditions on electronics, some
To determine if there is a potential problem, of which are easier to contend with than
engineers calculate the field strength from Earth-based equipment. In space, the
any offenders at the locations of sensitive ambient electromagnetic environment is
cables. Emissions levels not only have to dominated by on-board equipment.
meet standards but be low enough to not
disrupt spacecraft functions. References:
1 McCloskey, John, “EMC Testing on the Integrated Science Instrument
In addition to testing for radiated/ Module (ISIM),” Proceedings of the 2016 IEEE International Symposium on

conducted emissions and susceptibility, Electromagnetic compatibility.

2 McCloskey, John, “EMC Test Challenges for NASA’s James Webb Space
engineers must ensure that power quality Telescope,” Proceedings of the 2017 IEEE International Symposium on
at the system level doesn’t disrupt JWST Electromagnetic compatibility.

functions. A custom line-impedance 3 McCloskey, John and Ken Javor, “An Updated EMC Standard for
NASA’s Goddard Space Flight Center,” Proceedings of the 2012 IEEE
stabilization network (LISN) helps to control International Symposium on Electromagnetic compatibility.

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Design PCBs for EMI, part 1: How signals move
By Kenneth Wyatt, Contributing Writer

A
fter helping clients get their products compliant for
EMI, I’ve seen one underlying issue: Poor PC board
design. In my experience, IoT product designers run into
problems caused by poor PC board design. Poor design can
cause endless delays when on-board energy sources disrupt
sensitive receiver circuits, resulting in cellular compliance
failures. GPS and Wi-Fi receivers can also lose sensitivity.
In this part 1, you’ll see how signals move through PCB
traces and how EM fields affect that movement. In part 2, I’ll
contrast the difference between good and poor PCB stack-
ups. Part 3 covers signal routing and board partitioning.
There are many factors that contribute to poor EMI designs.
These include:
• Mixing noisy circuits, such as power and motor conversion
with digital and sensitive analog circuits.

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 • Locating clock drivers too close to fields—work together (are complementary) First, let’s consider how capacitors
board edges or near sensitive circuits. in propagating a digital signal through a seemingly allow the flow of electrons. After
• Poor trace routing which leads to cross- microstrip or stripline. all, isn’t that how decoupling capacitors
talk. Before you can understand how signals work? Referring to Figure 1, if we apply
• Running clock (or high speed) traces propagate in PC boards, you must first a battery to the capacitor, any positive
over gaps/slots in the return plane. understand some physics. charges applied to the top plate will repel
• And above all, incorrect layer stack-ups. We were all taught that “current” was positive charges on the bottom plate,
the flow of electrons in copper. This is leaving negative charges. If we apply an AC
I’ve already addressed crossing clock close to the truth, except we tend to think source to the capacitor, you might assume
traces over gaps in the return plane (Ref. of positive current flow—the lack of an that current flows through the dielectric,
1, 2). Fixing this last item regarding layer electron, often referred to as a “hole.” which is impossible. James Clerk Maxwell
stack-ups will, however, usually correct a Electrons and the “holes” (positive charge) called this “displacement current,” where
myriad of ills, including many of the other they leave behind, however, travel very positive charges merely displace positive
items on the list. slowly (Ref. 3). See the explanation coming charges on the opposite plate leaving
While attending university circuits classes up shortly. negative charges, and vice versa. This
most of us were taught incorrectly how This current flow is true, of course, for displacement current is defined as dE/dt
DC and AC current works in lumped or DC circuits (with exception of the initial (changing E-field with time).
distributed (transmission line) circuits. battery connection transient). But for AC You should also realize that electrons
In our “fields and waves” classes, we (or RF) circuits or for the “DC” output and the positively-charged holes do not
were not likely instructed in the practical (with transients) from switch mode power travel near light speed in copper as we
applications of circuit board design or supplies, we need to understand all were taught, but move at about 1 cm/
signal propagation through circuit boards. connecting wires/traces must now be sec, due to the very tight atomic bond of
In truth, these two concepts—circuits and considered transmission lines. the copper molecules (Ref. 4). There are

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Figure 1. The concept of displacement current through a capacitor.

Figure 2. Newton’s
Cradle, an analogy
certainly clouds of free electrons and holes, the speed of the EM field in the dielectric Let’s now consider a digital signal with a to demonstrate the
but these move slowly from molecule to material. In other words, jiggle one electron wave front moving at about half light speed “kink” in the E-field
as it travels from
molecule. This is called conduction current at one end of a microstrip and it jiggles the (about a typical 6 in./ns in FR4 dielectric)
one electron to the
and is what we would measure with an next, which jiggles the next, and so on, along a simple microstrip over an adjacent next.
ammeter. Conduction current is related to until it jiggles the last one at the end. This ground return plane (GRP) as illustrated in
the tangential component of the B-field, jiggling is called a kink in the E-field and Figure 3.
that is the curl B = J. can be envisioned as the Newton’s Cradle The next realization (thing to grasp) is that
The influence of one electron in the toy, a mechanical analogy, where the first the EM field of the digital signal travels in the
copper molecule to its neighbor (and on ball hits the next and this eventually pops dielectric space—not the copper. The copper
down the transmission line) propagates at off the end ball (Figure 2). merely “guides” the EM wave (Ref. 5 and 6).

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 When the signal (EM wave) is first applied
between the microstrip and GRP, it starts
to propagate along the transmission line
formed by the microstrip over an adjacent
GRP. There is a combination of conduction
current and displacement current (across
the dielectric).
All the exciting “EMI stuff” happens at the
wave front as the EM wave propagates. At
an instant it time, the electric field behind
the initial wave front is stable at whatever
the applied voltage is at the moment and
the electric field in front of the initial wave
front is zero. The fast rise or fall times of the
signal contain all the harmonic energy and
this is what creates the EMI.
If the load impedance is equal to the
characteristic impedance of the transmission
line, then there will be no reflections of the
EM wave back to the source. However, if
there is a mismatch, there will be reflected
Figure 3. The digital signal (an electromagnetic wave) travels through the dielectric space between the microstrip EM fields propagating back to the source. In
and ground reference plane (GRP).
reality, most realistic digital signals will have

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multiple reflections moving back and forth trace (or plane) adjacent to a GRP. For designs will be described in my next article,
through the transmission line simultaneously. example, locating multiple signal layers “Design PCBs for EMI, part 2: Basic
The transition zone (rise time or fall time) between power and ground reference stack-up.”
of these propagating waves will potentially planes will lead to real EMI issues for fast Acknowledgement: I’d like to thank Eric
produce EMI. signals. Observing these two rules will Bogatin for his valuable help in helping me
Now that you see how signals move in dictate the layer stack-up. understand the physics of electromagnetic
circuit boards, there are two very important In other words, every signal or power wave propagation in PC boards, as well as
principles when it comes to PC board trace (routed power) must have an adjacent Ralph Morrison, Daniel Beeker, and Rick
design: GRP and all power planes should have an Hartley for their training in proper PC board
1. Every signal and power trace (or plane) adjacent GRP. Multiple GRPs should be design for high frequency digital circuits.
on a PC board should be considered a tied together with a matrix of stitching vias. —Kenneth Wyatt is president and
transmission line. If you break the path for conduction principal consultant of Wyatt Technical
2. Digital signal propagation in current in the GRP through a gap or slot, Services.
transmission lines is really the we start to get “leakage” of the EM field
movement of electromagnetic fields in throughout the dielectric space, which References
the space between the copper trace leads to edge radiation from the board and 1 André, Patrick and Kenneth Wyatt, EMI Troubleshooting Cookbook for
Product Designers, Scitech Publishing, 2014.
and GRP. cross-coupling to other circuits through
2 Wyatt and Jost, Electromagnetic Compatibility EMC Pocket Guide, Scitech
via-to-via coupling. This also occurs when Publishers, 2013.

To construct a transmission line, you we pass a signal through multiple ground 3 Schmitt, Electromagnetics Explained - A Handbook for Wireless/RF, EMC,
and High Speed Electronics, Newnes, 2002.
need two adjacent pieces of metal that reference or power planes if there is no
4 Bogatin, Eric, Signal and Power Integrity - Simplified (3rd edition), Prentice
capture or contain the field. For example, adjacent stitching via or stitching capacitor Hall, 2018.

a microstrip over an adjacent GRP or a (to connect GRP to power planes). 5 Morrison, Ralph, Digital Circuit Boards: Mach 1 GHz, Wiley, 2012.

stripline adjacent to a GRP or a power These topics and specific PC board 6 Morrison, Ralph, Fast Circuit Boards: Energy Management, Wiley, 2018.

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Design PCBs for EMI, part 2: Basic stack-up
By Kenneth Wyatt, Contributing Writer

P
art 1 of this series described how digital signals propagate
through PC boards [Refs. 1, 2, 5, 6]. In part 2, we look at
specific board designs to achieve low EMI. The biggest
issue I see in my clients’ board designs is poor layer stack-up.
Reiterating the two fundamental rules from part 1 and realizing
digital signals and power (transients) are electromagnetic waves
moving in the dielectric layer, we see there are two very important
principles when it comes to PC board design:
1. Every signal and power trace (or plane) on a PC board should
be considered a transmission line.
2. Digital signal propagation in transmission lines is really the
movement of electromagnetic fields in the space between the
copper trace and GRP.

To construct a transmission line, you need two adjacent

pieces of metal that capture or contain the field. For example, a

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 Figure 1. A very
common, but poor,
microstrip over an adjacent ground return EMI stack-up design
plane (GRP) or a stripline adjacent to a (6-layer example).
Signal layers 4 and
GRP or a power trace (or plane) adjacent 6 are referenced to
to a GRP. For example, locating multiple power, while the GRP
and power planes
signal layers between power and ground are non-adjacent
reference planes will lead to real EMI issues with two signal layers
in between. This
for fast signals. Observing these two rules
will couple power
will dictate the layer stack-up. transients on those
In other words, every signal or power trace two signal layers.

(routed power) must have an adjacent GRP

and all power planes should have an adjacent
GRP. Multiple GRPs should be tied together
with a matrix of stitching vias. In this article,
we’ll examine several stack-up designs. referenced to the power plane and the capacitance, which in this case is relatively
power and ground return planes are non- small. In addition, these gaps in the return
Typical six-layer design (Altium) adjacent and too far apart. path result in field leakage into other areas
One stack-up I frequently see is this six- With few exceptions (some DDR RAM of the board’s dielectric layers. That, in turn,
layer design (Figure 1). This probably power and signals, for example) currents leads to cross-coupling and radiated EMI.
worked well enough in the 1990s through want to return to their sources, which are The second issue occurs when we have
early 2000s, but with today’s much faster referenced to the GRP. Referencing these the power and GRP separated by two signal
and mixed signal technologies, it’s recipe signals to the power plane is very EMI- layers. Any power network transients will
for EMI disaster. There are two issues risky, because there is no clearly defined cross-couple within the dielectric layers,
with this: the bottom two signal layers are return path, except through plane-to-plane coupling to any signal traces on layers 3 and

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4 along the way. You also lose any plane-to- Figure 2. This good
four-layer board stack-
plane capacitance benefit if these planes are up for improved EMI
separated by more than 3-4 mils. keeps the signals and
routed power near
The following are a several ideas for PC the ground reference
board stack-ups that comply with the planes.

transmission line aspects of digital signal

propagation.

Four-layer board: Design 1

A good four-layer board stack-up for Figure 3. This good
improved EMI (Figure 2). Instead of a four-layer board stack-
up for improved EMI
power plane, we use either routed or places the ground
poured power, along with signals on layers reference planes inside
the board.
2 and 3. Thus, each signal/power trace is
adjacent to a GRP. Also, it’s easy to run
vias between all layers, so long as the
two GRPs are connected together with a
matrix of stitching vias. If you run a row
of stitching vias along the perimeter (say,
every 5mm) you form a Faraday cage. access to the signal and routed/poured are positioned at the top and bottom, with
power traces, you may simply reverse the routed power and sufficient decoupling
Four-layer board: Design 2 layer pairs, such that the two GRP layers caps, rather than a power plane (Figure 3).
If, on the other hand, you’d prefer to have are in the middle and the two signal layers For both four-layer designs, you want to

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run a pattern of stitching vias connecting Figure 4. A good
EMI stack-up
the two GRPs about 1cm apart, maximum. design (8-layer
example). All
signal layers are
Eight-layer board (Altium) referenced to an
Both the four- and eight-layer board designs adjacent GRP,
while power is
(Figure 4) follow the two fundamental rules
also referenced
that preserve good transmission line design. to an adjacent
In addition, for the eight-layer design, the GRP.

power and GRP planes are now 4 mils

apart, providing fairly good plane-to-plane
capacitance. Closer would even be better.
For example, a spacing of 1 mil to 3 mils is
ideal for minimizing EMI. All GRPs should be
stitched together with a 1 cm pattern of vias.
Of course, there are many more iterations
on creating proper transmission line pairs
between signal and GRP or power and
GRP. technology. in today’s technology, we with NXP Semiconductor [Ref 5].
often need to use at least two layers to run Figure 5. An example of routed triplets
What about two-layer boards? signals. The answer is to run “triplets” with for signals, as well as attempting to
Simple, just run signals and routed power a ground return trace between two signal preserve the transmission line principles
on layer 1 and use a GRP on layer 2. traces (Figure 5). This was an idea from for routed power. Courtesy: Daniel Beeker,
Well, that may have worked in yesterday’s Daniel Beeker, Senior Applications Engineer NXP Semiconductor

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 Here, we see an attempt to preserve the Figure 5. An
transmission line properties for the routed example of
routed triplets for
power. The example also shows analog signals, as well
signal traces with a ground return trace as attempting
to preserve the
between them—a routed “triplet.” Because transmission line
the electromagnetic field is captured principles for routed
power. Courtesy:
adequately between each signal trace and
Daniel Beeker, NXP
the return trace, there is little field leakage. Semiconductor 
If you’d like to learn much more about
designing for EMI compliance in your PC
boards, I’d also recommend Rick Hartley as
an excellent source with his 2-day seminar
(Reference 6). Finally, I have to thank Ralph
Morrison, Dan Beeker, and Rick Hartley,
who really taught me about fast signals in
References
circuit boards [Refs 3, 4, 5, 6]. 1. Schmitt, Ron, Electromagnetics Explained - A Handbook for Wireless/RF,
EMC, and High Speed Electronics, Newnes, 2002.
Part 3 of this series will address
2. Bogatin, Eric, Signal Integrity - Simplified (3rd edition), Prentice Hall,
partitioning of circuit sections, routing of 2018.

high-speed traces, and a few other layout 3. Beeker, Daniel, Effective PCB Design: Techniques To Improve
Performance.
practices to help reduce EMI.
4. Hartley, Rick, Control of Noise, EMI and Signal Integrity in PC Boards
—Kenneth Wyatt is president and (2-day seminar), Rick Hartley Enterprises.

principal consultant of Wyatt Technical 5. Morrison, Ralph, Digital Circuit Boards: Mach 1 GHz, Wiley, 2012.
Services. 6. Morrison, Ralph, Fast Circuit Boards: Energy Management, Wiley, 2017.

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Design PCBs for EMI, part 3:
Partitioning and routing
By Kenneth Wyatt, Contributing Writer

P
art 1 of this series described how power conversion, RF, and things like motor
digital signals propagate through PC control or other high-power circuits.
boards, and Part 2 described specific Before we get to circuit layout, we must
board stack-up designs to achieve low first understand and visualize how return
EMI. Part 3 will address partitioning of currents flow and how the electromagnetic
circuit sections, routing of high-speed fields are distributed under high-speed
traces, and a few other layout practices circuit traces. At low frequencies—below
to help reduce EMI. about 50 kHz—return currents tend to
Besides proper layer stack-up, the next follow the path of lowest resistance. They
most important consideration when laying tend to travel along the shortest distance
out the circuitry on your board is partitioning between source and load, as simulated by Figure 1. Return current field distribution below 50 kHz follows the path of least
of circuit functions, such as digital, analog, the green area in Figure 1. resistance. Image courtesy Keysight Technologies

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 At roughly 50 kHz to 100 kHz, return Figure 2. Return
current field
currents tend to follow the path of lowest distribution at
impedance due to mutual impedance frequencies above
50 kHz, will return to
coupling effects between the signal path. the source through
These currents tend to travel directly the path of least
impedance. Image
underneath the signal path between source
courtesy Keysight
and load, as simulated by the green area in Technologies.
Figure 2.
You can now understand why analog
circuitry should be located well away from
digital or other noisy circuits. Keep these
“spread out” return currents from intermixing
with the return currents from noisy circuitry.
That’s the main reason why partitioning is so
important.
same dielectric space. Thus, you need to see that any analog or low-frequency
Partitioning partition major circuit functions. Figure 3 circuitry must be separated from digital,
Part 1 of this series described how the demonstrates one example of partitioning. power conversion, or motor controller
digital (and other high-frequency) signals Of course, this gets more challenging circuits. Likewise, sensitive RF receiver
propagate through a board’s dielectric as board size shrinks. Henry Ott also circuits, such as GPS, cellular, or Wi-
space. To avoid signal coupling and describes this concept in Reference 1. Fi devices must also be kept separate
crosstalk, you must not allow the various Knowing now that low frequency signal from digital, power conversion, or motor
return signals from intermixing within the returns tend to spread out more, we can controller circuitry, as well.

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 Signal routing
Here are some guidelines to follow when
routing signals on PCBs to minimize
interference.
Gaps in Return Planes: All ground return
planes (GRPs) should be as solid as possible
and designed without long gaps or slots. As
mentioned in Part 1, when a high frequency
trace crosses a gap in the return path, this
creates a source of common mode currents,
which generally couple all over the board and
create the potential for radiated emissions
failures (references 2 and 3).
These common mode currents couple to
power and I/O cables, which then radiate.
But the gap also causes field leakage within
the dielectric space, which can couple to
nearby vias from other signals, causing
unwanted coupling similar to crosstalk. It
Figure 2. Return current field distribution at frequencies above 50 kHz, will return to the source through the path of
least impedance. Image courtesy Keysight Technologies. also causes “edge radiation” directly from
the board. If the harmonic frequency of
the common mode currents is 1/4 to 1/2
wavelength of either the cables or board

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Figure 4. There dimension, they’ll act as transmitting
are two issues antennas and radiate. See my video demo
in this example;
we have a digital on “gaps in return planes” (Reference 4).
signal crossing Via penetration: Very often, you need to run
two gaps in the
GRP and it also
signals from the top side to the bottom side
crosses a “quiet” (or interior-to-interior layers), relying on vias to
analog plane.
get there. If you only need to pass from one
side of a GRP to the other, there’s no issue,
because the electromagnetic field of the signal
is contained along the entire path (Figure 5).
It’s only when you need to pass through
multiple planes that you might fail to provide
a return path for the electromagnetic wave
as it travels through the dielectric space of
the board (Figure 6).
If there’s no transmission-line continuity
between the planes (stitching via or
capacitor), then you will get field leakage
throughout the dielectric space as the signal
tries to find a way back to the source. This
field energy will couple to other vias, as well
Figure 5. Passing a signal trace through a single GRP allows field propagation along the entire path. as propagate out as “edge radiation.”
The dielectric layer is not shown for clarity and the field propagation is represented by the red “waves.”
If the two planes are GRPs, then you need

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 conventional method is to start with one or
more (depending on the number of layers)
power-ground “cores” and build the signal
layers from there, usually equally on each
side of the core for best manufacturability.
Typically, digital ground return is used for
this. Another big advantage is that when
spaced very close together (less than 3
mils), the power-ground core becomes a
good high-frequency decoupling capacitor.
Figure 6. Passing a signal trace through two planes results in field leakage withing the dielectric space, unless a As the number of layers increase, it’s often
defined path for return current is added. The dielectric layer is not shown for clarity and the field propagation is
best to locate two or more power-ground
represented by the red “waves.”
cores closer to the top and bottom of
to merely stitch them together in at least stitching capacitor needs to be installed next the stack-up—generally on layers 2-3
one location near the signal via. This allows to the signal via. If there are dozens of signal and 6-7 (on eight-layer boards, for
field propagation along the entire path. As penetrations on such a board, it may be example).
I’ll mention later, a matrix of ground vias impractical to add a stitching capacitor for The disadvantage is that stitching (or
is always a good practice and if they’re every signal penetration, so that’s one reason decoupling) capacitors are required to
located very close together (5 mm spacing to locate an even distribution of decoupling/ maintain transmission lines for the signals
is good), there’s no need to specifically stitching capacitors throughout the board. passing through. Other voltage rails are
locate one at each penetration. This will also help reduce “ground bounce” or then generally routed on signal layers.
If, however, the two planes are at different simultaneous switching noise (SSN). There’s one big advantage with routing all
potentials, such as a GRP and power, then a Routed power versus power planes: The power and using one, or more, GRPs. That

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is, all the GRPs can be stitched together NXP Semiconductor (Reference 5). Other guidelines to minimize EMI
in a matrix pattern and you won’t need Ground pours: It’s always a good practice Clock oscillators/crystals/drivers: Locate
dedicated stitching capacitors. Multiple to fill any spaces between signal traces with your clock oscillators towards the center of
GRPs, when located on outer layers, may ground pours. These ground pours must the board (or digital partition), as close to
be stitched together around the perimeter be connected in multiple places to all GRPs the device they’re driving, and away from
of the board to form a Faraday shield. within your board. This does two things; board edges and especially, I/O or power
On the other hand, every digital device will it provides additional shielding, as well as connectors.
need 2-3 decoupling capacitors per power paths for signal returns, and it enables a Clock traces: All clock traces should be
pin, or tight groupings of pins. In addition, better and reliable board design from a short and direct. Avoid running these along
rails (typically the main digital voltages) production standpoint. board edges, because that can physically
should have wider pours around any high Multiple ground vias: It’s a good couple to the board edge and cause board
di/dt devices, such as core voltage, drivers, practice to create a matrix of ground vias resonances and consequent board radiation.
ASICs, motor controllers, processors, etc. connecting all ground pours and GRPs I/O and power connectors: If possible,
This will help serve as your high frequency together using a spacing of about 5mm. locate your I/O and power connectors
decoupling. This will provide multiple return paths for along a single edge of the board. The
Routed triplets: In the case where you signals penetrating more than one GRP father apart one connector is located from
may not have a continuous GRP, such layer. In addition, if you use multiple GRPs, another, the more EMI-related noise voltage
as some two-layer board designs, both you should design via stitching all around can be measured between their connector
analog and digital traces may be routed as the periphery of the board to create a bodies. What is a high frequency noise
“triplets”, with a single return trace located Faraday cage for those signal layers in source between two long wires? A dipole
and routed along with two signal traces. between. This technique is especially antenna! You want to minimize the “noise”
This was described and illustrated in Part important when incorporating wireless voltage drop between all connectors.
2 and has been featured by Dan Beeker, of technology in the design. RF module transmission lines: All antenna

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transmission lines should be run short make 90-degree bends where needed success - not only for reduced EMI, but
and direct to the antennas or antenna (References 6, 7, and 8). for proper receive sensitivity of on-board
port connectors. These should be buried 20H Rule: There is also the so-called wireless technology.
in between two GRPs and may dictate “20H Rule” where the power plane should —Kenneth Wyatt is president and
eight, or more, layers to achieve a 50-Ω be set back from the edge of the GRP principal consultant of Wyatt Technical
impedance through “keep out” areas in the by 20 times the layer thickness. This Services.
layers immediately above and below the supposedly helped reduce fringing fields. If
transmission line(s). In addition, add rows of nothing else it simply makes the field lines References
1. Ott, Henry, Electromagnetic Compatibility Engineering, Wiley, 2009.
via stitching, spaced every 3 mm to 5 mm, longer (References 9 and 10).
2. André, Patrick and Kenneth Wyatt, EMI Troubleshooting Cookbook for
connecting all the GRPs along each side I suspect there’s many more and perhaps Product Designers, Scitech Publishing, 2014.

of every antenna transmission line. This will readers could add to the list through their 3. Wyatt, Kenneth and Randy J. Jost, Electromagnetic Compatibility EMC
Pocket Guide, Scitech Publishers, 2013.
provide additional shielding. comments.
4. Wyatt, Kenneth, Gaps in Return Planes (video)
Ethernet connectors: There should be a Part 3 concludes the series on minimizing
5 .Beeker, Daniel, Effective PCB Design: Techniques To Improve
ground return plane “keep out” area directly EMI in circuit boards. So many of my Performance

underneath Ethernet connectors. This will clients get the circuit board design wrong, 6. Johnson, Howard, “Who’s Afraid of the Big Bad Bend?”

help transition from single-ended signal usually starting with the stack-up, that I felt 7. Altium, PCB Routing Angle Myths: 45-Degree Angle versus 90-Degree
Angle, 2018
pairs to balanced signal pairs. compelled to relay what I’ve learned myself
8. Bogatin, Eric, “When to Worry About Trace Corners: Rule of Thumb #24,”
during the last three years of intensive EDN, https://www.edn.com/electronics-blogs/all-aboard-/4438573/

Urban legends study. Most of the projects I’ve been When-to-worry-about-trace-corners—Rule-of-Thumb—24

9. Chen, Huabo et al, Effects of 20-H Rule and Shielding Vias on

90-degree turns: It’s been pretty well fortunate enough to work on recently have Electromagnetic Radiation from Printed Circuit Boards (archived at
proven that for normal (to at least to several been IoT products, where partitioning and SpeedingEdge)

GHz) digital traces, it’s not necessary to getting the circuit board designed correctly 10. Shim, Hwan and Todd Hubing, 20-H Rule Modelling and Measurements,
Missouri University of Science & Technology (archived at Clemson
chamfer or round off corners. It’s OK to from the start are so very important for University)

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The connector is often the EMI problem
By Eric Bogatin, Contributing Writer

W
hen it comes to reducing EMI problems, most coax cables
behave the same. They are all just as good antenna for
common currents to radiate and fail an FCC certification
type test. It’s not the cable that is the chief source of EMC test
failures, it’s usually the connector.
If there were any net current, or common current on a cable, to
return through the stray fringe fields between the entire cable and the
floor, back to the chassis, it would radiate. In the most sensitive FCC
part 15 test condition—for 88 MHz and below—in a class B test, the
largest acceptable far field at 3 m from the product is 100 µV/m. This
is an important number to remember.
This means that if there is a larger field at 3m from the product than
100 µV/m, at 88 MHz, within the 120 kHz bandwidth of the FCC
test, the product will fail EMC certification and not be allowed for sale
in the US. Other countries have similar certification requirements.

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 When the source of the radiation is from
common currents on external cables such Figure 1. Illustration of
how ground bounce in
as those that connect to peripherals, using
a connector can drive
a “better” cable often has no impact at all common currents on a
on the radiated emissions. That’s because cable and fail an EMC
certification test.
the common currents are flowing on the
shield of the cable. Remarkably, it only
takes 3 µA of common current flowing on
the shield of a cable, 1 m long, to cause an
FCC class B failure. This is another really
important number to remember, and it’s a
tiny amount of current.
The most important driving voltage for these When the dI/dt of the return current circular rings of field lines circulating in one
common currents that causes EMC failures flows through the total inductance of the direction. The return current, if symmetrical
is ground bounce in the connector attaching connector, it generates a voltage, and about the signal path, generates the
the cable to the chassis. Ground bounce is this voltage between the chassis and the identical rings of magnetic field around
the voltage generated between two regions cable’s shield is what drives the common the cable, but circulating in the opposite
of the return path due to a changing current currents on the cable, which results in an direction. These two sets of magnetic field
flowing through the total inductance of the EMC failure. This is illustrated in Figure 1. lines exactly cancel out and there is no
return path. The total inductance of the A coax cable will have no ground bounce external magnetic field.
return path is related to the total number of because there is no external magnetic field But suppose at the connector, the return
field lines around the conductor per amp of around it. The signal current generates current is not perfectly symmetrical about
current flowing through it. an external magnetic field composed of the signal current. Maybe there is a pigtail,

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 Resources
maybe the clam shell is not well metalized, If the impedance the common current Register for our EMI testing
or maybe the connector only makes sees returning through all those fringe field step-by-step guide
contact at one or two points to the chassis. lines is about 200 Ω, this 2 mV of ground
Any asymmetry will mean the magnetic bounce voltage will drive I = 2 mV/200 Ω = Analyze EMI problems with the
field lines from the signal current and return 10 µA. Is this a lot or a little?
R&S®RTO / R&S®RTE
current will not perfectly cancel out. There
will be some net magnetic field lines and Remember, it only takes 3 µA of common
EMI debugging at board level
this will result in some total inductance of current to fail an EMC certification test. This
the return path. ground bounce driven current in the cable
Outstanding perspectives. With EMC
solutions from Rohde & Schwarz
In a typical 50 Ω coax cable, with a 1V shield will cause an EMC failure.
signal, having a 1ns rise time, the signal Is it any wonder it’s often a challenge to
R&S Elektra EMI Test Software
and return current is about 1 V/50 Ω = 20 pass an EMC certification test? If you know
mA. Even if the asymmetry is so slight as an EMC engineer who has help you pass a
to generate only 0.1 nH of total inductance certification test, take that engineer out to
around the return path of the connector, lunch and say thanks!
the ground bounce voltage generated Eric Bogatin is a Signal Integrity
would be: Evangelist with Teledyne LeCroy and
the Dean of the Teledyne LeCroy Signal
Integrity Academy, at www.beTheSignal.
com.

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Characterize DC-DC converter EMI
with near-field probes Figure 1. When
characterizing the
By Kenneth Wyatt, Contributing Writer waveform from a DC-
DC power converter
located on a typical
IoT board, you should

E
couple your probe to
MI from on-board DC-DC converters is a common problem with IoT the output inductor.
Inductors are readily
products. These small circuits generally switch between 1 MHz and
identified by their
3 MHz and use very fast sub-nanosecond edge speeds. The result relatively large round
is broadband EMI often extending above 2 GHz. This EMI can affect package. The probe
should be held flat, as
the sensitivity of sensitive receiver circuits, especially cellular and Global shown, for maximum
Navigation Satellite System (GNSS). coupling.

One useful way to characterize the EMI performance of a DC-DC

converter is to measure the rise time and ringing using a small H-field
probe in the time domain. This may be done non-invasively by coupling
an H-field probe to the converter output inductor (Figure 1).
It is important to characterize ringing on the switched waveform,

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because this ring frequency can translate EMV, TekBox, Tektronix, and others.]
to broad peaking in the emission To prove this characterization
characteristics. H-field probes are quick measurement, let’s examine the math
and safe because they don’t require direct (Figure 2). There will be some unknown
connection to the circuitry - just couple it to mutual coupling factor (M in the equations
the DC-DC converter output inductor. below) between the inductor and H-field
The Rohde & Schwarz HZ-15 near-field probe. Because we don’t know the mutual
probe kit (review) includes several H-field coupling factor, the amplitude won’t
probes (loops). Because we want to couple compare with actually measuring with an
to currents in traces and components, that’s oscilloscope probe. For EMI purposes,
the type to use. The largest one may be we’re mainly interested in the rise time,
too sensitive and thus has less resolution general switched wave shape, and ringing Figure 2. The switched waveform (SW) between the output inductor of a DC-DC
converter and H-field probe couple through mutual inductance (M).
that you may need to isolate the source of frequency, if any.
emissions. The next smaller one (model RS A DC-DC converter usually has a near
H 50-1), which is about 1 cm in diameter, is square wave signal (VL) from the converter Assuming the H-field probe is held close
about right to identify and characterize EMI switch node (SW) and output inductor (L) to the inductor, you get some mutual
at the board level. Simply connect the probe input to ground return and this is what we’d coupling, M (unknown), and the output of
to a 50-Ω oscilloscope input and adjust for measure with an oscilloscope probe. The the probe is:
an adequate displayed waveform. current through the inductor is related to
[Editor’s note: EMI probe kits are also that voltage as:
available from Beehive, Com-Power, ETS- Combining the first two equations results
Lindgren, Keysight Technologies, Langer in:

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 Therefore, factoring out the constant,
M/L, we see VOUT ∞ VL.
Because VOUT is proportional to VL, the
most important characteristics for EMI
are now easily and quickly measured
without the risk of shorting connections
with oscilloscope probe tips. By using
the H-field probe held close to each DC-
DC converter inductor, you can measure
the rise time (indicates the upper range
of harmonic frequencies), pulse width
and period (also factors into harmonic
frequencies), and ringing frequency
(which can cause broad resonant
peaking in the broad band spectrum.
Figure 3 and Figure 4 compare the
switched waveform characteristics
Figure 3. Probing the DC-DC converter output inductor of a typical IoT device using a coupled H-field probe (top trace) and direct-
from a RT-ZS20 1.5 GHz bandwidth connected single-ended probe (bottom trace) show similar waveforms. Using the H-field probe, you can quickly measure rise time,
oscilloscope probe (with short probe period, and ringing without risk of shorting circuits.

tips) and the RS H 50-1 H-field probe.

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The measured results are comparable,
except for amplitude.
With the same H-field probe
connected to a Siglent SSA 3032X
spectrum analyzer with start and
stop frequencies at 1 and 500 MHz,
respectively, and with a 120 kHz
resolution bandwidth, you can the 8
MHz resonance within the resulting
broadband spectrum (Figure 5).
In many cases I’ve seen, this ring
frequency can easily be in the 100s of
MHz and cause major broad peaking
in the emission spectrum, which can
cause EMI failures if coupled to an
efficient antenna-like structure (cables,
typically).
Acknowledgments: Thanks to Rohde
& Schwarz for the use of their HZ-15
near field probe kit, the RT-ZS20 active Figure 4. Measurement of the ringing on the DC-DC converter. This could translate to broad peaking in the EMI at 8 MHz (plus higher-
probe and RTE 1204 oscilloscope. order harmonics).

Thanks, also, to my colleague and

friend, Arturo Mediano, for his help

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analyzing the math showing that the
non-invasive coupling method depicts
the essential switching characteristics
accurately.
—Kenneth Wyatt is president and
principal consultant of Wyatt Technical
Services.

References
1. Ott, Henry, Electromagnetic Compatibility Engineering, Wiley, 2009.

2. André, Patrick and Kenneth Wyatt, EMI Troubleshooting Cookbook for

Product Designers, Scitech Publishing, 2014.

3. Paul, Clayton, Introduction to Electromagnetic Compatibility (2nd Edition),

Wiley, 2006.

Figure 5. The resulting broadband frequency spectrum from this DC-DC converter, shows the 8 MHz resonance peak at Marker 1.

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How to improve EMC in a PFC circuit
for electric vehicles
Using interleaved PFC and careful filter-design techniques, designers can keep EVs compliant with strict EMI standards
despite high-voltage, high-frequency dc switching and ripple-current effects

By Karl Wallinger, Applications Engineer, Integrated Power Management, and

Ankur VERMA, Applications Engineer, Signal Chain Texas Instruments

E
lectric vehicles (EVs) use several kilowatts To help designers in this process, this article
of energy to drive the ac synchronous explains the system-level architecture of an
propulsion motor from 400-V lithium-ion (Li- EV onboard charger and why power factor
ion) batteries. The dc/dc circuits used to charge correction (PFC) is needed. We then show how
the batteries generate large amounts of EMI that to design an input EMI filter that helps to meet
can surpass stringent standards, such as IEC radiation standards such as CISPR25, including
61000-3-2 or IEC 61000-3-4 [1], so designers calculations to select the filter components.
need to use an input filter with carefully selected The application example covers a 50-Hz 220-
components. Vac input ac offline power supply used for an

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automotive on-board charger in an EV. The applications may require additional voltage used to charge the batteries and
same principles also can be applied when electromagnetic interference (EMI) filters to run the system. Boosting is typically done
designing an industrial grid, power delivery pass the standard [2]. with the PFC stage in order to increase
systems, and motor position sensing efficiency and reduce losses (see “ Why is
systems [1, 3]. System overview: on-board charger PFC important?”).
for EV In these high-power ranges, the PFC stage
EMI sources The on-board charger for an electric vehicle is commonly interleaved to reduce the output
The on-board dc/dc circuitry used for deals with high power that can range from ripple current and mitigate EMI emissions.
battery charging typically uses pulse- 1.5 kW to 3 kW, depending on the system. The PFC boost output voltage of 380 to
width modulation (PWM) controllers The universal input voltage of 90- to 265- 400 Vdc typically supports currents above
that implement power factor control Vac must be boosted up to 380–400 Vdc 10 A. An H-bridge circuit is used to chop it
at switching frequencies that can vary before the field-effect transistor (FET) full- down in order to match the Li-ion battery’s
anywhere between 50–100 kHz. The large bridge can chop it down to the lower dc charging profile (Fig. 1). The system also
voltages at such high-switching frequencies Fig. 1: System
are the source of the electromagnetic diagram of a typical
automotive on-
radiation that sometimes can surpass IEC
board charging
61000-3-2 or IEC 61000-3-4. solution. The PFC
These standards typically require output of 380 to
400 V is chopped
admissible harmonic current components using an H-bridge
for emissions values to be within certain to match the Li-ion
battery’s charging
limits. Active PFC techniques, such as profile.
boost, help to mitigate electromagnetic
compatibility (EMC). However, stringent

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must support functional safety requirements multiple phases. In a two-phase interleaved
and meet emissions standards. In addition, converter, for example, the input phases
the designer needs to understand how power run at 180° out of phase from each other.
factor control is implemented and why it is Some PWM controllers for the PFC boost
critical in the system-design process. operation have phase-management
capability that can help to manage Table 1: Inductor loss reduction for interleaved PFC phases. Each
PFC and its impact on EMI compromises between the switching and additional phase further reduces losses.

Along with high dc/dc switching frequencies, conduction losses.

other sources of EMI include higher ripple Also, current harmonics at the input of the harmonic components of input current.
currents. These can lead to high dV/dt in the power supply directly contribute to the EMI These standards dictate a maximum level
system, causing EMI emissions. Also, the content. Each additional phase reduces of each system fundamental frequency
boost’s output current is discontinuous and the input ripple current; hence, the input harmonic up to the 40th harmonic.
may lead to EMI emissions because of its EMI filter size can be reduced accordingly. Also, there may be radiated emissions
high RMS currents; thus, it requires filteringMoreover, the phases reduce I2R requirements for the system, such as CISPR
by the output capacitor. conduction losses in the inductor (Table 1). 25, which is dedicated to radio emissions
Power factor control can help reduce Now we will look at an example design to limits for vehicles from 150 kHz to 2.5 GHz.
EMI with the help of a PWM controller show how to tackle EMI in a 50-Hz, 220-Vac To minimize EMI and harmonic distortion
that performs interleaving, as mentioned input ac offline power supply used for an and to meet these requirements, an EMI
above (a good example for reference is the automotive on-board charger used in an EV. filter should be placed at the input of the
UCC28070-Q1). Interleaving’s introduction PFC boost converter. This example looks at
of multiple phases that are out of phase Tackling EMI with filter design input-filter design and component selection
greatly reduces both input and output ripple. Different standards, such as the IEC61000- to reduce the harmonic emissions of the on-
Interleaving can be done in two or 3-2 and IEC61000-3-4, provide limits for board charger using a PFC boost converter.

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 One example of an EMI filter is created value based on size, current, and cost. For
using an inductor-capacitor (LC) filter. this example, we choose 470 µH. Now we
Two common options are second- and can calculate the C value using Equation 4.
fourth-order LC filters. Although other Equation 1.
filters can be used, our example looks at
these. A second-order LC filter achieves Fc is the crossover frequency, F is the
attenuation of –40 dB per decade, while a frequency at which you need to attenuate, Equation 4.
fourth-order LC filter achieves attenuation and a is the amount of attenuation desired
of –80 dB per decade. For this reason, a in dB. Applying the values from this ex- C is the filter capacitance, Fc is the cross-
second-order LC filter requires higher-value ample, F = 150 kHz and attenuation = 50 over frequency, and L is the filter inductance.
L and C components for the same level dB, Equation 2 shows the calculation and Using the values from this example, Fc =
of attenuation, creating higher cost and Equation 3 shows the result. 32.6 kHz and L = 470 µH, C can be calcu-
a larger solution. Therefore, we will use a lated using Equations 5 and 6.
fourth-order LC filter in our example.
First, we need to run a design simulation
or take actual board measurements of the Equation 2.
Equation 5.
design’s EMI levels. Let us assume that
we ran a simulation and that a 50-dB Fc = 32.6 kHz
reduction must be achieved at 150 kHz. Equation 3. C = 50.7 nF
Because a fourth-order LC filter has –80 Equation 6.
dB/decade attenuation, we calculate the Since this is a fourth-order LC filter, we will
filter’s crossover frequency using need two LC filters, each with a 32.6-kHz We chose a 75-nF capacitor to allow for
Equation 1. crossover frequency. Next, choose an L dc bias and capacitor tolerance. This lets

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 References:
us build the filter circuit using two 470-µH current and improve EMC performance. 1. Ankur Verma and Brian Rodriguez. “Electrical design considerations for

inductors and two 75-nF capacitors. To further improve EMI in order to meet industrial resolver sensing applications.” Texas Instruments White Paper
(slyy100), June 2016
harmonic emissions or radiated emissions 2. Ankur Verma. “How to reduce total harmonic distortion to below 10%.” TI
Conclusion requirements, use a fourth-order LC filter to E2E Community Power House blog, May 28, 2013

When designing an ac offline power system attenuate emissions above the crossover 3. Verma, Ankur and Anand Chellamuthu. “Design considerations for
resolver-to-digital converters in electric vehicles.” Texas Instruments
like an automotive on-board charging frequency. By selecting the appropriate Analog Applications Journal, 1Q 2016

module, implement a PFC controller to components, the EMI filter can sufficiently
improve power factor and efficiency. When reduce emissions levels to meet the strict
doing so, implement it as a multi-phased requirements of current industry standards.
boost converter, to reduce the input ripple

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