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JANUARY 2021 • VOL. 38 • NO. 1
FIRST PERSON
6 CAVEAT LECTOR PRINTED CIRCUIT
DESIGN & FAB
Fabricator blowout revisited?
Mike Buetow
MONEY MATTERS
12 ROI
The Covid- and people-free factory.
Peter Bigelow FEATURES
19 DATA TRANSFER
13 BOARD BUYING New DfX Module for IPC-2581 Slices
How to respond to supplier price increases. Design-Manufacturing Time, Errors
Greg Papandrew The latest IPC-DPMX standard offers unique bidirectional
data exchange between design houses and their
manufacturing partners.
by HEMANT SHAH
TECH TALK
22 CHIPLETS
14 DESIGNER’S NOTEBOOK
Evaluation of System-in-Package
Estimating the PCB design cycle.
Implementation Options in the Chiplet World
John Burkhert, Jr. As chiplet usage increases, chip-level concerns shift into the area of system-
in-package implementation. A case study of the cost vs. performance tradeoff.
by STEVE WATT
16 MATERIAL GAINS
From autos to airplanes, change 24 HDP
is in the air. Are Older Standards Still Valid, or Holding the Industry Back?
Despite the Covid-19 lockdown, HDP is coming off one of its most successful years yet,
Alun Morgan
having completed 13 projects. New executive director Larry Marcanti and HDP facilita-
tor John Davignon give an update of the consortium’s latest work and future plans.
17 MATERIAL MATTERS by MIKE BUETOW
A methodology for selecting the right 26 ELECTROCHEMICAL RELIABILITY
material and the right price point. Process Control Plan to Monitor Acceptable Levels of Flux
Bill Hargin and Other Residues
IPC J-STD-001G, Amendment 1, requires sampling plans to ensure soldering
processes remain in control once qualified and validated. A well-vetted control
40 GETTING LEAN plan that monitors the process and its performance on challenging components
A near real-time feedback loop between provides assurance that the process maintains control during the qualification stage.
layout and assembly. by BILL CAPEN, JASON EDGAR, DR. MIKE BIXENMAN, and MARK MCMEEN
Hom-Ming Chang 33 SMART MANUFACTURING cover story
Lights Out at USI
42 SEEING IS BELIEVING The EMS behemoth is on the cusp of an all-automated future.
by MIKE BUETOW
What’s more in need of rehabilitation?
The bonepile or supplier gateway?
IN THE DIGITAL EDITION
Robert Boguski
The Digital Route
PCEA in the rearview mirror.
44 DEFECT OF THE MONTH by KELLY DACK
Intermittent area array packages.
IEEC
Bob Willis State-of-the-Art Technology Flashes
Updates in silicon and electronics technology.
by BINGHAMTON UNIVERSITY
48 TECHNICAL ABSTRACTS
ON PCB CHAT (pcbchat.com)
DEPARTMENTS CAF and Electrochemical Migration
with GRAHAM NAISBITT
8 AROUND THE WORLD
Changes in the Mainstream PCB CAD Market
11 MARKET WATCH with MANNY MARCANO
Solder Voiding
45 OFF THE SHELF with TIM O’NEILL, PRAKASH GANGO and KALYAN NUKALA
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4 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

CAVEAT LECTOR
‘Future Factories’ Require

Thinking ‘Smart’ Today
T
WENTY YEARS HAS passed since the US was a With its acquisition of AsteelFlash complete, USI
world leader in printed circuit board fabrication can now roll out 5 Star to more than 25 manufacturing
MIKE production. And not just in revenues, which tend- facilities worldwide.
BUETOW ed to run neck-and-neck with Japan. The US also had As we reported in November, Lacroix Electronics is
EDITOR-
the capability and capacity to build the largest-format undertaking a similar transformation.
IN-CHIEF
boards in volume. It has started work on the Symbiose smart factory
That was 2000. in France, a greenfield project predicted to have 60%
I remember talking with Jack Fisher, then the techni- more output than similar-sized plants yet with the same
cal director of the tech consortium ITRI, about the com- number (450) of staff when it opens this year. The com-
ing year. We were reviewing the latest bullish industry pany is committing $30 million toward a 205,000 sq. ft.
forecasts, in which some of the major fabricators were (19,000 sq. m.) facility that it expects to generate annual
quoting lead-times of six to 12 months(!). revenues of more than $120 million. Lacroix will use
That unbridled optimism prompted Jack to observe industry-developed open source IoT communications
that any hope of the US investing in HDI technology standards for its digital factory.
would be pushed out at least another year. Since order At its Shanghai smart factory, USI builds SIPs for
books were full for large boards, fabs saw no need to smartwatches. Lacroix is heavily vested in automotive.
invest in next-generation technology. Both are lower-mix, high-volume segments. It is predict-
Or so they thought. Because, as we all know, then able, then, that domestic North American assemblers
the dot-com crash occurred. will say, “Good for them, but it doesn’t apply to me.”
It’s hard to believe that was 20 years ago. But we That’s what we heard from fabricators two decades
might be edging toward history repeating. ago.
Smart manufacturing, which is generally defined as One person who has studied the implementation
the use of fully integrated, collaborative manufactur- of the smart factory matter deeply over the past year
ing systems that respond in real time to meet changing believes the US is five to seven years behind Europe and
demands and conditions in the smart factory, in the sup- as much as 10 years behind the leaders in Asia.
ply network, and in customer needs, is quickly becom- How many fabricators wish they could go back in
ing reality. time and invest in a laser drill or five? The US misplayed
It’s been a long time coming. OEMs of assembly pro- the technology game at immense cost to the region. The
cess equipment have long had the capability to see inside idea that assembly is somehow insulated from a similar
a customer’s factory to perform software upgrades, view outcome is wholly misguided.
maintenance reports, and verify their machines were The US shouldn’t cede entire markets, as it currently
performing to spec. Manufacturer IT personnel, on the does with consumer and mobile, thinking that aero-
other hand, have historically resisted such intrusions space, defense and medical are permanently sustainable
to their networks. With IT and IP security recognized and impervious to foreign competition. Fabricators
as intrinsic to operational success, most manufacturers learned the hard way that you can’t always depend on
have checked suppliers at the proverbial door. what you have now.
In some of the largest EMS companies, that’s Instead of saying, “Convince me,” it would behoove
changed, and it’s working its way down to mid-tier North American shops to say, “Catch me up.” And then
companies as well. As we report in our cover story act accordingly.
this month, Universal Scientific Industrial, which ranks
12th in the CIRCUITS ASSEMBLY Top 50, is all-in on an
all-digital platform. Its Worldwide 5 Star Management
System is bringing Industry 4.0 principles to every layer
of the company. USI uses a common platform strat- mbuetow@upmediagroup.com
egy to standardize the data automation protocols and @mikebuetow
equipment, and develop lead times and costs. They are
making tremendous progress toward a true lights-out
operation, having already reduced headcount in certain P.S. We are pleased to bring back the PCB East confer-
operations from the hundreds to single digits. AGVs ence and exhibition to the Boston area in May. Check
move product from component stores to SMT lines out the details at pcbeast.com.
several floors away, and inventory replenishment and
vendor orders are triggered by software, not humans.

AROUND THE WORLD
3D Glass Solutions, Nokia Collaborate on D-Band

PCDF People Signal Transport
Altair appointed Matthew
Brown senior vice president ALBUQUERQUE, NEW MEXICO – 3D Glass Solutions collaborated with Nokia to deliver
and chief financial officer. D-band signal transport. D-band signal transport requires integrated mm-wave mod-
Brown previously served in
ules with high spectral-efficiency. 3DGS worked with Nokia to develop a demonstra-
finance leadership roles at Nor-
tonLifeLock, including as inter- tor for ultra >30Gbps speed wireless backhaul systems.
im CFO from November 2019 to July 2020. “This solution allows designers in D Band TX/RX modules the lowest loss and
lowest cost point for TX/RX modules, as demonstrated by this radio-on-glass archi-
Altium promoted Christopher
Donato to head of digital chan- tecture for Nokia, operating up to 160GHz with less than 1dB of loss from the chip
nel. He’s been with the com- to the antenna output/input ports,” said Jeb Flemming, CTO, 3DGS.
pany in account management “One of the reasons we’ve been able to achieve such extraordinary performance
and sales positions since 2004. numbers using our RFIC on glass is because we’ve been working closely with the
CMR Surgical named Jesus Castane senior engineers at 3DGS,” said Shahriar Shahramian, director of sensing and communica-
PCB engineer. tion ASICs research, Nokia Bell Labs. “Its unique etching process allows us to build
Kent Balius and Ken Smythe have launched things on glass that simply aren’t possible using any other process. At the same time,
EPIC Front-End Engineering. 3DGS’ willingness to collaborate and explore unexplored areas and applications has
allowed us to build something incredible.”
“This is the next generation of ultra-high-performance radio-on-glass modules
PCDF Briefs operating at these frequencies,” said Flemming. “Our demand for data continues to
Amazon has shifted part of the computing grow, and we are pleased to work with Nokia to deliver record-breaking solutions
for its Alexa voice assistant to custom- that can keep up with that demand.” (CD)
designed chips, aiming to make the work
faster and cheaper, while moving it away
from chips supplied by Nvidia.
Altium to Sell Tasking Business to PE Firm
Apple has selected WLCSP/fan-in for its lat-
SAN DIEGO – Altium will sell its Tasking business unit to a private equity group for
est iPhones. Apple is expected to ramp up
flexible circuit demand for its 2021 devices, more than $100 million in what the ECAD company is calling a “strategic divest-
and is looking to work more closely with ment.” FSN Capital, a European private equity firm, will pay up to $110 million for
ZDT, Compeq, Unimicron and Career Tech- Tasking, $10 million of it conditional on the company hitting certain revenue targets
nology, according to reports. in the 2021 financial year.
Amphenol will acquire MTS Systems The deal will close in the second half of Altium’s current fiscal year, which ends
for approximately $1.7 billion, including in June. Altium will instead focus on its PCB design software.
assumption of outstanding debt and liabili- Tasking produces embedded systems development software. The unit recorded
ties, net of cash.
flat sales of $20 million in Altium’s fiscal 2020 due to Covid-related market issues.
Calumet Electronics is expanding its PCB “While Tasking is a great business, it does not play a central role in our design to
manufacturing operations in Michigan to realization strategy for the electronics industry, which is being delivered through our
meet market demand.
new cloud platform, Altium 365,” Altium said in announcing the deal.
China is stepping up the development of “The strategic divestment of Tasking, combined with our recent organizational
homegrown EDA software and systems as changes and hard pivot to the cloud, marks an inflection point for Altium in its
part of its efforts to boost self-sufficiency
pursuit of industry transformation,” said Aram Mirkazemi, chief executive, Altium.
in semiconductor, and many EDA startups
have become operational with government “The divestment of Tasking will free up organizational capacity and allow Altium
subsidies, according to reports. leadership to focus on our main game, which is to expand Altium 365 and accelerate
its adoption.”
Delta Sigma will use Zuken’s Harness
Builder for E3.series for its electrical har- Altium acquired Tasking in 2001.
ness design. On Nov. 19, Altium guided for fiscal 2021 full-year revenue of $200 million to
$212 million. Announcing the Tasking deal, it reiterated that guidance, less Tasking,
Firan Technology Group achieved Nadcap
accreditation and certification at its PCB implies a lower forecast for its PCB tools going forward in calendar 2021. (MB)
manufacturing facility in Fredericksburg, VA.
IMI Inc. successfully completed an inten-

sive audit to IPC-1791, Trusted Electron-
Infinera Wins Best Overall Design in
ic Designer, Fabricator and Assembler
Requirements and has earned a Qualified
Mentor’s PCB Design Awards
Manufacturer’s Listing under IPC’s Valida- WILSONVILLE, OR – A team from Infinera and Jabil has been selected as designers of
tion Services program.
the best overall circuit board by a group of industry experts under the auspices of
Jingwang Electronic Technology’s new Mentor. (Mentor is now officially Siemens EDA.)
157,000 sq. m., $175 million PCB fabrica- Now in its 28th incarnation, the PCB Technology Leadership Awards recognize
tion campus is expected to open this year.
engineers and designers who use innovative methods and design tools to address

AROUND THE WORLD
complex PCB system design challenges and produce industry-leading products.

MKS Instruments has received an order
The contest is open to any designs created with Mentor PCB solutions. Judging for multiple ESI Geode HDI laser drills in
is based on design complexity and overcoming associated challenges, such as small Taiwan.
form factors, high-speed protocols, multi-discipline team collaboration, advanced
Nano Dimension announced an additional
PCB fabrication technologies, and design-cycle time reduction. 10 customers owning one or more older
Experts in the PCB industry judged entries from around the world in categories DragonFly Pro machines have upgraded
representing computers, blades and servers, memory systems; consumer electronics to the next-generation DragonFly LDM
and handheld designs; industrial control, instrumentation, security and medical appli- machines.
cations; military and aerospace solutions; telecom, network controllers, line cards; SiC technologies are gaining the confi-
transportation and automotive designs. dence of many customers and are pen-
The panel of judges this year included Dr. Rajan Bedi, Stephen Chavez, Mike etrating various applications, especially
electric vehicles, a new report claims.
Creeden, Gary Ferrari, Rick Hartley, Steve Herbstman, Happy Holden, Pete Waddell
and Susy Webb. (CD) University of Southampton’s Optoelec-
tronics Research Centre demonstrated an
all-silicon optical modulator at 100Gb/s
Emerald EMS Acquires Saline Lectronic, Veris and beyond, without the use of digital
signal processing.
Manufacturing Ventec has passed the ISO 9001:2015
audit for its Quality Management System
SALEM, NH – Emerald Electronics Manufacturing Services has acquired a pair of elec- at its facility in Fullerton, CA.
tronics manufacturing service providers, extending its range to the Midwest US and
Zuken and Electro Magnetic Applications
adding capacity in Southern California. The deals also expand the EMS company’s
have entered a partnership to improve
reach into the defense and medical end-markets. the accuracy of cable harness simulation
Both Saline, MI-based Saline Lectronics and Brea, CA-based Veris Manufacturing models for complex electrical subsystems
are manufacturers of high-mix, low- to medium-volume printed circuit board assem- in aircraft and vehicles.
blies and box-builds for high-reliability end markets, including industrial controls,
aerospace and defense, and medical.
CA People
“All of us at Emerald are excited about the expanded geographic reach and
manufacturing capabilities that Saline Lectronics and Veris Manufacturing bring to Benetel named Alan Hynes director of
engineering.
the mix,” said Vic Giglio, chief executive, Emerald EMS. “Their addition expands the
Emerald EMS footprint into Southern California and the Midwest domestically, bring- Creative Electron named Jeff Darby vice
ing increased geographic flexibility and expanded capacity to all of our customers.” president of business development.
Founded in 2002, Saline is a full-service electronics solutions company with a Enics appointed Kristiina Lep-
110,000-sq. ft. manufacturing facility providing engineering, PCB assembly, testing, pänen chief financial officer.
electromechanical box build, and direct fulfillment for the industrial controls, aero- Prior to joining Enic, Leppänen
was CFO for Cavotec, among
space and defense, medical and oil industry end-markets.
other executive positions.
Originally known as Quality Control Manufacturing, Veris was founded in
1987. The company’s 40,000-sq. ft. facility provides manufacturing and engineering Nordson Test & Inspection
named Dennis Rutherford
services focused on the aerospace and medical end-markets.
general manager, rest of Asia.
“Our partnership with Emerald EMS will allow us to offer our customers He joined Nordson in 2016
expanded capacity, as well as access to lower-cost options through Emerald’s Shen- after 15 years in high level
zhen, China, manufacturing facilities, while Emerald gains a strong Midwest pres- sales positions with electron-
ence,” said Mario Sciberra, president and CEO, SLI. ics inspection OEMs.
“Joining Emerald expands our access to new markets and provides investment Fred Dimock recently started
opportunities for us to build on our capabilities in order to stay ahead of the demands Fred C Dimock Global Services,
of our growing customer base,” said Jay Cadler, president, Veris. focusing on thermal processes
and profiling. He spent the pre-
Day-to-day operations are expected to remain unchanged at both SLI and Veris,
vious 20 years as manager, pro-
which will continue to operate under their existing brand names under the Emerald cess technology at BTU.
umbrella, Giglio said.
Yamaha appointed Nick Iso-
Emerald EMS was formed in July 2020 through the acquisitions of Data Ed and
mura division manager of the
Bestronics by New Water Capital, a Chicago-based private equity firm. (MB) Intelligent Machinery (SMT
Equipment and Robotics)
Syrma Technology, SGS Tekniks Merge Division. He has more than
20 years’ experience in SMT
equipment sales, and previously was
SAN JOSE – Syrma Technology in November merged with SGS Tekniks in a cash and
group manager of Europe, Southeast Asia
stock deal of Indian EMS companies. and Americas SMT sales for Yamaha in
Syrma SGS Technologies will have a combined revenue of more than Rs 10 bil- Japan.
lion ($134 million). Some 55% of revenues are from exports to the US and Europe.
JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 9

AROUND THE WORLD
Zestron named James Mueller

Western regional sales man- The combined company aims for 20% year-over-year growth.
ager. He has over two decades The companies did not disclose any financial terms of the deal.
of professional sales man- Syrma SGS Technologies will have eight manufacturing facilities in India and
agement success, 12 years of three design centers, including in Chennai and Gurgaon, India, and Stuttgart, Ger-
which has been centered on
many. Currently, Syrma and SGS each have four factories in India.
achieving sales growth within the preci-
sion and critical cleaning marketplaces. Syrma designs and manufactures RFID technology, power electronics, and turn-
key manufacturing services and custom magnetics, and delivers IoT products for the
automotive, computing, industrial, medical, power, and telecom companies. Medical
CA Briefs and defense electronics are surging, the firm says. (CD)
Absolute EMS installed a Hanwha HM520
SMT line.
AIM Solder opened a 12,000 sq. ft. ISO of Administration. NovaCentrix appointed Torenko & Associ-
9001-certified solder manufacturing facil- ates rep in Texas, Oklahoma, Louisiana,
Foxconn said a facility in Mexico has Arkansas and the interior of Mexico.
ity in Malaysia.
returned to normal following a ransom-
Amazon has laid off dozens of R&D and ware attack in December. It also confirmed PDF Solutions has entered into a definitive
manufacturing staff from its delivery it has placed a bid to take over a stake in agreement to acquire Cimetrix for a $35
drone project, Amazon Prime Air, and will foundry Silterra. million cash payment, net of cash, and
outsource production. subject to other closing adjustments.
Indium and Valuetronics have formed a
Apple has reportedly started sending fold- strategic partnership to serve customers in Pegatron’s board has approved an initial
able iPhones to Foxconn for testing, with a the Americas with their cored wire, rework investment of $150 million for building
possible release in September 2022. fluxes, and bar solder products. manufacturing facilities in India.
Apple’s plans to move the production of Intellitronix acquired a SpeedPrint 700 Qualcomm received a license from the
devices away from China received a major series screen printer and Europlacer iineo+ US government to sell 4G mobile phone
upswing, with several partners entering pick-and-place system, and Universal chips to Huawei, an exemption to US trade
India through the government’s Produc- Instrument model 5362i conveyors. restrictions imposed amid rising tensions
tion-Linked Scheme (PLI). with China.
Intervala is reportedly considering a move
SMIC and China Electronics Technology in Pittsburgh that would increase its foot- Saki opened the Saki Virtual Showroom, a
Group are among more than 30 compa- print from 136,500 sq. ft. to about 220,000 digital reproduction of the Solution Center
nies blacklisted by the Trump administra- sq. ft. housed in its Tokyo headquarters.
tion for their suspected ties to the Chinese
KIC appointed Rocka Specialty Solutions SEMI submitted comments to the US
military. CETG is the parent of TPV Tech-
manufacturers’ representative throughout Department of Commerce urging cau-
nology and Shenzhen Kaifa, two of the
Mexico. tion and the adoption of regulatory best
largest ODM/EMS companies in the world.
practices and microelectronics industry
Mentor will now be known as Siemens recommendations to ensure its identifica-
Chase Corp. finalized the acquisition of
EDA. The company will continue to oper- tion of foundational technologies does
ABchimie, a developer of coatings for
ate as part of Siemens Digital Industries not restrain US innovation and exports
electronics, in an all-cash deal.
Software. without furthering essential US national
Cogiscan announced a strategic partner- security interests.
Fresh off its acquisition of Tabtronics in
ship with Mycronic to provide machine
November, Mirac announced plans to will South-Tek Systems appointed Torenko &
connectivity for Industry 4.0 applications.
build an 11,800 sq. ft. EMS plant in Man- Associates manufacturers’ rep in Mexico.
Creative Electron has been awarded a pat- chester, OH.
ent for AI-powered programming of x-ray TT Electronics has completed the acquisi-
Mountain Electronics acquired ALJ Elec- tion of Torotel, a manufacturer of power
inspection systems.
tronics/ALJCO. and electromagnetic assemblies and com-
Datest announced a new technical part- ponents for the aerospace and defense
MRSI and Palomar Technologies have
nership with Aster Technologies. markets.
reached an agreement that settles all lit-
Ease announced the availability of a igation currently pending between the TT Electronics opened an electronics man-
complimentary new ebook, The Ultimate companies. ufacturing facility in Kuantan, Malaysia.
Guide to Layered Process Audits, which
NexLogic Technologies added a 3,000 sq. Universal Scientific Industrial in December
details layered process audits and offers
ft. Class 10,000 clean room to its EMS completed the acquisition of Asteelflash
advice, checklists and tips and tricks.
operations in San Jose. through the acquisition of its parent com-
(https://go.ease.io/Ultimate-Guide-to-
LPAs_LP.html) Nordson Dage named Murray Percival pany, Financière. USI also broke ground
representative of its Assure series of x-ray on a 65,000 sq. m. facility in Haiphong
Eolane acquired a Kurtz Ersa Versaflow City, Vietnam, with a planned investment
component counters in the Midwest US.
4/55 selective soldering oven for its of $200 million for phase one.
Valence Romans Agglo site. Northrop Grumman awarded Kitron a
three-year, NOK 20 million ($2.2 million) Vantage Specialty Chemicals named Creyr
Foxconn is not expected to receive tax Innovation manufacturers’ representative
contract to update a F-35 test program set
credits from Wisconsin in the next three for its surface treatment technologies.
and provide a repair capability.
years, according to the state Department

EDITED by CHELSEY DRYSDALE MARKET WATCH
METALS INDEX OUT OF STORAGE

Trends in the US electronics % CHANGE
equipment market (shipments only) AUG. SEP. OCT. YTD%
Computers and electronics products 0.5 1.6 2.2 3.5
Computers -0.7 4.3 1.7 -8.5
Storage devices -1.3 -5.2 17.5 33.5
Other peripheral equipment 3.0 -7.9 2.1 9.5
Nondefense communications equipment 1.7 2.8 10.6 11.3
Defense communications equipment 6.2 -5.1 -0.4 5.9
A/V equipment -3.0 4.0 1.6 -5.3
Components1 0.7 0.3 0.9 10.0
Nondefense search and navigation equipment -0.8 0.0 2.6 -5.7
Defense search and navigation equipment -3.2 2.9 0.8 2.5
Medical, measurement and control 2.8 1.1 1.7 -1.1
rRevised.*Preliminary. 1Includes semiconductors. Seasonally adjusted.
Source: U.S. Department of Commerce Census Bureau, Dec. 4, 2020
US MANUFACTURING INDICES
JUL. AUG. SEP. OCT. NOV.
PMI 54.2 56.0 55.4 59.3 57.5
New orders 61.5 67.6 60.2 67.9 65.1
Production 62.1 63.3 61.0 63.0 60.8
Inventories 47.0 44.4 47.1 51.9 51.2
Customer inventories 41.6 38.1 37.9 36.7 36.3
Backlogs 51.8 54.6 55.2 55.7 56.9
Source: Institute for Supply Management, Dec. 1, 2020
KEY COMPONENTS
JUN. JUL. AUG. SEP. OCT.
Semiconductor equipment billings1 14.4% 26.7% 32.5% 40%r 26.9%p
Semiconductors2 4.9% 4.23% 4.94% 5.79%r 5.95%p
PCBs3 (North America) 1.12 1.00 0.94 0.93 0.97
Computers/electronic products4 5.44 5.28 5.22 5.15r 5.00p
Sources: 1SEMI, 2SIA (3-month moving average growth), 3IPC, 4Census Bureau, ppreliminary, rrevised
Hot Takes
was down an estimated 1.4% compared to the same quarter
■ The global wearables market grew 35.1% year-over-year in 2019. (SEMI)
during the third quarter, with total shipments reaching 125 ■ India has 268 mobile and accessories factories, more than
million units. (IDC) twice the number often quoted by many senior leaders in
■ Flexible hybrid electronics is expected to be an approxi- the government. (India Cellular & Electronics Association)
mately $3 billion market by 2030. (IDTechEx) ■ Fiberglass yarn and fiberglass cloth materials for PCBs saw
■ Desktop and notebook PC shipments are expected to grow a 20% increase in quotes, reflecting strong demand for 4.5G
18% year-over-year in the fourth quarter, followed by 1.4% and 5G applications. (TPCA)
growth in 2021. (IDC) ■ India has the potential to become a $100-billion global
■ Smartphone shipments are forecast to grow 2.4% year-over- manufacturing and export hub for printed circuit board
year in the fourth quarter, followed by 4.4% year-over-year assembly by 2025-26. (ICEA)
growth in 2021. (IDC) ■ The worldwide telecom EMS market was worth $155.7
■ The market for high bandwidth memory is projected to billion in 2019 and is projected to grow at a CAGR of 7%
grow 49% in wafers, including DRAM and logic layers, from 2020 through 2027. (Statista)
from 2020 to 2024. (TechSearch International) ■ Worldwide server shipments declined 0.2% year-over-year
■ Third-quarter world electronic equipment shipment growth to nearly 3.1 million units during the third quarter. (IDC)

ROI
Revealed: Technology Really Works!

Now, just how many people can we move off the floor?
THIS PAST YEAR was most unusual, distracting and processes, verifying and validating product, and gener-
challenging, and many of those distractions and chal- ating documentation. On a traditional shop floor these
lenges appear they will remain with us well into the tasks take place side-by-side by different employees
first half of the year. As industry begins to focus on with different skill sets.
post-pandemic planning, however, much has been The thought is if those responsible for the “soft”
learned over the past year that can and is being applied tasks do them remotely, it will reduce shop-floor traffic.
to planning for the future. Less traffic means fewer distractions and greater flex-
Possibly the most significant thing learned is tech- ibility, and there is less opportunity a “parking lot” will
nology can – and does – work! A generation of manu- develop as people chit-chat, reducing throughput and
facturing and technology leaders knew little of plat- efficiency. Wherever traffic is, you frequently end up
forms such as Zoom, WebEx, etc. Through baptism with an area filled with inert employees and products.
by fire, we have become believers in virtual interaction, Performing those “soft” tasks virtually, however,
its effectiveness and value. Equally significant is the requires more than just a Zoom account. And that’s
realization that for many business functions, includ- where creative process engineers are working to har-
ing those in manufacturing, remote working – aka ness sensors, test and measurement equipment and
working from home – works and offers much more basic automation with the anticipation that a reason-
flexibility than the traditional structured workplace. able happy medium can be achieved.
Manufacturers have by necessity reconfigured For years it has been possible to monitor equip-
shop floors to accommodate social distancing, clean- ment such as drill machines remotely. Likewise, com-
ing protocols, and all that has gone with the Covid puter-driven CMM equipment can be operated offsite.
pandemic. Adding space between production lines can Ditto for verification documentation, such as a FAI.
accommodate social distancing. But while effective, Employees who handle these tasks from home or in a
it has proven costly. Splitting shifts is another tactic. cubicle off the shop floor will continue to be the norm.
Employees may be willing today to change schedules But much of the other tasks in manufacturing are more
to keep a job; however, it is not ideal in the long term. challenging.
Meanwhile, in the office environment social distanc- High-volume manufacturing offers some oppor-
ing is accomplished via interactive technology. Further, tunity to lean out the shop-floor traffic as well. More
many claim the efficiency and flexibility from employ- than a few process engineers are looking at how to
ees working remotely and communicating virtually has reduce the number of people in a work cell by locating
been significantly better than they imagined. The office one or a few off the shop floor, while they still monitor
environment success and flexibility from harnessing the process or line. Staggering work-cell schedules, not
virtual communication technology has not gone unno- by multiples of shifts but by minutes, can also separate
ticed by the manufacturing manager. setup from operators from test and verification, col-
Over the past couple months, I have had many lectively reducing shop-floor traffic.
conversations with colleagues in our industry and High-mix, low-volume manufacturing environ-
other manufacturing fields about how to apply the ments have the greatest challenge to deploying vir-
lessons learned as we attempt to return to “normal,” tual interactive technology to reduce shop-floor traffic.
or as a “new normal” emerges. Much of the conver- And more opportunities exist. Creating data and tool-
sation has focused not on how to reduce headcount ing packages can be done remotely, as can much of the
PETER BIGELOW
is president and
and therefore costs, but instead on how to reduce the end verification and validation data creation. Staging
CEO of IMI Inc.; “traffic” and “parking” on the shop floor via harness- work through a network of onsite and offsite staff –
pbigelow@imipcb. ing virtual interaction technology to increase efficiency implemented thoughtfully – can increase flexibility and
com. His column and reduce process time. One of the observations I throughput and reduce traffic.
appears monthly. keep hearing is that with fewer people congregating on Finally, for those who thought Industry 4.0 was
the shop floor at the same time, product seems to move interesting, much of the past year has provided valida-
faster through work cells and from process to process. tion that the technologies are in place and work well.
Further discussion has centered on rethinking Many colleagues are moving feverishly to take advan-
manufacturing processes: separating the “hard” tasks tage of the available tools now that employees and
of manufacturing, which require an onsite human managers – many who have never imagined utilizing
operating a piece of equipment and touching product, such technology – are experiencing their power and
from the “soft” tasks, which are often monitoring convenience on a personal and professional level. •

BOARD BUYING
PCB Costs Are Going Up. Here’s What to Do

How to respond to supplier price increases.
DEMAND FOR PRINTED circuit boards is going up. But mium finish only when truly necessary. From a pricing
so are production costs. standpoint, there is more than one “metallic” way to
Raw PCB material pricing has jumped about 40% assemble a PCB.
since June, with the exact increase dependent on mate- Do you order the same part number and quantity
rial type. This price increase was inevitable and is, in monthly? If so, review those repetitive purchase orders
fact, overdue. and have a heart-to-heart talk with your customer.
During the early months of the Covid crisis, most Your PCB vendor would prefer to run a larger quantity
PCB suppliers were hesitant to pass on their already- when and wherever possible. Ordering a larger quar-
increasing material costs. But as China has rebounded terly quantity of PCBs and accepting them in monthly
faster from the Covid slowdown than the US and deliveries is a great way to get a discount.
Europe, demand for production has escalated. PCB Also, start leveraging your PCB spend with your
vendors are now more willing to pass higher material vendors. Have them visit (for now, you may have to
costs onto their customers. And the price increases are conduct a virtual meeting) and ask what else you can
by no means over. do to reduce costs. At the same time, remind them of
The price of gold salt and the precious metals used your annual spend and length of business relationship.
for metallic finishes of the PCB are on the rise as well. Have a serious discussion about performance issues.
While the cost for the application of ENIG finish is If your supplier intends to raise prices, demand those
the same regardless of the layer count, the percentage increased costs come with enhanced service.
of price increase is inversely proportional to the PCB Keep in mind, though, that the best way to keep
layer count, meaning a double-sided board will see a pricing in check is to always pay your PCB vendors on
higher percentage price increase than a 10-layer PCB. time. Timely payment will dictate the strength of your
To add insult to injury, American buying power relationships with suppliers. Habitually paying beyond
has fallen almost 6% since January as the value of the the agreed-upon terms can harm your business rela-
US dollar has declined against the Chinese RMB. tionship in a variety of ways, including lowering your
When it comes to PCB costs, we are in a perfect level of customer service, giving you less favorable pay-
storm. The price of raw materials, gold and precious ment terms in the future, and increasing your pricing.
metals is on the rise, along with production demand. The more you string out payments to vendors, the
At the same time, the dollar is weaker. That means less likely those vendors will be to jump through hoops
higher prices for US PCB buyers. – bending to price pressures, responding quickly when
Here’s the bottom line: You can expect over the an expedite is needed, or acting to resolve a quality
next few months to see an additional price increase problem – when you need them to.
of eight to 10% for doubled-sided boards, depending It always surprises me when a PCB buyer gets
on technology and quantity requirements. Multilayer upset when I inquire about late payment. If one of my GREG
PCBs are expected to rise five to eight percent. PCB shipments were late, that same customer would PAPANDREW has
However, PCB buyers may be able to fend off demand to know its whereabouts. Just as you as a more than 25 years’
some of those increases by buying smarter and more buyer demand prompt delivery of product, you should experience selling
PCBs directly for
strategically. also be a consistently prompt payer.
various fabricators
Putting PCBs in an array for ease of assembly A customer who doesn’t pay is not really a cus-
and as founder of a
makes sense, but I can’t tell you how many times I have tomer. That applies to your company as well. Paying
leading distributor.
seen wasted circuit board real estate when it comes to your PCB vendors on time increases their confidence in He is cofounder of
panelization design. More square inches mean a more you as a business partner, and you will reap the ben- Better Board Buying
expensive board. Buyers need to push back on their efits of that confidence over and again. It’s a big part of (boardbuying.com);
production and engineering departments by asking fostering a good relationship with your vendors, and greg@boardbuying.
questions such as, “Does this array really need to have it makes it much easier to get price concessions, even com.
rails this wide?” or “Can we score instead of route?” during tough times. •
Does every board you buy require a gold finish?
Yes, ENIG is lead-free; it has great coplanarity features
and a long shelf life. But does every assembly on your
production floor really need all those costly benefits?
Don’t allow a boilerplate company standard to
unnecessarily inflate costs. Be selective. Use a pre-

DESIGNER'S NOTEBOOK
Estimating the PCB Design Cycle with Limited

Information (and Then Making It Happen)
What Charlie Brown can teach us about board design.
NOT ALL BOARDS are alike. In fact, no two are exactly remaining funds.
the same. That’s kind of the point. We always do some- I once owned one of those operations. The worst
thing that hasn’t been done before, or we wouldn’t be possible outcome was that I would have to subcontract
doing it. The best we can say is many boards share simi- work out. In that case, it was more like being a broker
larities. Just the same, someone in every organization than a designer. If my plate was full, I would no-bid a
wants to know when the one-off job will be completed. proposal or quote a-higher-than-normal rate. Getting
Often, there is a predetermined schedule in which a lot of business in a short amount of time is a mixed
someone who has never drawn a trace decides when blessing.
the PCB layout needs to be finished. Such a schedule The mid-design updates trigger an ECO charge
is usually the result of market forces. It could be back- that can be quite substantial. The incentive is to quote
to-school, CES, or even (especially) a rocket launch an aggressive but doable schedule. Once underway, the
date that drives the deadline. Still, it’s not unusual for plan is to tack on fees if the design cycle is interrupted
stakeholders to ask your opinion about the estimated by improvements. Some customers appreciate they are
tape-out date. spending money to pull in the launch date. You want
repeat customers, so be careful not to overextend
Life in a service bureau or as an outside contrac- yourself.
tor. Service bureaus live or die by the accuracy of their One of the main metrics in the design cycle is the
bids. If their bid is too many hours, the customer will number of pins. Back in the day, it was a dollar per pin.
shop around. If the bid is too few, the designers end up Some pins matter more than others. A length-matched
eating that cost with overtime or, worse, missing the pin counts as three pins because you take more time
date and facing customer dissatisfaction. The one thing to dial it in with the rest of the bus. RF pins are two-
that saves them is that the service bureau is working for-one because of the expected back-and-forth with
from a baseline plan that does not usually include co- the analog engineer. As you build your portfolio, take
development. note of the actual vs. estimated duration so you can
JOHN BURKHERT A statement of work including a few milestones fine-tune your scheduling quotes.
JR. is a career PCB will put the customer in lockstep with the vendor. A New component footprints, whether built in the
designer experienced definition of success that includes the delivery date CAD tool or imported from a vendor or library ser-
in military, telecom,
will also have a few intermediate milestones, including vice, take time. You must take them into account for
consumer hardware
schematic capture, mechanical lockdown, placement the estimate. Of course, not all components are created
and, lately, the
approval, and so on (FIGURE 1). The hourly amount equal. Higher pin-count and fine-pitch devices are
automotive industry.
Originally, he was an
the service bureau charges is more than it pays the another weighting factor in the pin-count. Board den-
RF specialist but is designer. Even in a one-person shop, overhead comes sity is in play, too. Test fixtures will usually go more
compelled to flip the first, and the owner-operator gets paid out of the quickly than production form-factors. The stack-up
bit now and then to
fill the need for high-
speed digital design.
He enjoys playing
bass and racing bikes
when he's not writing
about or performing
PCB layout. His
column is produced
by Cadence Design
Systems and runs
monthly.
FIGURE 1. A scheduling tool helps keep the progress front and center.

DESIGNER'S NOTEBOOK
technology will be a factor of all the above parameters. a service bureau every night, it took just under three months.
It seems flippant in hindsight, but I used to ask how many That included Saturdays and short shifts on Sundays to keep
engineers are on the project. The old saying goes, if you want the outside vendors on track. In the end, schematic and outline
three opinions, ask two engineers. The various subject matter revisions were out of our control. It’s difficult enough when
experts believe their function to be the most important. Get- you have not done something before. When a brand-new team
ting mixed messages based on different priorities puts us on does something for the first time, count on half-again more for
the throne of King Solomon. There should always be a lead expected churn.
engineer who makes the final decisions. When conflicting The most optimistic people in the business seem to go
instructions come to light, loop in that leader. into program management. They may put the PCB designer
nominally in charge of driving the schedule, yet we have vir-
Captive designers: No plan survives contact ... Most of tually no authority over the team that ultimately determines
us are captive designers. The rule here is everything changes the outcome. It is easy to get ahead of yourself when working
except the tape-out date. Some of you may remember the Pea- alone at your desk.
nuts cartoon strip in which Charlie Brown would attempt to Adding to that uncertainty, some people are unconcerned
kick the football. Inevitably, his foil Lucy would pull the ball with the schedule in the first place. Perfection, or simply better,
away, leaving poor Charlie Brown on his back. It was a recur- is the enemy of good enough. Digital circuits either work or
ring theme: He never once got a foot on the ball. they don’t. It’s the analog engineers (I am one) who chase that
That’s a metaphor for board design if you’re expecting to last bit of performance. Prototypes will always require some
go from start to finish without a course-correction (FIGURE improvements, and you won’t know what those improvements
2). After Google bought Nest, one of the Nest PCB design- are until you have that first round of hardware.
ers wanted to join the Chrome team. I interviewed the guy
and recommended approval of his transfer. For one thing, he When it comes to schedule progress, sharing is caring.
knew how to code in Pearl and other tools for automating the Simply sharing the data at the end of each day may not be
drudgery. enough. Asking one question related to the work may be suf-
The program manager asked him for a time estimate for a ficient to get the other people to look at the design. You’re
complex smartphone breakout board. He was savvy enough to making design decisions all day long.
quote three months based on the usual co-development with a A real-life example goes like this: The vias under the SOC
large team. He was being too real, and the PM wasn’t having are too closely spaced to allow placement of the capacitors. We
it. Not knowing his projection when she asked for my opinion, have to find one mil somewhere. Should we reduce the via size,
I said two months, best case, but it would not surprise me if the pad size or the allowable pad-to-via airgap?
it went four. If you make that decision yourself, then you own the
That was also “too real,” so it became one of those team problem should one arise. Let’s say you take the third choice,
efforts. Even with partitioning and sending the design out to reducing the airgap from four mils to three. Then, two days
after tape-out, the vendor calls and says there
is risk of exposed metal because of solder mask
expansion. It’s a little late to be thinking about the
padstack options.
Getting to the end date with a viable board
takes strong communication. The more urgent the
schedule, the more you must be risk-averse. Res-
pinning that critical-path layout is a much bigger
schedule hit than taking the time to get buy-in on
the deviation. No one likes surprises. Take a cue
from Charlie Brown to avoid those traps. •
FIGURE 2. A Gantt chart helps visualize scheduling dependencies.

MATERIAL GAINS
Today’s Best Technologies are the Roadmap to an

Even Better Future
From autos to airplanes, change is in the air.
2020 HAS BEEN an unusual and challenging year, Hybrid-EVs and battery-electric vehicles as we
although many of us can be thankful for the resilience of know them today have some notable drawbacks. Car-
high-tech industries. Indeed, activity has surged in some rying both internal combustion and electric power
sectors, and generally the outlook is relatively buoyant. systems makes today’s hybrids heavier and more
In my other role as president of the EIPC (Europe- expensive than is ideal. Also, problems are associated
an Institute for the PCB Community), I moderated the with sourcing rare materials such as lithium, which is
Institute’s Technical Snapshot webinar last November, an issue because Li-ion is currently the most suitable
at which Dr. Shiuh-Kao Chiang of Prismark described battery technology. Natural lithium deposits are dwin-
how various sectors have fared. While 5G infrastruc- dling, although mining remains more cost-effective
ture rollouts slowed and handset shipments fell about than reclaiming the material from scrap batteries. Nev-
10%, the PC market has been buoyed by the increase ertheless, automotive electrification has helped create a
in work-from-home, and certain consumer markets sizeable market for Li-ion battery recycling that should
such as wearables and smart appliances have also done reach $17 billion by 2027.
well. Overall, he noted a surprising robustness across I’m optimistic the coming transition to hybrids and
the electronics, semiconductor and substrate markets. EVs will be just the beginning of our journey toward
The automotive sector has been among the hardest even better vehicles. They will be enabled by a variety
hit, along with conventional commercial aerospace. of technologies, some of which are already known,
Rebuilding after the damage to sales caused by the while others remain undiscovered. Prospects are great
pandemic is just one of the challenges facing vehicle for PCB stators, for example. These not only save the
manufacturers right now. They are also contending weight and losses of traditional laminated-iron cores
with the push toward higher levels of driving automa- but also allow direct integration of circuitry for impor-
tion, mandatory smart systems such as autonomous tant features such as sensing, condition monitoring,
emergency braking, and real-time V2X capabilities, and IoT connectivity.
which are expensive to develop. At the same time, Insofar as energy for EVs is concerned, the hydro-
governments are signaling their intentions to accelerate gen fuel cell could help relieve demand for lithium.
electrification, which will require all manufacturers to Easy and fast to recharge, it could alleviate range
move their entire product ranges to hybrid-electric or anxiety, while at the same time permitting a significant
pure battery-EV platforms. The UK government has reduction in battery size. On the other hand, this, too,
brought its intended start date forward to 2030. There could be a steppingstone toward another solution that
is no doubt about the urgency, although I am sure will be more efficient and safer, easier to live with, and
at least hybrid-EVs will prove a steppingstone to the ready to offer more rewarding experiences than any we
kinds of vehicles we use in the future. can imagine today.
Technical progress often happens this way. Consider In addition to road vehicles, shipping and aviation
where we are now with low-energy lighting, for exam- are elements of the transportation mix heavily depen-
ple. Filament bulbs were the dominant technology light- dent on combustion engines. The shipping industry is
ing homes and had changed little in a hundred years. As under pressure to move from traditional heavy fuel oil,
we saw the imperative to reduce the energy consumed with or without the use of exhaust scrubbing to remove
by lighting, we first adopted compact fluorescent lamps sulfur-based compounds, in favor of cleaner fossil fuels
ALUN MORGAN
(CFLs). Disliked for many reasons, they could be slow or, ultimately, electrification. Leading logistics busi-
is technology
to reach full brightness. The lumen output degraded nesses and technology developers are teaming up to
ambassador at
Ventec International
badly over time, and they presented a hazardous waste create solutions such as high-capacity marine batteries,
Group (ventec-group. problem at end of life. Clearly, the world needed to step high-power low-voltage diesel-electric hybrid drives,
com); alun.morgan@ beyond these and realize a better solution. and hydrogen fuel-cell generators. Ferries, which cover
ventec-europe.com. Today’s solid-state domestic lighting is enabled by short distances along fixed routes, could be the first step
innovations in LED fabrication, of course, and by the toward full electrification of long-distance shipping.
enhanced thermal performance of insulated metal sub- In the mission to decarbonize aviation, leading
strate (IMS) technology, developed within the PCB indus- aircraft manufacturers are taking their first steps with
try. We are now rewarded with even better lighting, not
only more energy-efficient than those early CFLs but with
improved reliability and more options than ever to create continued on pg. 38
various lighting effects to suit our moods and activities.

THE DIGITAL ROUTE
PCEA 2020: Small Rearview Mirror, Big Windshield

A successful first year promises even bigger things to come.
IN THIS MONTH’S forward-driving column, I glance industry professionals from all over, including Canada.
back at PCEA’s year in “rearview,” which included an
energetic jump-start, some challenging air filter retro- October PCEA Chapter Meeting
fitting, some remote diagnostics, and a final refueling Local chapter presidents Luke Hausherr (San Diego
at a successful virtual chapter meeting. Next, I hit chapter) and Randy Kumagai (Phoenix chapter)
cruise control and rely on PCEA chairman Stephen kicked off the meeting on Oct. 28 with greetings and
Chavez, who focuses on what lies ahead between an introduction to PCEA chairman Stephen Chavez.
the vanishing points of highways 2020 and 2021. As Steph gave an overview and called on people to spread
always, I’ll also point out some interesting events for the word that the PCEA was ready to fulfill its mission
you to consider attending. of leadership, membership and continually growing
industry sponsorship. Recent sponsor Insulectro deliv-
PCEA Updates ered a technical session on design innovation related
The past year can be viewed as one of the many good to PCB materials, given by VP of technology Chris
metaphors based on cars and driving, pointing out Hunrath and technical director of design education
the differences in size between a rearview mirror and Mike Creeden, who is also PCEA vice chairman (FIG-
a windshield. You only need to glance in a rearview URES 1 and 2).
mirror when backing up or trying to see what may be Topics covered included:
overtaking you. But if you’re driving forward, your ■ Design innovation
main focus should be on the large, clear windshield to ■ Hybrid stackup models
see what’s coming. ■ Material properties and considerations
2020 was a great year for the PCEA. It had to be ■ Effects of loss tangent
because it’s the only one we’ve had. A group of design- ■ Mixing laminates
ers, engineers and PCB industry professionals found ■ Embedded capacitance
themselves looking for a new role after the dissolution ■ Advanced HDI structures.
of the IPC Designers Council in November 2019. The After the presentation, the chapters hosted a raffle
group was not ready to hang up their passion for high- with some outstanding prizes. Luke selected the winners
lighting and representing PCB designers. Additionally, (FIGURE 3). The grand prize was a seat of PCB Library
they acknowledged a more intimate organizational Expert, thoughtfully provided by PCB Libraries.
structure was needed to better cultivate and grow
relationships with all vital stakeholders to understand Message from the Chairman
and communicate each other’s requirements during the by Stephen Chavez, MIT, CID+
vital phases of design, manufacturing, procurement
and test. What a year! We will never forget 2020. With every-
In January, meetings were called, and the group thing happening in the world today, it amazes me how
came together to prepare the vision and restart as a many have adapted to the virtual world, didn’t break
KELLY DACK, grassroots organization with a mission to collaborate, stride in meeting today’s challenges, and continue to
CIT, CID+, is educate and inspire the electronics industry to create be successful. Our industry’s evolution waits for no
the communication
better printed circuits. However, the group soon found one, and many have stepped up to the challenge and
officer for the Printed
themselves masked and quarantined, as did virtu- conquered it. When I think about how 2020 unfolded
Circuit Engineering
Association (PCEA).
ally all the electronics industry. Meeting over the past for the PCEA, we have far exceeded our initial expec-
Read past columns or months, the PCEA was forged and incorporated as a tations and goals for the year.
contact Dack; kelly. nonprofit. Stephen Chavez established this monthly From our grand opening on Jul. 14, our mem-
dack.pcea@gmail. column a few years ago, prior to the launch of the bership continues to see strong growth month after
com. PCEA. He delegated it to me after he was named chair- month. We are not only growing within the US, but
man of the PCEA. we also have internal growth. Our local and regional
In less than a year, the foundation of the PCEA PCEA chapters have seen momentum and success.
has been laid. The organization held its grand opening We now have 10 active domestic and international
event online and counts over 1,000 members among chapters, with eight chapters in their infancy and many
many local chapters itching to meet again. More others coming soon.
recently, the San Diego and Phoenix chapters hosted a What excites me most about the chapter activi-
successful virtual chapter meeting attended by over 50 ties is how each of the chapters is collaborating and
PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

THE DIGITAL ROUTE
Upcoming Events
functioning as one collective to better the industry. Even for
those of us who have been around for many years and actively ■ Mar. 8-12: IPC Apex Expo (Online)
involved within the industry, this chapter-to-chapter communi- ■ Apr. 13-15: DesignCon (San Jose, CA)
cation and activity has not been seen before. We truly have col- ■ May 10-12: PCB East (Marlborough, MA)
laboration, inspiration and education taking place, especially ■ May 11-13: IPC High-Reliability Forum 2021 (Baltimore,
within our chapters, from one virtual event to another. There is MD)
an exciting buzz within the industry about the PCEA. ■ Jun. 7-10: Zuken Innovation World (Scottsdale, AZ)
If these activities aren’t enough to make you want to join ■ Aug. 31-Sept. 3: PCB West (Santa Clara, CA)
the collective, then check out our industry affiliations and col- ■ Nov. 10: PCB Carolina (Raleigh, NC)
laboration, both domestic and international, which is seeing Spread the word. If you have a significant electronics
the same type of growth. Our sponsorships also continue to industry event that you would like to announce, please send
make strides as we continue to get positive feedback and buy- me the details at kelly.dack.pcea@gmail.com, and we will con-
in to what the PCEA is all about. And there are a lot of webi- sider adding it to the list.
nars offered for free, so take advantage of them when you can.
Our future looks extremely bright. For 2021, look for Conclusion
more activities, collaboration and synergy among all PCEA It’s sometimes a relief to look in your rearview mirror and
chapters. You’ll also see growth with our industry affiliates clearly see what you’ve left behind. But through a dirty wind-
and sponsors to solidify our mission to collaborate, inspire and shield, covered with Covid-19 and other challenges, it can be
educate. The year will be even better. daunting to drive forward without vision. At the PCEA, we
If you have not yet joined the collective, I highly encourage want to be the windshield wipers or the sponge and squeegee
you to do so by visiting our website at pce-a.org and becoming to help you wipe away your printed circuit engineering appre-
a member. hensions. Our collective will help you see where your industry
I continue to wish everyone and their families health and is going, inspire you to take the wheel, hit the gas, and enjoy
safety. I wish you all much success in 2021. the ride. Now is a great time to check us out at pcea-a.org
and make a New Year’s resolution to rideshare with us. We’re
Next Month in it for the long haul and have many experienced designated
As our leader, Steph is doing his job to set the vision, and the drivers.
PCEA executive staff will be meeting again soon. We will take See you next month or sooner! •
feedback from the local chapters and work with our sponsors
to make concrete plans for PCEA events to help the industry
connect and become more educated. I will report on the mate-
rialization of these evolving plans in our first column of 2021,
so stay tuned.
FIGURE 1. Mike Creeden. FIGURE 2. Chris Hunrath. FIGURE 3. Luke Hausherr.

MATERIAL MATTERS
Cutting Your Losses Upfront in PCB Design

A methodology for selecting the right material and the right price point.
WHEN I STARTED writing this column a couple years negative way, and the details need to be accounted for
ago, I wondered how much I’d have to say. An expe- across not just one PCB stackup, but across stackups
rienced media guy told me to watch my inbox for from every PCB fabricator involved with a design.
topics and questions that may be of general interest.
That turned out to be excellent advice. Here’s one such 5dB interconnect loss at 5GHz. Let’s say we’re tar-
example. geting 5dB total interconnect loss at 5GHz for a 15"
“What is the best laminate for a loss budget of x stripline run length using 0.5 oz. copper. We’ll ignore
dB for y inches? I was thinking in terms of Panasonic vias for this example and just focus on the laminate.
Megtron 6 or something like it.” Experience says this may require a material that’s
Megtron 6 is an excellent material, but it’s not indeed in the Meg6 range, but we don’t want to spend
cheap and it’s not the only horse in the race. My more money than we have to, so we’ll start with a loss
response was to focus on a loss and material-planning
methodology rather than making a firm material rec-
ommendation.
Why we care. Everything that improves material

performance – in particular, reductions in loss – comes
at a price. Loss versus cost is a classic optimization
problem. Designers want to pay just enough to meet
loss requirements, but not more than they need to.
In the past, speeds were slow, layer counts were
low, dielectric constants (aka Dk or Er) and loss tan-
gents (aka dissipation factor, or Df) were high, design
margins were wide, copper roughness didn’t matter,
and glass-weave styles didn’t matter. We called dielec-
trics “FR-4,” and their properties didn’t matter much.
As speeds increased in the 1990s and after, PCB fab-
ricators acquired software tools for designing stackups
and dialing-in target impedances. In the process, they
acquired PCB laminate libraries, providing proposed
stackups to their OEM customers, typically late in the
design process, including material thicknesses, copper FIGURE 1. Interconnect speed increases in gigabits per
thickness, dielectric constant and trace widths often second (Gbps) from 2000.
weeks or months after initial
signal-integrity simulation and
analysis should have taken place.
As speeds continued to
increase, design margins contin- BILL HARGIN
has more than 20
ued to tighten and OEM engi-
years’ experience in
neers began tracking signals in
PCB design software
millivolts (mV) and picoseconds and materials. He is
(ps). FIGURE 1 shows these trends director of everything
starting in 2000. Note in par- at Z-zero (z-zero.com);
ticular the PCI Express trajectory. billh@z-zero.com.
Critical factors for signal integ-
rity now include not only imped-
ance, but loss, copper roughness
and glass-weave skew. Indeed,
everything that happens in the
process of physically building a FIGURE 2. Our initial stripline configuration with Df=0.010 and a total loss of
PCB affects signal quality in a 8.82dB. (Image from Z-zero’s Z-solver software)

MATERIAL MATTERS
tangent (dissipation factor, Df) of 0.010 and see where we’re at surprises down the road or paying more than you need to for
for a starting point. laminate systems that are overkill for a design. Making these
choices early also allows you to avoid initial laminate lead times
FIGURE 2 shows the result, but some explanation is in order. The that can delay prototypes or early production. Because of pre-
blue line represents total loss, which is the sum of all other sourc- preg shelf-lives, fabricators carry only the laminates they know
es of loss. The orange line is conductor (copper) loss, which is the they can use within six months or less, following a just-in-time
sum of skin-effect loss (red) and copper roughness (magenta). approach. As in many other aspects of life, planning means
The graph shows loss in dB per inch, resulting in a total intercon- more options and fewer
nect loss of 8.82dB, a good bit above our target of 5.0dB. surprises. You can feed that
The next place I look is the insertion loss box, which is expensive signal-integrity
expanded in FIGURE 3. The two biggest contributors to loss solution Dk and Df data
here are the skin effect loss and dielectric loss, both at 0.24dB/ from the actual laminate
in. I know we can cut dielectric loss in half by cutting the Df system you’re planning
value in half, so let’s give that a try. Changing Df to 0.005 to use. Moreover, it may
results in a dielectric loss of 0.12dB/in. and a total loss of just allow you to hold to NPI
over 7.0dB – a significant improvement! Figure 3 also shows (new product introduction)
loss from copper roughness at 0.11dB/in. is very close to our schedules more consistent- FIGURE 3. The insertion loss
new dielectric-loss contribution. ly, while at the same time box, expanded from Figure 2.
The two biggest contributors
Figure 2 shows the core-side roughness for this hypotheti- relieving some of the pres- to loss here are the skin effect
cal laminate has an Rz roughness of 5.0µm. This corresponds sure you put on PCB sup- loss and dielectric loss, both at
to what many call RTF, or reverse-treated foil. I happen to pliers to make up for poor 0.24dB/in. (Image from Z-zero’s
know that materials in the 0.005 Df range generally offer planning. Everyone wins! • Z-solver software)
smoother copper either by default or as a loss-
reduction option. Let’s see what would happen with
VLP2 or “very-low profile, 2µm” copper. FIGURE
4 shows this change, along with the resulting total
interconnect loss, which is now 5.92dB – much
closer to our goal.
The total insertion loss is now 0.39dB/in. An
easy next step toward achieving our 5dB goal is to
create a routing rule that reduces the original 15" FIGURE 4. The trapezoidal shape of innerlayer traces, shown in a strip-
to 12". Let’s make that change and see where we line cross-section, where w2 is narrower than w1. (Image from Z-zero’s
end up. Z-solver software)
Voila! Total loss becomes
4.74dB. We now have a Df
target for a laminate sys-
tem, a copper-roughness
selection, and a routing rule.
That’s a lot of progress early
in the PCB design process.
We can now begin looking
for a material that aligns
with these parameters.
Two good places to ini-
tiate that search are with
your PCB fabricator(s) or
from laminate-vendor data.
Several materials that may
be worth looking into are
shown in FIGURE 5, based
on their vendor-published
Df numbers at 5GHz.
Wrapping up. If you can

make material decisions like
this early in the design pro- FIGURE 5. Materials to consider, based on their vendor-published Df numbers at 5GHz. (Image
cess, you’ll avoid prototype from Z-zero’s Z-planner software)

DATA TRANSFER
NEW DFX MODULE for IPC-2581 Slices

Design-Manufacturing Time, Errors
The latest IPC-DPMX standard offers unique bidirectional data
exchange between design houses and their manufacturing
partners. by HEMANT SHAH
The authors of IPC-DPMX, previously known as IPC-2581, the only functional module in an IPC-2581 file, or it can be
have come up with an innovative solution for addressing the included with the rest of the design data. Both fabricator and
needs of the industry for the latest version of the electronics OEM can create databases of issues for root cause analysis and
data transfer standard. Developed by the industry, IPC-DPMX improvement. Over time, this enables designers and manufac-
has many new enhancements. The just-released Revision C has turing partners to track responses to queries, collecting metrics
been reviewed and unanimously approved by the PCB design, over a period by class of design and by manufacturer/customer.
analysis and supply chain industry. With IPC-2581C, the manufacturer (fabricator or assem-
IPC-2581B introduced the concept of bidirectional data bler) and designer can use their specific viewing formats, while
exchange between design houses and their manufacturing sending the information in a neutral format. This avoids the
partners. It sought to eliminate the back-and-forth between need for fabricators to use customer-specific TQ formats.
partners at the very end of the design cycle for communicat- Product engineers can use a single, standardized GUI.
ing and ensuring that critical net impedances were achievable. The approved DfM files can be electronically stored within
This communication was important earlier in the design cycle the IPC-2581 file instead of on an engineer’s hard drive or
and impacted the layer stack-up, which is hard to change at another database.
the end, when design is complete and handed off. Although Some of the changes in addition to DfX module in revision
this innovation was unveiled almost seven years ago, it is still C include:
unmatched and unique within an open standard. ■ Overhauled support for rigid-flex, with support for mul-
Fast forward to 2020. IPC-2581C brings yet another tiple stack-ups by rigid-flex zones, as well as complete bend
innovation driven by consortium members who saw one more information that includes bend line, bend area, bend order,
thing that slows them down at the very end. When a design is bend type, direction, radius, and angle (FIGURE 1).
handed off, the manufacturing partner often wants to check ■ Support for embedded components (face-up/down – mir-
how efficiently the design can be built, including a look at the rored/not, pins on top) (FIGURE 2).
capability check, as well as any DfM errors within the design. ■ Impedance requirements can now be defined per logical net
Over 90% of finalized designs have DfM errors, some repeat- or physical net segment, in addition to the traditional per-
ed in every design. There is then a back-and-forth between layer or per-stack-up methods.
design and manufacturing to address the issues. Many times, ■ Impedance or attenuation requirements can now be expressed
manufacturers want something in writing in order to deviate in terms of loss (dB/inch or dB/mm). Also, power, signal or
from the very standard the designer wants the manufacturer to voltage loss can be defined for test or other purposes.
follow. This exchange and settlement can cost both companies ■ Ability to specify net-shorts for RF circuits or other circuits
time and effort. It’s a lose-lose situation. that have been intentionally shorted.
The result was that the consortium, with key contributions ■ Pin polarity support enhanced – component pins can now
from Cisco, proposed a new function mode: a module for DfX be tagged with a property to specify polarity, for example
sign-off between the designer and manufacturer that eliminates plus and minus for a polarized capacitor, or anode and
e-paper-based communications that are time-consuming and cathode for a diode.
frustrating for both sides. ■ Ports definition for wire bonds to custom or off-the-shelf
The DfX module within IPC-2581C enables OEMs and ICs, connectors to daughtercards, and pads to custom ICs.
manufacturers to communicate in a bidirectional manner any The custom ICs and daughtercards can be defined in a dif-
DfX error and technical queries. The DfX module can be ferent step to the main board step, creating a hierarchical

DATA TRANSFER
board structure within the same IPC-2581 file (FIGURE 3).

■ Component support enhancements, in addition to embedded compo-
nents, include formed/printed components, negative body extension for
package body below pins and silkscreen/outline/assembly on opposite
side of board.
■ Simple 3-D shapes to define coins or other objects (FIGURE 4).
■ Edge plating.
IPC-DPMX (IPC-2581) revision C provides an innovative solution for
addressing the needs of the industry.
Revision B saved design houses and manufacturing partners time that
was otherwise wasted toward aligning both parties on the design expecta-
tions. With a unique and previously unmet need for intelligent, traceable
bidirectional DfX exchange to complete support for rigid-flex PCBs to
embedded component support, IPC-2581C streamlines design handoff
and manufacturing intent communication, saving time. It remains the only
open, neutral standard that can do this, and enables smart factory automa-
tion when used in conjunction with IPC-CFX. •
HEMANT SHAH is an EDA veteran and chair of the IPC-2581 Consortium

(ipc2581.com).
Listen to the IPC-DPMX authors discuss the new standard on the PCB Chat
podcast (https://upmg.podbean.com/e/pcb-chat-episode-66-the-ipc-2581-
consortium-on-electronics-data-transfer).
FIGURE 1. The new spec supports rigid-flex with

multiple stack-ups (top) and all types of bends (bot-
tom).
FIGURE 2. IPC-DPMX supports all types of embed-

ded components.
“Polar's customers in the design and

PCB fabrication community wel-
come a move to a consistent format
for data transfer that permits effi-
cient and open communication be-
tween the designer's tools and the
fabricators environment. Polar com-
mits to support both export and FIGURE 3. Custom ICs like wirebonds can be defined
import of IPC-2581 compliant separately from the main board.
stackup data from Speedstack PCB
and Speedstack Si.”
— Martyn Gaudion
Polar Instruments
ipc2581.com FIGURE 4. Thermal relief coin.

CHIPLETS
Chiplet Implementation via VIRTUAL

PROTOTYPING
Assessing the cost vs. performance tradeoff. by STEVE WATT
In the evolution of silicon implementa- maximum results via virtual prototyping. Physical design and prototype costs are
tion, creative solutions to costly problems Virtual prototyping is inherent in rising rapidly. They are becoming cost-
have become standard practice. One of all types of designs, be they mechanical, prohibitive in a technical universe that
these solutions is the use of a “chiplet.” electrical, structural, or electronic. Using continually demands new and unique
A chiplet is precisely what it sounds like: software that allows entered data to functionality.
a smaller version of a chip. This doesn’t create various permutations of complex To develop a 5nm chip may cost
mean it’s a miniature version. It means integrated circuits in a 3-D view with $600 million or more. The high price
that only critical functions that derive many underlying performance charac- of development has stirred interest in
significant benefits from a 5 or 7nm fab- teristics and configurations is a boon to exploring more cost-effective options.
rication process are included on the chip. today’s electronic designers challenged In addition to cost, packaging is an
Other functions that will work well with with meeting cost and specific perfor- issue. In 2019, the VLSI Symposium
10nm or greater can then be fabricated mance measures. surveyed attendees regarding semicon-
with appropriate cost savings. Using an integrated design environ- ductor integration using 3-D packaging
Chiplet technology creates a chal- ment for single and multi-die, or chiplet technologies. Specifically, respondents
lenge, however. If all functions were packages for wire-bond, flip-chip, and were asked about the use of advanced
included in the chip, the interfaces could high-density advanced packaging, elec- packaging integration for logic, logic to
more easily be measured and evaluated. tronic designers may harness the capability memory, or logic to analog RF technol-
These items now must be accounted of early prototyping using different chips ogies, or all the technologies combined.
for on a package or, more accurately, a and package data. This enables design- They all indicated significant interest in
system-in-package (SiP) (FIGURE 1). This ers to quickly evaluate design iterations shifting advanced packaging interven-
places greater importance on the electri- while leveraging various wizards built tion via chiplet integration.
cal characteristics of those interfaces and into the packaging prototype software. How can electronic package design,
how that SiP implementation affects that These iterations can be evaluated against using a chiplet approach for heteroge-
behavior. Thus, there is a need to rapidly performance goals and cost estimates neous integration, lead to cost savings
assess these issues with minimal effort for to arrive at the best solution. If needed, or other advantages?
updated assign- At the forefront of savings is reduced
ment informa- die size. The smaller processor die size
tion can be passed reduces the cost of the processor. Less
back to the chiplet silicon is used when designing to the
design and into the higher nanometer ratings. A smaller die
PCB domain. size leads to higher yield and increased
reliability. Using different technology
Cost Savings nodes for the processor – vs. the memo-
As mentioned, a ry – can also realize cost savings.
significant advan- With a more generic approach using
tage of chiplet chiplet integration, a chip can be shared
implementation across multiple products; design once,
FIGURE 1. Example of a system-in-package (SiP) design. is cost savings. then spin off into multiple different ver-

CHIPLETS
sions. The design is economized. ■ Check that design goals and objectives converge on an ideal solution.
are being met, and the overall design ■ Incorporate bump changes due to
Chiplet Integration Advantages approach is viable. die or package optimizations without
When it comes to package design, the 4. Achieve rapid prototype design objec- restarting the design flow.
following advantages of chiplet integra- tives:
tion have been identified. ■ Enable the iteration of feasibility stud- Practical Use Cases
1. Achieve partitioning to create multi- ies with a short turnaround time with The scalability afforded by a chiplet
chip “floor plans”: chip and package prototyping design approach to heterogeneous integration
■ Consider power distribution, both for performed simultaneously. has led to cost and power savings in spe-
package die and off-die. ■ Enable autorouting between chiplets cific applications:
■ Achieve desired power efficiencies and chip to package, and determine ■ Intel’s embedded multi-die intercon-
within specification. tradeoffs and changes as needed. nect bridge (EMIB) or Foveros (Fove-
■ Attain verifiable connectivity to sup- ■ Ensure seamless power and signal ros is a high-performance 3-D inte-
port standard protocols. integrity verifications during design to grated circuit), or a hybrid of the two,
■ Reduce or minimize crosstalk and allow front-loading of the design and enables Intel to restrict die size and
noise. converge viable configurations. permits it to be economically manu-
■ Evaluate and manage any thermal 5. Achieve efficient bump placement: factured with a conventional yield.
issues. ■ Achieve design bump placement and ■ AMD has a 32Mb core “Zen” archi-
■ Support a power delivery architecture I/O cell floor planning while ensuring tecture. With a design split into four
aligned with the specifications. routability and electrical character- chiplets, the cost is reduced by as
2. Achieve heterogeneous integration istics. much as 60%.
and consider all factors influencing ■ Synthesize bump placement, bump net ■ Nvidia produces a ground referenced
SiP design: assignment, and I/O cell placement signaling (GRS interconnect). It per-
■ Resolve multiple interfaces between within specified design constraints. mits low-power data transfer among
different tools for the chip design and ■ Allow flexible tile configurations to the dies, with scalability. This scalabil-
SiP design. ity enables notable cost
■ Enable feasibility stud- savings.
ies at the conceptual Virtually prototyp-
design phase. ing ICs is inexpensive and
■ Rapidly evaluate dif- cost-effective. We tested a
ferent approaches and situation where CPU core
determine the best path chiplets were placed on a
forward via feasibility fan-out wafer-level packag-
studies. ing (FOWLP). The chiplet
■ Verify any informa- size was 2.5mm x 2.5mm.
tion from the proposed The chip had eight inter-
design against original face blocks facing down-
details, giving due con- ward, upward, right and
sideration to different left. The interface block
FIGURE 2. Waveform analysis of signals on the SiP.
tools used. [FIGURE 2] was 0.45mm x 0.6mm.
3. Achieve a more flexible The SiP or package size
design environment: was 15mm x 15mm with
■ Establish a seamless four layers and lines and
integration between spaces of 5µm.
the IC or chip, pack- In chiplet prototype
age, and PCB. design, the top bump
■ Enable an ability to cells were created and
move between differ- utilized as templates for
ent fabrics as quickly bump placement. Chiplet
as possible. bumps in I/O cell floor
■ Be able to merge fab- plans were then syn-
rics as needed and thesized. I/O cells were
verify their respective then placed in consider-
connectivity is aligned.
■ Ensure rapid analysis
capability exists in the FIGURE 3. SiP-level routing of the two different configurations under con- continued on pg. 44
initial design phase. sideration.

HDP
Are OLDER STANDARDS Still Valid,

or Holding the Industry Back?
That’s one of the questions the new leadership at HDP plans to
address in 2021. by MIKE BUETOW
This month Marshall Andrews stepped down as the longest- MB: And that industry has changed a lot over the past
serving head of The High-Density Packaging (HDP) User few years. It’s not just Tesla. All the automakers are get-
Group. But as Larry Marcanti assumes the role of executive ting into electric vehicles, and the electronics for EVs
director of the decades-old electronics consortium, don’t aren’t like your everyday Honda Accord. These are really
expect big changes. high-power boards.
On Andrews’ 15-year watch, HDP’s membership increased
by more than 30 companies, to reach more than 50 total. The LM: Right. We’re talking about performing CAF testing at
ongoing project portfolio rose from five to an average of 25 1500V and not electrocuting the testers. We have problems
member-driven activities. like that, which most folks in our industry haven’t faced head-
Despite the Covid-19 lockdown, HDP is coming off one on before.
of its most successful years yet, having completed 13 projects. We developed a skeleton automotive project and are look-
Marcanti and HDP facilitator John Davignon gave an ing to get OEM input for it. We have reached out to several
update of the consortium’s latest work and future plans in companies for input. That project is focused on providing
an exclusive interview with PCD&F/CIRCUITS ASSEMBLY in a high current/voltage guideline for building PWBs for the
December. 800V+ EV and HEV automotive industry.
We have an outline of a project now, but to make it rele-
MB: Larry, you’ve taken over as executive director from vant, it takes someone working in that business to give us input
Marshall Andrews. Do you see any major changes to the on their key issues. We are in the infant stages of that now.
goals of the organization going forward? Longer-term, we’d like to get back out like everyone else
and do more traditional networking and collaboration.
LM: We had a pretty successful run with Marshall at the helm.
I don’t see any major changes going forward, except maybe MB: How do you ensure there’s no overlap or redundancy
bringing in more from a “technology futures” perspective. Our with consortia like iNEMI that are also working on automo-
members are interested in understanding more about where tive electronics?
the technology is going. We are looking at ways to talk to other
groups and consortia to view where they are and cover that LM: We communicate quite a bit with them. We collaborated
with our membership to look at the key future technologies. with iNEMI on the Harsh Use Environment Alloy project. It’s
Automotive is an example of that. We (HDP) don’t have not smart for our members to have two separate projects doing
any automotive-centered companies. We had a webinar where the same thing.
we had different folks from the automotive sector come in We will have a similar approach to automotive.
and talk to better understand it ourselves. We have many We also have a class of projects called emerging technol-
suppliers and OEMs in our group. We’ve traditionally been ogy. We’ve looked at novel ways of building PCBs. We have
focused more on networking equipment. Covid has thrown us also looked at products that are used in harsh-use environ-
for a loop. We had planned for an automotive workshop in ments. New solder alloys are touted to be better for harsh-use
Europe this past May to get more automotive representation. environments. Autos operate in harsh-use environments, and
We wanted to get more of the supply chain involved. Automo- automotive electronics companies may see a benefit in the
tive companies are also more proprietary about what they are future.
doing insofar as electronics is concerned.

HDP
MB: I suppose Covid interrupted a proper send-off for will be if everything must be requalified because of the e-glass
Marshall. style changes. If the property changes more than the limits
allow, they might have to retest, which will be a burden for the
LM: We plan on doing that at our next opportunity to meet industry. We are evaluating if that’s a need.
face to face. We are targeting that for spring.
MB: With regard to the glass type comparison, can you
MB: Is Marshall retiring? talk about how those evaluations are done? Will new
tests be needed?
LM: He is taking a different role. Marshall will still be active
in HDP. His title is executive director emeritus. He will give JD: That’s a good question. Right now, UL 746A allows a
counsel to me and give his two cents to the board of directors 15% difference in flexural/tensile/impact strength and 10%
whether it’s asked for or not. (laughs) for dielectric strength. If there’s a >15% difference, UL consid-
ers it to be a different
MB: Was his decision material. We are just get-
a recent one or some- ting the results now to
thing that he planned? determine whether the
new low Dk glass lami-
LM: Marshall let the nates are inside or out-
board know. They did side that range. We may
an executive search for learn whether we need
a new leader. I was suc- a different type of test,
cessful in getting that but at this time, we are
position. evaluating the standard
test protocol. Glass was
MB: What else should never really thought of
we be looking for from because it was always
HDP in 2021-22? “e-glass”; it was “just
an inert structure of the
LM: I see 22 active proj- composition.” Many
ects right now. We com- standards didn’t look
pleted 13 projects last at this; it was always
year – that’s a record. Does the industry need to change the way it assesses e-glass? the resin and fillers that
Maybe because every- required new testing.
one was home. (laughs) But that’s changed. UL
We always have new projects coming. There are three new is the HDP project leader on this, so it’s not a matter of having
ones. to sell them. They are helping to make this determination. We
The Harsh Use Alloy Evaluation 2 project is looking at have an HDP member who is really asking the question, and
increased dwell times. Some of these materials have very dif- we have a lot of suppliers and OEMs who always have a lot of
ferent metallurgies. The typical ATC testing uses a 10-minute skin in the game to help with samples.
dwell time; we are now looking at a 60-minute dwell time to
better understand alloy degradation using a dwell time more MB: Is the 15% limit arbitrary, and if so, do we need to
characteristic of service conditions. change that?
Then there’s the Automotive PWB project and a new one
for copper peel strength. JD: I can’t comment on that. We are in the data-gathering
phase. If everything came up 18%, should we move the cutoff
JD: We are looking at standards and guidelines for some of to 20%? I don’t know. UL is there to make sure things are safe,
our projects. The Copper Peel Strength and Glass Type Com- and the industry is protected. I don’t know how they would
parison projects are looking at older standards. We are ques- arbitrarily move a spec, but once we get the data, we might be
tioning if they are still valid, or are they holding the industry able to do that analysis. Maybe the mechanicals aren’t the only
back? For copper peel strength, what’s the peel strength you way to look at it. Perhaps long-term aging, which has always
really need to build a board, and are they keeping the copper been a significant part of the testing, will give more insight. It’s
suppliers and OEMs from moving into higher speeds? hard for me to imagine the glass would affect the resin/filler
For glass, it’s questioning all the new glasses, like low-loss structure for that, but we are right at the cusp of finishing the
and low Dk glasses; are they an entire class by themselves,
and does UL need to test everything coming our way? Or are
their fundamental properties similar to e-glass, and can they be continued on pg. 38
allowed without retesting? You can imagine how upsetting it

Recent Chats:
CAF and
Electrochemical
Migration
with
Graham Naisbitt
Changes in the
Mainstream PCB
CAD Market
with
Manny Marcano
Solder Voiding
with Tim O’Neill,
Prakash Gango,
Kalyan Nukala,
and Mike Konrad
upmg.podbean.com
The PCB Podcast

ELECTROCHEMICAL RELIABILITY
PROCESS CONTROL PLAN to

Monitor Acceptable Levels of Flux and
Other Residues
Because electrochemical failure risk is site-specific, different
components need different plans. by BILL CAPEN, JASON EDGAR,
DR. MIKE BIXENMAN and MARK MCMEEN
Highly dense electronic assemblies incorporate bottom-termi- the system is in operation, the electrical field attraction of the
nated components. Miniaturized components create numerous positively charged metal ions migrate to the negative conduc-
challenges, resulting in a shorter distance between conductors tor. These metal ions can plate small dendrites, resulting in
of opposite polarity, solder sphere size reduction, low-standoff leakage currents and/or parasitic leakage. As such, ionic resi-
gaps, flux entrapment under the bottom termination, blocked due testing is used to test for problematic residues that could
outgassing channels, and more significant potential for leakage hinder reliable circuit function.3
currents.1 The core concept for materials compatibility and residue
In the presence acceptability is a qualified manufacturing process (QMP).4
of humidity, mois- In a QMP, the manufacturing materials and processes used
ture (mono-layers to produce electronics hardware have been benchmarked and
of water) hydrogen validated against electrical performance in hot/humid condi-
bonds with ionic tions. The art of characterizing what chemical residues exist
contaminants to on a manufactured assembly allows an assembler to determine
create an electro- the impact of those residues on electrical performance. The test
lytic solution. Ions methodology is useful in developing a risk profile.
such as flux acti- After a manufacturing process has been qualified, the next
vators can dissolve step is to define how to monitor that qualified manufactur-
metal oxides pres- ing process for ionic residues. The establishment of an ionic
ent in the flux resi- process monitoring plan is a requirement for mission-critical,
due at the soldered high-reliability electronic products. The sampling plan for
FIGURE 1. QFN-88 that failed SIR testing. connection.2 When ionic residues should be periodic, and with sample sizes such
that a manufacturer has confidence,
the process is in control.
High-Performance Electronic
Products
The classification we build products
to is IPC Class 3/A. Class 3/A boards
call for very stringent manufacturing
criteria, since the boards must remain
operational in critical conditions. The
electronics must provide continued
performance and performance on
demand. When deployed, there can be
no equipment downtime. The prod-
ucts must work correctly every time.
Processes for building the elec-
tronics must be qualified and vali-
FIGURE 2. Failed SIR testing result. dated. No process residues are accept-

Process Control Plan

able. Once validated, there must be a process control plan.
Site-specific characterization on components with the highest Temperature-Humidity-Bias (SIR test method) was studied
probability of electrochemical failures is required to ensure for use in developing a process control plan. Our opera-
every component is reliable. tions favor electrical resistance measurement methods. The
Materials characterization must be in compliance with IPC reason: Electrical resistance measurement permits detection
J-STD-001 [Rev. F – H] Amendment 1, Cleanliness. Testing of process residues that are both ionic and non-ionic. These
requires custom test boards that detect electrochemical reliabil- process residues are located under the components’ termina-
ity across different component designs. Once qualified, there tion and commonly bridge conductor pathways. The residue
must be a process control plan to monitor for cleanliness on is not visible to existing process control methods, specifically
challenging components and processes that are representative the resistance of solvent extraction (ROSE). We are looking
of production hardware. for process deviations. Is our process consistent lot-to-lot? Is
Highly dense electronics are now designed with miniature there variability?
components. Designs require leadless and bottom-terminated IPC pass/fail for SIR testing is 8 Log10Ωs. For this experi-
components. These component types create numerous chal- ment, we decided to build in a margin of safety by setting the
lenges. The problem is these components trap flux residues lower SIR limit at 8.5 Log10Ω resistance. FIGURE 3 illustrates
under the bottom terminations. They are harder to clean. With the mean insulation resistance on a specific component. The
a tighter pitch, there is a shorter distance between conductors of lower and upper limit was set from 8.5 Log10Ωs to 12.0
opposite polarity. Tighter pitch poses a greater risk to reliability. Log10Ωs. The chart shows all 10 boards tested were within the
FIGURE 1 is a QFN-88 component that had partially specification range.
cleaned flux residues left under the bottom termination after
cleaning. Surface insulation testing detected leakage currents. Research Hypotheses
The components were sheared off the board and inspected. The following are our temperature/humidity/bias hypotheses:
Monitoring for these types of defects on high-risk components 1. Electrical resistance measurements under bias and elevated
offers a useful process control method. environmental conditions are long-accepted quality metrics.
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2. The first hours of a test card subjected to temperature/ • For this experiment, analyze the data within defined
humidity/bias voltage represent the most ionic activity/ periods.
change. The SIR testing unit process control module allows the
3. This change can be used to determine the similarity of the user to create and manage their test boards. Specific fields
process. (Similarly cleaned and produced boards should enable one to set up a particular process control profile. For
have similar starting resistance values, end resistance values, each channel on the test board, the user can name the profile,
and general curve shape.) and set an upper and lower specification limit. Other settings
4. Deviation in process should be visible as a change. include time duration, measurement interval, temperature,
relative humidity, bias voltage, and measurement voltage.
Test board. QFN-88 and QFN-124 components were selected
for this study. A custom SIR test board was designed with the Data Findings
QFNs horizontally positioned in Q1 and Q2. The QFNs were Twenty test boards were assembled and cleaned using defined
rotated 45° in Q3 and Q4 (FIGURE 4). process settings. The test boards were subjected to SIR testing
The 0.5mm pitch QFN 88 chip is representative of produc- using the following settings:
tion hardware (FIGURE 5). The tight pitch and large thermal ■ Temperature: 40°C
lug are useful in defining cleanliness levels under similar com- ■ Relative humidity: 90%
ponent package styles. This part can be used to test no-clean ■ Bias voltage: 5V
flux systems for SIR cleanliness levels and to determine wheth- ■ Measurement voltage: 5V
er the cleaning process is capable and efficient in achieving the ■ Measurement interval: 5 min.
desired SIR levels for these types of component packages. Results were analyzed over a variety of periods. Baseline
The 0.5mm pitch QFN-124 BTC has a dual-row pin-out ROSE testing was performed on test samples.
with ground lug, which makes this particular BTC more chal- FIGURE 7 is a chart of the SIR results for board #11. Chan-
lenging than the standard QFN package style, which is a single nels A&D represented the QFN-88, and Channels B and C
row around the periphery of the package (FIGURE 6). represented the QFN-124. The QFN-88 values were below
the lower limit, which is not acceptable. The QFN-124 values
Experimental were acceptable.
Phase 1: Data collection.
■ Perform a series of temperature-humidity-bias tests with the In a review of the data, we noticed parallels between the
same card to monitor process deviations. early-stage data and the full 168-hr. data that supported our
■ Perform ROSE as a direct comparison. hypothesis. FIGURES 8 to 11 show the mean data for each of
■ Collect the raw data and analyze the data for statistical the 4-channels on all 20 test cards in our data set.
significance within several blocks of time: first 30 min., first Following SIR testing, each of the 20 boards was ROSE
hour, 2 hr., 6 hr., etc. tested (FIGURE 12).
Phase 2: Process deviation monitoring. Data Analysis

■ Tests must all be run under the same conditions. ■ Data was initially plotted in its entirety to look at overall
• Ramp speed of the chamber will be a factor, so it will be trends.
critical all tests are run with the same chamber. ■ A smoothing function was applied to visualize the trend in
• Chamber control feature should be used on a powered- the data better.
down chamber to ensure all tests start under the same ■ General observations:
ambient conditions and rise in a similar fashion. • The dual-row QFN-124 SIR profile appears to be more
■ Tests must all end at the same time. promising due to a tighter standard deviation.
FIGURE 3. Electrical resistance of 8.5 – 12 Log10Ωs. FIGURE 4. SIR test vehicle.

• QFN-88 had a relatively uni-

form spread of data over the
range of 7 to 11 Log10Ωs.
Many data points were below
the lower limits. Clearly, the
cleaning process was not
properly dialed in to clean
this part within the upper and
lower specification limits.
• The higher variation QFN-88
results in a higher standard
deviation. A higher standard FIGURE 5. QFN-88 single row dimensions. FIGURE 6. QFN-124 dual-row component
deviation indicates a lack of dimensions.
consistency with regard to
ionic residue present at the
signal pins and under the component termination.
FIGURES 13 and 14 represent the average SIR values per hour

of testing. The mean and standard deviation were plotted over
time (FIGURES 15 and 16). The following observations were
made:
■ SIR value tends to start to flatten out around 50 hr.
■ Specific periods had larger variation than others.
■ This is probably noise-related.
Inferences from the data findings. Electrochemical risk fac-

tors are not consistent across a printed circuit board; instead,
they are specific to components that trap residues under the
bottom termination and next to signal pins. The data find dif-
ferent meaningful results between the QFN-88 and QFN-124.
In this study,
■ QFN-88 was harder to clean. FIGURE 7. SIR test values for board #11.
■ There wash higher variability.
■ QFN-88 had many unacceptable results.
Research Hypotheses
Temperature-Humidity-Bias Environment Hypothesis #1: Electrical resistance measurements under bias
■ Induces defects from ionic residues on targeted components. and elevated environmental conditions are long-accepted
■ Induces defects from non-ionic residues on target compo- quality metrics. Hypothesis #1 is accepted for the following
nents. reasons:
■ These defects are reflective of undesirable process devia- SIR testing is considered the gold standard for detecting
tions. ionic contamination. SIR is the best test method for determin-
■ Electrochemical risk is by nature site-specific, rather than an ing the electrochemical reliability of:
average risk assessment. ■ High-density interconnected board designs populated with
miniaturized leadless and bottom-terminated components.
Inferences include: ■ Multiple soldering operations that include SMT compo-
■ The large standard deviations on the QFN-88 component nents on the top and bottom side of the board.
require more work to optimize the cleaning process. ■ Through-hole processes using both wave and selective sol-
■ Temperature-humidity-bias testing is useful to determine the dering.
similarity of the process. ■ Rework and repair operations.
■ A shorter SIR test time can detect process deviations. ■ Conformal coating materials characterization.
■ Contamination is not consistent across the PCB.
■ Some component types are at greater risk of electrochemical Hypothesis #2: The first hours of a test card subjected to
failure. temperature/humidity/bias voltage represent the most ionic
■ ROSE testing is not a predictable method for site-specific activity/change. Hypothesis #2 is accepted/rejected for the fol-
testing. lowing reasons:
Accepted: When ionic contamination is present, SIR will
be lower at the beginning of the test. The QFN-88 insulation

FIGURE 8. QFN-88 Channel A charts plotted over different time FIGURE 9. QFN-124 Channel B charts plotted over different time
periods. periods.
resistance had lower insulation resistance at the beginning of accepted SIR test method. The first hours clearly detect process
the test. As the test ran, the insulation resistance improved due contamination that reduces insulation resistance.
to the ionic residue drying out and not being mobile in mono-
layers of water present in the humid environment. Hypothesis #4: Deviation in process should be visible as a
Rejected: A short test period does not detect leakage cur- change. Hypothesis #4 is accepted for the following reason:
rents and dendritic formations. These typically require longer The QFN-88 was clearly different from the QFN-124. Process
test time to form and propagate. contamination was detected.
Hypothesis #3: This change can be used to determine the simi- Conclusion
larity of the process. (Similarly, cleaned and produced boards Electrical testing results, with power on during extremes of
should have similar starting resistance values, end resistance temperature and humidity, detect the presence of ionic con-
values, and general curve shape.) Hypothesis #3 is accepted tamination. The challenge industry faces today is the risk
for the following reason: The research finds that much can factor for electrochemical failures is not the same across a
be learned from careful analysis of the first hours of the long PCB. The risk is site-specific, being more problematic across

FIGURE 10. QFN-124 rotated 45° Channel C charts plotted over dif- FIGURE 11. QFN-88 rotated 45° Channel D charts plotted over dif-
ferent time periods. ferent time periods.
different components.
Process control requires an objective sampling plan for Follow-on research. Follow-on research is needed to develop
measuring ionic residues of the process. This study looked at a “process control plan.” The research team plans to perform a
two test methods. The ROSE bulk extraction test method is series of tests by first developing the “golden image” to define
a nondestructive test method that can be used on the actual upper and lower process limits. Using the same test card, the
product. The problem is this method is not consistent in detect- process will be varied to validate the method work for detect-
ing problematic residues across site-specific components. ing the cleanliness state.
Electrical testing using SIR temperature-humidity-bias is a
far superior test method. The problem with this method is it Acknowledgments
cannot be used on the actual production board. This method The authors want to thank and show our gratitude to many
requires a test board or coupon that is representative of the people who helped make this research possible. Many people
complex components used on production hardware. When behind the scenes executed many of the steps to run this study.
using a representative test board or coupon, this test method The authors acknowledge Anna Ailworth and David Lober
can be used to monitor and control the process with accuracy. for statistically analyzing the data. The authors acknowledge

Ed.: This article was first published in the SMTA International Proceed-
Bobby Glidwell for his design and process control method ings in October 2020 and is republished here with permission of the
development using temperature-humidity-bias testing. The authors and SMTA. Copyright Honeywell Federal Manufacturing &
Technologies LLC, 2021. Notice: This manuscript has been authored
authors acknowledge Caroline Spencer, Ph.D., for her work in
by Honeywell Federal Manufacturing & Technologies under contract
removing components and imaging. The authors acknowledge No.DE-NA-0002389 with the US Department of Energy. The United
the assembly line people who built and cleaned the test vehicles States Government retains and the publisher, by accepting the article
and perform the testing. • for publication, acknowledges the United States Government retains
a nonexclusive, paid-up, irrevocable, worldwide license to publish or
reproduce the published form of this manuscript, or allow others to do
so, for US Government purposes.
REFERENCES
1. IPC-J-STD-001G, Amendment 1, Requirements for Soldering Electrical
and Electronic Assemblies, September 2018.
2. M. Bixenman, V. Sitko and M. McMeen, Qualified Manufacturing Pro-
cess Development by Applying IPC J-STD-001G Cleanliness Standard,
February 2020.
3. IPC-9202, Material and Process Characterization/Qualification Test Pro-
tocol for Assessing Electrochemical Performance, October 2011.
4. D. Pauls, et al., IPC-WP-019A, An Overview on Global Change in Ionic
Cleanliness Requirements, August 2017.
WILLIAM (BILL) CAPEN is senior engineering technical specialist

at Honeywell FM&T (kcnsc.doe). JASON EDGAR is lead electrical
FIGURE 12. ROSE testing for each board. engineer at Honeywell FM&T. DR. MIKE BIXENMAN and MARK
MCMEEN are co-inventors at Magnalytix (magnalytix.com).
FIGURE 13. QFN-124 average per hour. FIGURE 14. QFN-88 average per hour.
FIGURE 15. QFN-124 mean and standard deviation averaged every FIGURE 16. QFN-88 mean and standard deviation averaged every
hour. hour.

Dennis Ralston
Sr. Director –
Government Relations and Cooperative R&D
KLA
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SEMI IS MORE
SMART MANUFACTURING
Lights Out at USI
The EMS behemoth is on the cusp of an all-automated future.

BY MIKE BUETOW
By almost any measure Universal Scientific Industrial is an EMS JC: At USI, we have a very detailed Industry 4.0 Smart manu-
behemoth. Yet most of the press surrounding USI over the past facturing plan and roadmap. We call it Worldwide 5 Star I4.0
few years has been tied to its recent acquisition of AsteelFlash. Smart Manufacturing Roadmap and Management System. It
The deal, completed last month, added 17 manufacturing sites lays out our stage-by-stage plan over the next five to seven
and about $1 billion in topline revenue. For the first time, USI years to bring up the Smart manufacturing level of our world-
will have sites in the US, Africa and Western Europe. wide factories. Every year we measure the progress we made.
Today, USI has 27 manufacturing locations in 10 countries, We have month-by-month reviews of the system, and at the
over 24,000 employees and revenue of more than $7 billion. end of the year we do a more careful rating of all the factories
That’s good for the 11th spot in the current CIRCUITS ASSEM- of the progress made toward the goal.
BLY Top 50 rankings. There’s no missing the company now. Our Smart manufacturing definition is based on the Indus-
Yet for all its size, USI could just as easily be recognized for try 4.0 contents, and it has four pillars:
its technical prowess. The company is on the cutting edge of 1. Automate all machines. The focus is to reduce manual labor
so-called lights-out manufacturing, where few if any staff are and minimize any manual handling costs and issues.
found on the factory floor where hundreds of SMT machines 2. Industry 4.0 data automation. Data automation is the
run seamlessly, connected by sophisticated software and AGVs essence of I4.0. It digitizes and connects all data to the cen-
feeding the cells on a just-in-time basis. tral server, so we have real-time data from all production
Jim Cao, general manager of the Greater Shanghai and equipment and process SPC data and RMS (recipe manage-
Smart Manufacturing/SiM business unit, USI, is charged with ment system). Every production lot is scan-in and scan-out
developing and overseeing the company’s worldwide Smart at every process station using 2-D barcode. One hundred
manufacturing strategy. The company is entering year six of percent of the units, through the entire production line, also
the plan, and the progress is notable. He spoke about how have a 2-D barcode system, and are scanned and loaded in a
Industry 4.0 has changed the way the EMS firm operates with central server. We know exactly, for every unit we ship out,
CIRCUITS ASSEMBLY in late November. if there is any issue coming back; it is easy to trace back to
which unit, which shift and
MB: In a press release on which hour.
Nov. 10, you said, “USI 3. Our Automatic Mate-
is adopting Smart manu- rial Handling System. That
facturing to enhance our fully automates our entire
competitiveness through components incoming to the
the digitalization of our warehouse and dispatched
production processes, by AGV to each SMT pick-
including the automation of and-place in JIT mode, right
infrastructure and logistics before a pick-and-place
using robotics and auto- machine runs out of compo-
mated guided vehicles.” nents (FIGURE 1). We have
What does Smart manufac- eliminated the kitting room
turing mean to USI? FIGURE 1. All inspection machines from SPI to AOI are linked and and associated labor. Every
constantly driving process improvements. machine we have is linked

SMART MANUFACTURING
to a production floor
management system
we call Shop Floor.
Shop Floor is con-
nected to our ERP
system. Our data
automation is inte-
grated with Shop
Floor, so we know
exactly to the minute
when every machine
is running out of
material. The system
would automatically
dispense the right
components from
Smart Storage driven
by robots by retriev-
ing right correspond- FIGURE 2. Robotic cells replaced hundreds of technicians and markedly improved speed and quality.
ing component reels
and put the reel on a
cart, which carries them to the corresponding machine. JC: We do both. For all the automation equipment, we
4. AI-based learning system. We are just getting started. migrated from the original third-party design and program-
It’s a major undertaking. We see huge potential there as ming. Now a majority is in-house design and programming.
well, to have the machine at a certain level, automatically Obviously, we have to integrate all the standard, off-the-shelf,
adjust the inspection criteria, to reduce or reject, and also third-party production software, but we work with them and
eliminate under-rejects, to inspect and fine-tune the param- integrate together, mainly through two methodologies. The
eters, because there are so many variables (FIGURE 2). For first is the SECS/GEM protocol. Not all the equipment has
instance, the substrates we use have thickness variations SECS/GEM, especially the older equipment (five to seven years
within a certain spec range, and components do as well, so if old). We also developed our own protocols to use with LORA
we keep fine-tuning the process parameters within our spec- IoT through machine signal tower, so we know machine sta-
ifications, driven by the SPI, we can improve our quality. tus: for example, green light, yellow light, red light. SECS/
GEM is by far the most flexible, comprehensive machine tool
MB: Do all the facilities use the same equipment sets? central server data communication platform. It offers two-way
data transfer. The central server can control the machine, and
JC: We have factories worldwide. If you look at our US report- the machine provides real-time data to the server. For older
ing, our business is pretty much two portions. The first part, machines without SECS/GEM, it’s pretty much a one-way
which is the major part, is the so-called system-in-package (SiP) communication from the machine to the server. It was limited
miniaturized modules. The second part is the EMS business. data transmission from the server to the machine, unless we
For EMS, the equipment is less complicated than the SiP can work with the supplier to have access to their PLCs and
factories. The SiP factories’ process flow is very similar to typi- machine-level PCs.
cal IC assembly and test factories. The only major difference is
we use SMT instead of wirebond. The rest of the backend and MB: Are the AGVs you use purchased from traditional
test processes are very much the same. It’s much more difficult electronics factory suppliers or from outside our indus-
to make modules than single-chip IC products. try?
Not all the factories are at the same level yet. My philoso-
phy is we use the Zhangjian factory in Shanghai, where our JC: We use a third-party supplier based in China. That tech-
Smart manufacturing development team is located, to develop nology is pretty mature now. It’s been in the market for the last
all the common platforms. We use a common platform strat- 25 years. In my career, I first saw the AGV in the Intel factory
egy to standardize the data automation protocols and equip- in Chandler, Arizona, about 22 years ago. It’s now popular in
ment, which produces our development lead times and costs as China.
well. Our strategy is to develop the common platforms, then
fan out to the worldwide factories, as each factory needs it. MB: We in the US are way behind you.
MB: Was the software, which is extensive, developed in- JC: I’m not so sure. I worked in the States for close to 30 years.
house, or do you start with machine software and modify When you say the US is behind, I think the main reason is the
it to meet your needs? loss of most of the manufacturing jobs, which moved to China,

SMART MANUFACTURING
initially for the cheap labor. But the China labor rate is inflat- JC: It’s a good question. Our suppliers are mostly the IC
ing every year, and every China company is under pressure to manufacturers. Our customers mostly are fabless. They typi-
speed up their own automation to stay competitive. cally do assembly and test in one of the major OSATs. They
are not pushing that heavily yet.
MB: You talked about some of your recipes. How deep In terms of their trust of their system, I think it would be
does that go? Are you able to go back all the way to the much more trustworthy to them because, if we have the fully
component distributors or even the component OEMs integrated customer forecast to the supplier demand system
and tie your inventory needs on the line, as they are fully linked, it would take out a lot of the human errors or
starting to wear down, all the way back to the component manipulations. It would be data to data. It’s a real B2B. It
supplier level so the just-in-time is as tight as possible? would be much more accurate and trustworthy to our suppli-
ers in terms of demand numbers. Right now, everyone is mov-
JC: The answer is not yet. Let me explain a little bit. Our ing slowly in that direction. It will happen. There’s no doubt.
material planning system is very much SAP-based. We do not It will improve the productivity of our customers and suppliers
typically store months and months of inventory. Especially and ourselves as well.
for the products we make, the material supply is quite tight.
We use SAP to manage that material demand. In our Five
Star I4.0 Roadmap, the last stage would be exactly what you MB: You talked a bit about what the AGVs are doing in
said. We plan to integrate with our customer’s ERP system, so the factory. Are there any other areas where you have
that when the customer dumps their forecast for the next six implemented robots, and if that’s the case, what are you
months, by connecting their ERP with our ERP, our system having those robots do?
automatically checks the inventory, calculates yield loss, and
cuts it down to the particular component-level demand for the JC: The product we make are modules. It’s a system, not an
next six months, and automatically transmits to the suppliers’ individual IC. The test time for each can be very long … a
ERP system. That’s a fully integrated supply chain. We are not couple minutes. Each robot can support eight to 10 test sock-
there yet. Obviously, the reason is very much dependent on ets for long-test-time module testing. We have hundreds and
our customers’ readiness and, more importantly, our suppliers’ hundreds of robots (FIGURE 3). In the old days, three to four
readiness. years ago, we had hundreds and hundreds of operators manu-
ally inserting parts into the socket, closing the socket, pushing
the button. It’s a lot of human errors. Now those hundreds of
MB: Have you found that component manufacturers human operators are gone, replaced with robots, with much
are eager to get to that point, or are they concerned higher efficiency and much higher productivity.
that would create less clarity for the inventory levels You probably see the AGV on the floor (Figure 3). That’s
because of concerns of double or triple ordering during the project we are working on right now. My plan is to have
tight inventory times? How trusting are they of software- USI’s first lights-out test floor factory next year. We’re going to
driven inventory pulls? have at least 91 of those test systems totally lights-out, all prod-
uct loading and offloading and machine status done remotely.
FIGURE 3. AGV move component trays hands-free across multiple floors to feed assembly machines.

SMART MANUFACTURING
We use AGVs to carry carts similar to the one on the right there’s clear definitions in terms of what we use for one star,
in Figure 1 upstairs to an elevator and then to a system next to two stars, or a half star. Typically the measurements include
the machine that needs the parts. It’s a fully integrated AMHS the manufacturing process automation rate. For each produc-
system. At the heart of that is the so-called Smart Storage sys- tion machine, we divide it into three steps: loading, process,
tem (FIGURE 4). Inside are all the component reel slots, which and uploading. Each station has three steps.
are all handled by robots moving quite fast, managing all the If we automate the processing part, we still need a key-
component reels. They are put on the shelves and retrieved as board to load the parts, offload parts, so we only count as
needed, then moved on the automatic conveyor connected to one of three. If we automate all, it would be three steps. So,
the robots at the other end to put on the AGV carts. the measuring system is doing all the manufacturing process
We have lots of dashboards around the factory. One is the systems. The percentage of machines connected to the data
AMHS Smart Storage dashboard (FIGURE 5). It shows how system network, we call it connection rate. It’s machine down-
many reels are inside, the size of them and how many parts time reduction, or MBTF-based. With I4.0 data automation,
they have on them. All the data are real-time, on display in the we have very much reduced machine downtime because when
system and fully automatic. you have hundreds of thousands of equipment on the produc-
tion floor, a lot of things are happening. When a machine goes
MB: I’m assuming USI does studies every time you down, the equipment technician or engineer may not know
implement an automated system. Are there standard which machine is waiting for assistance.
metrics that you use to compare how much faster and Now we have a system to send automatic text messages
accurate and higher-yielding a particular process has to the responsible engineers, so they know immediately which
become? machine is down and what kind of problem, so they can
quickly fix it, instead of wasting a lot of machine time waiting
JC: There’s a day-and-night difference in terms of accuracy. for a human. We also measure the DL [direct labor] and IDL
When we have human labor to do the work, the accuracy is [indirect labor] headcount reduction, which is a fundamental
way off. There’s no comparison. The robot we typically use objective to improve productivity. How many headcounts
has higher repeatability, placement accuracy, +/-20 microns. did we reduce? What percentage? How many technicians do
Humans wouldn’t be close. They’re not as dependable as we use to collect data, to go to the production floor and col-
machines in terms of material handling. lect SPC and yield data, for instance, and write it down on a
piece of paper, go back to an office and enter in a computer,
MB: Regarding the Five Star Rating System, how did that which is not productive? Now we have real-time data collec-
name come about? tion and transmission to a central server and displayed on the
dashboard, on your office desktop computer or even your
JC: The “five stars” name is commonly used for hotels, and smartphone. We have a comprehensive system to measure the
bottom-line results from I4.0 Smart
manufacturing.
MB: In the Zhangjian factory,

is SMT assembly laid out in a
straight line?
JC: We probably have best SMT

production lines in the world in
terms of speed and accuracy. We
have multiple lines grouped togeth-
er by process in order to maximize
machine efficiency (FIGURE 6). We
do not link the front-end machine
to the backend machine dedicated
through a conveyor belt, which
is very old-fashioned and not so
flexible because, very simply, if one
of the machines in the chain goes
down, the WIP will start piling
up. The other machines upstream
and downstream all go down. We
FIGURE 4. Parts are stored on reels inside intelligent storage systems in USI's component focus very much on efficiency and
warehouses. machine utilization.

SMART MANUFACTURING
FIGURE 5. Among the data the AMHS Smart Storage dashboard shows are the number of reels, their size and how many parts they
contain.
MB: I count at least eight placement machines in that management system.

configuration.
JC: The first parameter management system we have imple-
JC: Yes. mented is the inline SPC. The SMT line in the photo has
an inline SPC system in terms of the component placement
MB: That would be a single product being shipped accuracy. We measure, collect the data, and feed it to the SPC
through all those machines? control module, so we know when the process is going to devi-
ate. As you can imagine, we have hundreds and hundreds of
JC: Correct. vacuum cups on those pick-and-place machines. If any of the
vacuum cups are worn out or the component is off, then we
MB: And the line is running from left to right. How many catch that because we have the fully integrated AOI machine
printers would feed that configuration? there, so we know exactly which vacuum cup caused the prob-
lem. It’s our first step we are implementing. Down the road,
JC: One. The products we build are miniaturized. It’s actually the parameter management system will allow the spec to fine-
smaller than your fingernail. tune the machine parameters based on certain self-learning
capabilities.
MB: I’m surprised that one printer can keep up. I’ll give you another example. We have fully automated all
the outgoing cosmetic inspection processes. We are very par-
JC: It can. To maximize our productivity, we use a large-size ticular about any cosmetic defects, such as a very fine scratch
PCB. Typically, we use a 95 by 240mm substrate. On the sub- or a tiny black dot that we could not see with our eyeballs. We
strate, depending on the size of the product, we have anywhere have fully automated that. On the day-by-day fine-tuning of
from 100+ to 400 units. We just print at the PCB level instead the parameters, we still have over-reject and under-reject rates.
of the unit level. Our next step is to implement what I called the closed-loop
The smallest components we use in production are 01005 machine-learning-based parameter management system. Based
or 008004. It’s very, very high density. Each module typically on the outcome of the over-reject and under-reject rates that
has 100 to 200 different components, or even more. The small- came from the system, the machine is going to fine-tune the
est module we make typically has 800+ components. It’s very inspection parameters to narrow the defects.
high density.
MB: How long did it take to design and implement all of
MB: You’ve referred in press releases to a parameter this?

SMART MANUFACTURING
JC: We started five years ago. One of my responsibilities is to the business situation. Each factory is different. If the factory is
lead the worldwide manufacturing effort. I do have a dedicated booming, the manager is more willing to invest capex in auto-
team to develop all the machine and data automation and help mation. We are making progress very steadily toward our goal.
to implement those. It’s been about five years. We take 4.0 Smart manufacturing very seriously. We invest
a lot of resources and capex. We want to upgrade our manu-
MB: How close to the original schedule are you? facturing capabilities and improve our competitiveness. We are
marching toward our final goal. We are on the way. •
JC: We are very much on schedule. On average last year, the
worldwide factories improved about a quarter star. Some fac- MIKE BUETOW is editor in chief of PCD&F/CIRCUITS
tories made more progress, some less. It very much depends on ASSEMBLY; mbuetow@upmediagroup.com.
FIGURE 6. A single printer can feed eight SMT placement machines. USI says up to 400 highly dense SiP modules may be processed
on a single substrate.
Material Gains, continued from pg. 16 HDP, continued from pg. 25
hybrid and all-electric propulsion. Airbus has been flying experi- mechanical testing and will be analyzing the data prior to
mental platforms of various configurations since 2010 and, in moving to the long-term aging phase.
2015, successfully crossed the English Channel between France Some of these projects directly affect the industry as a
and England, with the E-Fan 1.0 all-electric single-seater. It’s a whole, not just the pursuit of higher technical knowledge
tremendously significant route, recalling Louis Blériot’s historic for our members. For some of these problems, we are trying
channel crossing of 1909. He completed the 24-mile journey to determine if it affects the industry, not just HDP mem-
less than six years after the Wright brothers achieved the first- bers. But HDP members always gain from this information.
ever powered flight, managing to stay airborne for less than one
thousand feet. LM: HDP is a member-driven organization, so we listen to
Those early pioneers could hardly have imagined what was what they want us to do. We have quite a few different proj-
to come. And neither, I am sure, can we. • ects going on right now. Some are proprietary, and some are
open. More information about the projects is available here:
https://bit.ly/3qSnTuY •
MIKE BUETOW is editor in chief of PCD&F/CIRCUITS

ASSEMBLY; mbuetow@upmediagroup.com.

GETTING LEAN
Optimizing Design for Manufacturability Analysis

A near real-time feedback loop between layout and assembly.
TWO CORE TENETS of Lean manufacturing philoso- • Tombstoning, if the chip’s package is smaller
phy are eliminating defect opportunities and minimiz- than its land pattern
ing process variation. Consequently, most companies • Insertion problems, if the PTH pin diameter is
embracing Lean principles do some form of design for larger than the holes
manufacturability (DfM) analysis to identify manu- • Inability to use a component when the wrong
facturability issues either during design or in the new package is specified.
product introduction phase. In some cases, this is an ■ 70% of projects had via-in-pad issues where
automated feature of design software. In other cases, exposed via-to-pad clearance was too small. This
this is done manually. results in the solder paste being wicked into the via,
SigmaTron has adopted a hybrid process that uses creating an insufficient solder situation for the SMT
software automation to speed basic analysis, followed component.
by an engineering review. This E-DFM software tool ■ 50% of projects had insufficient pad-to-pad spacing
reduces the time it takes to create a detailed report or circuit-to-circuit spacing. The exposed pad-to-
from several days to a few hours and works with Sig- pad spacing is too narrow for adequate separation
maTron’s existing Valor software platform. of solder paste on each pad, resulting in solder
Automating the process improves efficiency, since bridging during reflow.
the engineering team reviews the automatically gen- It is not unusual for OEM design teams to focus
erated reports and suggests solutions for accuracy on product fit, form and function, without considering
instead of individually performing a full analysis manufacturability. The E-DFM tool helps shorten the
themselves. They then can make suggestions to further DfM feedback response time back to OEM engineer-
optimize the recommendations, as needed. The tool ing teams, so recommendations can be considered as
has been customized from industry-standard PCBA early as possible in the design cycle.
design rules and SigmaTron’s equipment/process-spe- The feedback is color-coded and prioritized by
cific manufacturing guidelines, so it reflects equipment severity. The ranking scale is:
and process constraints. ■ Red – Critical: will affect reliability
The report output identifies the issue, explains the ■ Brown – Hot: will increase cost or affect reliability
consequence if the issue is not corrected, displays a visu- ■ Orange – Warm: impacts cost and creates process
al image of the issue, and suggests a solution. Its pro- inefficiencies
gramming covers SMT and through-hole technologies. ■ Light green – Cold: suggested as a future design
SigmaTron has long flexed its engineering resourc- improvement
es among facilities for better resource utilization and ■ Dark green – Closed: violation has been closed.
to take advantage of the expertise a core team may The ranking scale helps teams better understand
have developed based on the projects they’ve typically each violation in terms of its likely impact on prod-
encountered. For example, test engineers in Chicago uct and quality, which can be important in situations
and China support SigmaTron’s operations in Vietnam with time or cost constraints associated with adopting
when test complexity exceeds the latter’s capabilities. DfM recommendations. It also helps create a path to
HOM-MING In this case, the engineering team in China supports improved manufacturability on future design iterations.
CHANG is enhanced DfM requests for all facilities. From a Lean perspective, eliminating defect oppor-
vice president,
Another benefit of this process is enhanced focus tunities and issues that create process inefficiency prior
China operations
on common DfM mistakes and the ability to educate to production makes sense. From a practical perspec-
at SigmaTron
International
customer engineering teams on issues to avoid in lay- tive, resource constraints, short product development
(sigmatronintl.com); out. For example, the top three issues the engineering timelines and the cost of design approval processes can
homming.chang@ team saw in its third quarter 2020 analyses were: prevent DfM analysis from occurring or limit the rec-
sigmatronintl.com. ■ 90% of projects had issues with component pack- ommendations that are subsequently adopted. Entirely
ages not matched with recommended land patterns. automating the process may provide too generic an
When this issue isn’t discovered early, it can result approach. It is the classic equation of a good versus a fast
in project delays, particularly if long lead-time parts solution. Blending customized automation with an expe-
are involved. Attempting to work around this issue rienced engineering team enables a solution that is both
can cause defects and other issues such as: good and fast, providing the level of documentation
• Open circuits, if the pins fall outside the land design teams need to evaluate the recommendations and
pattern the speed needed in short product development cycles. •

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IEEC
State-of-the-Art Technology Flashes

Updates in silicon and electronics technology.
Ed.: This is a special feature courtesy of Binghamton University.

Optical polymer waveguide backplane for high-
performance computers has zero bit-error count.
Bending an organic semiconductor boosts electri- Optical communication technology can boost the
cal flow. Organic transistors based on single crystals speed of data transmission in many ways such as inter-
of rubrene can double the speed of electricity flowing and intra-datacenter and inter and intra-chip connec-
through them when a crystal is slightly bent (strained). tions. An important part of this architecture is the
This behavior cannot be easily achieved with tradition- computer backplane, which connects PCBs together
al semiconductors made of silicon. Rutgers University to form a computer bus. Optical communication can
researchers found molecules of rubrene are arranged greatly raise data transmission rates, helping to enable
in a herringbone pattern (upper left in figure), form- high-performance computers (HPCs). Researchers
ing highly ordered semiconducting molecular crystals from Huazhong University have developed a high-
that can be used to create rigid or flexible high- speed, large-capacity, compact optical backplane based
performance organic transistors, based on thick or on optical polymer waveguides that use vertical-cavity
ultra-thin single crystals, respectively. An example of a surface-emitting lasers (VCSELs) emitting at 850nm
freestanding rubrene transistor is shown on a fingertip. for data transmission. The backplane network reaches
This method could benefit next-generation electronics. 15Gb/s error-free data transmission via eight parallel
(IEEC file #11946, NASA Tech Briefs, 10/1/20) channels; in the optical backplane, the 10 Gb/s in a
channel is processed error-free by field-programmable
gate-array chips. (IEEC file #11945, Laser Focus
World, 10/13/20)
GARY MILLER
Memristor breakthrough: First single device to act is technology analyst
like a neuron. Analog computing with neuron-like at IEEC, Binghamton
devices could efficiently solve problems traditional University. He has
computers struggle with. One thing that’s kept copying over 40 years’ experi-
the brain’s power efficiency is the lack of an electronic ence in electronic
device that can act like a neuron. Hewlett Packard packaging. He previ-
researchers have invented a device that meets those ously was the chief
mechanical engineer
requirements. The most crucial part is the nanome-
at Lockheed Martin;
ters-thin niobium oxide (NbO2) layer that combines
gmiller@bingham-
resistance, capacitance, and what’s called a Mott mem-
ton.edu.
ristor. It’s predicted that if the possible device param-
eters were mapped, there would be regions of chaotic
INTEGRATED
Fluoride materials for extra-thin computer chips. behavior between regions where behavior is stable.
ELECTRONICS
To make electronic components smaller, semiconduc- At the edge of some of these chaotic regions, devices
ENGINEERING
tor two-dimensional (2-D) materials can be combined can exist that do what the new artificial neuron does. CENTER (IEEC)
with new types of insulator materials. Smaller is the (IEEC file #11950, IEEE Spectrum, 10/1/20) is a New York Center
direction in which computer chips are moving. 2-D of Advanced Technol-
materials are considered to have great potential since ogy (CAT) responsible
they are as thin as a material can possibly be and, in for the advance-
extreme cases, only one single layer of atoms. This ment of electronics
makes it possible to produce novel electronic compo- packaging. Its
nents with tiny dimensions, high speed, and optimal mission is to provide
research into elec-
efficiency. 2-D materials can only be used effectively if
tronics packaging to
they can be combined with suitable material systems
enhance partners’
such as special insulating crystals. Researchers at
products, improve
the University of Vienna analyzed this problem and reliability and under-
developed a transistor prototype with a calcium fluo- stand why parts fail.
ride insulator. (IEEC file #11947, NASA Tech Briefs, More information is
10/1/20) available at bing-
hamton.edu/ieec.

IEEC
Carbon metal wires create path to carbon-based comput- Solar-powered smart dust. Industrial ubiquity of MEMS,
ers. Transistors based on carbon rather than silicon could increasing computing power of chips, the miniaturization
potentially boost computing speed and cut power consumption of lab-on-a-chip devices, and increased connectivity, com-
more than thousandfold. University of California researchers bined with the emergence of nanotechnologies, gave rise to
have created the last tool in the toolbox, a metallic wire made the concept of smart dust, sub-millimeter-scale autonomous
entirely of carbon, setting the stage for a ramp-up in research computing not larger than a grain of sand. An individual
to build carbon-based transistors and computers. This has smart dust particle is a tiny sensor and computer, self-powered
been one of the key things missing in an all-carbon-based inte- and wirelessly connected to a large network. Each particle
grated circuit architecture. The team has worked for several can be left unattended and collects environmental data such
years to make semiconductors and insulators from graphene as light, temperature, pressure, vibrations, the existence of
nanoribbons, a structure composed entirely of carbon atoms toxins, etc. and transmits this data wirelessly. Smart dust can
arranged in an interconnected hexagonal pattern resembling lead to autonomous artificial intelligent computation near
chicken wire. (IEEC file #11949, Design Fax, 10/20/20) the end-user, such as authentication, medical procedures, and
healthcare monitoring, sensing, and tracking, industrial and
Colorful perovskites: Thermochromic window technolo- supply chain monitoring, and defense applications. (IEEC file
gies. Department of Energy NREL researchers report a #11967, Nanowerk, 10/27/20)
breakthrough in developing a next-generation thermochromic
window that not only reduces the need for air conditioning but High-pressure glass processing could reduce fiber-optic
simultaneously generates electricity. The technology, termed signal loss by 50%. Data transmission over optical fibers can
“thermochromic photovoltaic,” permits the window to change be significantly improved by producing the silica (SiO2) glass
color to block glare and reduce unwanted solar heating when fibers under high pressures, according to Penn State University
the glass gets warm on a hot, sunny day. This color change also researchers. They found that large voids form between silica
leads to the formation of a functioning solar cell that generates atoms when the glass is heated and then cooled (quenched)
on-board power. Thermochromic photovoltaic windows can under low pressure, but when this process occurs under 4
help buildings turn into energy generators, increasing their con- GPa, most of the large voids disappear, and the glass becomes
tribution to the broader energy grid’s needs. The newest break- a uniform lattice structure. Results show signal loss from silica
through now enables myriad colors and a broader range of glass fibers can be reduced by more than 50%, which could
temperatures that drive the color switch. This increases design dramatically extend the distance data can be transmitted with-
flexibility for improving energy efficiency, as well as control out the need for amplification. This would be a huge advance
over building aesthetics that is highly desirable for both archi- for the fiber-optic industry. (IEEC file #11968, Laser Focus
tects and end users. (IEEC file #1196, Science Daily, 10/20/20) World, 10/19/20)
New composite energizes the electric vehicle market. A new Light-driven

composite from Oak Ridge National Laboratory increases the quantum net-
electrical current capacity of copper wires, providing a new mate- work prom-
rial that can be scaled to improve energy-efficiency in electric vehi- ises faster,
cles. With an improved performance, manufacturers have the abil- enhanced
ity to reduce volume and increase the power density in advanced communica-
motor systems. The material can be deployed in any component tion. Using
that uses magnetic and
c o p p e r, semiconduct-
including materials,
ing bus researchers at
bars and the University of
smaller Rochester and
connectors Cornell University designed a nanoscale node capable of using
for elec- laser light to emit and accept photons to interact with other
tric vehicle nodes. The development capitalizes on light’s physical proper-
traction ties to deliver a faster, increasingly efficient method to perform
inverters, computations and detections. They arranged semiconductor
as well as and magnetic materials to form a platform that consisted of
for appli- an array of pillars, each 120nm in height. The pillars mark
cations such as wireless and wired charging systems. To produce the location of a distinct quantum state that can interact with
lighter weight and great conductive properties, the team created photons and allow the photons to contact other locations
lengths of composite copper-carbon nanotube materials, then across the device and with similarly constructed arrays at vari-
deposited and aligned carbon nanotubes on flat copper sub- ous locations. (IEEC file #11992, Photonics Media, 11/9/20)
strates. (IEEC file #11924, NASA Tech Briefs, 9/29/20)

IEEC
Flexible self-charging battery under development. Strate- whether someone carries the coronavirus, with or without
gic Elements is developing a self-charging battery technology symptoms. The team designed a multiplex testing method and
through its collaboration with the University of New South incorporates a low-cost sensor that can diagnose Covid-19 in
Wales. The battery cells create electricity from humidity in the 10 minutes or less. (IEEC file #11937, Science Times, 10/2/20)
air or skin surface to self-charge themselves within minutes.
No manual charging or wired power is required. Created with Flexible electronics are the future in wearable health
a printable ink, they are ideally suited for use in internet of monitoring. In a new research report, analysts find significant
things (IoT) devices. The battery ink is developed by integrat- opportunities for flexible electronics to be applied to health-
ing significant existing ink formulation and printed electronics care. They forecast the market for healthcare products contain-
intellectual property from the company’s Nanocube Memory ing flexible electronics to be worth over $8.3 billion by the year
Ink technology with an advanced graphene oxide material. 2030. A significant market trend is toward decentralized health-
Strong potential competitive advantages exist over lithium- care and utilizing technologies to monitor and care for people
based batteries that suffer from weight, safety and the need for remotely. During the Covid-19 pandemic, healthcare systems
constant power supply to recharge. (IEEC file #11969, Printed around the world rapidly deployed remote care services in the
Electronics World, 10/19/20) form of telehealth. Such efforts often need to be supported by
devices in the home capable of providing medical-grade data.
Bonding method attaches gallium nitride to thermal- But ultimately, monitoring efforts rely on the correct use of the
ly conductive materials. Georgia Institute of Technol- devices. (IEEC file #1196, Medical Design Briefs, 10/2/20)
ogy researchers have developed an easier way to attach wide
bandgap materials such as gallium nitride (GaN) to thermally LG’s rollable OLED-R TV. If you happen to live in South
conducting materials such as diamond. This would boost the Korea and have $87,000, LG has a rollable OLED TV for
cooling effect on GaN devices and lead to better performance you. LG has been demonstrating its rollable display technol-
through higher power levels, improved reliability, and lower ogy since 2014. At CES 2019, this technology was sufficiently
manufacturing costs. The technique could have applications mature for commercial launch. The LG Signature OLED R
for wireless transmitters, radars, and other high-power and is the world’s first rollable TV and will be made available at
high-frequency electronic devices. The technique, called sur- “several premium consumer electronics stores” located across
face-activated bonding, uses an ion source in a high-vacuum South Korea. The 65" screen can be rolled up into its brushed
to clean the surfaces of the GaN and diamond; it also activates aluminum casing. (IEEC file #11957, PC Mag, 10/20/20)
the surfaces by creating dangling bonds. Introducing small
amounts of silicon into the ion beams lets the process create
strong atomic bonds at room temperature, direct bonding
the GaN and single-crystal diamond to make a high-electron-
mobility transistor (HEMT). (IEEC file #12008, Machine
Design, 3/25/20)
Market Trends
VCSEL market to grow to $2.7 billion by 2025. The VCSEL
market is expected to be worth $1 billion in 2020 and to
show an 18.3% CAGR between 2020 and 2025 to reach $2.7
billion. While 3-D applications for mobile and consumer are
still booming, automotive, medical and AR/VR applications
are emerging. Mobile 3-D sensing will represent around 75%
of overall VCSEL revenues in 2020. In the VCSEL market,
telecom and infrastructure applications, mainly datacom, are
expected to reach $516 million in 2025, a CAGR of 13.2%.
Other applications are not significant yet but could emerge in
the mid- to long-term, such as automotive applications like Advanced packaging market to have steady growth
LiDAR or driver monitoring systems. (IEEC file #11941, Elec- of 8% to $40 billion by 2026. The advanced packaging
tronics Weekly, 10/12/20) market is set to grow from its current market value of $25+
billion to over $40 billion by 2026. Advanced packaging
Researchers develop graphene-based Covid-19 sensor. was developed to improve the performance of a device and
Caltech researchers have designed a new sensor that can enable simultaneously shrink the packages. It is termed as a general
at-home diagnosis of Covid-19 infection. With the coronavi- grouping of a variety of different techniques such as system-
rus disease a highly contagious disease transmissible even by in-package, 3D-IC, 2.5D, and fan-out wafer-level packaging.
people who do not display symptoms, subsequently respond- Semiconductor packaging materials are known to be a class
ing to people infected with it is both challenging and time criti- of electronic solutions utilized to form the connection of IC
cal. Rapid testing kits cut down on the time needed to assess chip to the packaging substrate. The advanced packaging

IEEC
market is bifurcated in terms of packaging type, application, structures include a plurality of conductive contacts and a first
and regional landscape. With respect to packaging type, the conductive layer; joining a second substrate with the semicon-
advanced packaging market is classified into 2.5D/3-D, fan- ductor structures; performing a thinning process on a backside
out, embedded-die, fan-in WLP and flip-chip. The fan-in WLP of the first substrate to expose the insulating layer and one end
segment will witness considerable growth. (IEEC file #11954, of the plurality of conductive contacts.
Semiconductor Digest,10/9/20)
Active package substrate having anisotropic conductive
Implantable sensor could measure bodily functions and layer (assignee: Intel Corp.) patent no. 10,790,257. Semi-
then safely biodegrade. Penn State University researchers conductor packages, including active package substrates, are
have designed a highly sensitive flexible gas sensor that can described. In an example, the active package substrate includes
be implanted in the body and safely biodegrade into materials an active die between a top substrate layer and a bottom sub-
that are absorbed by the body. The flexible and implantable strate layer. The top substrate layer may include a via, and the
sensor monitors various forms of nitric oxide (NO) and nitro- active die may include a die pad. An anisotropic conductive
gen dioxide (NO2) gas in the body. The team added a twist to layer may be disposed between the via and the die pad to con-
their sensor design by making it from materials that are not duct electrical current unidirectionally between the via and the
just implantable, flexible and stretchable, but also biodegrad- die pad. In an embodiment, the active die is a flash memory
able. The researchers say future work could look at designing controller, and a memory die is mounted on the top substrate
integrated systems that could monitor other bodily functions layer and placed in electrical communication with the flash
for healthy aging and various disease applications. (IEEC file memory controller through the anisotropic conductive layer. •
#12000, Science Daily, 11/10/20)
Recent Patents
Liquid cooling through conductive interconnect (assign-
ee: Intel Corp.) pub. no. 16/379619. Embodiments include
semiconductor packages and cooling semiconductor packag-
ing systems. A semiconductor package includes a second die
on a package substrate, first dies on the second die, conductive
bumps between the first dies and the second die, a cold plate
and a manifold over the first dies, second die, and package
substrate, and first openings in the manifold. The first open-
ings are fluidly coupled through the conductive bumps. The
semiconductor package may include a first fluid path through
the first openings of the manifold, where a first fluid flows
through the first fluid path.
Flexible printed circuit to mitigate cracking at through-

holes (assignee: CommScope) patent no. 10,798,819.
Flexible fingers for flexible printed circuits improve the crack
resistance of prior art designs. The crack resistance can be
improved by encapsulating the trace inside additional layers
such that the outer two layers include only the lands of the
through-hole, and all other copper is etched away. The crack
resistance can also be improved by strategically adding copper
on layers other than the trace layer, including attaching it to
the land of the through-hole as a stub. These two designs can
be combined to include a stub trace into a four-layered design.
Method for 3-D integrated wiring structure and semicon-

ductor structure (assignee: Yangtze Memory Tech.) pub.
no. US10796993. Embodiments of methods and structures
for forming a 3-D integrated wiring structure are disclosed.
The method can include forming an insulating layer on a front
side of a first substrate; forming a semiconductor layer on a
front side of the insulating layer; patterning the semiconductor
layer to expose at least a portion of a surface of the insulating
layer; forming a plurality of semiconductor structures over the
front side of the first substrate, wherein the semiconductor

SEEING IS BELIEVING
Encrypted Opinions
What’s more in need of rehabilitation? The bonepile, or supplier gateway?
HELLO, I WOULD like to get some information about developed a roadmap toward meeting the NIST stan-
your capabilities for Bonepile Rehabilitation. I have dard, which we would be happy to share if a project
some legacy circuit cards that were previously tested goes forward.
on a FACTRON 750. Can you reverse engineer the Meanwhile, if you would like to proceed further,
schematics/gerbers from a known good board? Once send me an NDA and I’ll review and sign it immedi-
you have diagnosis (sic) the problem on a failed board, ately. Then we can discuss in depth the particulars of
can you also perform the repair? Are you cybersecurity your project.
certified for ITAR data? Any questions? Does this sound like a plan? When
This is how an unsolicited customer engagement can we get started? Tomorrow? Next week?
often begins. No unusual requirements here, other We’re interested. You’ll be hearing next from our
than the obvious need for remedial grammar lessons. security and purchasing groups, the first to establish
“Yes, yes and yes.” your bona fides, the second to install you in our ERP
Good. Then you may be able to assist us. What is system as a vendor. This is urgent.
your process? That was September. Our next communication
Bonepile rehabilitation and reverse engineering arrived in February. Urgent indeed.
in our world are two different things. When we say Greetings Robert: Our company wishes to discuss
bonepile rehabilitation, we are usually talking about and potentially engage in the process of CCA reha-
troubleshooting boards that have failed, either in the bilitation with your company, and to further pursue
field or in functional/system test, and using the tools and release details I am enclosing our Standard Bilat-
we have here at our facility to troubleshoot, repair, and eral NDA for your review and execution. How many
restore them to service. In most cases design documen- weeks will it take your legal department to review and
tation (bill of materials, CAD, schematic, Gerber files, amend and sign this document?
etc.) still exist, and are used in this activity, especially “About 10 minutes.”
to develop test programs (flying probe, JTAG/bound- Seriously? How can you do that so fast and with-
ary scan, etc.). out the assistance of legal counsel?
I would classify what you are asking for more as “I see one to two of them every week. That’s 50
reverse engineering, in that (I assume) documentation to 100 per year. I know what to look for and what the
and data are mostly or completely gone, due to time, pinch points are. The review takes no time at all if you
business transitions, or recordkeeping ineptitude. Full know what you’re looking for. It’s in the attorneys’
restoration of a doc set, compared with bonepile reha- best interest that you remain ignorant of that. Anyway,
bilitation, is a more difficult, time-consuming, and, by I should have a signed, scanned copy of your NDA
nature, expensive task. It typically involves various ready for countersigning back to you within the hour.”
forms of flying probe testing, CT scanning of indi- Good. Once the NDA is received, you will receive
vidual layers, followed by re-layout and redesign using an invitation to become a vendor from our ERP sys-
the forensic data our tools provide. If copy exact meth- tem. You will also receive a security notification asking
ods are required, the process will not work. Time and that you authenticate yourself and your company.
faded memory demand some latitude of interpretation. Sure enough, next day comes the email prompt.
Projects like these usually start at about $10,000 per You have been invited by a Member of our Suppli-
ROBERT
part number (very simple part numbers), and go up er System to join their select supply network. You were
BOGUSKI is
president of Datest
from there, frequently way up. If it is a bargain you nominated by a Customer Buyer. Please supply your
Corp. (datest.com); seek, you’re in the wrong place. Federal Tax ID Number; your DUNNS number; your
rboguski@datest. To give you a definitive answer whether we can CAGE Code; a copy of your DDTC (ITAR) letters and
com. His column help you with a particular board, I would need to see your ISO9001/AS9100 certifications for review.
runs bimonthly. it. Ideally, I’d need to see one assembled board and one Invited? Nominated?
bare board at a minimum. Or condemned?
That is our process. In order to transact with a Supplier System Cus-
We are ITAR registered and AS9100 certified. tomer, you must complete all of the actions indicated
Matter of fact, we just had our AS9100D transition below. All potential/pending purchase orders will
audit two weeks ago. Regarding data security, I’m be held pending completion of the vendor profile
assuming you are asking whether we meet NIST 800- and two-factor authentication registration. Failure to
171 and related DFARs. Today we do not, but we have complete all of these listed actions, in the sequence

SEEING IS BELIEVING
described below, will result in immediate rejection of this is also accessible via the P2P section of the website. The
application with no appeal. same access credentials noted above apply, with the addi-
In plain English, don’t screw it up. tion of a signed, notarized letter on company letterhead
1. Register with our Supplier System (SS), which provides authorizing access to SS Customer Support, and stating the
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The SS Customer Service team is available online via the

SS Customer Support Self-Help site. The Self-Help site

DEFECT OF THE MONTH
Resolving Intermittent Area Array Packages with

Video Simulation
Excessive temperature or moisture may be to blame.
OPEN CONNECTIONS ON area array packages can be minor popcorning due to moisture. Both faults can be
difficult to spot, particularly if they are intermittent simulated and recorded with video for reference.
electrical failures like the examples in FIGURE 1. One Secondary reflow of solder joints can cause intermit-
or more open joints can occur between the package tent connections of packages. This occurs when adjacent
and solder sphere or at the PCB pad interface. Reflow packages are reworked or when the board passes through
soldering with either convection or vapor phase can wave or selective soldering under excessive soldering
cause packages to move and separate. This can be temperature. Using video simulation in the process can be
BOB WILLIS
caused by warping of the package or in some cases helpful to solve process defects. In such instances, while
is a process
engineering
soldering boards, the opera-
consultant; bob@ tor is also observing reflow
bobwillis.co.uk. His optically or with x-ray. See
column appears https://bit.ly/3mZsSYw for
monthly. an example.
We have presented
live process defect clinics
at exhibitions all over the
world. Many of our Defect
of the Month videos are
available online at youtube.
FIGURE 1. Opens on a BGA package. com/user/mrbobwillis. •
Chiplets, continued from pg. 23
ation of bump assignment and the RDL Another had four columns and three rows ■ The interface signals between the chips
routability of the assigned nets. of bumps. Also, two different floor plans were selected, topology extracted, and
In package prototype design, the with different tile arrangement methods signal integrity analysis performed.
chiplet design data can be placed directly were created for evaluation. ■ Signal latency was confirmed by its
as a component with no need for spread- Two test cases of the SiP prototype better physical implementation as
sheet communication. Creating a con- designs for the chiplets were created (FIG- improved in case two.
nection between chiplets when placing URE 3). Since the design was performed on ■ More desirable electrical characteristics
these components is also possible. This a common platform, elements were con- could quickly be determined during
facilitated a scalable multi-die integra- firmed on the SiP while feeding changes to this prototype design phase.
tion, escape routing from bumps, die-to- the chiplet as needed, allowing the user to Electronic designers have a newfound
die, and die-to-ball routing via autoroute turn around various configuration changes capability to rapidly generate feasibility
functions, all within a short turnaround quickly. Each of these sample iterations studies and obtain visibility into the per-
time within the prototype design. took approximately 30 min. to create. formance of different configurations. Sig-
The SiP was then similarly merged Potential performance of the proto- nal integrity and power integrity may be
with the prototype PCB for validation and type design was judged using some factors evaluated quickly, with their interfaces in
viability evaluation. After implementing such as trace length and latency: place to assess designs at a more granular
critical signal physical data, the electri- ■ In case two, the bump depth was level using the simulation tool of choice.
cal characteristics and power integrity reduced to shorten the escape route In one platform, we can now simulta-
were checked during the prototype with length. neously examine configuration and trad-
embedded simulators. ■ The route length between chiplets was eoffs with visibility into the entire SiP, to
more closely matched. allow intelligent and expeditious decision-
Favorable results. Two tiled test cases ■ Compared to case one, case two con- making. This ensures that targets for cost
were created with different depths from firmed that the critical signal length and performance are met while adhering
the chip edge of the tile bumps cells while variation of 20 signals was reduced by to the design schedule. •
considering the routability of the SiP and 90% or more. STEVE WATT is manager of engineering
its power constraints. One iteration had ■ The total routing length was reduced operations, SOZO Center at Zuken USA
three columns and four rows of bumps. by 25%. (zukenusa.com); steve.watt@zukenusa.com.

MACHINES MATERIALS TOOLS
MACHINESSYSTEMSMATERIALSSOFTWARE
TOOLS SYSTEMS SOFTWARE
DOWNSTREAM CAM350/DFMSTREAM ORBOTECH APEIRON INNOLAS LINEXO

V. 14.5 Apeiron performs UV laser drilling on Linexo laser processing worksta-
CAM350/DFMStream v. 14.5 now sup- flexible printed circuits in a roll-to-roll tion is for R&D and smaller substrate
ports importation and visualization of manufacturing configuration. Multi-path production, e.g., ceramic PCBs. Fea-
CAD designs containing flex, rigid-flex and technology with two laser beams and tures fixed optic or scanner setup,
embedded component data in both 2-D four large-scan-area drilling heads can single- or dual-process heads, pro-
and 3-D views. Imports and visualizes flex/ drill in four locations simultaneously. cess gas (N2, O2, Ar, etc.). Can pro-
rigid-flex data created by PCB CAD tools Internal roll-to-roll using roll-inside tech-
nology. Provides built-in beam validation cess one or more substrates in parallel.
in 2-D and 3-D view ports, as well as docu-
menting rigid/rigid-flex stack-ups; can share tools for size, roundness and energy Other features include automatic cam-
documentation with fabricators. Features distribution with continuous beam uni- era calibration, automated routines for
include import/export ODB++ and IPC-2581 formity technology. Offers roll-to-roll and reference runs, automated process con-
modification; import/export modification to sheet-by-sheet handling of thin flex cores trol, and automated vision system for
support PCB core material data; stack-up with capacity to drill two panel sheets precision alignment and scaling, offset,
visualizer modification; 3-D view port modi- side by side. Optional roll widths of trapezoidal and rotation compensation.
fication; area tool modification; DfM analysis 260mm and up to 520mm. Minimum via Comes as standalone or integrated in
modification; parametric solder and paste size is 20 µm. Footprint is 5 sq. m. production line.
mask generation; assembly panel creation.
DownStream Technologies Orbotech Innolas Solutions
downstreamtech.com orbotech.com innolas-solutions.com
OTHERS OF NOTE OTHERS OF NOTE
MACDERMID HELIOFAB AG 7921 DOWNSTREAM BLUEPRINT-PCB V. 6 EASYLOGIX PCB-INVESTIGATOR V. 12

HelioFab AG 7921 silver electroplating BluePrint-PCB v. 6 has a 2-D/3-D environ- PCB-Investigator v. 12 CAD/CAM includes
process for leadframe-based LED pack- ment for improved PCB post-processing. new plugin for DfT preparation. Defines
ages is said to consistently deposit highly Is designed to automate, streamline and test probes for fixture and fixtureless
reflective silver with measured GAM val- improve PCB documentation. Common devices using different rules and can be
ues around 2.0 over a current density database among all DownStream prod- exported for Seica, Takaya and HP3070
window of 10 to 70ASD. Bath produces ucts allows easy file-sharing and transi- machines. Extended design report: more
a stable deposit over the standard 100 tions. New user interface for continuity. images, analyze results, and intelligent
AH/L industry bath life metric. Deposit linking. Fully supports Gerber X2.
passes all standard testing for LED per-
formance such as 1,000-hr. luminous
decay, as well as assembly functional
testing for gold wire bond pull and die
attach shear strength.
MacDermid Alpha Electronics DownStream Technologies EasyLogix
macdermidalpha.com downstreamtech.com pcb-investigator.com/en
VISHAY VEMD4010X01, NUMBER ONE SYSTEMS EASY-PC HIROSE CX90MW CONNECTOR

VEMD4110X01 V. 24 CX90MW waterproof USB 3.2 Gen 1
VEMD4010X01 and VEMD4110X01 sur- Easy-PC v. 24 ECAD has more than 50 Type-C connector is for applications that
face-mount automotive-grade silicon PIN new enhancements. Delivers perfor- require miniaturization with resistance to
photodiodes come in 0805 case size with mance in schematic capture and PCB liquid, vibration and/or shock. Mounting
0.7mm profile. Offered in black pack- layout and is simple to learn. Enables area reportedly 22% smaller than other
ages, opaque side walls eliminate side control of thermal spokes on individual receptacles. Is rated to IPX8. Includes
illumination to increase signal-to-noise pads or pad styles; pads on same net can front sealing gasket that prevents water
ratio. Are RoHS-compliant, halogen-free, be allocated to different thermal spokes penetration into shell, while potting pre-
and MSL 3. depending on size. Shows net details. vents water intrusion into interior. Sup-
ports data rates up to 5Gbps.
Vishay Number One Systems Hirose
vishay.com numberone.com hirose.com/us

MACHINES MATERIALS TOOLS SYSTEMS SOFTWARE
TEKTRONIX 6 SERIES B ECD SELECTIVERIDER ESPEC AR SERIES

6 series B mixed signal oscilloscope SelectiveRider soldering process mea- Four new models of AR series environ-
extends performance to 10GHz and surement pallet performs automated mental stress chambers are capable of
50GS/sec. Offers signal fidelity with verification for wave, reflow and selec- precise control over a temp. range of
12-bit ADCs and low noise, 10GHz band- tive processes. Validates three phases of -70° to +180°C (with optional support
width and up to 8 FlexChannel inputs. selective soldering: fluxing, pre-heating for up to 200°C) and a humidity range of
Contributes less than 51.1µV of noise at and soldering. Verifies flux location and 10% to 98%RH. Air temp. can be raised
1mV/div and 1GHz and less than 1.39mV accuracy; confirms dispense X/Y posi- or lowered at rate of 10°C per min. or
of noise at 50 mV/div and 10GHz. Band- tional precision; IDs blocked or unprimed 15°C per min. during testing between
width is more than 2GHz with 4, 6 or 8 spray heads; verifies dot size, and more. -40° and +125°C. with or without humid-
channels. Built-in digital down convert- ity control. Comply with IEC international
ers behind every channel enable multi- standards and LV 124. Stable control
channel spectrum analysis. possible for 95°C/98%RH and other high-
temp., high-humidity tests.
Tektronix ECD Espec
tektronix.com ecd.com espec.com
OTHERS OF NOTE
MASTER BOND EP42HT-4AOMED DELO DUALBOND GE4918 ELECTROLUBE ER6006, ER7006

BLACK Dualbond GE4918 light- and humidity- ER6006 and ER7006 Bio epoxy resins
EP42HT-4AOMed Black two-part epoxy curing sealant for connectors for vehi- provide good flow characteristics for
created for medical device manufactur- cle control units or sensors. Reportedly potting of difficult and complex geom-
ing is biocompatible and non-cytotoxic, offers pin sealing properties, increases etries. ER6006 is two-part high thermally
passing USP Class VI and ISO 10993- connector life and permits efficient pro- conductive epoxy encapsulation resin
5 certifications. Withstands aggressive duction. Adheres to mercaptan coating primarily developed for encapsulation
chemical sterilants, radiation and repeat- and connector housing materials PA and of LED driver units. Offers high chemical
ed cycles of autoclaving. Offers cryogen- PBT. Temp. resistance up to +150°C. resistance and protection in a range of
ic serviceability and heat resistance with environments. Cures in 1 hr. at 100°C, 3
service temp. range from 4K to 400°F. hr. at 60°C or 24 hr. at room temp.
Room temp. curable.
Master Bond Delo Electrolube
masterbond.com delo-adhesives.com electrolube.in
THERMO FISHER AXIA CHEMISEM HUMISEAL VIVID CURE UV6041, SHENMAO SMEF-Z3 FLUX
Axia ChemiSEM scanning electron micro- UV7041 SMEF-Z3 joint-enhanced flux is designed
scope includes always-on EDS analysis. Vivid Cure UV6041 and UV7041 liquid, for fine-pitch assembly and LED die
New auto-alignment and auto-focus tech- optically clear adhesives (LOCA) provide
nology lowers need for training. Chamber attach. Is compatible with solder paste.
enhanced optical properties and improved
and stage design aids in investigation of durability of optical devices and displays. Can be applied after solder paste print-
samples of all shapes and sizes, includ- Are formulated for wireless communica- ing and cured simultaneously during
ing samples up to 10kg. Offers instant tions, automotive displays, medical devic- reflow process. Can be used for pin-
quantitative elemental information with- es, and aerospace and avionic controls. transfer and stencil printing processes.
out additional setup or switching between Properties include low shrinkage, superior
UIs. Large, flexible chamber accommo- and variable light transmission properties,
dates samples traditionally considered too resistance to discoloration, and resistance
heavy for investigations involving elec- to both thermal and mechanical damage.
Cured to final properties using UVA or vis-
tron microscopy. ible light. 100% VOC-free.
Thermo Fisher Scientific Humiseal Shenmao
thermofisher.com chasecorp.com/humiseal shenmao.com

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Toll Blending · Product Modifications
1 (877) 259-1669 ∙ resinlab.com

TECHNICAL ABSTRACTS
In Case You Missed It

AI-Based Semiconductors ture is exposed to heat. Mechanical stresses may also
“Fully Light-Controlled Memory and Neuromorphic affect intermetallic growth behavior. These stresses
Computation in Layered Black Phosphorusy” arise not only from external loadings but also from
Authors: Taimur Ahmed, et al. thermal mismatch of the materials constituting the
Abstract: Imprinting vision as memory is a core joint, and from the mismatch produced by the change
attribute of human cognitive learning. Fundamental in shape and volume due to the chemical reactions of
to artificial intelligence systems are bioinspired neuro- IMC formation. This explains why in this paper spe-
morphic vision components for the visible and invis- cial attention is paid to the influence of stresses on the
ible segments of the electromagnetic spectrum. Real- kinetics of the IMC growth. The authors have devel-
ization of a single imaging unit with a combination oped an approach that couples mechanics with the
of in-built memory and signal processing capability is chemical reactions leading to the formation of IMC,
imperative to deploy efficient brain-like vision systems. based on the thermodynamically sound concept of the
However, the lack of a platform that can be fully con- chemical affinity tensor, which was recently used in
trolled by light without the need to apply alternating general statements and solutions of mechanochemistry
polarity electric signals has hampered this technologi- problems. The authors start with a report of experi-
cal advance. Here, a neuromorphic imaging element mental findings regarding the IMC growth at the inter-
based on a fully light-modulated 2-D semiconductor face between copper pads and tin-based solder alloys
in a simple reconfigurable phototransistor structure in different microchips during a high-temperature
is presented. This standalone device exhibits inher- storage test. Then the growth kinetics are analyzed by
ent characteristics that enable neuromorphic image means of a continuum model. By combining experi-
pre-processing and recognition. Fundamentally, the ment, theory, and a comparison of experimental data
unique photo response induced by oxidation-related and theoretical predictions, the authors finally find the
defects in 2-D black phosphorus (BP) is exploited to values of the diffusion coefficient and an estimate for
achieve visual memory, wavelength-selective multibit the chemical reaction constant. A comparison with
programming, and erasing functions, which allow in- literature data is also performed. (Journal of Electronic
pixel image pre-processing. Furthermore, all optically- Materials, September 2020, https://link.springer.com/
driven neuromorphic computation is demonstrated by article/10.1007/s11664-020-08433-y)
machine learning to classify numbers and recognize
images with an accuracy of over 90%. The devices Thermistors
provide a promising approach toward neurorobotics, “Inkjet Printing of Perovskites for Breaking Perfor-
human-machine interaction technologies, and scal- mance-Temperature Tradeoffs in Fabric-Based Therm-
able bionic systems with visual data storage/buffer- istors”
ing and processing. (Advanced Materials, November Authors: Shujie Li, Alex Kosek, Mohammad Naim
2020, https://onlinelibrary.wiley.com/doi/abs/10.1002/ Jahangir, Rajiv Malhotra and Chih-Hung Chang.
adma.202004207) Abstract: A novel low-temperature route is devel-
oped for inkjet printing of the perovskite Cs2SnI6
to create wearable negative-temperature-coefficient
Solder Alloys thermistors with unprecedented performance on ther-
“Experimental and Theoretical Studies of Cu-Sn Inter- mally sensitive fabrics. A low processing temperature
metallic Phase Growth During High-Temperature of 120°C is achieved by creating a stable and printable
Storage of Eutectic SnAg Interconnects” ink using binary metal iodide salts, which is ther-
Author: A. Morozov, A. B. Freidin, et al. mally transformed into dense Cs2SnI6 crystals after
Abstract: The growth of intermetallic compound printing. The optimally printed Cs2SnI6 shows a tem-
(IMC) layers is considered. After soldering, an IMC perature measurement range up to 120°C, high sen-
layer appears and establishes a mechanical contact sitivity (4400K), temperature coefficient of resistivity
This column provides
between eutectic tin-silver solder bumps and Cu inter- (0.05°C−1), and stability under ambient environmental
abstracts from recent
connects in microelectronic components. Intermetallics conditions and bending. The approach breaks a criti-
industry conferences
are relatively brittle in comparison with copper and cal tradeoff that has hindered wearable fabric-based
and company white
papers. Our goal is
tin. In addition, IMC formation is typically based thermistors by enabling damage-free fabrication of
to provide an added on multi-component diffusion, which may include devices with commercially comparable performance,
opportunity for read- vacancy migration leading to Kirkendall voiding. Con- evincing significant applications in multifunctional
ers to keep abreast of sequently, the rate of IMC growth has a strong impli- textiles and beyond. (Advanced Functional Materi-
technology and busi- cation on solder joint reliability. Experiments show the als, September 2020, https://onlinelibrary.wiley.com/
ness trends. intermetallic layers grow considerably when the struc- doi/10.1002/adfm.202006273)

UPGR ADE
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HDP: Breaking the E-Glass Mold

F a c t ory of the Futu

Flex Residue Monitoring

POSTMASTER: Send address changes to

DESIGN TECHNICAL EDITOR

PCD&F CONTRIBUTING EDITORS

UP MEDIA GROUP, INC.

Printed Circuit Design & Fab/Circuits Assembly is distributed without charge to

Postmaster: Send address changes to

4 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

‘Future Factories’ Require

6 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

3D Glass Solutions, Nokia Collaborate on D-Band

IMI Inc. successfully completed an inten-

8 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

complex PCB system design challenges and produce industry-leading products.

JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 9

Zestron named James Mueller

10 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

METALS INDEX OUT OF STORAGE

JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 11

Revealed: Technology Really Works!

12 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

PCB Costs Are Going Up. Here’s What to Do

JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 13

Estimating the PCB Design Cycle with Limited

14 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

FIGURE 2. A Gantt chart helps visualize scheduling dependencies.

JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 15

Today’s Best Technologies are the Roadmap to an

16 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

PCEA 2020: Small Rearview Mirror, Big Windshield

PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

FIGURE 1. Mike Creeden. FIGURE 2. Chris Hunrath. FIGURE 3. Luke Hausherr.

PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

Cutting Your Losses Upfront in PCB Design

Why we care. Everything that improves material

JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 17

Wrapping up. If you can

18 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

NEW DFX MODULE for IPC-2581 Slices

JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 19

board structure within the same IPC-2581 file (FIGURE 3).

HEMANT SHAH is an EDA veteran and chair of the IPC-2581 Consortium

FIGURE 1. The new spec supports rigid-flex with

FIGURE 2. IPC-DPMX supports all types of embed-

“Polar's customers in the design and

ipc2581.com FIGURE 4. Thermal relief coin.

20 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

Chiplet Implementation via VIRTUAL

22 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 23

Are OLDER STANDARDS Still Valid,

24 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

JANUARY 2021 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY 25

The PCB Podcast

PROCESS CONTROL PLAN to

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Process Control Plan

The CIRCUITS ASSEMBLY

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PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

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40 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY JANUARY 2021

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