MPC5674F

NXP Semiconductors Document Number: MPC5674F
Data Sheet: Technical Data Rev. 11, 10/2021
MPC5674F
MPC5674F Microcontroller TEPBGA–416
27mm x 27mm
TEPBGA–516
27mm x 27mm
Data Sheet
Covers: MPC5674F and MPC5673F TEPBGA–324
23mm x 23mm
• Dual issue, 32-bit CPU core complex (e200z7) single action, double action, pulse width modulation
– Compliant with the Power Architecture® embedded (PWM) and modulus counter operation
category • Four enhanced queued analog-to-digital converters
– 16 KB I-Cache and 16 KB D-Cache (eQADC)
– Includes an instruction set enhancement allowing – Support for 64 analog channels
variable length encoding (VLE), optional encoding of – Includes one absolute reference ADC channel
mixed 16-bit and 32-bit instructions, for code size – Includes eight decimation filters
footprint reduction • Four deserial serial peripheral interface (DSPI) modules
– Includes signal processing extension (SPE2) instruction • Three enhanced serial communication interface (eSCI)
support for digital signal processing (DSP) and modules
single-precision floating point operations • Four controller area network (FlexCAN) modules
• 4 MB on-chip flash • Dual-channel FlexRay controller
– Supports read during program and erase operations, and • Nexus development interface (NDI) per IEEE-ISTO
multiple blocks allowing EEPROM emulation 5001-2003/5001-2008 standard
• 256 KB on-chip general-purpose SRAM including 32 KB • Device and board test support per Joint Test Action Group
of standby RAM (JTAG) (IEEE 1149.1)
• Two direct memory access controller (eDMA2) blocks • On-chip voltage regulator controller regulates supply
– One supporting 64 channels voltage down to 1.2 V for core logic
– One supporting 32 channels
• Interrupt controller (INTC)
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
• External bus interface (EBI) for calibration and application
development (not available on all packages)
• System integration unit (SIU)
• Error correction status module (ECSM)
• Boot assist module (BAM) supports serial bootload via
CAN or SCI
• Two second-generation enhanced time processor units
(eTPU2) that share code and data RAM.
– 32 standard channels per eTPU2
– 24 KB code RAM
– 6 KB parameter (data) RAM
• Enhanced modular input output system supporting 32
unified channels (eMIOS) with each channel capable of
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 35
1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4.8 Oscillator and FMPLL Electrical Characteristics . . . . . 35
1.2 MPC567xF Family Differences . . . . . . . . . . . . . . . . . . . .4 4.9 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 37
2 MPC5674F Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4.9.1 ADC Internal Resource Measurements . . . . . . 39
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 40
3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1 324-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6 4.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .9 4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 44
3.3 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . .14 4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4 Signal Properties and Muxing . . . . . . . . . . . . . . . . . . . .19 4.12.1 Generic Timing Diagrams . . . . . . . . . . . . . . . . 45
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 46
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.12.3 IEEE 1149.1 Interface Timing . . . . . . . . . . . . . 47
4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21 4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.1 General Notes for Specifications at 4.12.5 External Bus Interface (EBI) Timing . . . . . . . . . 53
Maximum Junction Temperature . . . . . . . . . . . .23 4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 57
4.3 EMI (Electromagnetic Interference) Characteristics . . .24 4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .25 4.12.9 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .29 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.6.1 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.1 324-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.2 416-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.6.3 Power Sequencing and POR Dependent on VDDA 5.3 516-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
30 6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30 Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 73
4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .33 Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.7.2 I/O Pad VDD33 Current Specifications . . . . . . . .34
MPC5674F Microcontroller Data Sheet, Rev. 11

2 NXP Semiconductors
Ordering Information
1 Ordering Information
1.1 Orderable Parts
Figure 1 and Table 1 describe and list the orderable part numbers for the MPC5674F.
M PC 5674F F 3 M VR 3 R
Qualification status
Core code
Note: Not all options are
available on all Device number
devices. Refer to Fab Revision ID
Table 1. Revision of Silicon
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Temperature Range Package Identifier Operating Frequency Tape and Reel Status
M = –40 °C to 125 °C VZ = 324 BGA Pb-free 2 = 200 MHz R = Tape and reel
VR = 416 BGA Pb-free 3 = 264 MHz (blank) = Trays
VY = 516 BGA Pb-free
VV = 516 BGA SnPb Fab and Mask Indicator
F = ATMC Fab
Qualification Status Revision of Silicon K = TSMC Fab
P = Pre qualification 3 = Rev 3 (ATMC) A = ATMC Fab or TSMC Fab
M = Fully spec. qualified, general market flow 0 = Rev 0 (TSMC14) Second digit usually differentiate
S = Fully spec. qualified, automotive flow mask rev
Figure 1. MPC5674F Orderable Part Number Description
Table 1. Orderable Part Numbers
Speed (MHz)1 Operating Temperature2

NXP Part Number Package Description
Nominal Max3 (fMAX) Min (TL) Max (TH)
SPC5674FK0MVR3 416 PBGA, no EBI, Pb-free 264 270 –40 °C 125 °C

SPC5674FK0MVY3 516 PBGA, w/EBI, Pb-free 264 270 –40 °C 125 °C
SPC5674FK0MVV3R 516 PBGA, w/EBI, SnPb 264 270 –40 °C 125 °C
SPC5674FK0MVV3 516 PBGA, w/EBI, SnPb 264 200 –40 °C 125 °C
SPC5674FK0MVY3R 516 PBGA, w/EBI, Pb-free 264 270 –40 °C 125 °C
SPC5673FK0MVR2R 416 PBGA, no EBI, Pb-free 200 200 –40 °C 125 °C
SPC5673FK0MVR2 416 PBGA, no EBI, Pb-free 200 200 –40 °C 125 °C
SPC5673FK0MVV2R 324 PBGA, no EBI, Pb-free 200 200 –40 °C 125 °C
SPC5673FK0MVV2 324 PBGA, no EBI, Pb-free 200 200 –40 °C 125 °C
SPC5673FF3MVR2 416 PBGA, no EBI, Pb-free 200 200 -40°C 125 °C

NXP Semiconductors 3
Ordering Information
Table 1. Orderable Part Numbers (continued)
Speed (MHz)1 Operating Temperature2

NXP Part Number Package Description
Nominal Max3 (fMAX) Min (TL) Max (TH)
SPC5673FF3MVV2 516 PBGA, w/EBI, SnPb 264 200 –40 °C 125 °C

SPC5673FF3MVY2 516 PBGA, w/EBI, SnPb 264 200 –40 °C 125 °C
SPC5674FF3MVY3 516 PBGA, w/EBI, SnPb 264 200 –40 °C 125 °C
SPC5674FAMVR3 416 PBGA, no EBI, Pb-free 200 200 -40°C 125 °C
SPC5674FAMVY3 516 PBGA, w/EBI, SnPb 264 200 –40 °C 125 °C
SPC5674FF3MVV3 516 PBGA, w/EBI, SnPb 264 200 –40 °C 125 °C
1
For the operating mode frequency of various blocks on the device, see Table 28.
2
The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH.
3 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
270 MHz parts allow for 264 MHz system clock + 2% FM.
1.2 MPC567xF Family Differences

Table 2 lists the differences between the MPC567xF devices. Refer to the MPC5674F Reference Manual for a full feature list
and comparison.
Table 2. MPC567xF Family Differences
Feature MPC5674F MPC5674F MPC5673F MPC5673F
Package 416 BGA 324 BGA 416 BGA 324 BGA
516 BGA 516 BGA
Flash 4 MB 4 MB 3 MB 3 MB
SRAM 256 KB 256 KB 192 KB 192 KB
External bus Yes No Yes No
(516 BGA only) (516 BGA only)
Serial 3 2 3 2
eSCI_A Yes Yes Yes Yes
eSCI_B Yes Yes Yes Yes
eSCI_C Yes No Yes No
SPI 4 3 4 3
DSPI_A Yes No Yes No
DSPI_B Yes Yes Yes Yes
DSPI_C Yes Yes Yes Yes
DSPI_D Yes Yes Yes Yes
eMIOS 32 channel 22 channel 32 channel 22 channel
eTPU2 64 channel 47 channel 64 channel 47 channel
eTPU_A Yes (32 ch) Yes (26 ch) Yes Yes (26 ch)
eTPU_B Yes (32 ch) Yes (21 ch, no Yes Yes (21 ch, no
TCRCLK) TCRCLK)
ADC 64 channel 48 channel 64 channel 48 channel
eQADC_A 1 Yes (24 ch) Yes (24 ch)
Yes (64 ch) Yes (64 ch)1
eQADC_B Yes (24 ch) Yes (24 ch)
1
There are are two pairs of 24 channels plus 16 shared channels. This gives 64 channels total: 40 per
ADC (since 16 are shared).

MPC5674F Blocks
2 MPC5674F Blocks
2.1 Block Diagram
Figure 2 shows a top-level block diagram of the MPC5674F device.
MPC5674F Power™
e200z7 Core
Interrupt SPE2
Nexus JTAG
Controller VLE
MMU
eDMA2 eDMA2 16K 16K
64 Channel 32 Channel I-Cache D-Cache FlexRay
EBI
(Calibration
&
Crossbar Switch Development
Use)
MPU
4MB I/O 256KB SRAM Boot Assist I/O

Flash Bridge SIU (32K S/B) Module Bridge ECSM
eQADC eQADC
DECFILx8
FlexCAN
FlexCAN
FlexCAN
FlexCAN
6KB
DSPI
DSPI
DSPI
DSPI
eSCI
eSCI
eSCI
Data ADCi ADCi

eMIOS eTPU2 RAM eTPU2
32 32 32
ADC
ADC
ADC
ADC
Channel Channel 24KB Channel
Code
RAM
AMux
LEGEND
ADC – Analog to digital convertor eSCI – Enhanced serial communications interface
ADCi – ADC interface eTPU2 – Enhanced time processing unit 2
AMux – Analog multiplexer FlexCAN– Controller area network
DECFIL – Decimation filter MMU – Memory management unit
DSPI – Deserial/serial peripheral interface MPU – Memory protection unit
EBI – External bus interface S/B – Stand-by
ECSM – Error correction status module SIU – System integration unit
eDMA2 – Enhanced direct memory access SPE2 – Signal processing engine 2
eMIOS – Enhanced modular I/O system SRAM – General-purpose static RAM
eQADC – Enhanced queued A/D converter module VLE – Variable length instruction encoding
Figure 2. Block Diagram
3 Pin Assignments
The figures in this section show the primary pin function. For the full signal properties and muxing table, see Appendix A,
Signal Properties and Muxing.

Pin Assignments
3.1 324-ball TEPBGA Pin Assignments

Figure 3 shows the 324-ball TEPBGA pin assignments. The same information is shown in Figure 4 through Figure 5.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
REF– REF–
A VSS VDD RSTOUT ANA0 ANA1 ANA4 ANA5 ANA15 VDDA_A0 VRH_A VRL_A VDDA_ B0 VRL_B VRH_B ANB2 ANB3 ANB6 ANB7 ANB22 VSS A
BYPCB1 BYPCB1
REF– REF–
B VDDEH1 VSS VDD TEST ANA2 ANA3 ANA6 ANA7 VDDA_A0 VSSA_A1 VDDA_ B1 VSSA_ B0 ANB0 ANB1 ANB4 ANB5 ANB19 ANB23 VSS TCRCLKC B
BYPCA BYPCB
C ETPUA21 ETPUA26 VSS VDD ANA8 ANA10 ANA9 ANA13 ANA17 ANA19 ANA21 ANA23 ANB10 ANB9 ANB11 ANB12 ANB14 ANB16 ANB20 VSS ETPUC0 VDDEH7 C
D ETPUA23 ETPUA25 ETPUA31 VSS VDD ANA11 ANA12 ANA14 ANA16 ANA18 ANA20 ANA22 ANB8 ANB13 ANB15 ANB17 ANB18 ANB21 VSS ETPUC1 ETPUC3 ETPUC2 D
E ETPUA20 ETPUA22 ETPUA24 ETPUA30 ETPUC5 ETPUC10 ETPUC11 ETPUC4 E
F ETPUA13 ETPUA14 ETPUA15 ETPUA27 ETPUC12 ETPUC14 ETPUC13 ETPUC9 F

MPC5674F 324 TEPBGA
G ETPUA10 ETPUA11 ETPUA12 ETPUA17 (as viewed from top through the package) ETPUC20 ETPUC18 ETPUC19 ETPUC17 G
H ETPUA5 ETPUA6 ETPUA9 ETPUA16 VDDEH7 ETPUC23 ETPUC22 ETPUC21 H
J ETPUA1 ETPUA2 ETPUA3 ETPUA4 VSS VSS VSS VSS VSS VSS ETPUC27 ETPUC28 ETPUC26 ETPUC24 J
K TCRCLKA ETPUA0 VDD VSTBY VSS VSS VSS VSS VSS VSS ETPUC31 ETPUC30 ETPUC29 ETPUC25 K
BOOT-
L PLLCFG1 PLLCFG2 VDDEH1 VSS VSS VSS VSS VSS VSS ETPUB12 ETPUB13 ETPUB14 VDDEH7 L
CFG1
M JCOMP RESET PLLCFG0 RDY VDDE2 VSS VSS VSS VSS VSS ETPUB7 ETPUB10 ETPUB11 ETPUB9 M
N VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VSS VSS VSS VSS ETPUB0 VDDEH6 ETPUB8 ETPUB6 N
P EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VSS VSS VSS VSS TCRCLKB ETPUB16 ETPUB5 ETPUB4 P
R MDO2 MDO3 MDO4 MDO5 ETPUB1 ETPUB17 ETPUB3 ETPUB2 R
T MDO6 MDO7 MDO8 VDDE2 ETPUB19 ETPUB18 VDDEH6 REGCTL T
U MDO9 MDO10 MDO11 MDO15 ETPUB31 ETPUB30 VDDREG VSSSYN U
V MDO12 VDDE2 MDO14 VDD33_2 VDD REGSEL VSSFL EXTAL V
W TDO MDO13 TMS VSS VDD VDDE2 PCSB2 VDDEH4 VDD EMIOS8 EMIOS9 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNTXC CNRXC CNRXB VSS VDD VDD33_3 XTAL W
FR_A_ FR_B_
Y TCK TDI VSS VDD SCKA SCKB PCSB0 EMIOS2 EMIOS5 EMIOS14 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNRXD VSS VDD VDDSYN Y
TX TX
FR_A_ FR_B_
AA ENGCLK VSS VDD PCSA5 SINA SINB EMIOS0 EMIOS3 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS28 EMIOS29 CNRXA SCKC SINC VSS VDD AA
RX RX
FR_A_ FR_B_
AB VSS VDD VDDE2 TX_EN PCSA0 SOUTA SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 CNTXA SOUTC PCSC0 VDDEH4 CNTXD VSS AB
TX_EN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Figure 3. MPC5674F 324-ball TEPBGA (full diagram)

Pin Assignments
1 2 3 4 5 6 7 8 9 10 11
A VSS VDD RSTOUT ANA0 ANA1 ANA4 ANA5 ANA15 VDDA_A0 VRH_A VRL_A A
REF–
B VDDEH1 VSS VDD TEST ANA2 ANA3 ANA6 ANA7 VDDA_A0 VSSA_A1 B
BYPCA
C ETPUA21 ETPUA26 VSS VDD ANA8 ANA10 ANA9 ANA13 ANA17 ANA19 ANA21 C
D ETPUA23 ETPUA25 ETPUA31 VSS VDD ANA11 ANA12 ANA14 ANA16 ANA18 ANA20 D
E ETPUA20 ETPUA22 ETPUA24 ETPUA30
F ETPUA13 ETPUA14 ETPUA15 ETPUA27

MPC5674F 324 TEPBGA
G ETPUA10 ETPUA11 ETPUA12 ETPUA17 (as viewed from top through the package)
H ETPUA5 ETPUA6 ETPUA9 ETPUA16
J ETPUA1 ETPUA2 ETPUA3 ETPUA4 VSS VSS VSS J
K TCRCLKA ETPUA0 VDD VSTBY VSS VSS VSS K
BOOT-
L PLLCFG1 PLLCFG2 VDDEH1 VSS VSS VSS L
CFG1
M JCOMP RESET PLLCFG0 RDY VDDE2 VSS VSS M
N VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VSS N
P EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VSS P
R MDO2 MDO3 MDO4 MDO5
T MDO6 MDO7 MDO8 VDDE2
U MDO9 MDO10 MDO11 MDO15
V MDO12 VDDE2 MDO14 VDD33_2
W TDO MDO13 TMS VSS VDD VDDE2 PCSB2 VDDEH4 VDD EMIOS8 EMIOS9 W
FR_A_ FR_B_
Y TCK TDI VSS VDD SCKA SCKB PCSB0 EMIOS2 EMIOS5 Y
TX TX
FR_A_ FR_B_
AA ENGCLK VSS VDD PCSA5 SINA SINB EMIOS0 EMIOS3 EMIOS10 AA
RX RX
FR_A_ FR_B_
AB VSS VDD VDDE2 PCSA0 SOUTA SOUTB EMIOS1 EMIOS4 EMIOS7 AB
TX_EN TX_EN
1 2 3 4 5 6 7 8 9 10 11
Figure 4. MPC5674F 324-ball TEPBGA (1 of 2)

Pin Assignments
12 13 14 15 16 17 18 19 20 21 22
REF– REF–
A VDDA_ B0 VRL_B VRH_B ANB2 ANB3 ANB6 ANB7 ANB22 VSS A
BYPCB1 BYPCB1
REF–
B
BYPCB VDDA_ B1 VSSA_ B0 ANB0 ANB1 ANB4 ANB5 ANB19 ANB23 VSS TCRCLKC B
C ANA23 ANB10 ANB9 ANB11 ANB12 ANB14 ANB16 ANB20 VSS ETPUC0 VDDEH7 C
D ANA22 ANB8 ANB13 ANB15 ANB17 ANB18 ANB21 VSS ETPUC1 ETPUC3 ETPUC2 D
ETPUC5 ETPUC10 ETPUC11 ETPUC4 E
ETPUC12 ETPUC14 ETPUC13 ETPUC9 F

MPC5674F 324 TEPBGA
(as viewed from top through the package) ETPUC20 ETPUC18 ETPUC19 ETPUC17 G
VDDEH7 ETPUC23 ETPUC22 ETPUC21 H
J VSS VSS VSS ETPUC27 ETPUC28 ETPUC26 ETPUC24 J
K VSS VSS VSS ETPUC31 ETPUC30 ETPUC29 ETPUC25 K
L VSS VSS VSS ETPUB12 ETPUB13 ETPUB14 VDDEH7 L
M VSS VSS VSS ETPUB7 ETPUB10 ETPUB11 ETPUB9 M
N VSS VSS VSS ETPUB0 VDDEH6 ETPUB8 ETPUB6 N
P VSS VSS VSS TCRCLKB ETPUB16 ETPUB5 ETPUB4 P
ETPUB1 ETPUB17 ETPUB3 ETPUB2 R
ETPUB19 ETPUB18 VDDEH6 REGCTL T
ETPUB31 ETPUB30 VDDREG VSSSYN U
VDD REGSEL VSSFL EXTAL V
W EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNTXC CNRXC CNRXB VSS VDD VDD33_3 XTAL W
Y EMIOS14 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNRXD VSS VDD VDDSYN Y
AA EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS28 EMIOS29 CNRXA SCKC SINC VSS VDD AA
AB EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 CNTXA SOUTC PCSC0 VDDEH4 CNTXD VSS AB
12 13 14 15 16 17 18 19 20 21 22

Pin Assignments

Figure 6 shows the 416-ball TEPBGA pin assignments in one figure. The same information is shown in Figure 7 through
Figure 10.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
REF–
A VSS VDD RSTOUT ANA0 ANA4 ANA8 ANA11 ANA15 VDDA_A0 VRL_A VRH_A AN28 AN32 AN36 VDDA_B0 REF– VRL_B VRH_B ANB7 ANB11 ANB14 ANB17 ANB21 ANB23 VSS A
BYPCA1 BYPCB1
REF– AN33 VDDA_B1 VSSA_B0 REF– ANB6
B VDDEH1 VSS VDD TEST ANA1 ANA5 ANA10 ANA14 VDDA_A1 VSSA_A1 BYPCA AN24 AN27 AN29
BYPCB
ANB8 ANB10 ANB15 ANB18 ANB22 VSS TCRCLKC B
C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 ANA9 ANA13 ANA17 ANA19 ANA21 ANA23 AN26 AN30 AN34 AN37 AN38 ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 VSS ETPUC0 ETPUC1 C
D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 ANA7 ANA12 ANA16 ANA18 ANA20 ANA22 AN25 AN31 AN35 AN39 ANB1 ANB2 ANB3 ANB9 ANB13 ANB20 VSS VDDEH7 ETPUC2 ETPUC3 D
E ETPUA23 ETPUA24 ETPUA25 ETPUA26 VDDEH7 ETPUC4 ETPUC5 ETPUC6 E
F ETPUA19 ETPUA20 ETPUA21 ETPUA22 ETPUC7 ETPUC8 ETPUC9 ETPUC10 F
G ETPUA15 ETPUA16 ETPUA17 ETPUA18

MPC5674F 416-ball TEPBGA ETPUC11 ETPUC12 ETPUC13 ETPUC14 G
(as viewed from top through the package)
H ETPUA11 ETPUA12 ETPUA14 ETPUA13 ETPUC15 ETPUC16 ETPUC17 ETPUC18 H
J ETPUA7 ETPUA8 ETPUA9 ETPUA10 ETPUC19 ETPUC20 ETPUC21 ETPUC22 J
K ETPUA3 ETPUA4 ETPUA5 ETPUA6 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC23 ETPUC24 ETPUC25 ETPUC26 K
L TCRCLKA ETPUA0 ETPUA1 ETPUA2 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC27 ETPUC28 ETPUC29 ETPUC30 L
M VDD33_1 TXDA RXDA VSTBY VSS VSS VSS VSS VSS VSS VSS VSS ETPUC31 ETPUB15 ETPUB14 VDDEH7 M
BOOT– VDDE2 VSS VSS VSS VSS VSS VSS VSS

N RXDB CFG1 WKPCFG VDD VDDEH6 ETPUB11 ETPUB12 ETPUB13 N
P TXDB PLLCFG1 PLLCFG2 VDDEH1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB7 ETPUB8 ETPUB9 ETPUB10 P
R JCOMP RESET PLLCFG0 RDY VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB3 ETPUB4 ETPUB5 ETPUB6 R
T VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS TCRCLKB ETPUB0 ETPUB1 ETPUB2 T
U EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB19 ETPUB18 ETPUB17 ETPUB16 U
V MDO2 MDO3 MDO4 MDO5 ETPUB26 ETPUB22 ETPUB21 ETPUB20 V
W MDO6 MDO7 MDO8 VDDE2 REGSEL ETPUB25 ETPUB24 ETPUB23 W
Y MDO9 MDO10 MDO11 MDO15 ETPUB29 ETPUB28 ETPUB27 REGCTL Y
AA MDO12 MDO13 MDO14 VDD33_2 VDD33_3 ETPUB30 VDDREG VSSSYN AA
AB TDO TCK TMS VDD VDD ETPUB31 VSSFL EXTAL AB
AC VDDE2 TDI VDD VSS VDDE2 PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4 VDD EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1 VSS VDD VDDEH6 XTAL AC
FR_A_ FR_B_
AD ENGCLK VDD VSS PCSA5 SOUTA SCKA PCSB0 PCSB3 EMIOS2 EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNTXD SCKC RXDC PCSC3 VSS VDD VDDSYN AD
TX TX
FR_A_ FR_B_
AE VDD VSS PCSA4 PCSA0 PCSA3 SCKB SINB EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0 SINC PCSC2 PCSC5 VSS VDD AE
RX RX
FR_A_ FR_B_
AF VSS VDDE2 TX_EN TX_EN VDDEH3 PCSB5 SINA PCSB2 SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 VSS AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13
REFBYP-
A VSS VDD RSTOUT ANA0 ANA4 ANA8 ANA11 ANA15 VDDA_A0 VRL_A VRH_A AN28 A
CA1
B VDDEH1 VSS VDD TEST ANA1 ANA5 ANA10 ANA14 VDDA_A1 VSSA_A1 REFBYPCA AN24 AN27 B
C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 ANA9 ANA13 ANA17 ANA19 ANA21 ANA23 AN26 C
D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 ANA7 ANA12 ANA16 ANA18 ANA20 ANA22 AN25 D
E ETPUA23 ETPUA24 ETPUA25 ETPUA26 E
F ETPUA19 ETPUA20 ETPUA21 ETPUA22 F
MPC5674F 416-ball TEPBGA

G ETPUA15 ETPUA16 ETPUA17 ETPUA18 (as viewed from top through the package) G
(1 of 4)
H ETPUA11 ETPUA12 ETPUA14 ETPUA13 H
J ETPUA7 ETPUA8 ETPUA9 ETPUA10 J
K ETPUA3 ETPUA4 ETPUA5 ETPUA6 VSS VSS VSS VSS K
L TCRCLKA ETPUA0 ETPUA1 ETPUA2 VSS VSS VSS VSS L
M VDD33_1 TXDA RXDA VSTBY VSS VSS VSS VSS M
N RXDB BOOTCFG1 WKPCFG VDD VDDE2 VSS VSS VSS N
1 2 3 4 5 6 7 8 9 10 11 12 13

Pin Assignments
14 15 16 17 18 19 20 21 22 23 24 25 26
REFBYP-
A AN32 AN36 VDDA_B0 VRL_B VRH_B ANB7 ANB11 ANB14 ANB17 ANB21 ANB23 VSS A
CB1
B AN29 AN33 VDDA_B1 VSSA_B0 REFBYPCB ANB6 ANB8 ANB10 ANB15 ANB18 ANB22 VSS TCRCLKC B
C AN30 AN34 AN37 AN38 ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 VSS ETPUC0 ETPUC1 C
D AN31 AN35 AN39 ANB1 ANB2 ANB3 ANB9 ANB13 ANB20 VSS VDDEH7 ETPUC2 ETPUC3 D
E VDDEH7 ETPUC4 ETPUC5 ETPUC6 E
F ETPUC7 ETPUC8 ETPUC9 ETPUC10 F

G (as viewed from top through the package) ETPUC11 ETPUC12 ETPUC13 ETPUC14 G
(2 of 4)
H ETPUC15 ETPUC16 ETPUC17 ETPUC18 H
J ETPUC19 ETPUC20 ETPUC21 ETPUC22 J
K VSS VSS VSS VSS ETPUC23 ETPUC24 ETPUC25 ETPUC26 K
L VSS VSS VSS VSS ETPUC27 ETPUC28 ETPUC29 ETPUC30 L
M VSS VSS VSS VSS ETPUC31 ETPUB15 ETPUB14 VDDEH7 M
N VSS VSS VSS VSS VDDEH6 ETPUB11 ETPUB12 ETPUB13 N
14 15 16 17 18 19 20 21 22 23 24 25 26

Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13
P TXDB PLLCFG1 PLLCFG2 VDDEH1 VDDE2 VDDE2 VSS VSS P
R JCOMP RESET PLLCFG0 RDY VDDE2 VDDE2 VSS VSS R
T VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VDDE2 VSS T
U EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VDDE2 VSS U
V MDO2 MDO3 MDO4 MDO5 V
W MDO6 MDO7 MDO8 VDDE2 W

Y MDO9 MDO10 MDO11 MDO15 (as viewed from top through the package) Y
(3 of 4)
AA MDO12 MDO13 MDO14 VDD33_2 AA
AB TDO TCK TMS VDD AB
AC VDDE2 TDI VDD VSS VDDE2 PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4 VDD EMIOS8 AC
AD ENGCLK VDD VSS FR_A_TX FR_B_TX PCSA5 SOUTA SCKA PCSB0 PCSB3 EMIOS2 EMIOS5 EMIOS9 AD
AE VDD VSS FR_A_RX FR_B_RX PCSA4 PCSA0 PCSA3 SCKB SINB EMIOS0 EMIOS3 EMIOS6 EMIOS10 AE
FR_A_ FR_B_
AF VSS VDDE2 TX_EN TX_EN VDDEH3 PCSB5 SINA PCSB2 SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 AF
1 2 3 4 5 6 7 8 9 10 11 12 13

Pin Assignments
14 15 16 17 18 19 20 21 22 23 24 25 26
P VSS VSS VSS VSS ETPUB7 ETPUB8 ETPUB9 ETPUB10 P
R VSS VSS VSS VSS ETPUB3 ETPUB4 ETPUB5 ETPUB6 R
T VSS VSS VSS VSS TCRCLKB ETPUB0 ETPUB1 ETPUB2 T
U VSS VSS VSS VSS ETPUB19 ETPUB18 ETPUB17 ETPUB16 U
V ETPUB26 ETPUB22 ETPUB21 ETPUB20 V
W REGSEL ETPUB25 ETPUB24 ETPUB23 W

Y (as viewed from top through the package) ETPUB29 ETPUB28 ETPUB27 REGCTL Y
(4 of 4)
AA VDD33_3 ETPUB30 VDDREG VSSSYN AA
AB VDD ETPUB31 VSSFL EXTAL AB
AC EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1 VSS VDD VDDEH6 XTAL AC
AD EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNTXD SCKC RXDC PCSC3 VSS VDD VDDSYN AD
AE EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0 SINC PCSC2 PCSC5 VSS VDD AE
AF EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 VSS AF
14 15 16 17 18 19 20 21 22 23 24 25 26

Pin Assignments

Figure 11 shows the 516-ball TEPBGA pin assignments in one figure. The same information is shown split into four quadrants
in Figure 12 through Figure 15.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
REF– REF–
A VDD RSTOUT ANA0 ANA4 ANA9 ANA11 ANA15 VDDA_A0 VRL_A VRH_A AN28 AN29 AN36 VDDA_B0 VRL_B VRH_B ANB5 ANB9 ANB12 ANB18 ANB21 VSS A
BYPCA1 BYPCB1
REF– REF–
B VDDEH1 VSS VDD TEST ANA1 ANA5 ANA10 ANA14 VDDA_A1 VSSA_A1 AN24 AN27 AN30 AN32 VDDA_B1 VSSA_B0 ANB4 ANB8 ANB10 ANB13 ANB19 ANB22 VSS VSS B
BYPCA BYPCB
C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 ANA7 ANA13 ANA17 ANA19 ANA21 ANA22 AN25 AN31 AN34 AN39 AN37 ANB0 ANB7 ANB6 ANB11 ANB15 ANB20 VSS ETPUC0 ETPUC1 C
D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 ANA8 ANA12 ANA16 ANA18 ANA20 ANA23 AN26 AN33 AN35 AN38 ANB1 ANB2 ANB3 ANB14 ANB16 ANB17 VSS VDDEH7 ETPUC2 ETPUC3 D
E ETPUA23 ETPUA24 ETPUA25 ETPUA26 VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ANB23 VSS VSS VDDEH7 ETPUC4 ETPUC5 ETPUC6 E
F ETPUA19 ETPUA20 ETPUA21 ETPUA22 VSS VDDE8 VDDE8 VDDE8 VDDE8 VSS VSS VDDE10 VDDE10 VDDE10 VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10 F
G ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18 MPC5674F 516-ball TEPBGA ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15 G
H ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16 ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21 H
J ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12 ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27 J
K TXDB TXDA RXDA TCRCLKA ETPUA6 ETPUA10 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15 K
BOOT– BOOT–
L PLLCFG1 PLLCFG2 CFG1 CFG0 RXDB ETPUA0 VSS VSS VSS VSS VSS VSS VSS VSS VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10 L
M VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG VSS VSS VSS VSS VSS VSS VSS VSS D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7 M
N D_WE0 D_WE2 D_WE3 VDD RESET VDDE8 VDDE2 VSS VSS VSS VSS VSS VSS VSS VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4 N
P D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS VDDE10 ETPUB13 D_OE D_ALE D_DAT0 D_DAT1 P
D_RD_
R D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB9 ETPUB12 ETPUB14 ETPUB15 WR R
T VDDE2 D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11 T
U D_CS2 JCOMP RDY MCKO MSEO1 MSEO0 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6 U
V EVTI EVTO MDO0 MDO2 MDO3 ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0 V
W MDO4 MDO5 MDO6 VDDE2 MDO8 MDO1 ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18 W
Y MDO7 MDO9 MDO10 MDO11 MDO12 ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL Y
AA MDO13 MDO14 MDO15 VDD33_1 VDDE8 VSS PCSA5 SOUTB VDD33_4 VDDE9 VDD33_4 EMIOS23 EMIOS31 CNRXB VSS VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA
AB TDO TCK TMS VDD VSS VDDE9 VDDE9 SCKA SINB D_CS1 D_ADD21 D_ADD29 EMIOS1 EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9 VDDE9 VDDE9 VDDE9 VSS VDD ETPUB30 VSSFL EXTAL AB
AC VDDE2 TDI VDD VSS VDDE2 PCSA1 SOUTA SCKB PCSB3 VDDEH3 VDDEH4 VDD EMIOS0 EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1 VSS VDD VDDEH6 XTAL AC
FR_A_ FR_B_
AD ENGCLK VDD VSS PCSA0 PCSA3 PCSB2 D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD SCKC RXDC PCSC3 VSS VDD VDDSYN AD
TX TX
FR_A_ FR_B_
AE VDD VSS PCSA4 PCSB5 SINA PCSB1 D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0 SINC PCSC2 PCSC5 VSS VDD AE
RX RX
FR_A_ FR_B_ D_
AF VDDE2 VDDEH3 PCSA2 PCSB4 PCSB0 D_TA D_ADD24 D_ADD27 CLKOUT EMIOS4 EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 AF
TX_EN TX_EN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13
REF-
A VDD RSTOUT ANA0 ANA4 ANA9 ANA11 ANA15 VDDA_A0 VRL_A VRH_A AN28 A
BYPCA1
B VDDEH1 VSS VDD TEST ANA1 ANA5 ANA10 ANA14 VDDA_A1 VSSA_A1 REFBYPCA AN24 AN27 B
C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 ANA7 ANA13 ANA17 ANA19 ANA21 ANA22 AN25 C
D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 ANA8 ANA12 ANA16 ANA18 ANA20 ANA23 AN26 D
E ETPUA23 ETPUA24 ETPUA25 ETPUA26 VSS VDD VSS VSS VSS VSS VSS VSS VSS E
F ETPUA19 ETPUA20 ETPUA21 ETPUA22 VSS VDDE8 VDDE8 VDDE8 VDDE8 VSS F
G ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18 MPC5674F 516-ball TEPBGA G

(1 of 4)
H ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16 H
J ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12 J
K TXDB TXDA RXDA TCRCLKA ETPUA6 ETPUA10 VSS VSS VSS VSS K
L PLLCFG1 PLLCFG2 BOOTCFG1 BOOTCFG0 RXDB ETPUA0 VSS VSS VSS VSS L
M VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG VSS VSS VSS VSS M
N D_WE0 D_WE2 D_WE3 VDD RESET VDDE8 VDDE2 VSS VSS VSS N
1 2 3 4 5 6 7 8 9 10 11 12 13

Pin Assignments
14 15 16 17 18 19 20 21 22 23 24 25 26
A AN29 AN36 VDDA_B0 REF- VRL_B VRH_B ANB5 ANB9 ANB12 ANB18 ANB21 VSS A
BYPCB1
B AN30 AN32 VDDA_B1 VSSA_B0 REFBYPCB ANB4 ANB8 ANB10 ANB13 ANB19 ANB22 VSS VSS B
C AN31 AN34 AN39 AN37 ANB0 ANB7 ANB6 ANB11 ANB15 ANB20 VSS ETPUC0 ETPUC1 C
D AN33 AN35 AN38 ANB1 ANB2 ANB3 ANB14 ANB16 ANB17 VSS VDDEH7 ETPUC2 ETPUC3 D
E VSS VSS VSS VSS VSS VSS ANB23 VSS VSS VDDEH7 ETPUC4 ETPUC5 ETPUC6 E
F VSS VDDE10 VDDE10 VDDE10 VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10 F

G (as viewed from top through the package) ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15 G
(2 of 4)
H ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21 H
J ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27 J
K VSS VSS VSS VSS ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15 K
L VSS VSS VSS VSS VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10 L
M VSS VSS VSS VSS D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7 M
N VSS VSS VSS VSS VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4 N
14 15 16 17 18 19 20 21 22 23 24 25 26

Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13
P D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1 VDDE2 VDDE2 VSS VSS P
R D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16 VDDE2 VDDE2 VSS VSS R
T VDDE2 D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3 VDDE2 VDDE2 VDDE2 VSS T
U D_CS2 JCOMP RDY MCKO MSEO1 MSEO0 VDDE2 VDDE2 VDDE2 VSS U
V EVTI EVTO MDO0 MDO2 MDO3 V

W MDO4 MDO5 MDO6 VDDE2 MDO8 MDO1 (3 of 4) W
Y MDO7 MDO9 MDO10 MDO11 MDO12 Y
AA MDO13 MDO14 MDO15 VDD33_1 VDDE8 VSS PCSA5 SOUTB VDD33_4 VDDE9 AA
AB TDO TCK TMS VDD VSS VDDE9 VDDE9 SCKA SINB D_CS1 D_ADD21 D_ADD29 EMIOS1 AB
AC VDDE2 TDI VDD VSS VDDE2 PCSA1 SOUTA SCKB PCSB3 VDDEH3 VDDEH4 VDD EMIOS0 AC
AD ENGCLK VDD VSS FR_A_TX FR_B_TX PCSA0 PCSA3 PCSB2 D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 AD
AE VDD VSS FR_A_RX FR_B_RX PCSA4 PCSB5 SINA PCSB1 D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 AE
FR_A_ FR_B_
AF VDDE2 VDDEH3 PCSA2 PCSB4 PCSB0 D_TA D_ADD24 D_ADD27 D_CLKOUT EMIOS4 AF
TX_EN TX_EN
1 2 3 4 5 6 7 8 9 10 11 12 13

Pin Assignments
14 15 16 17 18 19 20 21 22 23 24 25 26
P VSS VSS VSS VSS VDDE10 ETPUB13 D_OE D_ALE D_DAT0 D_DAT1 P
R VSS VSS VSS VSS ETPUB9 ETPUB12 ETPUB14 ETPUB15 D_RD_WR R
T VSS VSS VSS VSS ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11 T
U VSS VSS VSS VSS ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6 U
V
MPC5674F 516-ball TEPBGA ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0 V
(4 of 4)
W ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18 W
Y ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL Y
AA VDD33_4 EMIOS23 EMIOS31 CNRXB VSS VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA
AB EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9 VDDE9 VDDE9 VDDE9 VSS VDD ETPUB30 VSSSFL EXTAL AB
AC EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1 VSS VDD VDDEH6 XTAL AC
AD EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD SCKC RXDC PCSC3 VSS VDD VDDSYN AD
AE EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0 SINC PCSC2 PCSC5 VSS VDD AE
AF EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 AF
14 15 16 17 18 19 20 21 22 23 24 25 26

Pin Assignments
3.4 Signal Properties and Muxing

See Appendix A, Signal Properties and Muxing, for a listing and description of the pin functions and properties.

Electrical Characteristics
4 Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5674F.
The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These
specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon these
specifications will be met. Finalized specifications will be published after complete characterization and device qualifications
have been completed.
4.1 Maximum Ratings

Table 3. Absolute Maximum Ratings1
Spec Characteristic Symbol Min Max Unit
1 1.2 V Core Supply Voltage VDD –0.3 2.0 2 V
2 SRAM Standby Voltage VSTBY –0.3 6.4 3,4 V
3 Clock Synthesizer Voltage VDDSYN –0.3 5.3 4,5 V
4 I/O Supply Voltage (I/O buffers and predrivers) VDD33 –0.3 5.3 4,5 V
5 Analog Supply Voltage (reference to VSSA6) VDDA7 –0.3 6.4 3,4 V
6 I/O Supply Voltage (fast I/O pads) VDDE –0.3 5.3 4,5 V
3,4
7 I/O Supply Voltage (medium I/O pads) VDDEH –0.3 6.4 V
8 Voltage Regulator Input Supply Voltage VDDREG –0.3 6.4 3,4 V
9 Analog Reference High Voltage (reference to VRL8) VRH9 –0.3 6.4 3,4 V
10 VSS to VSSA8 Differential Voltage VSS – VSSA –0.1 0.1 V
11 VREF Differential Voltage VRH – VRL –0.3 6.4 3,4 V
12 VRL to VSSA Differential Voltage VRL – VSSA –0.3 0.3 V
13 VDD33 to VDDSYN Differential Voltage VDD33 – VDDSYN –0.1 0.1 V
14 VSSSYN to VSS Differential Voltage VSSSYN – VSS –0.1 0.1 V
15 Maximum Digital Input Current 10 (per pin, applies to all IMAXD –3 11 3 11 mA

digital pins)
16 Maximum Analog Input Current 12 (per pin, applies to all IMAXA –37 3 7,11 mA
analog pins)
17 Maximum Operating Temperature Range 13 – Die Junction TJ –40.0 150.0 oC
Temperature
18 Storage Temperature Range Tstg oC

–55.0 150.0
19 Maximum Solder Temperature 14 Tsdr oC
Pb-free package — 260.0

SnPb package — 245.0
20 Moisture Sensitivity Level 15 MSL — 3 —

1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause permanent damage to the device.
2
2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
3
4
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
5
6
MPC5674F has two analog power supply pins on the pinout: VDDA_A and VDDA_B.
7
MPC5674F has two analog ground supply pins on the pinout: VSSA_A and VSSA_B.
8
MPC5674F has two analog low reference voltage pins on the pinout: VRL_A and VRL_B.
9
MPC5674F has two analog high reference voltage pins on the pinout: VRH_A and VRH_B.
10
Total injection current for all pins must not exceed 25 mA at maximum operating voltage.
11
Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated
time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under
this stress condition.
12 Total injection current for all analog input pins must not exceed 15 mA.
13 Lifetime operation at these specification limits is not guaranteed.
14 Solder profile per CDF-AEC-Q100.
15 Moisture sensitivity per JEDEC test method A112.
4.2 Thermal Characteristics

Table 4. Thermal Characteristics, 416-pin TEPBGA Package1
Characteristic Symbol Value Unit
Junction to Ambient 2,3 Natural Convection (Single layer board) RθJA 24 °C/W
2,4
Junction to Ambient Natural Convection (Four layer board 2s2p) RθJA 18 °C/W
Junction to Ambient (@200 ft./min., Single layer board) RθJMA 19 °C/W
Junction to Ambient (@200 ft./min., Four layer board 2s2p) RθJMA 14 °C/W
Junction to Board 5 RθJB 9 °C/W
6
Junction to Case RθJC 6 °C/W
7
Junction to Package Top Natural Convection ΨJT 2 °C/W
1
Thermal characteristics are targets based on simulation that are subject to change per device
characterization. This data is PRELIMINARY based on similar package used on other devices.
2 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
4 Per JEDEC JESD51-6 with the board horizontal.
5
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
6
Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
7
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.

Table 5. Thermal Characteristics, 516-pin TEPBGA Package1
Characteristic Symbol Value Unit

2,3
Junction to Ambient Natural Convection (Single layer board) RθJA 25 °C/W
Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p) RθJA 18 °C/W
Junction to Ambient (@200 ft./min., Single layer board) RθJMA 20 °C/W
Junction to Ambient (@200 ft./min., Four layer board 2s2p) RθJMA 15 °C/W
Junction to Board 5 RθJB 10 °C/W
Junction to Case 6 RθJC 6 °C/W
7
Junction to Package Top Natural Convection ΨJT 2 °C/W
1
2
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
3 Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
4
Per JEDEC JESD51-6 with the board horizontal.
5
6
temperature.
7
Table 6. Thermal Characteristics, 324-pin Package1
MPC5674F Thermal Characteristic Symbol Value Unit

2, 3,
Junction to ambient natural convection (one-layer board) RθJA 29 °C/W
Junction to ambient 1, 4, natural convection (four-layer board 2s2p) RθJA 19 °C/W
Junction to ambient (@200 ft./min., one-layer board) RθJMA 23 °C/W
Junction to ambient (@200 ft./min., four-layer board 2s2p) RθJMA 16 °C/W
5
Junction to board (four-layer board 2s2p) RθJB 10 °C/W
Junction to case 6 RθJC 7 °C/W
7,
Junction to package top natural convection ΨJT 2 °C/W
1
2
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
3 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
4
Per JEDEC JESD51-6 with the board horizontal.
5

6
temperature.
7
4.2.1 General Notes for Specifications at Maximum Junction Temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA * PD) Eqn. 1
where:
TA = ambient temperature for the package (oC)
RθJA = junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to
ambient thermal resistance:
RθJA = RθJC + RθCA Eqn. 2
where:
RθJA = junction to ambient thermal resistance (oC/W)
RθJC = junction to case thermal resistance (oC/W)
RθCA = case to ambient thermal resistance (oC/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:
TJ = TT + (ΨJT x PD) Eqn. 3
where:
TT = thermocouple temperature on top of the package (oC)
ΨJT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
• C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
• G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53-58, March 1998.
• B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
4.3 EMI (Electromagnetic Interference) Characteristics

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go
to www.nxp.com and perform a keyword search for “radiated emissions.” The following tables list the values of the device's
radiated emissions operating behaviors.
Table 7. EMC Radiated Emissions Operating Behaviors: 416 BGA
fOSC Frequency Level

Symbol Description Conditions Unit Notes
fSYS band (MHz) (max.)
1
VRE_TEM Radiated emissions, VDD = 1.2 V 40 MHz crystal 0.15–50 26 dBμV
electric field and VDDE = 3.3 V 264 MHz
50–150 30
magnetic field VDDEH = 5 V (fEBI_CAL = 66
TA = 25 °C MHz) 150–500 34
416 BGA
EBI off 500–1000 30
CLK on IEC and SAE level I2 — 1, 3
FM off
1
50–150 25
TA = 25 °C MHz) 150–500 25
416 BGA
EBI off 500–1000 21
CLK off IEC and SAE level K5 — 1,3
FM on4
1
Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM
Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband
TEM (GTEM) Cell Method.
2 I = 36 dBμV
3 Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.

4
“FM on” = FM depth of ±2%
5
K = 30 dBμV
Table 8. EMC Radiated Emissions Operating Behaviors: 516 BGA
fOSC Frequency Level

Symbol Description Conditions Unit Notes
fSYS band (MHz) (max.)
1
50–150 48
TA = 25 °C MHz) 150–500 48
516 BGA
EBI on 500–1000 47
CLK on IEC and SAE level G2 — 1, 3
FM off
1
50–150 44
TA = 25 °C MHz) 150–500 41
516 BGA
EBI on 500–1000 36
CLK on IEC and SAE level G2 — 1, 3
FM on4
1 Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM
Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband
TEM (GTEM) Cell Method.
2 G = 48 dBμV
3
Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
4
“FM on” = FM depth of ±2%
4.4 ESD Characteristics

Table 9. ESD Ratings1,2
Spec Characteristic Symbol Value Unit
1 ESD for Human Body Model (HBM) VHBM 2000 V

2 ESD for Charged Device Model (CDM) VCDM 750 (corners) V
500 (other)
1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the
device specification.
4.5 PMC/POR/LVI Electrical Specifications

Note: For ADC internal resource measurements, see Table 21 in Section 4.9.1, “ADC Internal Resource Measurements.”

Table 10. PMC Operating conditions
Name Parameter Condition Min Typ Max Unit Note
VDDREG 1
Supply voltage VDDREG LDO5V / SMPS5V mode 4.5 5 5.5 V
5V nominal
VDDREG 1
Supply voltage VDDREG LDO3V mode 3.0 3.3 3.6 V
3V nominal
2
VDD33 Supply voltage VDDSYN / LDO3V mode 3.0 3.3 3.6 V
VDD33 3.3V nominal
3
VDD Core supply voltage — 1.14 1.2 1.32 V
1
Voltage should be higher than maximum VLVDREG to avoid LVD event
2
Applies to both VDD33 (flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum VLVD33
to avoid LVD event
3 Voltage should be higher than maximum V
LVD12 to avoid LVD event
NOTE
In the following table, "untrimmed” means “at reset" and "trimmed” means “after reset".
Table 11. PMC Electrical Specifications
ID Name Parameter Min Typ Max Unit
1 VBG Nominal bandgap reference voltage 0.608 0.620 0.632 V
1a — Untrimmed bandgap reference voltage VBG – 5% VBG VBG + 5% V
2 VDD12OUT Nominal VRC regulated 1.2V output VDD — 1.27 — V
2a — Untrimmed VRC 1.2V output variation before band VDD12OUT – 14% VDD12OUT VDD12OUT + 10% V
gap trim (unloaded)
Note: Voltage should be higher than maximum
VLVD12 to avoid LVD event
2b — Trimmed VRC 1.2V output variation after band gap VDD12OUT – 10% VDD12OUT VDD12OUT + 5% V
trim (REGCTL load max. 20mA, VDD load max.
1A)1
2c VSTEPV12 Trimming step VDD12OUT — 10 — mV
3 VPORC POR rising VDD 1.2V — 0.7 — V
3a — POR VDD 1.2V variation VPORC – 30% VPORC VPORC + 30%
3b — POR 1.2V hysteresis — 75 — mV
4 VLVD12 Nominal rising LVD 1.2V — 1.100 — V

Note: ~VDD12OUT × 0.87
4a — Untrimmed LVD 1.2V variation before band gap trim VLVD12 – 6% VLVD12 VLVD12 + 6% V
Note: Rising VDD
4b — Trimmed LVD 1.2V variation after band gap trim VLVD12 – 3% VLVD12 VLVD12 + 3% V
Rising VDD

Table 11. PMC Electrical Specifications (continued)
4c — LVD 1.2V Hysteresis 15 20 25 mV
4d VLVDSTEP12 Trimming step LVD 1.2V — 10 — mV
5 IREGCTL VRC DC current output on REGCTL — — 20 mA
6 — Voltage regulator 1.2V current consumption — 3 — mA

VDDREG
7 VDD33OUT Nominal VREG 3.3V output — 3.3 — V
7a — Untrimmed VREG 3.3V output variation before band VDD33OUT – 6% VDD33OUT VDD33OUT + 10% V
gap trim (unloaded)
Note: Rising VDDSYN
7b — Trimmed VREG 3.3V output variation after band gap VDD33OUT – 5% VDD33OUT VDD33OUT + 10% V
trim (max. load 80mA)
7c VSTEPV33 Trimming step VDDSYN — 30 — mV
8 VLVD33 Nominal rising LVD 3.3V — 2.950 — V

Note: ~VDD33OUT × 0.872
8a — Untrimmed LVD 3.3V variation before band gap trim VLVD33 – 5% VLVD33 VLVD33 + 5% V
Note: Rising VDDSYN
8b — Trimmed LVD 3.3V variation after bad gap trim VLVD33 – 3% VLVD33 VLVD33 + 3% V
Note: Rising VDDSYN
8c — LVD 3.3V Hysteresis — 30 — mV
8d VLVDSTEP33 Trimming step LVD 3.3V — 30 — mV
9 IDD33 VREG = 4.5 V, max DC output current — — 80 mA

VREG = 4.25 V, max DC output current, crank — — 40 mA
condition
Note: Max current supplied by VDDSYN that does
not cause it to drop below VLVD33
10 — Voltage regulator 3.3V current consumption — 2 — mA

VDDREG
Note: Except IDD33
11 VPORREG POR rising on VDDREG — 2.00 — V
11a — POR VDDREG variation VPORREG – 30% VPORREG VPORREG + 30% V
11b — POR VDDREG hysteresis — 250 — mV
12 VLVDREG Nominal rising LVD VDDREG — 2.950 — V

(LDO3V / LDO5V mode)
12a — Untrimmed LVD VDDREG variation before band VLVDREG – 5% VLVDREG VLVDREG + 5% V
gap trim
Note: Rising VDDREG
12b — Trimmed LVD VDDREG variation after band gap VLVDREG – 3% VLVDREG VLVDREG + 3% V
trim
Note: Rising VDDREG

Table 11. PMC Electrical Specifications (continued)
12c — LVD VDDREG Hysteresis — 30 — mV

12d VLVDSTEPREG Trimming step LVD VDDREG — 30 — mV

13 VLVDREG Nominal rising LVD VDDREG — 4.360 — V

(SMPS5V mode)
13a — Untrimmed LVD VDDREG variation before band VLVDREG – 5% VLVDREG VLVDREG + 5% V
gap trim
Note: Rising VDDREG
13b — Trimmed LVD VDDREG variation after band gap VLVDREG – 3% VLVDREG VLVDREG + 3% V
trim
Note: Rising VDDREG
13c — LVD VDDREG Hysteresis — 50 — mV

(SMPS5V mode)
13d VLVDSTEPREG Trimming step LVD VDDREG — 50 — mV

(SMPS5V mode)
14 VLVDA Nominal rising LVD VDDA — 4.60 — V
14a — Untrimmed LVD VDDA variation before band gap VLVDA – 5% VLVDA VLVDA + 5% V
trim
14b — Trimmed LVD VDDA variation after band gap trim VLVDA – 3% VLVDA VLVDA + 3% V
14c — LVD VDDA Hysteresis — 150 — mV
14d VLVDASTEP Trimming step LVD VDDA — 20 — mV
15 — SMPS regulator output resistance — 15 25 Ohm

Note: Pulup to VDDREG when high, pulldown to
VSSREG when low.
16 — SMPS regulator clock frequency (after reset) 1.0 1.5 2.4 MHz
17 — SMPS regulator overshoot at start-up2 — 1.32 1.4 V
18 — SMPS maximum output current — 1.0 — A
19 — Voltage variation on current step2 (20% to 80% of — — 0.1 V

maximum current with 4 usec constant time)
1
VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 uA. When using the
recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core
voltage is up to 1A.
2 Parameter cannot be tested; this value is based on simulation and characterization.

4.6 Power Up/Down Sequencing

There is no power sequencing required among power sources during power up and power down in order to operate within
specification as long as the following two rules are met:
• When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.
• When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the
internal 3.3V regulator.
The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up
each VDDE/VDDEH first and then power up VDD. For power down, drop VDD to 0 V first, and then drop all VDDE/VDDEH
supplies. There is no limit on the fall time for the power supplies.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,
the state of the I/O pins during power up/down varies according to Table 12 and Table 13.
Table 12. Power Sequence Pin States for MH and AE pads
VDD VDD33 VDDE MH Pad MH+LVDS Pads1 AE/up-down Pads
High High High Normal operation Normal operation Normal operation

— Low High Pin is tri-stated (output buffer, Outputs disabled Pull-ups enabled,
input buffer, and weak pulls pull-downs disabled
disabled)
Low High Low Output low, Outputs disabled Output low,
pin unpowered pin unpowered
Low High High Pin is tri-stated (output buffer, Outputs disabled Pull-ups enabled,
input buffer, and weak pulls pull-downs disabled
disabled)
1
MH+LVDS pads are output-only.
Table 13. Power Sequence Pin States for F and FS pads
VDD VDD33 VDDE F and FS pads
low low high Outputs Disabled

low high — Outputs Disabled
high low low Outputs Disabled
high low high Outputs Disabled
high high low Normal operation - except no drive current
and input buffer output is unknown.1
high high high Normal Operation
1
The pad pre-drive circuitry will function normally but since VDDE is unpowered
the outputs will not drive high even though the output pmos can be enabled.
4.6.1 Power-Up
If VDDE/VDDEH is powered up first, then a threshold detector tristates all drivers connected to VDDE/VDDEH. There is no limit
to how long after VDDE/VDDEH powers up before VDD must power up. If there are multiple VDDE/VDDEH supplies, they can
be powered up in any order. For each VDDE/VDDEH supply not powered up, the drivers in that VDDE/VDDEH segment exhibit
the characteristics described in the next paragraph.

If VDD is powered up first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that
pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current
injection specification. There is no limit to how long after VDD powers up before VDDE/VDDEH must power up.
The rise times on the power supplies are to be no faster than 25 V/millisecond.
4.6.2 Power-Down
If VDD is powered down first, then all drivers are tristated. There is no limit to how long after VDD powers down before
VDDE/VDDEH must power down.
If VDDE/VDDEH is powered down first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy
load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the
current injection specification. There is no limit to how long after VDDE/VDDEH powers down before VDD must power down.
There are no limits on the fall times for the power supplies.
4.6.3 Power Sequencing and POR Dependent on VDDA

During power up or down, VDDA can lag other supplies (of magnitude greater than VDDEH/2) within 1 V to prevent any
forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between VDDA and VDDEH
is more than 1 V, the following will result:
• Triggers POR (ADC monitors on VDDEH1 segment which powers the RESET pin) if the leakage current path created,
when VDDA is sufficiently low, causes sufficient voltage drop on VDDEH1 node monitored crosses low-voltage detect
level.
• If VDDA is between 0–2 V, powering all the other segments (especially VDDEH1) will not be sufficient to get the part
out of reset.
• Each VDDEH will have a leakage current to VDDA of a magnitude of ((VDDEH – VDDA – 1 V(diode drop)/200 KOhms)
up to (VDDEH/2 = VDDA + 1 V).
• Each VDD has the same behavior; however, the leakage will be small even though there is no current limiting resistor
since VDD = 1.32 V max.
4.7 DC Electrical Specifications

Table 14. DC Electrical Specifications
1 Core Supply Voltage (External Regulation) VDD 1.14 1.321,2 V

3
1a Core Supply Voltage (Internal Regulation) VDD 1.08 1.32 V
2 I/O Supply Voltage (fast I/O pads) VDDE 3.0 3.61,4 V
3 I/O Supply Voltage (medium I/O pads) VDDEH 3.0 5.251,5 V
4 3.3 V I/O Buffer Voltage VDD33 3.0 3.61,4 V
5 Analog Supply Voltage VDDA 4.75 5.251,5 V
6a SRAM Standby Voltage VSTBY_LOW 0.956 1.2 V
Keep-out Range: 1.2V–2V
6b SRAM Standby Voltage VSTBY_HIGH 2 6 V
Keep-out Range: 1.2V–2V
7 Voltage Regulator Control Input Voltage7 VDDREG 2.78 5.51,5 V

Table 14. DC Electrical Specifications (continued)
8 Clock Synthesizer Operating Voltage9 VDDSYN 3.0 3.61,4 V

9 Fast I/O Input High Voltage VIH_F VDDE + 0.3 V
Hysteresis enabled 0.65 × VDDE
Hysteresis disabled 0.55 × VDDE
10 Fast I/O Input Low Voltage VIL_F VSS – 0.3 V
Hysteresis enabled 0.35 × VDDE
Hysteresis disabled 0.40 × VDDE
11 Medium I/O Input High Voltage VIH_S VDDEH + 0.3 V
Hysteresis enabled 0.65 × VDDEH
Hysteresis disabled 0.55 × VDDEH
12 Medium I/O Input Low Voltage VIL_S VSS – 0.3 V
Hysteresis enabled 0.35 × VDDEH
Hysteresis disabled 0.40 × VDDEH
13 Fast I/O Input Hysteresis VHYS_F 0.1 × VDDE — V
14 Medium I/O Input Hysteresis VHYS_S 0.1 × VDDEH — V
15 Analog Input Voltage VINDC VSSA – 0.1 VDDA + 0.1 V
16 Fast I/O Output High Voltage10 VOH_F 0.8 × VDDE — V
11
17 Medium I/O Output High Voltage VOH_S 0.8 × VDDEH — V
10
18 Fast I/O Output Low Voltage VOL_F — 0.2 × VDDE V
19 Medium I/O Output Low Voltage11 VOL_S — 0.2 × VDDEH V
12
20 Load Capacitance (Fast I/O) CL
DSC(PCR[8:9]) = 0b00 — 10 pF
DSC(PCR[8:9]) = 0b01 — 20 pF
DSC(PCR[8:9]) = 0b10 — 30 pF
DSC(PCR[8:9]) = 0b11 — 50 pF
21 Input Capacitance (Digital Pins) CIN — 7 pF
22 Input Capacitance (Analog Pins) CIN_A — 10 pF
24 Operating Current 1.2 V Supplies @ fsys = 264 MHz
VDD @1.32 V IDD — 850 mA
VSTBY13 @1.2 V and 85oC IDDSTBY — 0.10 mA
VSTBY @6.0 V and 85oC IDDSTBY6 — 0.15 mA

VDD3314 IDD33 — note14 mA
VDDSYN IDDSYN — 715 mA

VDDA IDDA — 5016 mA
Analog Reference Supply Current (Transient) IREF — 1.0 mA
VDDREG IREG — 22 mA

Table 14. DC Electrical Specifications (continued)
27 Operating Current VDDE/VDDEH17 Supplies

VDDE2 IDD2 — mA
VDDEH1 IDD1 — mA
VDDEH3 IDD3 — mA
VDDEH4 IDD4 — note17 mA
VDDEH5 IDD5 — mA
VDDEH6 IDD6 — mA
VDDEH7 IDD7 — mA
28 Fast I/O Weak Pull Up/Down Current18
3.0 V–3.6 V IACT_F 42 158 μA
29 Medium I/O Weak Pull Up/Down Current19 IACT_S
3.0 V–3.6 V 15 95 μA
4.5 V–5.5 V 35 200 μA
30 I/O Input Leakage Current20 IINACT_D –2.5 2.5 μA
31 DC Injection Current (per pin) IIC –1.0 1.0 mA
32 Analog Input Current, Channel Off21, AN[0:7], AN38, IINACT_A –250 250 nA
AN39
Analog Input Current, Channel Off, all other analog –150 150 nA
inputs AN[x]
33 VSS Differential Voltage VSS – VSSA –100 100 mV
34 Analog Reference Low Voltage VRL VSSA VSSA + 100 mV
35 VRL Differential Voltage VRL – VSSA –100 100 mV
36 Analog Reference High Voltage VRH VDDA – 100 VDDA mV
37 VREF Differential Voltage VRH – VRL 4.75 5.25 V
38 VSSSYN to VSS Differential Voltage VSSSYN – VSS –100 100 mV
39 Operating Temperature Range—Ambient (Packaged) TA (TL to TH) –40.0 125.0 οC
40 Slew rate on power supply pins — — 25 V/ms

22,
41 Weak Pull-Up/Down Resistance 200 K Option RPUPD200K 130 280 kΩ
42 Weak Pull-Up/Down Resistance22, 100 K Option RPUPD100K 65 140 kΩ
43 Weak Pull-Up/Down Resistance22, 5 K Option RPUPD5K 1.4 7.5 kΩ
23
44 Pull-Up/Down Resistance Matching Ratios RPUPDMTCH –2.5 +2.5 %
(100K/200K)
1 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
2
3
Assumed with DC load.
4 5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
5
6
VSTBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode.
7
Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with VDDREG = 4.5 V (min).
8
2.7 V minimum operating voltage allowed during vehicle crank for system with VDDREG = 3.0 V (min). Normal operating voltage
should be either VDDREG = 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected.
9
Required to be supplied when 3.3 V regulator is disabled. See Section 4.5, “PMC/POR/LVI Electrical Specifications.”

10
IOH_F = {16,32,47,77} mA and IOL_F = {24,48,71,115} mA for {00,01,10,11} drive mode with VDDE = 3.0 V. This spec is for
characterization only.
11
IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDE = 4.5 V;
IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDE = 3.0 V. These specs are for characterization only.
12
Applies to D_CLKOUT, external bus pins, and Nexus pins.
13
VSTBY current specified at 1.0 V at a junction temperature of 85 oC. VSTBY current is 700 µA maximum at a junction temperature
of 150 oC.
14
Power requirements for the VDD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on
the I/O segments. See Section 4.7.2, “I/O Pad VDD33 Current Specifications,” for information on both fast (F, FS) and medium
(MH) pads. Also refer to Table 16 for values to calculate power dissipation for specific operation.
15
This value is a target that is subject to change.
16
This value allows a 5 V reference to supply ADC + REF.
17
Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. See Section 4.7.1, “I/O Pad Current Specifications,” for information on I/O pad
power. Also refer to Table 15 for values to calculate power dissipation for specific operation. The total power consumption of
an I/O segment is the sum of the individual power consumptions for each pin on the segment.
18 Absolute value of current, measured at V and V .
IL IH
19 Absolute value of current, measured at V and V .
IL IH
20 Weak pull up/down inactive. Measured at V
DDE 3.6 V and VDDEH = 5.25 V. Applies to pad types F and MH.
=
21 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types AE and AE/up-down. See Appendix A,
Signal Properties and Muxing.
22 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics
23 Pull-up and pull-down resistances are both enabled and settings are equal.
4.7.1 I/O Pad Current Specifications

The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power
consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from
Table 15 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency,
and load parameters that fall outside the values given in Table 15.
The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”
Table 15. VDDE/VDDEH I/O Pad Average DC Current1
Frequency Load2 Voltage Drive/Slew

Spec Pad Type Symbol Current (mA)
(MHz) (pF) (V) Rate Select
1 Medium IDRV_MH 50 50 5.25 11 16.0

2 20 50 5.25 01 6.3
3 3.0 50 5.25 00 1.1
4 2.0 200 5.25 00 2.4
5 Fast IDRV_FC 66 10 3.6 00 7.4
6 66 20 3.6 01 10.5
7 66 30 3.6 10 12.3
8 66 50 3.6 11 35.2

Table 15. VDDE/VDDEH I/O Pad Average DC Current1 (continued)
Frequency Load2 Voltage Drive/Slew

(MHz) (pF) (V) Rate Select
9 Fast w/ Slew IDRV_FSR 66 50 3.6 11 12.7

Control
10 50 50 3.6 10 6.7
11 33.33 50 3.6 01 4.2
12 20 50 3.6 00 2.6
13 20 200 3.6 00 9.1
1
These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.
2
All loads are lumped.
4.7.2 I/O Pad VDD33 Current Specifications

The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption
is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be
calculated from Table 16 dependent on the voltage, frequency, and load on all F type pins. The VDD33 current draw on medium
pads can be calculated from Table 16 dependent on voltage and independent on the frequency and load on all MH type pins.
Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 16.
The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”
Table 16. VDD33 Pad Average DC Current1
Frequency Load2 VDD33 VDDE Drive/Slew

(MHz) (pF) (V) (V) Rate Select
1 Medium I33_MH — — 3.6 5.5 — 0.0007

2 Fast I33_FC 66 10 3.6 3.6 00 0.92
3 66 20 3.6 3.6 01 1.14
4 66 30 3.6 3.6 10 1.50
5 66 50 3.6 3.6 11 2.19
6 Fast w/ Slew I33_FSR 66 50 3.6 3.6 11 0.74
Control
7 50 50 3.6 3.6 10 0.52
8 33.33 50 3.6 3.6 00 0.19
9 20 50 3.6 3.6 00 0.19
10 20 200 3.6 3.6 00 0.19
1
These are average IDDE for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input
pins only for the medium pads.
2 All loads are lumped.

4.7.3 LVDS Pad Specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI
module.
Table 17. DSPI LVDS pad specification
Min. Typ. Max.

# Characteristic Symbol Condition Unit
Value Value Value
Data Rate
1 Data Frequency fLVDSCLK — — 50 — MHz
Driver Specs
2 Differential output voltage VOD SRC=0b00 or 0b11 150 — 400 mV

SRC=0b01 90 — 320
SRC=0b10 160 — 480
3 Common mode voltage (LVDS), VOS — 1.06 1.2 1.39 V
VOS
4 Rise/Fall time TR/TF — — 2 — ns
5 Propagation delay (Low to High) TPLH — — 4 — ns
6 Propagation delay (High to Low) TPHL — — 4 — ns
7 Delay (H/L), sync Mode tPDSYNC — — 4 — ns
8 Delay, Z to Normal (High/Low) TDZ — — 500 — ns
9 Diff Skew Itphla-tplhbI or TSKEW — — — 0.5 ns
Itplhb-tphlaI
Termination
10 Trans. Line (differential Zo) — — 95 100 105 ohms

11 Temperature — — –40 — 150 °C
4.8 Oscillator and FMPLL Electrical Characteristics

Table 18. FMPLL Electrical Specifications1
(VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
1 PLL Reference Frequency Range2 (Normal Mode) MHz

Crystal Reference (PLLCFG2 = 0b0) fref_crystal 8 20
Crystal Reference (PLLCFG2 = 0b1) fref_crystal 16 403
External Reference (PLLCFG2 = 0b0) fref_ext 8 20
External Reference (PLLCFG2 = 0b1) fref_ext 16 40
2 Loss of Reference Frequency4 fLOR 100 1000 kHz
3 Self Clocked Mode Frequency5 fSCM 4 16 MHz
4 PLL Lock Time6 tLPLL — < 400 μs

Table 18. FMPLL Electrical Specifications1 (continued)

5 Duty Cycle of Reference 7 tDC 40 60 %

6 Frequency un-LOCK Range fUL –4.0 4.0 % fsys
7 Frequency LOCK Range fLCK –2.0 2.0 % fsys
8, 9
8 D_CLKOUT Period Jitter Measured at fSYS Max CJitter –5 5 %fclkout
Cycle-to-cycle Jitter
9 Peak-to-Peak Frequency Modulation Range Limit 10,11 Cmod 0 4 %fsys
(fsys Max must not be exceeded)
10 FM Depth Tolerance12 Cmod_err –0.25 0.25 %fsys
11 VCO Frequency fVCO 192 600 MHz
13
12 Modulation Rate Limits fmod 0.400 1 MHz
13 Predivider output frequency range14 fprediv 4 10 MHz
1
All values given are initial design targets and subject to change.
2
Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default
PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.
3 Upper tolerance of less than 1% is allowed on 40MHz crystal.
4 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
5 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f
LOR. This
frequency is measured at D_CLKOUT. A default RFD value of (0x05) is used in SCM mode, and the programmed MFD and
RFD values have no effect
6 This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
7 For Flexray operation, duty cycle requirements are higher.
8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f .
sys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval. D_CLKOUT divider set to divide-by-2.
9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
jitter + Cmod.
10 Modulation depth selected must not result in f value greater than the f maximum specified value.
pll pll
11 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in
control register are: 2%, 3%, and 4% peak-to-peak.

12 Depth tolerance is the programmed modulation depth ±0.25% of F . Violating the VCO min/max range may prevent the
sys
system from exiting reset.
13 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz
will result in reduced calibration accuracy.

14 Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.

Table 19. Oscillator Electrical Specifications1

1 Crystal Mode Differential Amplitude2 Vcrystal_diff_amp | Vextal – Vxtal | > 0.4 V — V

(Min differential voltage between EXTAL and XTAL)
2 Crystal Mode: Internal Differential Amplifier Noise Vcrystal_diff_amp_nr — | Vextal – Vxtal | < 0.2 V V
Rejection
3 EXTAL Input High Voltage VIHEXT ((VDD33/2) + 0.4 V) — V
Bypass mode, External Reference
4 EXTAL Input Low Voltage VILEXT — (VDD33/2) – 0.4 V V
Bypass mode, External Reference
5 XTAL Current3 IXTAL 1 3 mA
6 Total On-chip stray capacitance on XTAL CS_XTAL — 1.5 pF
7 Total On-chip stray capacitance on EXTAL CS_EXTAL — 1.5 pF
8 Crystal manufacturer’s recommended capacitive load CL See crystal spec See crystal spec pF
9 Discrete load capacitance to be connected to EXTAL CL_EXTAL — (2 × CL – CS_EXTAL pF
– CPCB_EXTAL4)
10 Discrete load capacitance to be connected to XTAL CL_XTAL — (2 × CL – CS_XTAL pF
– CPCB_XTAL4)
1
All values given are initial design targets and subject to change.
2
This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode.
In that case, Vextal – Vxtal ≥ 400 mV criterion has to be met for oscillator’s comparator to produce output clock.
3
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
4 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
4.9 eQADC Electrical Characteristics

Table 20. eQADC Conversion Specifications (Operating)
1 ADC Clock (ADCLK) Frequency fADCLK 2 16 MHz

2 Conversion Cycles CC ADCLK cycles
Single Ended Conversion Cycles 12 bit resolution 2 + 14 128 + 14
Single Ended Conversion Cycles 10 bit resolution
Single Ended Conversion Cycles 8 bit resolution 2 + 12 128 + 12
Note: Differential conversion (min) is one clock
cycle less than the single-ended 2 + 10 128 + 10
conversion values listed here.
3 Stop Mode Recovery Time1 TSR 10 — μs
2
4 Resolution — 1.25 — mV
3 –44 44 LSB5
5 INL: 8 MHz ADC Clock INL8
6 INL: 16 MHz ADC Clock3 INL16 –84 84 LSB
3
7 DNL: 8 MHz ADC Clock DNL8 –34 34 LSB
8 DNL: 16 MHz ADC Clock3 DNL16 –34 34 LSB

Table 20. eQADC Conversion Specifications (Operating) (continued)
9 Offset Error without Calibration OFFNC 04 1004 LSB

4 4
10 Offset Error with Calibration OFFWC –4 4 LSB
11 Full Scale Gain Error without Calibration GAINNC –1204 04 LSB
12 Full Scale Gain Error with Calibration GAINWC –44,6 44,6 LSB
13 Non-Disruptive Input Injection Current 7, 8, 9, 10 IINJ –3 3 mΑ
11, 12 4 4
14 Incremental Error due to injection current EINJ –4 4 Counts
13, 14 4,6 4,6
15 TUE value at 8 MHz (with calibration) TUE8 –4 4 Counts
16 TUE value at 16 MHz 13, 14 (with calibration) TUE16 –8 8 Counts
15
17 Maximum differential voltage
(DANx+ - DANx-) or (DANx- - DANx+)
PREGAIN set to 1X setting DIFFmax — (VRH – VRL)/2 V
PREGAIN set to 2X setting DIFFmax2 — (VRH – VRL)/4 V
PREGAIN set to 4X setting DIFFmax4 — (VRH - VRL)/8 V
18 Differential input Common mode voltage15 DIFFcmv (VRH – VRL)/2 (VRH – VRL)/2 V
(DANx- + DANx+)/2 – 5% + 5%
1 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that
the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms.
2 At V
RH – VRL = 5.12 V, one count = 1.25 mV without using pregain.
3 INL and DNL are tested from V
RL + 50 LSB to VRH – 50 LSB. The eQADC is guaranteed to be monotonic at 10 bit accuracy
(12 bit resolution selected).
4 New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully
included.
5 At V
RH – VRL = 5.12 V, one LSB = 1.25 mV.
6 The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.
7 Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than
VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions.
8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do
not affect device reliability or cause permanent damage.

9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values.
10 Condition applies to two adjacent pins at injection limits.
11 Performance expected with production silicon.
12 All channels have same 10 kΩ < Rs < 100 kΩ Channel under test has Rs = 10 kΩ, I =I
INJ INJMAX,IINJMIN.
13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.
14 TUE does not apply to differential conversions.
15 Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the
differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode
voltage of the differential signal violates the Differential Input common mode voltage specification.

4.9.1 ADC Internal Resource Measurements

Table 21. Power Management Control (PMC) Specification
Spec Characteristic Symbol Min Typical Max Unit
PMC Normal Mode

1 Bandgap 0.62 V VADC145 — 0.62 — V
ADC0 channel 145
2 Bandgap 1.2 V VADC146 — 1.22 — V
ADC0 channel 146
3 Vreg1p2 Feedback VADC147 — VDD / 2.045 — V
ADC0 channel 147
4 LVD 1.2 V VADC180 — VDD / 1.774 — V
ADC0 channel 180
5 Vreg3p3 Feedback VADC181 — Vreg3p3 / 5.460 — V
ADC0 channel 181
6 LVD 3.3 V VADC182 — Vreg3p3 / 4.758 — V
ADC0 channel 182
7 LVD 5.0 V VADC183 — — V
ADC0 channel 183
— LDO mode VDDREG / 4.758
— SMPS mode VDDREG/7.032
Table 22. Standby RAM Regulator Electrical Specifications
Spec Characteristic Symbol Min Typ Max Unit
Normal Mode
1 Standby Regulator Output VADC194 — 1.2 — V

ADC1 channel 194
2 Standby Source Bias VADC195 150 — 360 mV

150 mV to 360 mV (30mV Increment @
vref_sel)
ADC1 channel 195
Default Value 150 mV (@vref_sel = 1 1 1)
3 Standby Brownout Reference VADC195 500 — 850 mV

ADC1 channel 195

Table 23. ADC Band Gap Reference / LVI Electrical Specifications
1 4.75 LVD (from VDDA) VADC196 — 4.75 — V

ADC1 channel 196
2 ADC Bandgap VADC45 1.171 1.220 1.269 V
ADC0 channel 45
ADC1 channel 45
Table 24. Temperature Sensor Electrical Specifications
1 Slope VSADC1281 — 5.8 — mV/ °C

–40 °C to 100 °C ±1.0 °C
100 °C to 150 °C ±1.6 °C
ADC0 channel 128
ADC1 channel 128
2 Accuracy — — — °C
–40 °C to 150 °C ±10.0
ADC0 channel 128
ADC1 channel 128
1 Slope is the measured voltage change per °C.
4.10 C90 Flash Memory Electrical Characteristics

Table 25. Flash Program and Erase Specifications
Initial
Spec Characteristic Symbol Min Typ1 Max3 Unit
Max2
1 Double Word (64 bits) Program Time4 tdwprogram — 38 — 500 μs

4,5
2 Page Program Time tpprogram — 45 160 500 μs
3 16 KB Block Pre-program and Erase Time t16kpperase — 270 1000 5000 ms
1
Typical program and erase times assume nominal supply values and operation at 25 oC.
2
Initial factory condition: ≤ 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency.
3 The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.

4 Program times are actual hardware programming times and do not include software overhead.
5 Page size is 128 bits (4 words).

Table 26. Flash EEPROM Module Life
Spec Characteristic Symbol Min Typical1 Unit
1 Number of program/erase cycles per block for 16 KB and 64 P/E 100,000 — cycles
KB blocks over the operating temperature range (TJ)
2 Number of program/erase cycles per block for 128 KB and 256 P/E 1,000 100,000 cycles
KB blocks over the operating temperature range (TJ)
3 Minimum Data Retention at 85 °C ambient temperature2 Retention years
Blocks with 0–1,000 P/E cycles 20 —
Blocks with 1,001–10,000 P/E cycles 10 —
Blocks with 10,001–100,000 P/E cycles 5 —
1
Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional
information on the NXP definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for
Nonvolatile Memory.
2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
Table 27 shows the Platform Flash Configuration Register 1 (PFCPR1) settings versus frequency of operation. Refer to the
device reference manual for definitions of these bit fields.
Table 27. PFCPR1 Settings vs. Frequency of Operation1
Maximum Frequency2
(MHz)
Clock APC =
Spec WWSC DPFEN3 IPFEN3 PFLIM4 BFEN5
Mode RWSC
Core Platform
fsys fplatf
1 Enhanced 264 MHz6 132 MHz6 0b011 0b01 0b0 0b0 0b00 0b0
0b1 0b1 0b01 0b1
0b1x
2 Enhanced/ 200 MHz 100 MHz 0b010 0b01 0b0 0b0 0b00 0b0
Full 0b1 0b1 0b01 0b1
0b1x
3 Legacy 132 MHz 132 MHz 0b100 0b01 0b0 0b0 0b00 0b0
0b1 0b1 0b01 0b1
0b1x
Default setting after reset: 0b111 0b11 0b00 0b00 0b00 0b0
1 Illegal combinations exist. Use entries from the same row in this table.
2
This is the nominal maximum frequency of operation: platform runs at fsys/2 in Enhanced Mode .
3 For maximum flash performance, set to 0b1.
4 For maximum flash performance, set to 0b10.
5
For maximum flash performance, set to 0b1.
6
This is the nominal maximum frequency of operation in Enchanced Mode. Max speed is the maximum speed
allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system core clock(fsys) + 2% FM
and 132 Mhz platform clock (fplatf)+ 2% FM.

4.11 AC Specifications
4.11.1 Clocking
The Figure 16 shows the operating frequency domains of various blocks on MPC5674F.
PLLCFG[0:1]
CORE
fsys
SYSDIV ÷2
÷X fplatf PLATFORM /
EXTAL PLL BLOCKS /
IPG DIV SEL
fperiph FLASH
SIU_SYSDIV[SYSCLKDIV[0:1]]
X = 2, 4, 8, or 16
fetpu eTPU /
ETPU DIV SEL
SIU_SYSDIV[BYPASS] NDEDI
X=1
febi_cal
SIU_SYSDIV[IPCLKDIV[0:1]] DIV EBI
CAL BUS
SIU_ECCR[EBDF[0:1]]
Note: tcycsys = 1 / fsys
tcyc = 1 / fplatf
÷ 2 = divide-by-2 D_CLKOUT
÷ X = divide-by-X, depending on SIU_SYSDIV[BYPASS] (D_CLKOUT is not available
and SIU_SYSDIV[SYSCLKDIV]. on all packages and cannot
be programmed for faster
than fsys/2.)
Figure 16. MPC5674F Block Operating Frequency Domain Diagram
Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see
Table 29 and Table 30 for descriptions of bit settings).
Table 28. MPC5674F Operating Frequencies1, 2
SIU_ECCR fsys fplatf fetpu

Mode
[EBDF[0:1]]3 (platform and all blocks (eTPU, eTPU RAM, febi_cal4,5 Unit
(core)
except eTPU) and NDEDI)
Enhanced 01 264 132 132 66 MHz

11 264 132 132 33
Full 01 200 100 200 50 MHz
11 200 100 200 25
Legacy 01 132 132 132 66 MHz
11 132 132 132 33
1
The values in the table are specified at:
VDD = 1.02 V to 1.32 V
VDDE = 3.0 V to 3.6 V
VDDEH = 4.5 V to 5.5 V
VDD33 and VDDSYN = 3.0 V to 3.6 V
TA = TL to TH.

2
Up to the maximum frequency rating of the device (refer to Table 1). The fsys speed is the nominal maximum frequency.
270 Mhz parts allow for 264 Mhz system clock + 2% FM.
3
See the MPC5674F Reference Manual for full description as not all bit combinations are valid.
4
EBI/Calibration bus is not available in all packages.
5
The EBI/Calibration Bus operating frequency, febi_cal , depends on clock divider settings of block’s max allowed
frequency of operation. Normally febi_cal = fplatf /2, but can be limited to < fplatf /2 in Full Mode.
Table 29. IPCLKDIV Settings
SIU_SYSDIV
Mode Description
[IPCLKDIV[0:1]]
00 Enhanced CPU frequency is doubled (Max 264Mhz). Platform,

peripheral, and eTPU clocks are 1/2 of CPU frequency
01 Full CPU and eTPU frequency is doubled (Max 200Mhz).
Platform and peripheral clocks are 1/2 of CPU frequency.
10 — Reserved
11 Legacy CPU, eTPU, platform, and peripheral’s clocks all run at
same speed (Max 132Mhz).
Table 30. SYSCLKDIV Settings
SIU_SYSDIV
Description
[SYSCLKDIV[0:1]]
00 Divide by 2.
01 Divide by 4.
10 Divide by 8.
11 Divide by 16.

4.11.2 Pad AC Specifications

Table 31. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V)1
Out Delay2,4 Rise/Fall3,4 Load Drive

Spec Pad SRC/DSC
L → H/H → L (ns) (ns) (pF)
1 Medium5 00 152/165 70/74 50

2 205/220 96/96 200
3 01 28/34 12/15 50
4 52/59 28/31 200
5 11 12/12 5.3/5.9 50
6 32/32 22/22 200
7 Fast6 00 10
8 01 20
2.5 1.2
9 10 30
10 11 50
11 Fast with Slew Rate 00 40/40 16/16 50
12 50/50 21/21 200
13 01 13/13 5/5 50
14 19/19 8/8 200
15 10 8/8 2.4/2.4 50
16 12/12 5/5 200
17 11 5/5 1.1/1/1 50
18 8/8 2.6 2.6
19 Pull Up/Down (3.6 V max) — — 7500 50
20 Pull Up/Down (5.25 V max) — 6000 5000/5000 50
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH.
2
This parameter is supplied for reference and is not guaranteed by design and not tested.
3
This parameter is guaranteed by characterization before qualification rather than 100% tested.
4 Delay and rise/fall are measured to 20% or 80% of the respective signal.
5
Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock.
6

Table 32. Derated Pad AC Specifications (VDDEH = 3.3 V)1
Out Delay2,3 Rise/Fall4,3 Load Drive

Spec Pad SRC/DSC
L → H/H → L (ns) (ns) (pF)
1 Medium5 00 200/210 86/86 50

2 270/285 120/120 200
3 01 37/45 15.5/19 50
4 69/82 38/43 200
5 11 18/17 7.6/8.5 50
6 46/49 30/34 200
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH.
2
This parameter is supplied for reference and is not guaranteed by design and not tested.
3
Delay and rise/fall are measured to 20% or 80% of the respective signal.
4
This parameter is guaranteed by characterization before qualification rather than 100% tested.
5
VDDEn / 2
Pad VDDEHn / 2
Data Input
Rising Falling
Edge Edge
Output Output
Delay Delay
VOH
Pad VOL
Output
Figure 17. Pad Output Delay
4.12 AC Timing
4.12.1 Generic Timing Diagrams

The generic timing diagrams in Figure 18 and Figure 19 apply to all I/O pins with pad types F and MH. See Appendix A, Signal
Properties and Muxing, for the pad type for each pin.

D_CLKOUT VDDE / 2
A
B
I/O Outputs VDDEn / 2

VDDEHn / 2
A – Maximum Output Delay Time B – Minimum Output Hold Time

Figure 18. Generic Output Delay/Hold Timing
D_CLKOUT VDDE / 2
B
A
I/O Inputs VDDEn / 2

VDDEHn / 2
A – Minimum Input Setup Time B – Minimum Input Hold Time

Figure 19. Generic Input Setup/Hold Timing
4.12.2 Reset and Configuration Pin Timing

Table 33. Reset and Configuration Pin Timing1
1 RESET Pulse Width tRPW 10 — tcyc2

2 RESET Glitch Detect Pulse Width tGPW 2 — tcyc2
3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid tRCSU 10 — tcyc2
4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid tRCH 0 — tcyc2
1
Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA = TL to TH.

2
See Notes on tcyc on Figure 16 and Table 28 in Section 4.11.1, “Clocking.”
RESET 1
RSTOUT
PLLCFG
BOOTCFG
WKPCFG
Figure 20. Reset and Configuration Pin Timing
4.12.3 IEEE 1149.1 Interface Timing

Table 34. JTAG Pin AC Electrical Characteristics1
1 TCK Cycle Time tJCYC 100 — ns

2 TCK Clock Pulse Width (Measured at VDDE / 2) tJDC 40 60 ns
3 TCK Rise and Fall Times (40%–70%) tTCKRISE — 3 ns
4 TMS, TDI Data Setup Time tTMSS, tTDIS 5 — ns
5 TMS, TDI Data Hold Time tTMSH, tTDIH 25 — ns
6 TCK Low to TDO Data Valid tTDOV — 10 ns
7 TCK Low to TDO Data Invalid tTDOI 0 — ns
8 TCK Low to TDO High Impedance tTDOHZ — 20 ns
9 JCOMP Assertion Time tJCMPPW 100 — ns
10 JCOMP Setup Time to TCK Low tJCMPS 40 — ns
11 TCK Falling Edge to Output Valid tBSDV — 50 ns
12 TCK Falling Edge to Output Valid out of High Impedance tBSDVZ — 50 ns
13 TCK Falling Edge to Output High Impedance tBSDHZ — 50 ns
14 Boundary Scan Input Valid to TCK Rising Edge tBSDST 50 — ns
15 TCK Rising Edge to Boundary Scan Input Invalid tBSDHT 50 — ns

1
JTAG timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and
CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 35 for functional
specifications.
TCK
2 2
3
1 3
Figure 21. JTAG Test Clock Input Timing
TCK
TMS, TDI
7 8
TDO
Figure 22. JTAG Test Access Port Timing

TCK
10
JCOMP
Figure 23. JTAG JCOMP Timing
TCK
11 13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 24. JTAG Boundary Scan Timing

4.12.4 Nexus Timing

Table 35. Nexus Debug Port Timing1
1 MCKO Cycle Time tMCYC 22 8 tCYC3

2 MCKO Duty Cycle tMDC 40 60 %
3 MCKO Low to MDO Data Valid4 tMDOV –0.1 0.2 tMCYC
4 MCKO Low to MSEO Data Valid4 tMSEOV –0.1 0.2 tMCYC
4
5 MCKO Low to EVTO Data Valid tEVTOV –0.1 0.2 tMCYC
6 EVTI Pulse Width tEVTIPW 4.0 — tTCYC3
7 EVTO Pulse Width tEVTOPW 1 — tMCYC
8 TCK Cycle Time tTCYC 45 — tCYC3
9 TCK Duty Cycle tTDC 40 60 %
10 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8 — ns
11 TDI, TMS Data Hold Time TNTDIH, tNTMSH 5 — ns
12 TCK Low to TDO Data Valid tNTDOV 0 10 ns
13 RDY Valid to MCKO6 — — — —
1
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified
at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with
DSC = 0b10.
2 The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending
on the system frequency, not to exceed maximum Nexus AUX port frequency.
3
See Notes on tcyc in Table 28 in Section 4.11.1 Clocking.
4 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
5 Lower frequency is required to be fully compliant to standard.
6 The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.

MCKO
3
4
5
MDO
MSEO Output Data Valid
EVTO
6
EVTI
Figure 25. Nexus Timings

TCK
10
11
TMS, TDI
12
TDO
Figure 26. Nexus TCK, TDI, TMS, TDO Timing

4.12.5 External Bus Interface (EBI) Timing

Table 36. Bus Operation Timing 1
66 MHz (Ext. Bus Freq)2 3

Spec Characteristic Symbol Unit Notes
Min Max
1 D_CLKOUT Period tC 15.2 — ns Signals are measured at 50% VDDE.

2 D_CLKOUT Duty Cycle tCDC 45% 55% tC
3 D_CLKOUT Rise Time tCRT — —4 ns
4
4 D_CLKOUT Fall Time tCFT — — ns
5 D_CLKOUT Posedge to Output tCOH 1.0/1.5 — ns Hold time selectable via
Signal Invalid or High Z (Hold Time) SIU_ECCR[EBTS] bit:
EBTS = 0: 1.0 ns
D_ADD[9:30] EBTS = 1: 1.5 ns
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
6 D_CLKOUT Posedge to Output tCOV — 7.0/7.5 ns Output valid time selectable via
Signal Valid (Output Delay) SIU_ECCR[EBTS] bit:
EBTS = 0: 7.0 ns
D_ADD[9:30] EBTS = 1: 7.5 ns
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]

Table 36. Bus Operation Timing 1 (continued)
66 MHz (Ext. Bus Freq)2 3

Spec Characteristic Symbol Unit Notes
Min Max
7 Input Signal Valid to D_CLKOUT tCIS 5.0/4.5 — ns Input setup time selectable via
Posedge (Setup Time) SIU_ECCR[EBTS] bit:
EBTS = 0; 5.0ns
D_ADD[9:30] EBTS = 1; 4.5ns
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
8 D_CLKOUT Posedge to Input tCIH 1.0 — ns
Signal Invalid (Hold Time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
9 D_ALE Pulse Width tAPW 6.5 — ns The timing is for Asynchronous
external memory system.
10 D_ALE Negated to Address Invalid tAAI 2.0/1.0 5 — ns The timing is for Asynchronous
external memory system.
ALE is measured at 50% of VDDE.
1 EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and
CL = 30 pF with DSC = 0b10.
2 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
270 MHz parts allow for 264 MHz system clock + 2% FM.
3 Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency.
The maximum external bus frequency is 66 MHz.
4 Refer to Fast pad timing in Table 31 and Table 32.
5
ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0 °C. 2.0 ns spec applies to
temperatures > 0 °C. This spec has no dependency on SIU_ECCR[EBTS] bit.
VOH_F
VDDE / 2
VOL_F
D_CLKOUT
3 2
4
1
Figure 27. D_CLKOUT Timing

D_CLKOUT VDDE / 2
6
5
Output
VDDE / 2
Bus
6
5
Output VDDE / 2
Signal
Output
Signal VDDE / 2
Figure 28. Synchronous Output Timing

D_CLKOUT
VDDE / 2
Input
VDDE / 2
Bus
Input
Signal VDDE / 2
Figure 29. Synchronous Input Timing
ipg_clk
D_CLKOUT
D_ALE
D_TS
D_ADD/D_DAT ADDR DATA
10
Figure 30. ALE Signal Timing

4.12.6 External Interrupt Timing (IRQ Pin)

Table 37. External Interrupt Timing1
1 IRQ Pulse Width Low tIPWL 3 — tcyc2

2 IRQ Pulse Width High tIPWH 3 — tcyc2
3 IRQ Edge to Edge Time3 tICYC 6 — tcyc2
1
IRQ timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL
to TH.
2
See Notes on tcyc on Figure 16 and Table 28 in Section 4.11.1 Clocking.
3 Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
1 2
3
Figure 31. External Interrupt Timing
4.12.7 eTPU Timing

Table 38. eTPU Timing1
1 eTPU Input Channel Pulse Width tICPW 4 — tcyc2

2 eTPU Output Channel Pulse Width tOCPW 13 — tcyc2
1
eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH,
and CL = 200 pF with SRC = 0b00.
2
3 This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

eTPU Input
and TCRCLK
eTPU
Output
Figure 32. eTPU Timing
4.12.8 eMIOS Timing

Table 39. eMIOS Timing1
1 eMIOS Input Pulse Width tMIPW 4 — tcyc2

2 eMIOS Output Pulse Width tMOPW 13 — tcyc2
1 eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH,
and CL = 50 pF with SRC = 0b00.
2
3 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

eMIOS Input
eMIOS
Output
Figure 33. eMIOS Timing
4.12.9 DSPI Timing

Table 40. DSPI Timing1 2
Peripheral Bus Freq: 132 MHz

Spec Characteristic Symbol Unit
Min Max
1 DSPI Cycle Time3, 4 tSCK tSYS * 2 tSYS*32768*7 ns

Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
2 PCS to SCK Delay5 tCSC 12 — ns
3 After SCK Delay6 tASC ns
Master mode tSYS * 2 —
Slave mode tSYS *3 –
constraints 7
4 SCK Duty Cycle tSDC 0.33 * tSCK 0.66 * tSCK ns
5 Slave Access Time tA — 25 ns
(SS active to SOUT valid)
6 Slave SOUT Disable Time tDIS — 25 ns
(SS inactive to SOUT High-Z or invalid)
7 PCSx to PCSS time tPCSC tSYS * 2 tSYS * 7 ns
8 PCSS to PCSx time tPASC tSYS * 2 tSYS * 7 ns

Table 40. DSPI Timing1 2 (continued)
Peripheral Bus Freq: 132 MHz

Spec Characteristic Symbol Unit
Min Max
9 Data Setup Time for Inputs tSUI

Master (MTFE = 0) 20 — ns
Slave 4 — ns
Master (MTFE = 1, CPHA = 0)8 6 — ns
Master (MTFE = 1, CPHA = 1) 20 — ns
10 Data Hold Time for Inputs tHI
Master (MTFE = 0) –3 — ns
Slave 7 — ns
Master (MTFE = 1, CPHA = 0)8 12 — ns
Master (MTFE = 1, CPHA = 1) –3 — ns
11 Data Valid (after SCK edge) tSUO
Master (MTFE = 0) — 5 ns
Slave — 25 ns
Master (MTFE = 1, CPHA = 0) — 13 ns
Master (MTFE = 1, CPHA = 1) — 5 ns
12 Data Hold Time for Outputs tHO
Master (MTFE = 0) –5 — ns
Slave 2.5 — ns
Master (MTFE = 1, CPHA = 0) 3 — ns
Master (MTFE = 1, CPHA = 1) –5 — ns
1
DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA = TL to TH
2 Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed allowed including
frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (fsys) + 2% FM.
3
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two devices communicating over a DSPI link.
4
The actual minimum SCK cycle time is limited by pad performance.
5 The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
6
The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
7
For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS
8 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.
DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high
speed operation.
Table 41. DSPI LVDS Timing1, 2
Characteristic Symbol Min Max Unit
LVDS Clock to Data/Chip Select Outputs tLVDSDATA –0.25 × +0.25 × ns

tSCYC tSCYC
1 These are typical values that are estimated from simulation.
2
See DSPI LVDS Pad related data in Table 17.

2 3
PCSx
4 1
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
SIN First Data Data Last Data
12 11
SOUT First Data Data Last Data
Figure 34. DSPI Classic SPI Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
12 11
Figure 35. DSPI Classic SPI Timing — Master, CPHA = 1

3
2
SS
1
SCK Input 4
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
12 11 6
9
10
Figure 36. DSPI Classic SPI Timing — Slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5 6
12
9
10
Figure 37. DSPI Classic SPI Timing — Slave, CPHA = 1

3
PCSx
4 1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9 10
12 11
Figure 38. DSPI Modified Transfer Format Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
12 11
Figure 39. DSPI Modified Transfer Format Timing — Master, CPHA = 1

3
2
SS
SCK Input
(CPOL = 0)
4 4
SCK Input
(CPOL = 1)
11 12 6
5
9 10
Figure 40. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5 6
12
9
10
Figure 41. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
7 8
PCSS
PCSx
Figure 42. DSPI PCS Strobe (PCSS) Timing

Package Information
5 Package Information
The latest package outline drawings are available on the product summary pages on our website:
http://www.nxp.com/powerarchitecture. The following table lists the package case number. Use these numbers in the webpage’s
keyword search engine to find the latest package outline drawings.
Table 42. Package Information
Package Type Case Outline Number
324 TEPBGA 98ASS23840W
416 TEPBGA 98ARE10523D
516 TEPBGA 98ARS10503D

Package Information
5.1 324-Pin Package

The package drawings of the 324-pin TEPBGA package are shown in Figure 43 and Figure 44.
Figure 43. 324 TEPBGA Package (1 of 2)

Package Information

Package Information
5.2 416-Pin Package


Package Information

Package Information
5.3 516-Pin Package


Package Information

Product Documentation
6 Product Documentation
This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these
types are available at: http://www.nxp.com.
The following documents are required for a complete description of the device and are necessary to design properly with the
parts:
• MPC5674F Microprocessor Reference Manual (document number MPC5674FRM).

Signal Properties and Muxing
Appendix A Signal Properties and Muxing

The following table shows the signals properties for each pin on the MPC5674F. For each port pin that has an associated
SIU_PCRn register to control its pin properties, the supported functions column lists the functions associated with the
programming of the SIU_PCRn[PA] bit in the order: Primary function (P), Function 2 (F2), Function 3 (F3), and GPIO (G). See
Figure 49.
U
Table 2. Signal Properties Summary
P/
GPIO/ F/ Pad
PCR1 Signal Name2 G Function3 Function Summary I/O Type
Primary Functions
are listed First 113 TCRCLKA_IRQ7_GPIO113 P TCRCLKA eTPU A TCR clock I 5V M
Secondary Functions A1 IRQ7 External interrupt request I

are alternate functions
A2 — — —
GPIO Functions are G GPIO113 GPIO I/O

listed Last
Function not implemented on this device
Figure 49. Supported Functions Example

74
Table 43. Signal Properties and Muxing Summary

GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
2 4 State during State
Signal Name Function Function Summary
RESET7 after RESET8
324
416
516
eTPU_A
113 TCRCLKA_IRQ7_ P TCRCLKA eTPU A TCR clock I MH VDDEH1 —/Up —/Up K1 L1 K4

GPIO113
A1 IRQ7 External interrupt request I
A2 — — —
G GPIO113 GPIO I/O
114 ETPUA0_ETPUA12_ P ETPUA0 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K2 L2 L6

GPIO114
A1 ETPUA12 eTPU A channel (output only) O
A2 — — —
G GPIO114 GPIO I/O
115 ETPUA1_ETPUA13_ P ETPUA1 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J1 L3 J1

GPIO115
A2 — — —
G GPIO115 GPIO I/O
116 ETPUA2_ETPUA14_ P ETPUA2 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J2 L4 J2
GPIO116
A2 — — —
G GPIO116 GPIO I/O
117 ETPUA3_ETPUA15_ P ETPUA3 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J3 K1 H4

GPIO117
A2 — — —
G GPIO117 GPIO I/O
NXP Semiconductors
118 ETPUA4_ETPUA16_ P ETPUA4 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J4 K2 J4

GPIO118
A2 — — —
G GPIO118 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
Signal Name2 Function4 Function Summary
RESET7 after RESET8
324
416
516
119 ETPUA5_ETPUA17_ P ETPUA5 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H1 K3 H1
GPIO119
A2 — — —
G GPIO119 GPIO I/O
120 ETPUA6_ETPUA18_ P ETPUA6 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H2 K4 K5

GPIO120
A2 — — —
G GPIO120 GPIO I/O
121 ETPUA7_ETPUA19_ P ETPUA7 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — J1 H2
GPIO121
A2 — — —
G GPIO121 GPIO I/O
122 ETPUA8_ETPUA20_ P ETPUA8 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — J2 H3

GPIO122
A2 — — —
G GPIO122 GPIO I/O
123 ETPUA9_ETPUA21_ P ETPUA9 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H3 J3 J3

GPIO123
A2 — — —
G GPIO123 GPIO I/O
124 ETPUA10_ETPUA22_ P ETPUA10 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G1 J4 K6
GPIO124
A2 — — —
G GPIO124 GPIO I/O
75
76
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
125 ETPUA11_ETPUA23_ P ETPUA11 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G2 H1 G1
GPIO125
A2 — — —
G GPIO125 GPIO I/O
126 ETPUA12_PCSB1_ P ETPUA12 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G3 H2 J5

GPIO126
A1 PCSB1 DSPI B peripheral chip select O
A2 — — —
G GPIO126 GPIO I/O
127 ETPUA13_PCSB3_ P ETPUA13 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F1 H4 G2
GPIO127
A2 — — —
G GPIO127 GPIO I/O
128 ETPUA14_PCSB4_ P ETPUA14 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F2 H3 H5

GPIO128
A2 — — —
G GPIO128 GPIO I/O
129 ETPUA15_PCSB5_ P ETPUA15 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F3 G1 G3

GPIO129
A2 — — —
G GPIO129 GPIO I/O
130 ETPUA16_PCSD1_ P ETPUA16 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H4 G2 H6
GPIO130
A1 PCSD1 DSPI D peripheral chip select O
NXP Semiconductors
A2 — — —
G GPIO130 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
131 ETPUA17_PCSD2_ P ETPUA17 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G4 G3 G4
GPIO131
A2 — — —
G GPIO131 GPIO I/O
132 ETPUA18_PCSD3_ P ETPUA18 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — G4 G5

GPIO132
A2 — — —
G GPIO132 GPIO I/O
133 ETPUA19_PCSD4_ P ETPUA19 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — F1 F1
GPIO133
A2 — — —
G GPIO133 GPIO I/O
134 ETPUA20_IRQ8_ P ETPUA20 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E1 F2 F2

GPIO134
A2 — — —
G GPIO134 GPIO I/O
135 ETPUA21_IRQ9_ P ETPUA21 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG C1 F3 F3

GPIO135
A2 — — —
G GPIO135 GPIO I/O
136 ETPUA22_IRQ10_ P ETPUA22 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E2 F4 F4
GPIO136
A2 — — —
G GPIO136 GPIO I/O
77
78
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
137 ETPUA23_IRQ11_ P ETPUA23 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D1 E1 E1
GPIO137
A2 — — —
G GPIO137 GPIO I/O
138 ETPUA24_IRQ12_ P ETPUA24 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E3 E2 E2

GPIO138
A2 — — —
G GPIO138 GPIO I/O
139 ETPUA25_IRQ13_ P ETPUA25 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D2 E3 E3
GPIO139
A2 — — —
G GPIO139 GPIO I/O
140 ETPUA26_IRQ14_ P ETPUA26 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG C2 E4 E4

GPIO140
A2 — — —
G GPIO140 GPIO I/O
141 ETPUA27_IRQ15_ P ETPUA27 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F4 D1 D1

GPIO141
A2 — — —
G GPIO141 GPIO I/O
142 ETPUA28_PCSC1_ P ETPUA28 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — D2 D2
GPIO142
A1 PCSC1 DSPI C peripheral chip select O
NXP Semiconductors
A2 — — —
G GPIO142 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
143 ETPUA29_PCSC2_ P ETPUA29 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — D3 D3
GPIO143
A2 — — —
G GPIO143 GPIO I/O
144 ETPUA30_PCSC3_ P ETPUA30 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E4 C1 C1

GPIO144
A2 — — —
G GPIO144 GPIO I/O
145 ETPUA31_PCSC4_ P ETPUA31 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D3 C2 C2
GPIO145
A2 — — —
G GPIO145 GPIO I/O
eTPU_B
146 TCRCLKB_IRQ6_ P TCRCLKB eTPU B TCR clock I MH VDDEH6 —/Up —/Up P19 T23 V25
GPIO146
A2 — — —
G GPIO146 GPIO I/O
147 ETPUB0_ETPUB16_ P ETPUB0 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N19 T24 V26
GPIO147
A1 ETPUB16 eTPU B channel (output only) O
A2 — — —
G GPIO147 GPIO I/O
148 ETPUB1_ETPUB17_ P ETPUB1 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R19 T25 U22
GPIO148
A2 — — —
G GPIO148 GPIO I/O
79
80
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
149 ETPUB2_ETPUB18_ P ETPUB2 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R22 T26 U23
GPIO149
A2 — — —
G GPIO149 GPIO I/O
150 ETPUB3_ETPUB19_ P ETPUB3 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R21 R23 T22
GPIO150
A2 — — —
G GPIO150 GPIO I/O
151 ETPUB4_ETPUB20_ P ETPUB4 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P22 R24 U24
GPIO151
A2 — — —
G GPIO151 GPIO I/O
152 ETPUB5_ETPUB21_ P ETPUB5 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P21 R25 U25
GPIO152
A2 — — —
G GPIO152 GPIO I/O
153 ETPUB6_ETPUB22_ P ETPUB6 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N22 R26 U26
GPIO153
A2 — — —
G GPIO153 GPIO I/O
154 ETPUB7_ETPUB23_ P ETPUB7 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M19 P23 T23
GPIO154
NXP Semiconductors
A2 — — —
G GPIO154 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
155 ETPUB8_ETPUB24_ P ETPUB8 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N21 P24 T24
GPIO155
A2 — — —
G GPIO155 GPIO I/O
156 ETPUB9_ETPUB25_ P ETPUB9 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M22 P25 R22
GPIO156
A2 — — —
G GPIO156 GPIO I/O
157 ETPUB10_ETPUB26_ P ETPUB10 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M20 P26 T25
GPIO157
A2 — — —
G GPIO157 GPIO I/O
158 ETPUB11_ETPUB27_ P ETPUB11 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M21 N24 T26
GPIO158
A2 — — —
G GPIO158 GPIO I/O
159 ETPUB12_ETPUB28_ P ETPUB12 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG L19 N25 R23
GPIO159
A2 — — —
G GPIO159 GPIO I/O
160 ETPUB13_ETPUB29_ P ETPUB13 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG L20 N26 P22
GPIO160
A2 — — —
G GPIO160 GPIO I/O
81
82
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
161 ETPUB14_ETPUB30_ P ETPUB14 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG L21 M25 R24
GPIO161
A2 — — —
G GPIO161 GPIO I/O
162 ETPUB15_ETPUB31_ P ETPUB15 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — M24 R25
GPIO162
A2 — — —
G GPIO162 GPIO I/O
163 ETPUB16_PCSA1_ P ETPUB16 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P20 U26 V24
GPIO163
A1 PCSA1 DSPI A peripheral chip select O
A2 — — —
G GPIO163 GPIO I/O
164 ETPUB17_PCSA2_ P ETPUB17 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R20 U25 T21
GPIO164
A2 — — —
G GPIO164 GPIO I/O
165 ETPUB18_PCSA3_ P ETPUB18 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T20 U24 W26
GPIO165
A2 — — —
G GPIO165 GPIO I/O
166 ETPUB19_PCSA4_ P ETPUB19 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T19 U23 W25
GPIO166
NXP Semiconductors
A2 — — —
G GPIO166 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
167 ETPUB20_ P ETPUB20 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — V26 W24
GPIO167
A1 — — —
A2 — — —
G GPIO167 GPIO I/O
168 ETPUB21_ P ETPUB21 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — V25 V22
GPIO168
A1 — — —
A2 — — —
G GPIO168 GPIO I/O
169 ETPUB22_ P ETPUB22 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — V24 V23
GPIO169
A1 — — —
A2 — — —
G GPIO169 GPIO I/O
170 ETPUB23_ P ETPUB23 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — W26 U21
GPIO170
A1 — — —
A2 — — —
G GPIO170 GPIO I/O
171 ETPUB24_ P ETPUB24 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — W25 Y25
GPIO171
A1 — — —
A2 — — —
G GPIO171 GPIO I/O
172 ETPUB25_ P ETPUB25 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — W24 W21
GPIO172
A1 — — —
A2 — — —
G GPIO172 GPIO I/O
83
84
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
173 ETPUB26_ P ETPUB26 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — V23 Y23
GPIO173
A1 — — —
A2 — — —
G GPIO173 GPIO I/O
174 ETPUB27_ P ETPUB27 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — Y25 Y24
GPIO174
A1 — — —
A2 — — —
G GPIO174 GPIO I/O
175 ETPUB28_ P ETPUB28 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — Y24 AA24
GPIO175
A1 — — —
A2 — — —
G GPIO175 GPIO I/O
176 ETPUB29_ P ETPUB29 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — Y23 W22
GPIO176
A1 — — —
A2 — — —
G GPIO176 GPIO I/O
177 ETPUB30_ P ETPUB30 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U20 AA24 AB24
GPIO177
A1 — — —
A2 — — —
G GPIO177 GPIO I/O
178 ETPUB31_ P ETPUB31 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U19 AB24 Y22
GPIO178
A1 — — —
NXP Semiconductors
A2 — — —
G GPIO178 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
GPIO, IRQ, FlexRay
440 TCRCLKC_ P — — — MH VDDEH7 —/Up —/Up B22 B26 F22

GPIO4409
A1 — — —
A2 — — —
G GPIO440 GPIO I/O
441 ETPUC0_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG C21 C25 C25

GPIO4419
A1 — — —
A2 — — —
G GPIO441 GPIO I/O
442 ETPUC1_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG D20 C26 C26
GPIO4429
A1 — — —
A2 — — —
G GPIO442 GPIO I/O
443 ETPUC2_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG D22 D25 D25

GPIO4439
A1 — — —
A2 — — —
G GPIO443 GPIO I/O
444 ETPUC3_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG D21 D26 D26

GPIO4449
A1 — — —
A2 — — —
G GPIO444 GPIO I/O
445 ETPUC4_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG E22 E24 E24
GPIO4459
A1 — — —
A2 — — —
G GPIO445 GPIO I/O
85
86
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
446 ETPUC5_ P — — I/O MH VDDEH7 —/WKPCFG —/WKPCFG E19 E25 E25
GPIO4469
A1 — — —
A2 — — —
G GPIO446 GPIO I/O
447 ETPUC6_ P — — I/O MH VDDEH7 —/WKPCFG —/WKPCFG — E26 E26

GPIO4479
A1 — — —
A2 — — —
G GPIO447 GPIO I/O
448 ETPUC7_ P — — I/O MH VDDEH7 —/WKPCFG —/WKPCFG — F23 F23
GPIO4489
A1 — — —
A2 — — —
G GPIO448 GPIO I/O
449 ETPUC8_ P — — I/O MH VDDEH7 —/WKPCFG —/WKPCFG — F24 F24

GPIO4499
A1 — — —
A2 — — —
G GPIO449 GPIO I/O
450 ETPUC9_IRQ0_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG F22 F25 F25

GPIO4509
A2 — — —
G GPIO450 GPIO I/O
451 ETPUC10__IRQ1_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG E20 F26 F26
GPIO4519
NXP Semiconductors
A2 — — —
G GPIO451 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
452 ETPUC11_IRQ2_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG E21 G23 G22
GPIO4529
A2 — — —
G GPIO452 GPIO I/O
453 ETPUC12_IRQ3_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG F19 G24 G23

GPIO4539
A2 — — —
G GPIO453 GPIO I/O
454 ETPUC13_3_IRQ4_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG F21 G25 G24
GPIO4549
A2 — — —
G GPIO454 GPIO I/O
455 ETPUC14_4_IRQ5_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG F20 G26 G25

GPIO4559
A2 — — —
G GPIO455 GPIO I/O
456 ETPUC15__ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG — H23 G26

GPIO4569
A1 — — —
A2 — — —
G GPIO456 GPIO I/O
457 ETPUC16_FR_A_TX_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG — H24 H22
GPIO4579
A1 FR_A_TX FlexRay A transfer O
A2 — — —
G GPIO457 GPIO I/O
87
88
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
458 ETPUC17_FR_A_RX_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG G22 H25 H23
GPIO4589
A1 FR_A_RX FlexRay A receive I
A2 — — —
G GPIO458 GPIO I/O
459 ETPUC18_FR_A_TX_EN_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG G20 H26 H24

GPIO4599
A1 FR_A_TX_EN FlexRay A transfer enable O
A2 — — —
G GPIO459 GPIO I/O
460 ETPUC19_TXDA_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG G21 J23 H21
GPIO4609
A1 TXDA eSCI A transmit O
A2 — — —
G GPIO460 GPIO I/O
461 ETPUC20_RXDA _ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG G19 J24 H25

GPIO4619
A1 RXDA eSCI A receive I
A2 — — —
G GPIO461 GPIO I/O
462 ETPUC21_TXDB_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG H22 J25 H26

GPIO4629
A1 TXDB eSCI B transmit O
A2 — — —
G GPIO462 GPIO I/O
463 ETPUC22_RXDB_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG H21 J26 J22
GPIO4639
A1 RXDB eSCI B receive I
NXP Semiconductors
A2 — — —
G GPIO463 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
464 ETPUC23_PCSD5_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG H20 K23 J23
GPIO4649
A2 MAA0 ADC A Mux Address 0 O
A3 MAB0 ADC B Mux Address 0 O
G GPIO464 GPIO I/O
465 ETPUC24_PCSD4_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG J22 K24 J24

GPIO4659
G GPIO465 GPIO I/O
466 ETPUC25_PCSD3_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG K22 K25 K21

GPIO4669
G GPIO466 GPIO I/O
467 ETPUC26_PCSD2_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG J21 K26 J25

GPIO4679
A2 — — —
G GPIO467 GPIO I/O
468 ETPUC27_PCSD1_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG J19 L23 J26

GPIO4689
A2 — — —
G GPIO468 GPIO I/O
469 ETPUC28_PCSD0_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG J20 L24 K22
GPIO4699
A1 PCSD0 DSPI D peripheral chip select I/O
A2 — — —
G GPIO469 GPIO I/O
89
90
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
470 ETPUC29_SCKD_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG K21 L25 K23
GPIO4709
A1 SCKD DSPI D clock I/O
A2 — — —
G GPIO470 GPIO I/O
471 ETPUC30_SOUTD_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG K20 L26 K24

GPIO4719
A1 SOUTD DSPI D data output O
A2 — — —
G GPIO471 GPIO I/O
472 ETPUC31_SIND_ P — — — MH VDDEH7 —/WKPCFG —/WKPCFG K19 M23 K25
GPIO4729
A1 SIND DSPI D data input I
A2 — — —
G GPIO472 GPIO I/O
eMIOS
179 EMIOS0_ETPUA0_ P EMIOS0 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA9 AE10 AC13
GPIO179
A1 ETPUA0 eTPU A channel O
A2 — — —
G GPIO179 GPIO I/O
180 EMIOS1_ETPUA1_ P EMIOS1 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB9 AF10 AB13
GPIO180
A2 — — —
G GPIO180 GPIO I/O
181 EMIOS2_ETPUA2_ P EMIOS2 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y10 AD11 AD13
NXP Semiconductors
GPIO181
A2 — — —
G GPIO181 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
182 EMIOS3_ETPUA3_ P EMIOS3 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA10 AE11 AE13
GPIO182
A2 — — —
G GPIO182 GPIO I/O
183 EMIOS4_ETPUA4_ P EMIOS4 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB10 AF11 AF13
GPIO183
A2 — — —
G GPIO183 GPIO I/O
184 EMIOS5_ETPUA5_ P EMIOS5 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y11 AD12 AF14
GPIO184
A2 — — —
G GPIO184 GPIO I/O
185 EMIOS6_ETPUA6_ P EMIOS6 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG — AE12 AE14
GPIO185
A2 — — —
G GPIO185 GPIO I/O
186 EMIOS7_ETPUA7_ P EMIOS7 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB11 AF12 AD14
GPIO186
A2 — — —
G GPIO186 GPIO I/O
187 EMIOS8_ETPUA8_ P EMIOS8 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W10 AC13 AC14
GPIO187
A2 — — —
G GPIO187 GPIO I/O
91
92
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
188 EMIOS9_ETPUA9_ P EMIOS9 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W11 AD13 AF15
GPIO188
A2 — — —
G GPIO188 GPIO I/O
189 EMIOS10_SCKD_ P EMIOS10 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA11 AE13 AE15
GPIO189
A1 SCKD DSPI D clock O
A2 — — —
G GPIO189 GPIO I/O
190 EMIOS11_SIND_ P EMIOS11 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB12 AF13 AB14
GPIO190
A1 SIND DSPI D data input I
A2 — — —
G GPIO190 GPIO I/O
191 EMIOS12_SOUTC_ P EMIOS12 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG AB13 AF14 AD15
GPIO191
A1 SOUTC DSPI C data output O
A2 — — —
G GPIO191 GPIO I/O
192 EMIOS13_SOUTD_ P EMIOS13 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG AA12 AE14 AC15
GPIO192
A2 — — —
G GPIO192 GPIO I/O
193 EMIOS14_IRQ0_ P EMIOS14 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG Y12 AC14 AF17
GPIO193
NXP Semiconductors
A2 CNTXD FlexCAN D transmit O

G GPIO193 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
194 EMIOS15_IRQ1_ P EMIOS15 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG Y13 AD14 AE16
GPIO194
A2 CNRXD FlexCAN D receive I
G GPIO194 GPIO I/O
195 EMIOS16_ETPUB0_ P EMIOS16 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB14 AF15 AD16
GPIO195
A1 ETPUB0 eTPU B channel O
A2 FR_DBG[3] FlexRay debug O

G GPIO195 GPIO I/O
196 EMIOS17_ETPUB1_ P EMIOS17 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA13 AE15 AB15
GPIO196
G GPIO196 GPIO I/O
197 EMIOS18_ETPUB2_ P EMIOS18 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W12 AC15 AD17
GPIO197
G GPIO197 GPIO I/O
198 EMIOS19_ETPUB3_ P EMIOS19 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y14 AD15 AB16
GPIO198
G GPIO198 GPIO I/O
199 EMIOS20_ETPUB4_ P EMIOS20 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB15 AF16 AF16
GPIO199
A2 — — —
G GPIO199 GPIO I/O
93
94
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
200 EMIOS21_ETPUB5_ P EMIOS21 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA14 AE16 AE17
GPIO200
A2 — — —
G GPIO200 GPIO I/O
201 EMIOS22_ETPUB6_ P EMIOS22 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W13 AC16 AC16
GPIO201
A2 — — —
G GPIO201 GPIO I/O
202 EMIOS23_ETPUB7_ P EMIOS23 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y15 AD16 AA16
GPIO202
A2 — — —
G GPIO202 GPIO I/O
203 EMIOS24_PCSB0_ P EMIOS24 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB16 AF17 AC17
GPIO203
A1 PCSB0 DSPI B peripheral chip select I/O
A2 — — —
G GPIO203 GPIO I/O
204 EMIOS25_PCSB1_ P EMIOS25 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA15 AE17 AF18
GPIO204
A2 — — —
G GPIO204 GPIO I/O
432 EMIOS26_PCSB2_ P EMIOS26 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y16 AD17 AE18
GPIO432
NXP Semiconductors
A2 — — —
G GPIO432 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
433 EMIOS27_PCSB3_ P EMIOS27 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W14 AC17 AD18
GPIO433
A2 — — —
G GPIO433 GPIO I/O
434 EMIOS28_PCSC0_ P EMIOS28 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA16 AF18 AC18
GPIO434
A1 PCSC0 DSPI C peripheral chip select I/O
A2 — — —
G GPIO434 GPIO I/O
435 EMIOS29_PCSC1_ P EMIOS29 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA17 AE18 AB17
GPIO435
A2 — — —
G GPIO435 GPIO I/O
436 EMIOS30_PCSC2_ P EMIOS30 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y17 AD18 AF19
GPIO436
A2 — — —
G GPIO436 GPIO I/O
437 EMIOS31_PCSC5_ P EMIOS31 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W15 AC18 AA17
GPIO437
A2 — — —
G GPIO437 GPIO I/O
eQADC
— ANA0 P ANA010 eQADC A analog input I AE/up- VDDA_A1 ANA0 ANA0 A4 A4 A4

down
— ANA1 P ANA110 eQADC A analog input I AE/up- VDDA_A1 ANA1 ANA1 A5 B5 B5

down
— ANA2 P ANA210 eQADC A analog input I AE/up- VDDA_A1 ANA2 ANA2 B5 C5 C5

down
95
96
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
— ANA3 P ANA310 eQADC A analog input I AE/up- VDDA_A1 ANA3 ANA3 B6 D6 D6
down
— ANA4 P ANA410 eQADC A analog input I AE/up- VDDA_A1 ANA4 ANA4 A6 A5 A5

down
— ANA5 P ANA510 eQADC A analog input I AE/up- VDDA_A1 ANA5 ANA5 A7 B6 B6

down
— ANA6 P ANA610 eQADC A analog input I AE/up- VDDA_A1 ANA6 ANA6 B7 C6 C6

down
— ANA7 P ANA710 eQADC A analog input I AE/up- VDDA_A1 ANA7 ANA7 B8 D7 C7

down
— ANA8 P ANA8 eQADC A analog input I AE VDDA_A1 ANA8 ANA8 C5 A6 D7

— ANA9 P ANA9 eQADC A analog input I AE VDDA_A1 ANA9 ANA9 C7 C7 A6
— ANA10 P ANA10 eQADC A analog input I AE VDDA_A1 ANA10 ANA10 C6 B7 B7
— ANA11 P ANA11 eQADC A analog input I AE VDDA_A1 ANA11 ANA11 D6 A7 A7

— ANA12 P ANA12 eQADC A analog input I AE VDDA_A1 ANA12 ANA12 D7 D8 D8
— ANA13 P ANA13 eQADC A analog input I AE VDDA_A1 ANA13 ANA13 C8 C8 C8
— ANA14 P ANA14 eQADC A analog input I AE VDDA_A1 ANA14 ANA14 D8 B8 B8

— ANA15 P ANA15 eQADC A analog input I AE VDDA_A1 ANA15 ANA15 A8 A8 A8

NXP Semiconductors
— ANA22 P ANA22 eQADC A analog input I AE VDDA_A1 ANA22 ANA22 D12 D12 C12
— ANA23 P ANA23 eQADC A analog input I AE VDDA_A1 ANA23 ANA23 C12 C12 D12
— AN24 P AN24 eQADC A and B shared analog input I AE VDDA_A0 AN24 AN24 — B12 B12
— AN25 P AN25 eQADC A and B shared analog input I AE VDDA_A0 AN25 AN25 — D13 C13
— AN26 P AN26 eQADC A and B shared analog input I AE VDDA_A0 AN26 AN26 — C13 D13
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
— AN27 P AN27 eQADC A and B shared analog input I AE VDDA_A0 AN27 AN27 — B13 B13
— AN28 P AN28 eQADC A and B shared analog input I AE VDDA_A0 AN28 AN28 — A13 A13
— AN29 P AN29 eQADC A and B shared analog input I AE VDDA_A0 AN29 AN29 — B14 A14
— AN30 P AN30 eQADC A and B shared analog input I AE VDDA_B1 AN30 AN30 — C14 B14
— AN31 P AN31 eQADC A and B shared analog input I AE VDDA_B1 AN31 AN31 — D14 C14
— AN32 P AN32 eQADC A and B shared analog input I AE VDDA_B1 AN32 AN32 — A14 B15
— AN33 P AN33 eQADC A and B shared analog input I AE VDDA_B0 AN33 AN33 — B15 D14
— AN34 P AN34 eQADC A and B shared analog input I AE VDDA_B0 AN34 AN34 — C15 C15
— AN35 P AN35 eQADC A and B shared analog input I AE VDDA_B0 AN35 AN35 — D15 D15
— AN36 P AN36 eQADC A and B shared analog input I AE VDDA_B1 AN36 AN36 — A15 A15
— AN37 P AN37 eQADC A and B shared analog input I AE VDDA_B0 AN37 AN37 — C16 C17
— AN38 P AN38 eQADC A and B shared analog input I AE VDDA_B0 AN38 AN38 — C17 D16
— AN39 P AN39 eQADC A and B shared analog input I AE VDDA_B0 AN39 AN39 — D16 C16
— ANB0 P ANB0 eQADC B analog input I AE/up- VDDA_B0 ANB0 ANB0 B15 C18 C18
down
— ANB1 P ANB1 eQADC B analog input I AE/up- VDDA_B0 ANB1 ANB1 B16 D17 D17
down
— ANB2 P ANB2 eQADC B analog input I AE/up- VDDA_B0 ANB2 ANB2 A17 D18 D18
down
— ANB3 P ANB3 eQADC B analog input I AE/up- VDDA_B0 ANB3 ANB3 A18 D19 D19
down
— ANB4 P ANB4 eQADC B analog input I AE/up- VDDA_B0 ANB4 ANB4 B17 C19 B19
down
— ANB5 P ANB5 eQADC B analog input I AE/up- VDDA_B0 ANB5 ANB5 B18 C20 A20
down
— ANB6 P ANB6 eQADC B analog input I AE/up- VDDA_B0 ANB6 ANB6 A19 B19 C20
down
— ANB7 P ANB7 eQADC B analog input I AE/up- VDDA_B0 ANB7 ANB7 A20 A20 C19
down
— ANB8 P ANB8 eQADC B analog input I AE VDDA_B0 ANB8 ANB8 D13 B20 B20
97
98
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
— ANB9 P ANB9 eQADC B analog input I AE VDDA_B0 ANB9 ANB9 C14 D20 A21
— ANB10 P ANB10 eQADC B analog input I AE VDDA_B0 ANB10 ANB10 C13 B21 B21
— ANB11 P ANB11 eQADC B analog input I AE VDDA_B0 ANB11 ANB11 C15 A21 C21
— ANB12 P ANB12 eQADC B analog input I AE VDDA_B0 ANB12 ANB12 C16 C21 A22
— ANB13 P ANB13 eQADC B analog input I AE VDDA_B0 ANB13 ANB13 D14 D21 B22
— ANB14 P ANB14 eQADC B analog input I AE VDDA_B0 ANB14 ANB14 C17 A22 D20
— ANB15 P ANB15 eQADC B analog input I AE VDDA_B0 ANB15 ANB15 D15 B22 C22
— ANB16 P ANB16 eQADC B analog input I AE VDDA_B0 ANB16 ANB16 C18 C22 D21
— ANB17 P ANB17 eQADC B analog input I AE VDDA_B0 ANB17 ANB17 D16 A23 D22
— ANB18 P ANB18 eQADC B analog input I AE VDDA_B0 ANB18 ANB18 D17 B23 A23
— ANB19 P ANB19 eQADC B analog input I AE VDDA_B0 ANB19 ANB19 B19 C23 B23
— ANB20 P ANB20 eQADC B analog input I AE VDDA_B0 ANB20 ANB20 C19 D22 C23
— ANB21 P ANB21 eQADC B analog input I AE VDDA_B0 ANB21 ANB21 D18 A24 A24
— ANB22 P ANB22 eQADC B analog input I AE VDDA_B0 ANB22 ANB22 A21 B24 B24
— ANB23 P ANB23 eQADC B analog input I AE VDDA_B0 ANB23 ANB23 B20 A25 E20
— VRH_A P VRH_A ADC A Voltage reference high I VDDINT VRH_A VRH_A VRH_A A10 A12 A12
— VRL_A P VRL_A ADC A Voltage reference low I VSSINT VRL_A VRL_A VRL_A A11 A11 A11
— VRH_B P VRH_B ADC B Voltage reference high I VDDINT VRH_B VRH_B VRH_B A16 A19 A19
— VRL_B P VRL_B ADC B Voltage reference low I VSSINT VRL_B VRL_B VRL_B A15 A18 A18
— REFBYPCB P REFBYPCB ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB REFBYPCB B12 B18 B18
— REFBYPCA P REFBYPCA ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA REFBYPCA B11 B11 B11
— VDDA_A0 P VDDA_A Internal logic supply input I VDDE VDDA_A0 VDDA_A0 VDDA_A0 A9 A9 A9
NXP Semiconductors
— VDDA_A1 P VDDA_A Internal logic supply input I VDDE VDDA_A1 VDDA_A1 VDDA_A1 B9 B9 B9
— REFBYPCA1 P REFBYPCA1 ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA1 REFBYPCA1 A12 A10 A10
— VSSA_A1 P VSSA_A Ground I VSSE VSSA_A1 VSSA_A1 VSSA_A1 B10 B10 B10
— VDDA_B0 P VDDA_B Internal logic supply input I VDDE VDDA_B0 VDDA_B0 VDDA_B0 A13 A16 A16
— VDDA_B1 P VDDA_B Internal logic supply input I VDDE VDDA_B1 VDDA_B1 VDDA_B1 B13 B16 B16
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
— VSSA_B0 P VSSA_B Ground I VSSE VSSA_B0 VSSA_B0 VSSA_B0 B14 B17 B17
— REFBYPCB1 P REFBYPCB1 ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB1 REFBYPCB1 A14 A17 A17
FlexRay
248 FR_A_TX_ P FR_A_TX FlexRay A transfer O FS VDDE2 —/Up —/Up Y5 AD4 AD4
GPIO248 (–/– for Rev.1 of (–/– for Rev.1 of
A1 — — — the device) the device)
A2 — — —
G GPIO248 GPIO I/O
249 FR_A_RX_ P FR_A_RX FlexRay A receive I FS VDDE2 —/Up —/Up AA4 AE3 AE3
A2 — — —
G GPIO249 GPIO I/O
250 FR_A_TX_EN_ P FR_A_TX_EN FlexRay A transfer enable O FS VDDE2 —/Up —/Up AB3 AF3 AF3
A1 — — —
the device) the device)
A2 — — —
G GPIO250 GPIO I/O
251 FR_B_TX_ P FR_B_TX FlexRay B transfer O FS VDDE2 —/Up —/Up Y6 AD5 AD5
A1 — — —
A2 — — —
G GPIO251 GPIO I/O
252 FR_B_RX_ P FR_B_RX FlexRay B receive I FS VDDE2 —/Up —/Up AA5 AE4 AE4
A2 — — —
G GPIO252 GPIO I/O
99
100
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
253 FR_B_TX_EN_ P FR_B_TX_EN FlexRay B transfer enable O FS VDDE2 —/Up —/Up AB5 AF4 AF4
A1 — — —
A2 — — —
G GPIO253 GPIO I/O
FlexCAN
83 CNTXA_TXDA_ P CNTXA FlexCAN A transmit O MH VDDEH4 —/Up —/Up AB17 AF19 AE19
GPIO83
A1 TXDA eSCI A transmit O
A2 — — —
G GPIO83 GPIO I/O
84 CNRXA_RXDA_ P CNRXA FlexCAN A receive I MH VDDEH4 —/Up —/Up AA18 AE19 AD19
GPIO84
A1 RXDA eSCI A receive I
A2 — — —
G GPIO84 GPIO I/O
85 CNTXB_PCSC3_ P CNTXB FlexCAN B transmit O MH VDDEH4 —/Up —/Up Y18 AD19 AC19
GPIO85
A2 — — —
G GPIO85 GPIO I/O
86 CNRXB_PCSC4_ P CNRXB FlexCAN B receive I MH VDDEH4 —/Up —/Up W18 AC19 AA19
GPIO86
A2 — — —
G GPIO86 GPIO I/O
87 CNTXC_PCSD3_ P CNTXC FlexCAN C transmit O MH VDDEH4 —/Up —/Up W16 AF20 AF20
NXP Semiconductors
GPIO87
A2 — — —
G GPIO87 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
88 CNRXC_PCSD4_ P CNRXC FlexCAN C receive I MH VDDEH4 —/Up —/Up W17 AE20 AE20
GPIO88
A2 — — —
G GPIO88 GPIO I/O
246 CNTXD_ P CNTXD FlexCAN D transmit O MH VDDEH4 —/Up —/Up AB21 AD20 AD20
GPIO246
A1 — — —
A2 — — —
G GPIO246 GPIO I/O
247 CNRXD_ P CNRXD FlexCAN D receive I MH VDDEH4 —/Up —/Up Y19 AC20 AC20
GPIO247
A1 — — —
A2 — — —
G GPIO247 GPIO I/O
eSCI
89 TXDA_ P TXDA eSCI A transmit O MH VDDEH1 —/Up —/Up — M2 K2

GPIO89
A1 — — —
A2 — — —
G GPIO89 GPIO I/O
90 RXDA _ P RXDA eSCI A receive I MH VDDEH1 —/Up —/Up — M3 K3

GPIO90
A1 — — —
A2 — — —
G GPIO90 GPIO I
91 TXDB_PCSD1_ P TXDB eSCI B transmit O MH VDDEH1 —/Up —/Up — P1 K1
GPIO91
A2 — — —
G GPIO91 GPIO I/O
101
102
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
92 RXDB_PCSD5_ P RXDB eSCI B receive I MH VDDEH1 —/Up —/Up — N1 L5
GPIO92
A2 — — —
G GPIO92 GPIO I/O
244 TXDC_ETRIG0_ P TXDC eSCI C transmit O MH VDDEH4 —/Up —/Up — AF23 AF23
GPIO244
A1 ETRIG0 eQADC trigger input I
A2 — — —
G GPIO244 GPIO I/O
245 RXDC_ P RXDC eSCI C receive I MH VDDEH5 —/Up —/Up — AD22 AD22
GPIO245
A1 — — —
A2 — — —
G GPIO245 GPIO I/O
DSPI
93 SCKA_PCSC1_ P SCKA DSPI A clock I/O MH VDDEH3 —/Up —/Up Y7 AD8 AB8
GPIO93
A2 — — —
G GPIO93 GPIO I/O
94 SINA_PCSC2_ P SINA DSPI A data input I MH VDDEH3 —/Up —/Up AA7 AF7 AE7
GPIO94
A2 — — —
G GPIO94 GPIO I/O
95 SOUTA_PCSC5_ P SOUTA DSPI A data output O MH VDDEH3 —/Up —/Up AB7 AD7 AC7
NXP Semiconductors
GPIO95
A2 — — —
G GPIO95 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
96 PCSA0_PCSD2_ P PCSA0 DSPI A peripheral chip select I/O MH VDDEH3 —/Up —/Up AB6 AE6 AD6
GPIO96
A2 — — —
G GPIO96 GPIO I/O
97 PCSA1_ P PCSA1 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up — AC6 AC6
GPIO97
A1 — — —
A2 — — —
G GPIO97 GPIO I/O
98 PCSA2_ P PCSA2 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up — AC7 AF6
GPIO98
A1 — — —
A2 — — —
G GPIO98 GPIO I/O
99 PCSA3_ P PCSA3 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up — AE7 AD7
GPIO99
A1 — — —
A2 — — —
G GPIO99 GPIO I/O
100 PCSA4_ P PCSA4 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up — AE5 AE5
GPIO100
A1 — — —
A2 — — —
G GPIO100 GPIO I/O
101 PCSA5_ETRIG1_ P PCSA5 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AA6 AD6 AA8
GPIO101
A1 ETRIG1 eQADC trigger input I
A2 — — —
G GPIO101 GPIO I/O
103
104
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
102 SCKB_ P SCKB DSPI B clock I/O MH VDDEH3 —/Up —/Up Y8 AE8 AC8
GPIO102
A1 — — —
A2 — — —
G GPIO102 GPIO I/O
103 SINB_ P SINB DSPI B data input I MH VDDEH3 —/Up —/Up AA8 AE9 AB9
GPIO103
A1 — — —
A2 — — —
G GPIO103 GPIO I/O
104 SOUTB_ P SOUTB DSPI B data output O MH VDDEH3 —/Up —/Up AB8 AF9 AA10
GPIO104
A1 — — —
A2 — — —
G GPIO104 GPIO I/O
105 PCSB0_PCSD2_ P PCSB0 DSPI B peripheral chip select I/O MH VDDEH3 —/Up —/Up Y9 AD9 AF8
GPIO105
A2 — — —
G GPIO105 GPIO I/O
106 PCSB1_PCSD0_ P PCSB1 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up — AC9 AE8
GPIO106
A1 PCSD0 DSPI D peripheral chip select I/O
A2 — — —
G GPIO106 GPIO I/O
107 PCSB2_SOUTC_ P PCSB2 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up W7 AF8 AD8
GPIO107
A1 SOUTC DSPI C data output O
NXP Semiconductors
A2 — — —
G GPIO107 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
108 PCSB3_SINC_ P PCSB3 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up — AD10 AC9
GPIO108
A1 SINC DSPI C data input I
A2 — — —
G GPIO108 GPIO I/O
109 PCSB4_SCKC_ P PCSB4 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up — AC8 AF7
GPIO109
A1 SCKC DSPI C clock I/O
A2 — — —
G GPIO109 GPIO I/O
110 PCSB5_PCSC0_ P PCSB5 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up — AF6 AE6
GPIO110
A1 PCSC0 DSPI C peripheral chip select I/O
A2 — — —
G GPIO110 GPIO I/O
235 SCKC_SCK_C_LVDSP_ P SCKC DSPI C clock I/O MH+ VDDEH4 —/Up —/Up AA19 AD21 AD21
GPIO235 LVDS
A1 SCK_C_LVDSP LVDS+ downstream signal positive O
output clock
A2 — — —
G GPIO235 GPIO I/O
236 SINC_SCK_C_LVDSM_ P SINC DSPI C data input I MH+ VDDEH4 —/Up —/Up AA20 AE22 AE22
GPIO236 LVDS
A1 SCK_C_LVDSM LVDS– downstream signal negative O
output clock
A2 — — —
G GPIO236 GPIO I/O
237 SOUTC_SOUT_C_LVDSP_ P SOUTC DSPI C data output O MH+ VDDEH4 —/Up —/Up AB18 AF21 AF21
GPIO237 LVDS
A1 SOUT_C_LVDSP LVDS+ downstream signal positive O
output data
A2 — — —
G GPIO237 GPIO I/O
105
106
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
238 PCSC0_SOUT_C_LVDSM_ P PCSC0 DSPI C peripheral chip select I/O MH+ VDDEH4 —/Up —/Up AB19 AE21 AE21
GPIO238 LVDS
A1 SOUT_C_LVDSM LVDS– downstream signal negative O
output data
A2 — — —
G GPIO238 GPIO I/O
239 PCSC1_ P PCSC1 DSPI C peripheral chip select O MH VDDEH4 —/Up —/Up — AC22 AC22
GPIO239
A1 — — —
A2 — — —
G GPIO239 GPIO I/O
240 PCSC2_GPIO240 P PCSC2 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up — AE23 AE23
A1 — — —
A2 — — —
G GPIO240 GPIO I/O
241 PCSC3_GPIO241 P PCSC3 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up — AD23 AD23
A1 — — —
A2 — — —
G GPIO241 GPIO I/O
242 PCSC4_GPIO242 P PCSC4 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up — AF24 AF24
A1 — — —
A2 — — —
G GPIO242 GPIO I/O
243 PCSC5_GPIO243 P PCSC5 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up — AE24 AE24
A1 — — —
NXP Semiconductors
A2 — — —
G GPIO243 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
EBI
256 D_CS0_ P D_CS0 EBI chip select 0 O F VDDE9 —/Up —/Up — — AD9
GPIO256
A1 — — —
A2 — — —
G GPIO256 GPIO I/O
257 D_CS2_D_ADD_DAT31_ P D_CS2 EBI chip select 2 O F VDDE8 —/Up —/Up — — U1

GPIO257
A1 D_ADD_DAT31 EBI data only in non-mux mode. I/O
Address and data in mux mode.
A2 — — —
G GPIO257 GPIO I/O
258 D_CS3_D_TEA_ P D_CS3 EBI chip select 3 O F VDDE8 —/Up —/Up — — T6

GPIO258
A1 D_TEA EBI transfer error acknowledge I
A2 — — —
G GPIO258 GPIO I/O
259 D_ADD12_ P D_ADD12 EBI address bus I/O F VDDE8 —/Up —/Up — — R1
GPIO259
A1 — — —
A2 — — —
G GPIO259 GPIO I/O
GPIO260
A1 — — —
A2 — — —
G GPIO260 GPIO I/O
GPIO261
A1 — — —
A2 — — —
G GPIO261 GPIO I/O
107
108
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
GPIO262
A1 — — —
A2 — — —
G GPIO262 GPIO I/O
263 D_ADD16_D_ADD_DAT16_ P D_ADD16 EBI address bus I/O F VDDE8 —/Up —/Up — — R5
GPIO263

A2 — — —
G GPIO263 GPIO I/O
264 D_ADD17_D_ADD_DAT17_ P D_ADD17 EBI address bus I/O F VDDE8 —/Up —/Up — — T5
GPIO264
A2 — — —
G GPIO264 GPIO I/O
GPIO265
A2 — — —
G GPIO265 GPIO I/O
GPIO266
A2 — — —
G GPIO266 GPIO I/O
NXP Semiconductors
GPIO267
A2 — — —
G GPIO267 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
268 D_ADD21_D_ADD_DAT21_ P D_ADD21 EBI address bus I/O F VDDE9 —/Up —/Up — — AB11
GPIO268
A2 — — —
G GPIO268 GPIO I/O
269 D_ADD22_D_ADD_DAT22_ P D_ADD22 EBI address bus I/O F VDDE9 —/Up —/Up — — AD10
GPIO269
A2 — — —
G GPIO269 GPIO I/O
270 D_ADD23_D_ADD_DAT23_ P D_ADD23 EBI address bus I/O F VDDE9 —/Up —/Up — — AE10
GPIO270
A2 — — —
G GPIO270 GPIO I/O
271 D_ADD24_D_ADD_DAT24_ P D_ADD24 EBI address bus I/O F VDDE9 —/Up —/Up — — AF10
GPIO271
A2 — — —
G GPIO271 GPIO I/O
GPIO272
A2 — — —
G GPIO272 GPIO I/O
109
110
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
GPIO273
A2 — — —
G GPIO273 GPIO I/O
274 D_ADD27_D_ADD_DAT27_ P D_ADD27 EBI address bus I/O F VDDE9 —/Up —/Up — — AF11
GPIO274
A2 — — —
G GPIO274 GPIO I/O
GPIO275
A2 — — —
G GPIO275 GPIO I/O
276 D_ADD29_D_ADD_DAT29_ P D_ADD29 EBI address bus I/O F VDDE9 —/Up —/Up — — AB12
GPIO276
A2 — — —
G GPIO276 GPIO I/O
GPIO277
A2 — — —
NXP Semiconductors
G GPIO277 GPIO I/O

NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
278 D_ADD_DAT0_ P D_ADD_DAT0 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — — P25
GPIO278 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO278 GPIO I/O
279 D_ADD_DAT1_ P D_ADD_DAT1 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — — P26

A1 — — —
A2 — — —
G GPIO279 GPIO I/O
280 D_ADD_DAT2_ P D_ADD_DAT2 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — — N24
A1 — — —
A2 — — —
G GPIO280 GPIO I/O
A1 — — —
A2 — — —
G GPIO281 GPIO I/O
A1 — — —
A2 — — —
G GPIO282 GPIO I/O
111
112
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
283 D_ADD_DAT5_ P D_ADD_DAT5 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — — M25
A1 — — —
A2 — — —
G GPIO283 GPIO I/O

A1 — — —
A2 — — —
G GPIO284 GPIO I/O
A1 — — —
A2 — — —
G GPIO285 GPIO I/O
A1 — — —
A2 — — —
G GPIO286 GPIO I/O
A1 — — —
A2 — — —
NXP Semiconductors
G GPIO287 GPIO I/O

NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
288 D_ADD_DAT10_ P D_ADD_DAT10 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — — L26
A1 — — —
A2 — — —
G GPIO288 GPIO I/O

A1 — — —
A2 — — —
G GPIO289 GPIO I/O
A1 — — —
A2 — — —
G GPIO290 GPIO I/O
291 D_ADD_DAT13 P D_ADD_DAT13 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — — L23
_GPIO291 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO291 GPIO I/O
292 D_ADD_DAT14_GPIO292 P D_ADD_DAT14 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — — L22
A1 — — —
A2 — — —
G GPIO292 GPIO I/O
113
114
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
293 D_ADD_DAT15_GPIO293 P D_ADD_DAT15 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — — K26
A1 — — —
A2 — — —
G GPIO293 GPIO I/O
294 D_RD_WR_GPIO294 P D_RD_WR EBI read/write O F VDDE10 —/Up —/Up — — R26

A1 — — —
A2 — — —
G GPIO294 GPIO I/O
295 D_WE0_GPIO295 P D_WE0 EBI write enable O F VDDE8 —/Up —/Up — — N1

A1 — — —
A2 — — —
G GPIO295 GPIO I/O
296 D_WE1_GPIO296 P D_WE1 EBI write enable O F VDDE8 —/Up —/Up — — P5

A1 — — —
A2 — — —
G GPIO296 GPIO I/O
297 D_OE_GPIO297 P D_OE EBI output enable O F VDDE10 —/Up —/Up — — P23
A1 — — —
A2 — — —
G GPIO297 GPIO I/O
298 D_TS_GPIO298 P D_TS EBI transfer start O F VDDE9 —/Up —/Up — — AE9
A1 — — —
NXP Semiconductors
A2 — — —
G GPIO298 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
299 D_ALE_GPIO299 P D_ALE EBI Address Latch Enable O F VDDE10 —/Up —/Up — — P24
A1 — — —
A2 — — —
G GPIO299 GPIO I/O
300 D_TA_GPIO300 P D_TA EBI transfer acknowledge I/O F VDDE9 —/Up —/Up — — AF9
A1 — — —
A2 — — —
G GPIO300 GPIO I/O
301 D_CS1_GPIO301 P D_CS1 EBI chip select O F VDDE9 —/Up —/Up — — AB10
A1 — — —
A2 — — —
G GPIO301 GPIO I/O
302 D_BDIP_GPIO302 P D_BDIP EBI burst data in progress O F VDDE8 —/Up —/Up — — M2
A1 — — —
A2 — — —
G GPIO302 GPIO I/O

A1 — — —
A2 — — —
G GPIO303 GPIO I/O
A1 — — —
A2 — — —
G GPIO304 GPIO I/O
115
116
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
305 D_ADD9_GPIO305 P D_ADD9 EBI address bus I/O F VDDE8 —/Up —/Up — — P1
A1 — — —
A2 — — —
G GPIO305 GPIO I/O
A1 — — —
A2 — — —
G GPIO306 GPIO I/O
A1 — — —
A2 — — —
G GPIO307 GPIO I/O
Reset and Clocks
— RESET P RESET External reset input I MH VDDEH1 RESET/Up RESET/Up M2 R2 N5
230 RSTOUT P RSTOUT External reset output O MH VDDEH1 RSTOUT/Low RSTOUT/ A3 A3 A3

High
211 BOOTCFG0_IRQ2_ P BOOTCFG0 Boot configuration I MH VDDEH1 BOOTCFG/ BOOTCFG/ — — L4

GPIO211 Down Down
A1 IRQ2 I
A2 — — —
G GPIO211 GPIO I/O
212 BOOTCFG1_IRQ3_ P BOOTCFG1 Boot configuration I MH VDDEH1 BOOTCFG/ Input/Down L1 N2 L3

GPIO212 Down
NXP Semiconductors
A2 — — —
G GPIO212 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
213 WKPCFG_NMI_ P WKPCFG Weak pull configuration input I MH VDDEH1 WKPCFG/Up Input/Up — N3 M5
GPIO213
A1 NMI Critical interrupt to core11 I
A2 — — —
G GPIO213 GPIO I
208 PLLCFG0_IRQ4_ P PLLCFG0 FMPLL mode configuration input I MH VDDEH1 PLLCFG/Up Input/Up M3 R3 M3
GPIO208
A2 — — —
G GPIO208 GPIO I/O
209 PLLCFG1_IRQ5_ P PLLCFG1 FMPLL mode configuration input I MH VDDEH1 PLLCFG/Up Input/Up L2 P2 L1
GPIO209 (for Rev2 of the
device: —/Up)
G GPIO209 GPIO I/O
— PLLCFG2 P PLLCFG2 FMPLL mode configuration input I MH VDDEH1 PLLCFG/ PLLCFG/ L3 P3 L2

Down Down
— XTAL P XTAL Crystal oscillator output O AE VDD33 XTAL XTAL W22 AC26 AC26
— EXTAL P EXTAL Crystal oscillator input I AE VDD33 EXTAL EXTAL V22 AB26 AB26
229 D_CLKOUT P D_CLKOUT EBI system clock output O F VDDE9 CLKOUT/ CLKOUT/ — — AF12
Enabled Enabled
214 ENGCLK P ENGCLK EBI engineering clock output O F VDDE2 ENGCLK/ ENGCLK/ AA1 AD1 AD1
Note: EXTCLK (External clock input) Enabled Enabled
selected through SIU register)
JTAG and Nexus

(see footnote12 about resets)
— EVTI –13 EVTI Nexus event in I F VDDE2 —/Up EVTI/Up N4 T4 V1
227 EVTO –13 EVTO Nexus event out O F VDDE2 ABS/Up EVTO/HI P1 U1 V2
(the BAM uses this pin to
select if auto baud rate is on or
off)
219 MCKO –13 MCKO Nexus message clock out O F VDDE2 O/Low Disabled14 N2 T2 U4
117
118
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
220 MDO0_GPIO220 –13 MDO015 Nexus message data out O F VDDE2 O/Low MDO0/Low P3 U3 V3
(GPIO function on this pin is
A1 — — —
only available on Rev.2 of the
device) A2 — — —
G GPIO220 GPIO I/O
221 MDO1_GPIO221 –13 MDO115 Nexus message data out O F VDDE2 O/Low —/Down P4 U4 W6
A1 — — —

G GPIO221 GPIO I/O
222 MDO2_GPIO222 – 13
MDO215 Nexus message data out O F VDDE2 O/Low —/Down R1 V1 V4
A1 — — —
G GPIO222 GPIO I/O
223 MDO3_GPIO223 – 13
MDO315 Nexus message data out O F VDDE2 O/Low —/Down R2 V2 V5
A1 — — —
G GPIO223 GPIO I/O
75 MDO4_GPIO75 –13 MDO415 Nexus message data out O F VDDE2 O/Low —/Down R3 V3 W1
A1 — — —
G GPIO75 GPIO I/O
76 MDO5_GPIO76 –13 MDO515 Nexus message data out O F VDDE2 O/Low —/Down R4 V4 W2
A1 — — —
NXP Semiconductors
G GPIO76 GPIO I/O
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
77 MDO6_GPIO77 –13 MDO615 Nexus message data out O F VDDE2 O/Low —/Down T1 W1 W3
A1 — — —
G GPIO77 GPIO I/O
78 MDO7_GPIO78 –13 MDO715 Nexus message data out O F VDDE2 O/Low —/Down T2 W2 Y1
A1 — — —

G GPIO78 GPIO I/O
79 MDO8_GPIO79 –13
MDO815 Nexus message data out O F VDDE2 O/Low —/Down T3 W3 W5
A1 — — —
G GPIO79 GPIO I/O
80 MDO9_GPIO80 –13
MDO915 Nexus message data out O F VDDE2 O/Low —/Down U1 Y1 Y2
A1 — — —
G GPIO80 GPIO I/O
81 MDO10_GPIO81 –13 MDO1015 Nexus message data out O F VDDE2 O/Low —/Down U2 Y2 Y3
A1 — — —
G GPIO81 GPIO I/O
82 MDO11_GPIO82 –13 MDO1115 Nexus message data out O F VDDE2 O/Low —/Down U3 Y3 Y4
A1 — — —
G GPIO82 GPIO I/O
119
120
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
231 MDO12_GPIO231 –13 MDO1215 Nexus message data out O F VDDE2 O/Low —/Down V1 AA1 Y5
A1 — — —
A2 — — —
G GPIO231 GPIO I/O
232 MDO13_GPIO232 –13 MDO1315 Nexus message data out O F VDDE2 O/Low —/Down W2 AA2 AA1
A1 — — —
A2 — — —
G GPIO232 GPIO I/O
233 MDO14_GPIO233 – 13
MDO1415 Nexus message data out O F VDDE2 O/Low —/Down V3 AA3 AA2
A1 — — —
A2 — — —
G GPIO233 GPIO I/O
234 MDO15_GPIO234 – 13
MDO1515 Nexus message data out O F VDDE2 O/Low —/Down U4 Y4 AA3
A1 — — —
A2 — — —
G GPIO234 GPIO I/O
224 MSEO0 –13 MSEO015 Nexus message start/end out O F VDDE2 O/Low MSEO/HI P2 U2 U6
225 MSEO1 – 13
MSEO115 Nexus message start/end out O F VDDE2 O/Low MSEO/HI N3 T3 U5
13
226 RDY – RDY Nexus ready output O F VDDE2 O/Low RDY/HI M4 R4 U3
13
— TCK – TCK JTAG test clock input I F VDDE2 TCK/Down TCK/Down Y1 AB2 AB2
— TDI –13 TDI JTAG test data input I F VDDE2 TDI/Up TDI/Up Y2 AC2 AC2
13
228 TDO – TDO JTAG test data output O F VDDE2 TDO/Up TDO/Up W1 AB1 AB1
NXP Semiconductors
13
— TMS – TMS JTAG test mode select input I F VDDE2 TMS/Up TMS/Up W3 AB3 AB3
— JCOMP –13 JCOMP JTAG TAP controller enable I F VDDE2 JCOMP/Down JCOMP/Down M1 R1 U2
— TEST — TEST Test mode select (not for customer I F VDDEH1 TEST/Down TEST/Down B4 B4 B4
use)
— VDDSYN — VDDSYN Clock synthesizer power input I VDDE VDDSYN VDDSYN VDDSYN Y22 AD26 AD26
NXP Semiconductors
GPIO/PCR1
Pad Type5
Package Location
Direction
Voltage6
P/A/G3
State during State
RESET7 after RESET8
324
416
516
— VSSSYN — VSSSYN Clock synthesizer ground input I VSSE VDDSYN VSSSYN VSSSYN U22 AA26 AA26
— VSTBY — VSTBY SRAM standby power input I VHV VDDEH1 VSTBY VSTBY K4 M4 M4
— REGSEL — REGSEL Selects regulator mode (Linear/Switch I AE VDDREG REGSEL REGSEL V20 W23 W23
mode)
— REGCTL — REGCTL Regulator controller output to O AE VDDREG REGCTL REGCTL T22 Y26 Y26
base/gate of power transistor
— VSSFL — VSSFL Tie to VSS I VSS VDDREG VSSFL VSSFL V21 AB25 AB25
— VDDREG — VDDREG Source voltage for on-chip regulators I VDDINT VDDREG VDDREG VDDREG U21 AA25 AA25
and Low voltage detect circuits
1 The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not have GPIO
functionality, this number is the PCR number.
2 The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices and is
indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.
3 P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.
4 Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are
designated in the PA field of the SIU_PCRn registers except where explicitly noted.
5 MH = High voltage, medium speed
F = Fast speed
FS = Fast speed with slew
AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)
VHV = Very high voltage
6 VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V (+5%/–10%)
power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.
7 The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in this column
is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select (during
Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the
slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled.
8 The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are
off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.
9 This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C.
10 During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system
clock propagates through the device.

11
NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers.
121
12 Nexus reset is different than system reset; MDO 1-11 are enabled when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO and MCKO
122
are also dependent on trace (RPM or FPM) being enabled.

13 The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU values
have no effect on the function of these pins once enabled.
14 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register).
15 Do not connect pin directly to a power supply or ground.
NXP Semiconductors
Table 45 lists the pin locations of the power and ground signals on the 324 TEPBGA package.
NXP Semiconductors
Table 44. 324-pin Power Supply Locations

VDD
A2 B3 C4 D5 K3 V19 W5 W9 W20 Y4 Y21 AA3 AA22 AB2
VDD33
W21 V4
VDDE2
AB4 M9 N1 N10 N9 P10 P9 T4 W6 V2
VDDEH1 VDDEH4 VDDEH6 VDDEH7

B1 L4 AB20 W8 N20 T21 C22 H19 L22
VSS
A1 A22 AA2 AA21 AB1 AB22 B2 B21 C20 C3 D19 D4 J10 J11 J12 J13 J14 J9
K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 N11
N12 N13 N14 P11 P12 P13 P14 W19 W4 Y20 Y3
123
124

VDD
A2 B3 C4 D5 N4 AB4 AB23 AC3 AC12 AC24 AD2 AD25 AE1 AE26
VDD33
M1 AA4 AA23
VDDE2
N10 P10 P11 R10 R11 T1 T10 T11 T12 U10 U11 U12 W4 AC1 AC5 AF2

B1 P4 AC10 AF5 AC11 AF22 AC21 AF25
VDDEH6 VDDEH7
N23 AC25 D24 E23 M26
VSS
A1 A26 B2 B25 C3 C24 D4 D23 K10 K11 K12 K13 K14 K15 K16 K17 L10 L11
L12 L13 L14 L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N11 N12 N13 N14
N15 N16 N17 P12 P13 P14 P15 P16 P17 R12 R13 R14 R15 R16 R17 T13 T14 T15
T16 T17 U13 U14 U15 U16 U17 AC4 AC23 AD3 AD24 AE2 AE25 AF1 AF26
NXP Semiconductors
NXP Semiconductors

VDD
A2 B3 C4 D5 E6 N4 AB4 AB23 AC3 AC12 AC24 AD2 AD25 AE1 AE26
VDD33 VDDE10
M1 P6 L21 AA4 AA11 AA14 AA23 F16 F17 F19 F21 N21 P21 AA22
VDDE2
N10 P10 P11 R10 R11 T1 T10 T11 T12 U10 U11 U12 W4 AC1 AC5 AF2
VDDE8 VDDE9
F6 F8 F10 F11 N6 AA5 AA13 AB6 AB7 AB18 AB19 AB20 AB21

B1 P4 AC10 AF5 AC11 AF22 AC21 AF25
VDDEH6 VDDEH7
N23 AC25 D24 E23 M26
VSS
A25 B2 B25 B26 C3 C24 D4 D23 E5 E7 E8 E9 E10 E11 E12 E13 E14 E15
E16 E17 E18 E19 E21 E22 F5 F13 F14 K10 K11 K12 K13 K14 K15 K16 K17 L10
L11 L12 L13 L14 L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N11 N12 N13
N14 N15 N16 N17 P12 P13 P14 P15 P16 P17 R12 R13 R14 R15 R16 R17 T13 T14
T15 T16 T17 U13 U14 U15 U16 U17 AA6 AA21 AB5 AB22 AC4 AC23 AD3 AD24 AE2 AE25
125
Revision History
Appendix B Revision History

Table 47 describes the changes made to this document between revisions.
Table 47. Revision History
Revision
Description of changes
(Date)
2 Initial release, NDA Required.

(Sept 2008)
3 Changes between Rev.2 and Rev. 3:

(Nov 2009)
Added 516-pin package figures.
Signals table: Updates throughout entire table.
Updated Section 4.6, “Power Up/Down Sequencing”
Updated features list.

Updated flash PFCPR1 settings table.
Fixed JTAG Test Clock Input Timing figure so the spec #’s in table matched figure.
Updated Orderable Part numbers table.
Moved signals table to be an appendix.
Added 324-pin package thermals.

Updated part numbers in orderable parts table (missing F: MPC5674F).
FMPLL Electrical Spec table:

Spec #1 changed min values of 4 to 8
Removed last sentence of footnote 2
Added note "Upper tolerance of less than 1% is allowed on 40MHz crystal."
Oscillator Electrical Spec table:

Moved predivider op. frequency spec from this table to the FMPLL Electrical Spec table
Removed footnote #3 (since VDDE9 is an external supply and has no relation to the oscillator, PMC, or PLL).
Added maximum solder temperature to Absolute Max Ratings table.
PMC Operating Conditions table:

Removed JTemp row.
Changed VDDR to VDDREG (naming consistency)
Changed VDD12 to VDD (naming consistency)
PMC Electrical Spec table:

Added VDDREG to this parameter “Trimmed bandgap reference voltage / voltage dependence (VDDREG)”
Changed VDDSTEP to LVDSTEP12 (naming consistency)
Added two conditons to the opening statements of Section 4.6, “Power Up/Down Sequencing.”
DC Electrical Specifications table:

spec #9 (Fast I/O Input High Voltage)
spec #10 (Fast I/O Input Low Voltage)
spec #24 (Operating Current 1.2 V Supplies; IDD)
spec #25 (Operating Current 3.3 V Supplies; IDDSYN)
spec #32 (Analog Input Current, Channel Off; IINACT_A)
footnote #12 ("IOH_S = {11.6} mA...")

Revision History
Table 47. Revision History (continued)
Revision
(Date)
3 eQADC Conversion Specifications table:

(cont.) Spec #7, 8: both +/-3, no dependency on frequency
Spec #15, 16: added "(with calibration)" to both
Flash Program and Erase Specifications table:

Added footnote 4 to spec #2.
Updated all initial max value times.
Updated entire AC Specifications: Clocking section.
Pad AC Specifications table: updated Medium pad specs

Derated Pad AC Specifications table: updated all specs
Updated entire Section 4.6, “Power Up/Down Sequencing.”
Updated Absolute Maximum Ratings (AMR) specs 1–11, 15, 16.

Changed name of IDDC to IREGCTL since it is the REGCTL max drive current.
Added two EMC Radiated Emissions Operating Behaviors tables and removed “EMI Testing Specifications”
table.
PMC Electrical Specifications table:

1b: Changed 1% to 2%
1c: Changed 150 to 300 ppm/C
2b: added footnote
2c: Changed from "Trimming step VDD" to "Trimming step VDD12OUT"
DC Electrical Specifications table:

6: Updated min value and added keep-out range
Standby RAM Regulator Electrical Specifications table:

Added brownout spec
PMC electrical spec table, added new specs: SMPS regulator output resistance, SPMS regulator clock
frequency, SMPS regulator overshoot at start-up, SMPS max output current, and voltage variation on current
step.
Added LVD VDDA specs to the PMC electrical spec table.

Removed specs for VDDF and VFLASH since those supplies are shorted with others in the package.
4
Changes between Rev.3 and Rev.4:
(Aug 2010)
Table “Derated Pad AC Specifications”, Spec #1: Changed 20ns to 200ns.
Added “324-ball TEPBGA Pin Assignments” section and mechanical drawings.
Appendix A (Signals):
Added “(the BAM uses this pin to select if auto baud rate is on or off)” to the EVTO pin description.
Added 324 pinout column.
Changed footnote from “NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through
the SIU DIRER register.“ to “NMI does not have a PCR PA configuration; it is enabled when NMI is enabled
through the SIU_IREER and SIU_IFEER registers.”
Updated eQADC signals to show that eQADC A and B each have dedicated channels (ANx0-23) and shared
channels (AN24-39).

Revision History
Revision
(Date)
4 “Temperature Sensor Electrical Specifications” table: Changed spec #2 to have one temperature range (-40 - 150
(cont) C) and changed spec value from ±1.0 to ±10.0 C.
“eQADC Conversion Specifications (Operating)” table: Changed spec #13 (non-disruptive injection current)
values from ±1 to ±3.
"IPCLKDIV Settings" table, removed footnote "eMIOS and DMA are not considered peripherals here."
5 Note 4 in Maximum Ratings updated from 2.0 V to 1.65 V.

(Feb-2011) Changed I/O Supply Voltage spec in DC Electrical specs, Spec 2, from 1.62 V min to 3.0 V min.
Changed the APC=RWSC value in line 1 of PFCPR1 Settings vs. Frequency of Operation table from 0b011 to
0b100
Changed note 1 for Pad AC Specifications table from Vdde = 1.62 V to 1.98 V to read Vdde = 3.0 V to 3.6 V
Changed note 6 for Signal Properties and Muxing Summary table by removing the voltage range 1.8 V - 3.3 V to
have 3.3 V instead of the range.
Spec 2 in Table 9 “ESD Ratings“ the spec for “ESD for Charged Device Model (CDM)” changed to 250 V (other)
from 500 V (other)
Removed voltage ranges 1.62-1.98 V and 2.25-2.75 V from spec 28 in Table 14
6 Same content as for Rev. 5

(Feb-2011)
7 Added entry for Rev. 6 and Rev. 7 to this table to fix a revision-numbering issue.
(Mar-2011)
8 Added the following footnotes to the “Signal Properties and Muxing Summary” table:
(Jun-2011) • Footnote 10, for the ANA[0:7] signals, “During and just after POR negates, internal pull resistors can be
enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock
propagates through the device.”
• Footnote 15, for MDO[0:15] and MSEO[0:1] signals, “Do not connect pin directly to a power supply or ground.”
Changed min and max values of ID 1 “Nominal bandgap reference voltage“ in Table 11 (PMC Electrical
Specifications) to 0.608 V min and 0.632 V max.
Changed min and max values of Spec 2 “ADC Bandgap” in Table 23 (ADC Band Gap Reference/LVI Electrical
Specifications) to 1.171 V min and 1.269 V max.
Changed Spec 3 of Table 26 (Flash EEPROM Module Life) from 'Minimum Data Retention at 25 °C ambient
temperature' to 'Minimum Data Retention at 85 °C ambient temperature'
Added Spec 41, 42, 43 and 44 to the “DC Electrical Specifications” table
Added Note 25 to the “DC Electrical Specifications” table for Spec 41, 42 and 43
Added Note 26 to the “DC Electrical Specifications” for Spec 44
Added Spec 17 to the “eQADC Conversion Specifications (Operating)” table.
Added Spec 18 to the “eQADC Conversion Specifications (Operating)” table.
Added Note 15 to the “eQADC Conversion Specifications (Operating)” table for Spec 17 and 18.

Revision History
Revision
(Date)
8 Removed spec 3 from Table 27 “PFCPR1 Settings vs Frequency of Operation”

(Jun-2011) Updated spec 2a (Untrimmed VRC 1.2V) in Table 11 “PMC Electrical Specifications“ to a max value of
VDD12OUT + 17%.
Updated item 26 (Operating Current VDDA Supply) in table 14 “Electrical Specifications” from 30 mA to 40 mA.
Updated Note 11 for Table 14 (Electrical Specifications) to read IOH_F = {16,32,47,77} mA and
IOL_F = {24,48,71,115} mA for {00,01,10,11} drive mode with VDDE = 3.0 V.
Updated ID 9 in Table 11 (PMC Electrical Specifications) to
VREG = 4.5 V, max DC output current with a max of 80 mA
VREG = 4.25 V, max DC output current, crank condition with a max of 40 mA
Updated Table 17 (DSPI LVDS Pad Specification) with the following:
• Spec 1 typical value updated from 40 MHz to 50 MHz
• Spec 2 added SRC conditions and associated values:
– SRC=0b00 or SRC=0b11 Min 150 mV Max 400 mV
– SRC=0b01 Min 90 mV Max 320 mV
– SRC=0b10 Min 160 mV Max 480 mV
• Spec 3
- Min value from 1.075 V to 1.06 V
- Max value from 1.325 V to 1.39 V
• Added Spec 5, 6 and 7
Updated table 17 "DSPI LVDS pad specification" to include Temperature with a min value of -40 C and max of
150 C
Updated Spec 5 of Table 18, "FMPLL Electrical Specifications" to < 400 us as the Max vaule.
Added the sentence "Violating the VCO min/max range may prevent the system from exiting reset." to the end
of Footnote 16 of Table 18, "FMPLL Electrical Specifications"
Updated Spec 1 of Table 18, "FMPLL Electrical Specifications", Crystal Reference (PLLCFG2 = 0b1) minimum
value from 40 MHz to 16 MHz.
Updated Spec 1 of Table 18, "FMPLL Electrical Specifications", External Reference (PLLCFG2 = 0b1) minimum
value from 40 MHz to 16 MHz.
Removed Note 9, 'Duty cycle can be 20–80% when PLL is used with a pre-divider greater than 1', from Table 18,
"FMPLL Electrical Specifications".
Updated ID 16 in Table 11, “PMC Electrical Specifications”, SMPS regulator clock frequency (after reset) 2.4MHz
Max
Updated Table 16 “Flash EEPROM Module Life”, spec 3, ‘Blocks with 10,001–100,000 P/E cycles’ to 5 Years.
Added Typ column to Table 25, “Flash Program and Erase Specifications”
Updated Table 3, “Absolute Maximum Ratings” with the following:

- Spec 1, ‘1.2 V Core Supply Voltage’, to a Max of 2.0 V
- Spec 3, ‘Clock Synthesizer Voltage’, to a Max of 5.3 V
- Spec 4, ‘I/O Supply Voltage’ to a Max of 5.3 V
- Spec 5, ‘Analog Supply Voltage’ to a Max of 5.3 V
- Note 2 to read, “2.0 V for 10 hours cumulative time, 1.32 V +10% for time remaining.“
- Note 3, “... 5.0 V + 10% ...” to “... 5.25 V + 10 % ...”
- Note 5, “... 3.3 V + 10% ...” to “... 3.60 V + 10 % ...”
Updated Spec 2 (ESD for Charged Device Model (CDM)) of Table 9, “ESD Ratings”, to 500 V
Updated Table 27, “PFCPR1 Settings vs. Frequency of Operation“, Spec 3, APC = RWSC column to 0b100.
Updated Spec 26, “Operating Current 5.0 V Supplies @ fsys = 264 MHz“ for IDDA to 50 mA, in Table 14, “DC
electrical specifications”.

Revision History
Revision
(Date)
9 Updated Table 1.,"Orderable Part Numbers" with actual available parts. Added new part number
SPC5673FF3MVY2 ,Package description 516 PBGA, w/EBI, Pb-free.Speed is 200 MHz nom and
max.—Removed note attached to “Orderable Part Numbers” and “Freescale Part Number”.
Updated footnotes of Table 3.,"Absolute Maximum Ratings" to:

• 2.0 V for 10 hours cumulative time, 1.2V +10% for time remaining.
Updated Table 6.,"Thermal Characteristics, 324-pin Package" to show MPC5674F thermal characteristics.
In Table 10.,"PMC Operating conditions", updated the parameter “Supply voltage VDD 1.2V nominal" to “Core
supply voltage".
In Table 11.,"PMC Electrical Specifications", updated the following rows:

• Parameter “Nominal VRC regulated 1.2V output VDD” updated column “Typ” to 1.27 V.
• The minimum and maximum value of “Untrimmed VRC 1.2V output variation before band gap trim (unloaded)”
updated to “-14%” and “+10%”, respectively.
• The minimum and maximum value of “Trimmed VRC 1.2V output variation after band gap trim (REGCTL load
max. 20mA, VDD load max 1A)” updated to “-10%” and “+5%”, respectively.
In Table 12.,"Power Sequence Pin States for MH and AE pads", updated the row (VDD33 = low, VDDE = high),
parameter “MH+LVDS Pads” to “Outputs disabled”.
In Table 13.,"Power Sequence Pin States for F and FS pads", updated the rows (VDD = low, VDD33 = low, VDDE
= high) and (VDD = high, VDD33 = low, VDDE = high), parameter “F and FS pad” to “Outputs Disabled”.
In Table 14.,"DC Electrical Specifications", updated the spec 'Operating Current 1.2 V Supplies @ fSYS = 264
MHz' with 'VDD @ 1.32 V' Max value to 850 mA from 1.0 A, and deleted corresponding footnote stating that the
previous information was preliminary.
Updated current (mA) values in Table 15.,"VDDE/VDDEH I/O Pad Average DC Current" from Spec 5 to 13:
• Spec 5 Current (mA) from 6.5 to 7.4
• Spec 13 Current (mA) from8.9 to 9.
In Table 35.,"Nexus Debug Port Timing", updated the footnote of parameter “tCYC” to “See Notes on tcyc in
Table27”. Removed references to “Section I/O Pad VDD33 Current Specifications” .
10 Updated Figure 1.,"MPC5674F Orderable Part Number Description" with changes in “Revision of Silicon” and
“Fab Revision ID”.
Updated Table 1.,"Orderable Part Numbers" with changes in Part numbers and Package Description.

Revision History
Revision
(Date)
10.1 In Figure 1.,"MPC5674F Orderable Part Number Description", replaced “Revision of Silicon for TSMC is 0 for
now. In future, it will be revision 1” with “0 = Rev 0 (TSMC14)”.
11 In Figure 1.,"MPC5674F Orderable Part Number Description", updated Fab and Masking Information.
In Table 1, added information about the available parts.

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Document Number: MPC5674F

Rev. 11
10/2021

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NXP Semiconductors Document Number: MPC5674F

Data Sheet: Technical Data Rev. 11, 10/2021

MPC5674F Microcontroller Data Sheet, Rev. 11

Operating frequency (MHz)

Tape and reel status

Figure 1. MPC5674F Orderable Part Number Description

Table 1. Orderable Part Numbers

Speed (MHz)1 Operating Temperature2

SPC5674FK0MVR3 416 PBGA, no EBI, Pb-free 264 270 –40 °C 125 °C

MPC5674F Microcontroller Data Sheet, Rev. 11

Table 1. Orderable Part Numbers (continued)

Speed (MHz)1 Operating Temperature2

SPC5673FF3MVV2 516 PBGA, w/EBI, SnPb 264 200 –40 °C 125 °C

1.2 MPC567xF Family Differences

MPC5674F Microcontroller Data Sheet, Rev. 11

4MB I/O 256KB SRAM Boot Assist I/O

Data ADCi ADCi

Figure 2. Block Diagram

MPC5674F Microcontroller Data Sheet, Rev. 11

3.1 324-ball TEPBGA Pin Assignments

E ETPUA20 ETPUA22 ETPUA24 ETPUA30 ETPUC5 ETPUC10 ETPUC11 ETPUC4 E

F ETPUA13 ETPUA14 ETPUA15 ETPUA27 ETPUC12 ETPUC14 ETPUC13 ETPUC9 F

H ETPUA5 ETPUA6 ETPUA9 ETPUA16 VDDEH7 ETPUC23 ETPUC22 ETPUC21 H

R MDO2 MDO3 MDO4 MDO5 ETPUB1 ETPUB17 ETPUB3 ETPUB2 R

T MDO6 MDO7 MDO8 VDDE2 ETPUB19 ETPUB18 VDDEH6 REGCTL T

U MDO9 MDO10 MDO11 MDO15 ETPUB31 ETPUB30 VDDREG VSSSYN U

V MDO12 VDDE2 MDO14 VDD33_2 VDD REGSEL VSSFL EXTAL V

Figure 3. MPC5674F 324-ball TEPBGA (full diagram)

MPC5674F Microcontroller Data Sheet, Rev. 11

E ETPUA20 ETPUA22 ETPUA24 ETPUA30

F ETPUA13 ETPUA14 ETPUA15 ETPUA27

H ETPUA5 ETPUA6 ETPUA9 ETPUA16

J ETPUA1 ETPUA2 ETPUA3 ETPUA4 VSS VSS VSS J

K TCRCLKA ETPUA0 VDD VSTBY VSS VSS VSS K

M JCOMP RESET PLLCFG0 RDY VDDE2 VSS VSS M

N VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VSS N

P EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VSS P

R MDO2 MDO3 MDO4 MDO5

T MDO6 MDO7 MDO8 VDDE2

U MDO9 MDO10 MDO11 MDO15

V MDO12 VDDE2 MDO14 VDD33_2

Figure 4. MPC5674F 324-ball TEPBGA (1 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 11

ETPUC5 ETPUC10 ETPUC11 ETPUC4 E

ETPUC12 ETPUC14 ETPUC13 ETPUC9 F

VDDEH7 ETPUC23 ETPUC22 ETPUC21 H

J VSS VSS VSS ETPUC27 ETPUC28 ETPUC26 ETPUC24 J

K VSS VSS VSS ETPUC31 ETPUC30 ETPUC29 ETPUC25 K

L VSS VSS VSS ETPUB12 ETPUB13 ETPUB14 VDDEH7 L

M VSS VSS VSS ETPUB7 ETPUB10 ETPUB11 ETPUB9 M

N VSS VSS VSS ETPUB0 VDDEH6 ETPUB8 ETPUB6 N

P VSS VSS VSS TCRCLKB ETPUB16 ETPUB5 ETPUB4 P

ETPUB1 ETPUB17 ETPUB3 ETPUB2 R

ETPUB19 ETPUB18 VDDEH6 REGCTL T

ETPUB31 ETPUB30 VDDREG VSSSYN U

VDD REGSEL VSSFL EXTAL V

Figure 5. MPC5674F 324-ball TEPBGA (2 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 11

3.2 416-ball TEPBGA Pin Assignments

E ETPUA23 ETPUA24 ETPUA25 ETPUA26 VDDEH7 ETPUC4 ETPUC5 ETPUC6 E