Freescale Semiconductor Document Number: MPC5676R

Data Sheet: Advance Information Rev. 4, 16 Feb 2016

MPC5676R

MPC5676R Microcontroller TEPBGA–416

27 mm x 27 mm
Data Sheet TEPBGA–516
27mm x 27mm

On-chip modules available within the family include the – Up to 96 eTPU2 channels (32 channels per eTPU2)
following features: – total of 36 KB code RAM
• Two identical dual issue, 32-bit CPU core complexes – total of 9 KB parameter RAM
(e200z7), each with • Enhanced modular input output system supporting 32
– Power Architecture embedded specification compliance unified channels (eMIOS) with each channel capable of
– Instruction set enhancement allowing variable length single action, double action, pulse width modulation
encoding (VLE), optional encoding of mixed 16-bit and (PWM) and modulus counter operation
32-bit instructions, for code size footprint reduction • Two enhanced queued analog-to-digital converter
– Signal processing extension (SPE) instruction support (eQADC) modules with
for digital signal processing (DSP) – two separate analog converters per eQADC module
– Single-precision floating point operations (FPU) – support for a total of 64 analog input pins, expandable to
– 16 KB I-Cache and 16 KB D-Cache 176 inputs with off-chip multiplexers
– Hardware cache coherency between cores – one absolute reference ADC channel
• 16 Hardware semaphores – interface to twelve hardware decimation filters
• 3 channel CRC module – enhanced ‘Tap’ command to route any conversion to two
• 6MB on-chip flash separate decimation filters
– Supports read during program and erase operations, and – Temperature sensor
multiple blocks allowing EEPROM emulation • Five deserial serial peripheral interface (DSPI) modules
• 384KB on-chip general-purpose SRAM including 48KB of • Three enhanced serial communication interface (eSCI)
standby RAM modules
• Two multi-channel direct memory access controllers • Four controller area network (FlexCAN) modules
(eDMA) • Dual-channel FlexRay controller
– 64 channels per eDMA • Nexus development interface (NDI) per IEEE-ISTO
• Dual core Interrupt controller (INTC) 5001-2003 standard, with some support for 2010 standard.
• Phase-locked loop with FM modulation (FMPLL) • Device and board test support per Joint Test Action Group
• Crossbar switch architecture for concurrent access to (JTAG) (IEEE 1149.1)
peripherals, flash, or RAM from multiple bus masters • On-chip voltage regulator controller regulates supply
• External Bus Interface (EBI) for calibration and voltage down to 1.2 V for core logic
application development • Self Test capability
• System integration unit (SIU) with error correction status
module (ECSM)
• Four protected port output pins (PPO)
• Boot assist module (BAM) supports serial bootload via
CAN or SCI
• Three second-generation enhanced time processor units
(eTPU2)

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2016. All rights reserved.
 Table of Contents
1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4.7.2 I/O Pad VDD33 Current Specifications . . . . . . . 24
1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 25
2 MPC5676R Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4.8 Oscillator and FMPLL Electrical Characteristics . . . . . 27
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4.9 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 29
3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 31
3.1 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6 4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .7 4.11.1 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .8 4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 33
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.12.1 Generic Timing Diagrams. . . . . . . . . . . . . . . . . 34
4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .9 4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 35
4.2.1 General Notes for Specifications at 4.12.3 IEEE 1149.1 Interface Timing. . . . . . . . . . . . . . 36
Maximum Junction Temperature . . . . . . . . . . . . 11 4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3 EMI (Electromagnetic Interference) Characteristics . . .12 4.12.5 External Bus Interface (EBI) Timing . . . . . . . . . 41
4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 46
4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .13 4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5.1 Regulator Example . . . . . . . . . . . . . . . . . . . . . .16 4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .18 4.12.9 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.6.1 Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.1 416-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6.3 Power Sequencing and POR Dependent 5.2 516-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
on VDDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .20 Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 59
4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .23 Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

MPC5676R Microcontroller Data Sheet, Rev. 4

2 Freescale Semiconductor
 Ordering Information

1 Ordering Information
1.1 Orderable Parts
Figure 1 and Table 1describe and list the orderable part numbers for the MPC5676R.

M PC 5676R D K2 M VU 1 R

Qualification status
Core code
Device number
(Optional) Dual-core identifier
Fab/Revision
Temperature range
Package identifier
Operating frequency
Tape and reel status

Temperature Range Package Identifier Operating Frequency Tape and Reel Status
M = –40 °C to 125 °C VU = 416 TEPBGA 1 = 2 x 180 MHz R = Tape and reel
Pb-Free (blank) = Trays
VY = 516 TEPBGA
Pb-Free Qualification Status
P = Pre qualification
M = Fully spec. qualified, general market flow
Note: Not all options are available on all devices. Refer to Table 1. S = Fully spec. qualified, automotive flow

Figure 1. MPC5676R Orderable Part Number Description

Table 1. Orderable Part Numbers

Speed (MHz)2 Operating Temperature3

NXP Part Number1 Package Description
Nominal Max4 (fMAX) Min (TL) Max (TH)

SPC5676RDK2MVU1R MPC5676R 416 package

180 184 –40 °C 125 °C
Lead-free (Pb-free)
SPC5676RDK2MVY1R MPC5676R 516 package
180 184 –40 °C 125 °C
Lead-free (Pb-free)
1 All packaged devices are PPC5676R, rather than MPC5676R or SPC5676R, until product qualifications are complete. The
unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.
Not all configurations are available in the PPC parts.
2
For the operating mode frequency of various blocks on the device, see Table 28.
3
The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH.
4
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
180 MHz parts allow for 180 MHz system clock + 2% FM.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 3
MPC5676R Blocks

2 MPC5676R Blocks
2.1 Block Diagram
The following figure shows a top-level block diagram of the MPC5676R. The purpose of the block diagram is to show the
general interconnection of functional modules through the crossbar switch and from the Dual Interrupt Controller, and provide
an indication of the modules that connect to external pins. For clarity, the following modules are omitted from the diagram:
PMU, SWT, STM, PIT, ECSM, DTS, and CRC.

Power Architecture Power Architecture

MPC5676R e200z7 Core e200z7 Core JTAG

SPE SPE Nexus

Dual Interrupt IEEE-ISTO
VLE 5001-2003
Controller VLE
MMU MMU

eDMA2 eDMA2 16K 16K 16K 16K

I-Cache D-Cache I-Cache D-Cache FlexRay EBI
64 Channels 64 Channels (Calibration)

Crossbar Switch

MPU

6MB I/O 384KB I/O Boot Assist

SIUA FLASH BridgeA STCU FMPLL SRAM BridgeB Semaphores Module
(48KB S/B)
FlexCAN
FlexCAN
FlexCAN
FlexCAN
6KB 3KB eQADC eQADC
DSPI
DSPI
DSPI
DSPI
DSPI

SIUB
eSCI
eSCI
eSCI

Data Data 12 x DECFILT

eMIOS eTPU2 RAM eTPU2 RAM eTPU2

ADC
ADC
ADC
ADC
32 32 32 32
Channel Channel 24KB Channel 12KB Channel
Code Code
RAM RAM PPO AMux

LEGEND
ADC – Analog to Digital Convertor I-Cache – Instruction Cache
AMux – Analog Pin Multiplexer IRC – Internal RC Oscillator
D-Cache – Data Cache JTAG – Joint Test Action Group controller
DECFILT– Decimation Filter MMU – Memory Management Unit
DSPI – Deserial/Serial Peripheral Interface MPU – Memory Protection Unit
EBI – External Bus Interface PPO – Protected Port Output
eDMA2 – Enhanced Direct Memory Access controller version 2 S/B – Stand-by
eMIOS – Enhanced Modular I/O System SIUA – System Integration Unit A
eQADC – Enhanced Queued Analog to Digital Converter SIUB – System Integration Unit B
eSCI – Enhanced Serial Communications Interface SPE – Signal Processing Engine
eTPU2 – Enhanced Time Processing Unit version 2 SRAM – Static RAM
FlexCAN– Flexible Controller Area Network controller STCU – Self Test Control Unit
FMPLL – Frequency Modulated Phase Lock Loop clock generator VLE – Variable Length instruction Encoding

Figure 2. MPC5676R Block Diagram

MPC5676R Microcontroller Data Sheet, Rev. 4

4 Freescale Semiconductor
 Pin Assignments

3 Pin Assignments
3.1 416-ball TEPBGA Pin Assignments
Figure 3 shows the 416-ball TEPBGA pin assignments.

CAUTION
This ball map is preliminary and subject to change. Do not use it for board design.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
REF–
A VSS VDD RSTOUT ANA0 ANA4 ANA8 ANA11 ANA15 VDDA_A0 VRL_A VRH_A AN28 AN32 AN36 VDDA_B0 REF– VRL_B VRH_B ANB7 ANB11 ANB14 ANB17 ANB21 ANB23 VSS A
BYPCA1 BYPCB1
REF– AN33 VDDA_B1 VSSA_B0 REF– ANB6
B VDDEH1 VSS VDD TEST ANA1 ANA5 ANA10 ANA14 VDDA_A1 VSSA_A1 BYPCA AN24 AN27 AN29
BYPCB
ANB8 ANB10 ANB15 ANB18 ANB22 VSS TCRCLKC B

C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 ANA9 ANA13 ANA17 ANA19 ANA21 ANA23 AN26 AN30 AN34 AN37 AN38 ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 VSS ETPUC0 ETPUC1 C

D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 ANA7 ANA12 ANA16 ANA18 ANA20 ANA22 AN25 AN31 AN35 AN39 ANB1 ANB2 ANB3 ANB9 ANB13 ANB20 VSS VDDEH7 ETPUC2 ETPUC3 D

E ETPUA23 ETPUA24 ETPUA25 ETPUA26 VDDEH7 ETPUC4 ETPUC5 ETPUC6 E

F ETPUA19 ETPUA20 ETPUA21 ETPUA22 ETPUC7 ETPUC8 ETPUC9 ETPUC10 F

G ETPUA15 ETPUA16 ETPUA17 ETPUA18

MPC5676R 416-ball TEPBGA ETPUC11 ETPUC12 ETPUC13 ETPUC14 G
(as viewed from top through the package)
H ETPUA11 ETPUA12 ETPUA14 ETPUA13 ETPUC15 ETPUC16 ETPUC17 ETPUC18 H

J ETPUA7 ETPUA8 ETPUA9 ETPUA10 ETPUC19 ETPUC20 ETPUC21 ETPUC22 J

K ETPUA3 ETPUA4 ETPUA5 ETPUA6 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC23 ETPUC24 ETPUC25 ETPUC26 K

L TCRCLKA ETPUA0 ETPUA1 ETPUA2 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC27 ETPUC28 ETPUC29 ETPUC30 L

M VDD33_1 TXDA RXDA VSTBY VSS VSS VSS VSS VSS VSS VSS VSS ETPUC31 ETPUB15 ETPUB14 VDDEH7 M

BOOT– VDDE2 VSS VSS VSS VSS VSS VSS VSS

N RXDB VDDEH6 ETPUB11 ETPUB12 ETPUB13 N
CFG1 WKPCFG VDD

P TXDB PLLCFG1 PLLCFG2 VDDEH1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB7 ETPUB8 ETPUB9 ETPUB10 P

R JCOMP RESET PLLCFG0 RDY VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB3 ETPUB4 ETPUB5 ETPUB6 R

T VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS TCRCLKB ETPUB0 ETPUB1 ETPUB2 T

U EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB19 ETPUB18 ETPUB17 ETPUB16 U

V MDO2 MDO3 MDO4 MDO5 ETPUB26 ETPUB22 ETPUB21 ETPUB20 V

W MDO6 MDO7 MDO8 VDDE2 REGSEL ETPUB25 ETPUB24 ETPUB23 W

Y MDO9 MDO10 MDO11 MDO15 ETPUB29 ETPUB28 ETPUB27 REGCTL Y

AA MDO12 MDO13 MDO14 VDD33_2 VDD33_3 ETPUB30 VDDREG VSSSYN AA

AB TDO TCK TMS VDD VDD ETPUB31 VSSFL EXTAL AB

AC VDDE2 TDI VDD VSS VDDE2 PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4 VDD EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1 VSS VDD VDDEH6 XTAL AC

FR_A_ FR_B_
AD ENGCLK VDD VSS EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNTXD SCKC RXDC PCSC3 VSS VDD VDDSYN AD
TX TX PCSA5 SOUTA SCKA PCSB0 PCSB3 EMIOS2
FR_A_ FR_B_
AE VDD VSS PCSA4 PCSA0 PCSA3 SCKB SINB EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0 SINC PCSC2 PCSC5 VSS VDD AE
RX RX
FR_A_ FR_B_
AF VSS VDDE2 TX_EN TX_EN VDDEH3 PCSB5 SINA PCSB2 SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 VSS AF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 3. MPC5676R 416-ball TEPBGA (full diagram)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 5
Pin Assignments

3.2 516-ball TEPBGA Pin Assignments

Figure 4 shows the 516-ball TEPBGA pin assignments.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
REF– REF–
A VDD RSTOUT ANA0 ANA4 ANA9 ANA11 ANA15 VDDA_A0 VRL_A VRH_A AN28 AN29 AN36 VDDA_B0 VRL_B VRH_B ANB5 ANB9 ANB12 ANB18 ANB21 VSS A
BYPCA1 BYPCB1

B VDDEH1 VSS VDD TEST ANA1 ANA5 ANA10 ANA14 VDDA_A1 VSSA_A1 REF– AN24 AN27 AN30 AN32 VDDA_B1 VSSA_B0 REF– ANB4 ANB8 ANB10 ANB13 ANB19 ANB22 VSS VSS B
BYPCA BYPCB

C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 ANA7 ANA13 ANA17 ANA19 ANA21 ANA22 AN25 AN31 AN34 AN39 AN37 ANB0 ANB7 ANB6 ANB11 ANB15 ANB20 VSS ETPUC0 ETPUC1 C

D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 ANA8 ANA12 ANA16 ANA18 ANA20 ANA23 AN26 AN33 AN35 AN38 ANB1 ANB2 ANB3 ANB14 ANB16 ANB17 VSS VDDEH7 ETPUC2 ETPUC3 D

E ETPUA23 ETPUA24 ETPUA25 ETPUA26 VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ANB23 VSS VSS VDDEH7 ETPUC4 ETPUC5 ETPUC6 E

F ETPUA19 ETPUA20 ETPUA21 ETPUA22 VSS VDDE8 VDDE8 VDDE8 VDDE8 VSS VSS VDDE10 VDDE10 VDDE10 VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10 F

G ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18 MPC5676R 516-ball TEPBGA ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15 G

H ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16 ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21 H
(as viewed from top through the package)
J ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12 ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27 J

K TXDB TXDA RXDA TCRCLKA ETPUA6 ETPUA10 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15 K

BOOT– BOOT–
L PLLCFG1 PLLCFG2 CFG1 CFG0 RXDB ETPUA0 VSS VSS VSS VSS VSS VSS VSS VSS VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10 L

M VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG VSS VSS VSS VSS VSS VSS VSS VSS D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7 M

N D_WE0 D_WE2 D_WE3 VDD RESET VDDE8 VDDE2 VSS VSS VSS VSS VSS VSS VSS VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4 N

P D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS VDDE10 ETPUB13 D_OE D_ALE D_DAT0 D_DAT1 P

D_RD_
R D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB9 ETPUB12 ETPUB14 ETPUB15 WR R

T VDDE2 D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11 T

U D_CS2 JCOMP RDY MCKO MSEO1 MSEO0 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6 U

V EVTI EVTO MDO0 MDO2 MDO3 ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0 V

W MDO4 MDO5 MDO6 VDDE2 MDO8 MDO1 ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18 W

Y MDO7 MDO9 MDO10 MDO11 MDO12 ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL Y

AA MDO13 MDO14 MDO15 VDD33_1 VDDE8 VSS PCSA5 SOUTB VDD33_4 VDDE9 VDD33_4 EMIOS23 EMIOS31 CNRXB VSS VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA

AB TDO TCK TMS VDD VSS VDDE9 VDDE9 SCKA SINB D_CS1 D_ADD21 D_ADD29 EMIOS1 EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9 VDDE9 VDDE9 VDDE9 VSS VDD ETPUB30 VSSFL EXTAL AB

AC VDDE2 TDI VDD VSS VDDE2 PCSA1 SOUTA SCKB PCSB3 VDDEH3 VDDEH4 VDD EMIOS0 EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1 VSS VDD VDDEH6 XTAL AC

FR_A_ FR_B_
AD ENGCLK VDD VSS PCSA0 PCSA3 PCSB2 D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD SCKC RXDC PCSC3 VSS VDD VDDSYN AD
TX TX
FR_A_ FR_B_
AE VDD VSS PCSA4 PCSB5 SINA PCSB1 D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0 SINC PCSC2 PCSC5 VSS VDD AE
RX RX
FR_A_ FR_B_ D_
AF VDDE2 VDDEH3 PCSA2 PCSB4 PCSB0 D_TA D_ADD24 D_ADD27 CLKOUT EMIOS4 EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 AF
TX_EN TX_EN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 4. MPC5676R 516-ball TEPBGA (full diagram)

MPC5676R Microcontroller Data Sheet, Rev. 4

6 Freescale Semiconductor
 Electrical Characteristics

3.3 Pin Muxing and Reset States

See Appendix A, Signal Properties and Muxing, for a listing and description of the pin functions and properties.

4 Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5676R.
The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon
these specifications will be met. Finalized specifications will be published after complete characterization and device
qualifications have been completed.

4.1 Maximum Ratings

Table 2. Absolute Maximum Ratings1

Spec Characteristic Symbol Min Max2 Unit

1 1.2 V Core Supply Voltage3 VDD –0.3 1.65 4 V

2 SRAM Standby Voltage VSTBY –0.3 5.5 5,6 V

6,7
3 Clock Synthesizer Voltage VDDSYN –0.3 4.5 V

4 I/O Supply Voltage (I/O buffers and predrivers) VDD33 –0.3 4.5 6,7 V

5 Analog Supply Voltage (reference to VSSA8) VDDA9 –0.3 5.5 5,6 V

6 I/O Supply Voltage (fast I/O pads) VDDE –0.3 4.5 6 V

7 I/O Supply Voltage (medium I/O pads) VDDEH –0.3 5.5 5,6 V

8 Voltage Regulator Input Supply Voltage VDDREG –0.3 5.55,6 V

9 Analog Reference High Voltage (reference to VRL10) VRH11 –0.3 5.5 5,6 V

10 VSS to VSSA8 Differential Voltage VSS – VSSA –0.1 0.1 V

11 VREF Differential Voltage VRH – VRL –0.3 5.5 5,6 V

12 VRL to VSSA Differential Voltage VRL – VSSA –0.3 0.3 V

13 VDD33 to VDDSYN Differential Voltage VDD33 – VDDSYN –0.1 0.1 V

14 VSSSYN to VSS Differential Voltage VSSSYN – VSS –0.1 0.1 V

12 13 13
15 Maximum Digital Input Current (per pin, applies to all IMAXD –3 3 mA
digital pins)

16 Maximum Analog Input Current 14 (per pin, applies to all IMAXA –3 9,13 3 9,13 mA
analog pins)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 7
Electrical Characteristics

Table 2. Absolute Maximum Ratings1 (continued)

Spec Characteristic Symbol Min Max2 Unit

17 Maximum Operating Temperature Range 15 – Die Junction TJ –40.0 150.0 o

C
Temperature

18 Storage Temperature Range Tstg o

–55.0 150.0 C

19 Maximum Solder Temperature 16 Tsdr o

C
Pb-free package — 260.0
SnPb package — 245.0

20 Moisture Sensitivity Level 17 MSL — 3 —

1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause permanent damage to the device.
2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have

not yet been determined.

3 1.2 V ±10% for proper operation. This parameter is specified at a maximum junction temperature of 150 °C.
4 2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
5 6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.
6 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
7 4.5 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
8 MPC5676R has two analog power supply pins on the pinout: VDDA_A and VDDA_B.
9 MPC5676R has two analog ground supply pins on the pinout: VSSA_A and VSSA_B.
10 MPC5676R has two analog low reference voltage pins on the pinout: VRL_A and VRL_B.
11 MPC5676R has two analog high reference voltage pins on the pinout: VRH_A and VRH_B.
12 Total injection current for all pins must not exceed 25 mA at maximum operating voltage.
13 Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated

time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under
this stress condition.
14 Total injection current for all analog input pins must not exceed 15 mA.
15 Lifetime operation at these specification limits is not guaranteed.
16 Solder profile per CDF-AEC-Q100.
17 Moisture sensitivity per JEDEC test method A112.

4.2 Thermal Characteristics

Table 3. Thermal Characteristics, 416-pin TEPBGA Package1

Characteristic Symbol Value Unit

Junction to Ambient 2,3 Natural Convection (Single layer board) RJA 24 °C/W

Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p) RJA 16 °C/W

Junction to Ambient (@200 ft./min., Single layer board) RJMA 18 °C/W

MPC5676R Microcontroller Data Sheet, Rev. 4

8 Freescale Semiconductor
 Electrical Characteristics

Table 3. Thermal Characteristics, 416-pin TEPBGA Package1 (continued)

Characteristic Symbol Value Unit

Junction to Ambient (@200 ft./min., Four layer board 2s2p) RJMA 13 °C/W

Junction to Board 5 RJB 8 °C/W

Junction to Case 6
RJC 4 °C/W

Junction to Package Top 7 Natural Convection JT 3 °C/W

1
Thermal characteristics are targets based on simulation that are subject to change per device
characterization.
2
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
4
Per JEDEC JESD51-6 with the board horizontal.
5
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
6
Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
7 Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.

Table 4. Thermal Characteristics, 516-pin TEPBGA Package1

Characteristic Symbol Value Unit

Junction to Ambient 2,3 Natural Convection (Single layer board) RJA 24 °C/W

Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p) RJA 17 °C/W

Junction to Ambient (@200 ft./min., Single layer board) RJMA 19 °C/W

Junction to Ambient (@200 ft./min., Four layer board 2s2p) RJMA 14 °C/W

Junction to Board 5 RJB 9 °C/W

Junction to Case 6 RJC 5 °C/W

Junction to Package Top 7 Natural Convection JT 2 °C/W

1 Thermal characteristics are targets based on simulation that are subject to change per device
characterization.
2 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
4 Per JEDEC JESD51-6 with the board horizontal.
5 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
6
Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 9
Electrical Characteristics

7
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.

4.2.1 General Notes for Specifications at Maximum Junction Temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

TJ = TA + (RJA * PD) Eqn. 1

where:
TA = ambient temperature for the package (oC)
RJA = junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to
ambient thermal resistance:

RJA = RJC + RCA Eqn. 2

where:
RJA = junction to ambient thermal resistance (oC/W)
RJC = junction to case thermal resistance (oC/W)
RCA = case to ambient thermal resistance (oC/W)
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:

TJ = TT + (JT x PD) Eqn. 3

where:
TT = thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.

MPC5676R Microcontroller Data Sheet, Rev. 4

10 Freescale Semiconductor
 Electrical Characteristics

References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
• C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
• G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53-58, March 1998.
• B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

4.3 EMI (Electromagnetic Interference) Characteristics

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go
to www.nxp.com and perform a keyword search for “radiated emissions.” The following tables list the values of the device's
radiated emissions operating behaviors.
Table 5. EMC Radiated Emissions Operating Behaviors: 416 BGA

fOSC Frequency Level

Symbol Description Conditions Unit Notes
fSYS band (MHz) (max.)

VRE_TEM 1
Radiated emissions, VDD = 1.2 V 40 MHz crystal 0.15–50 26 dBV
electric field and VDDE = 3.3 V 180 MHz
50–150 30
magnetic field VDDEH = 5 V (fEBI_CAL = 46
TA = 25 °C MHz) 150–500 34
416 BGA
EBI off 500–1000 30
CLK off IEC and SAE level I2 — 1, 3
FM off
1
VRE_TEM Radiated emissions, VDD = 1.2 V 40 MHz crystal 0.15–50 24 dBV
electric field and VDDE = 3.3 V 180 MHz
50–150 25
magnetic field VDDEH = 5 V (fEBI_CAL = 46
TA = 25 °C MHz) 150–500 25
416 BGA
EBI off 500–1000 21
CLK off IEC and SAE level K5 — 1,3
FM on4
1 Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell
Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM
(GTEM) Cell Method.
2 I = 36 dBV
3
Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
4
“FM on” = FM depth of ±2%
5 K = 30 dBV

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 11
Electrical Characteristics

4.4 ESD Characteristics

Table 6. ESD Ratings1,2

Spec Characteristic Symbol Value Unit

1 ESD for Human Body Model (HBM) VHBM 2000 V

2 ESD for Charged Device Model (CDM) VCDM 750 (corners) V

500 (other)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the
device specification.

4.5 PMC/POR/LVI Electrical Specifications

Table 7. PMC Operating conditions

Spec Name Parameter Condition Min Typ Max Unit

1 VDDREG Supply voltage VDDREG LDO5V / SMPS5V mode 4.5 5 5.5 V

5 V nominal1
2 VDDREG Supply voltage VDDREG LDO3V mode 3.0 3.3 3.6 V
3 V nominal1
3 VDD33 Supply voltage VDDSYN / LDO3V mode 3.0 3.3 3.6 V
VDD33 3.3 V nominal2
4 VDD Supply voltage VDD — 1.14 1.2 1.32 V
1.2 V nominal3
1
Voltage should be higher than maximum VLVDREG to avoid LVD event
2
Applies to both VDD33 (flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum VLVD33
to avoid LVD event
3 Voltage should be higher than maximum V
LVD12 to avoid LVD event

NOTE
In the following table, “untrimmed” means “at reset” and “trimmed” means “after reset”.

Table 8. PMC Electrical Specifications

Spec Name Symbol Condition Min Typ Max Unit

1 Nominal bandgap reference VBG — 0.59 0.620 0.65 V

voltage
1a Bandgap reference voltage — — VBG – 5% VBG VBG + 5% V
during power on reset

1b Bandgap reference voltage at — — VBG – 2% VBG VBG + 2% V

nominal voltage / nominal
temperature after power on
reset

MPC5676R Microcontroller Data Sheet, Rev. 4

12 Freescale Semiconductor
 Electrical Characteristics

Table 8. PMC Electrical Specifications

Spec Name Symbol Condition Min Typ Max Unit

1c Bandgap reference voltage / — — — 300 — ppm/C

temperature dependence after
power on reset

1d Bandgap reference voltage / — — — 1500 —

voltage dependence (VDDREG)
after power on reset

2 Nominal VRC regulated 1.2V VDD12OUT — — 1.2 — V

output VDD1

2a VRC 1.2V output variation at — At POR VDD12OUT – 8% VDD12OUT VDD12OUT + 10%

reset (unloaded)2

2b VRC 1.2V output variation after — After POR VDD12OUT – 5% VDD12OUT VDD12OUT + 10%
reset(REGCTL load max.
20mA, VDD load max. 1A)
2c Trimming step Vdd1p2 VSTEPV12 — — 10 — mV

3 POR rising VDD 1.2V VPORC — - 0.7 — V

3a POR VDD 1.2V variation — — VPORC – 30% VPORC VPORC + 30%

3b POR 1.2V hysteresis — — — 75 — mV

4 Nominal rising LVD 1.2V3 VLVD12 — — 1.100 — V

4a LVD 1.2V variation before band — At POR VLVD12 – 6% VLVD12 VLVD12 + 6%

gap trim4

4b LVD 1.2V variation after band — After POR VLVD12 – 3% VLVD12 VLVD12 + 3%
gap trim4
4c LVD 1.2V Hysteresis — — 15 20 25 mV

4d Trimming step LVD 1.2V VLVDSTEP12 — — 10 — mV

5 VRC 1.2V max DC output IREGCTL — — — 20 mA

current

6 Voltage regulator 1.2V current — — — 3 — mA

consumption VDDREG

7 Nominal Vreg 3.3V output5 VDD33OUT — — 3.3 — V

7a Vreg 3.3V output variation at — At POR VDD33OUT – 6% VDD33OUT VDD33OUT + 10%

reset (unloaded)6
7b Vreg 3.3V output variation after — After POR VDD33OUT – 5% VDD33OUT VDD33OUT + 10%
reset (max. load 60mA)

7c Trimming step VDDSYN VSTEPV33 — — 30 — mV

8 Nominal rising LVD 3.3V7 VLVD33 — — 2.950 — V

8a LVD 3.3V variation before band — At POR VLVD33 – 5% VLVD33 VLVD33 + 5%

gap trim6
8b LVD 3.3V variation after bad gap — After POR VLVD33 – 3% VLVD33 VLVD33 + 3%
trim6

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 13
Electrical Characteristics

Table 8. PMC Electrical Specifications

Spec Name Symbol Condition Min Typ Max Unit

8c LVD 3.3V Hysteresis — — — 30 — mV

8d Trimming step LVD 3.3V VLVDSTEP33 — — 30 — mV

9 Vreg 3.3V minimum peak DC IDD33 — 60 — — mA

output current supplied by
regulator without causing
VLVD338
10 Voltage regulator 3.3V current — — — 2 — mA
consumption VDDREG9
11 POR rising on VDDREG VPORREG — — 2.00 — V

11a POR VDDREG variation — — VPORREG – 30% VPORREG VPORREG + 30%

11b POR VDDREG hysteresis — — — 250 — mV

12 Nominal rising LVD VDDREG VLVDREG LDO3V / — 2.950 — V

LDO5V
mode

12a LVD VDDREG variation at — At POR VLVDREG – 5% VLVDREG VLVDREG + 5%

reset10
12b LVD VDDREG variation after — After POR VLVDREG – 3% VLVDREG VLVDREG + 3%
reset10

12c LVD VDDREG Hysteresis — LDO3V / — 30 — mV

LDO5V
mode

12d Trimming step LVD VDDREG VLVDSTEPREG LDO3V / — 30 — mV

LDO5V
mode

13 Nominal rising LVD VDDREG VLVDREG SMPS5V — 4.360 — V

mode

13a LVD VDDREG variation at — At POR VLVDREG – 5% VLVDREG VLVDREG + 5%

reset10
13b LVD VDDREG variation after — After POR VLVDREG – 3% VLVDREG VLVDREG + 3%
reset10

14 SMPS regulator output — — — 15 25 Ohm

resistance11
15 SMPS regulator clock frequency — After POR 1.0 1.5 — MHz

16 SMPS regulator overshoot at — GBD/GBC13 — 1.32 1.4 V

start-up12

17 SMPS maximum output current, — — — 1.0 — A

as required by SoC14

18 Voltage variation on current step — GBD/GBC13 — — 0.1 V

(20% to 80% of maximum
current with 4 usec constant
time)14

MPC5676R Microcontroller Data Sheet, Rev. 4

14 Freescale Semiconductor
 Electrical Characteristics

1
Nominal internal regulator output voltage is 1.27V
2
Voltage should be higher than maximum VLVD12 to avoid LVD event
3
~VDD12OUT *0.87
4
Rising VDD
5 Nominal internal regulator output voltage is 3.4V
6
Rising VDDSYN
7
~VDD33OUT *0.872
8
VDDSYN
9
Except IDD33
10
Rising VDDREG
11
Pull up to VDDREG when high, pull down to VSSREG when low.
12
Depends on external device, can be as high as 1.6V for short time (<100 usec each start-up)
13
GBD — Guaranteed By Design; GBC — Guaranteed by Characterization
14
Proper external devices required

4.5.1 Regulator Example

VDDREG

The resistor may or may

not be required.
This depends on the IPP_INA_SMPS_SEL5
allowable power dissipation of
the npn bypass transistor
device.

The bypass transistor

MUST be operated out VRCCTL MCU
of saturation region.

VDD1p2

Mandatory decoupling capacitor

network

VSS

VRCCTL capacitor: may or

may not be required
Figure 5. VRC 1.2 V LDO configuration with external bipolar

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 15
Electrical Characteristics

VDDREG

IPP_INA_SMPS_SEL5

VRCCTL

MCU

VDD1p2

Mandatory decoupling capacitor

network

VSS

No VRCCTL capacitor is allowed

Figure 6. VRC 1.2V buck SMPS LDO configuration with external MOS - Schottky diode

Table 9. VRC LDO recommended external devices

Part Name Part Type Nominal Description

NJD2873 NPN ON Semiconductor TM

Beta (Bf) From 60 to 550

Vbe From 0.4 V to 1.0 V

Vce From 0.2 V to 0.6 V depends on package / power

Capacitor 6 x 4.7 uF - 20 V Ceramic low ESR—One for each VDD pin

Capacitor 6 x 0.1 uF - 20 V Ceramic —One capacitor for each VDD pin

Capacitor 20 uF Supply decoupling cap (close to bipolar collector)

Capacitor 2.2 uF Snubber cap, required with NJD2873 (on bipolar base)

Resistor 12  Optional ESR for snubber cap

MPC5676R Microcontroller Data Sheet, Rev. 4

16 Freescale Semiconductor
 Electrical Characteristics

Table 10. VRC SMPS recommended external devices

Part Name Part Type Nominal Description

IR7353 HS nMOS + Low threshold n-MOS/Low Vf Schottky diode

Schottky

SS8P3L Schottky Low Vf Schottky diode

Vf From 0.4V to 0.6 V

SI3460 or equivalent nMOS Low threshold n-MOS

Vth Less than 2 V

Ids More than 1.5 A

Vds More than 12 V

Rdson Less than 100 Ohms

Cg Less than 5 nF

Turn on / off delay Less than 50 ns

Rise time Less than 90 ns

LQH66SN2R2M03 inductor 2.2 uH—3.2 A muRata TM shielded coil, preferred fmax > 40 MHz
C3225X7R1E106M capacitor 22 uF — 25 V TDK high capacitance ceramic SMD (on VDD close to coil)

C3225X7R1E225K capacitor 2 to 6 x 2.2 uF TDK ceramic SMD (on VDD close to MCU)
— 25 V

capacitor 6 x 0.1 uF Ceramic -One capacitor for each VDD pin

— 20 V

C3225X7R1E106M capacitor 22 uF — 25 V Supply decoupling cap—close to n-MOS drain

resistor 20 K Pull down for power n—MOS gate

4.6 Power Up/Down Sequencing

There is no power sequencing required among power sources during power up and power down in order to operate within
specification as long as the following two rules are met:
• When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.
• When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the
internal 3.3V regulator.
The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up
each VDDE/VDDEH first and then power up VDD. For power down, drop VDD to 0 V first, and then drop all VDDE/VDDEH
supplies. There is no limit on the fall time for the power supplies.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,
the state of the I/O pins during power up/down varies according to Table 11 and Table 12.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 17
Electrical Characteristics

Table 11. Power Sequence Pin States for MH and AE pads

VDD VDD33 VDDE MH Pad MH+LVDS Pads1 AE/up-down Pads

High High High Normal operation Normal operation Normal operation

— Low High Pin is tri-stated (output buffer, Outputs driven high Pull-ups enabled,
input buffer, and weak pulls pull-downs disabled
disabled)
Low High Low Output low, Outputs disabled Output low,
pin unpowered pin unpowered
Low High High Pin is tri-stated (output buffer, Outputs disabled Pull-ups enabled,
input buffer, and weak pulls pull-downs disabled
disabled)
1
MH+LVDS pads are output-only.

Table 12. Power Sequence Pin States for F and FS pads

VDD VDD33 VDDE F and FS pads

low low high Outputs drive high

low high — Outputs Disabled
high low low Outputs Disabled
high low high Outputs drive high
high high low Normal operation - except no drive current
and input buffer output is unknown.1
high high high Normal Operation
1
The pad pre-drive circuitry will function normally but since VDDE is unpowered
the outputs will not drive high even though the output pmos can be enabled.

4.6.1 Power-Up
If VDDE/VDDEH is powered up first, then a threshold detector tristates all drivers connected to VDDE/VDDEH. There is no limit
to how long after VDDE/VDDEH powers up before VDD must power up. If there are multiple VDDE/VDDEH supplies, they can
be powered up in any order. For each VDDE/VDDEH supply not powered up, the drivers in that VDDE/VDDEH segment exhibit
the characteristics described in the next paragraph.
If VDD is powered up first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that
pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current
injection specification. There is no limit to how long after VDD powers up before VDDE/VDDEH must power up.
The rise times on the power supplies are to be no faster than 25 V/millisecond.

4.6.2 Power-Down
If VDD is powered down first, then all drivers are tristated. There is no limit to how long after VDD powers down before
VDDE/VDDEH must power down.
If VDDE/VDDEH is powered down first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy
load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the
current injection specification. There is no limit to how long after VDDE/VDDEH powers down before VDD must power down.

MPC5676R Microcontroller Data Sheet, Rev. 4

18 Freescale Semiconductor
 Electrical Characteristics

There are no limits on the fall times for the power supplies.

4.6.3 Power Sequencing and POR Dependent on VDDA

During power up or down, VDDA can lag other supplies (of magnitude greater than VDDEH/2) within 1 V to prevent any
forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between VDDA and VDDEH
is more than 1 V, the following will result:
• Triggers POR (ADC monitors on VDDEH1 segment which powers the RESET pin) if the leakage current path created,
when VDDA is sufficiently low, causes sufficient voltage drop on VDDEH1 node monitored crosses low-voltage detect
level.
• If VDDA is between 0–2 V, powering all the other segments (especially VDDEH1) will not be sufficient to get the part
out of reset.
• Each VDDEH will have a leakage current to VDDA of a magnitude of ((VDDEH – VDDA – 1 V(diode drop)/200 KOhms)
up to (VDDEH/2 = VDDA + 1 V). .
• Each VDD has the same behavior; however, the leakage will be small even though there is no current limiting resistor
since VDD = 1.32 V max.

4.7 DC Electrical Specifications

Table 13. DC Electrical Specifications1

Spec Characteristic Symbol Min Max Unit

1 Core Supply Voltage (External Regulation) VDD 1.14 1.322, 3 V

1a Core Supply Voltage (Internal Regulation)4 VDD 1.08 1.32 V

2 I/O Supply Voltage (fast I/O pads) VDDE 3.0 3.62 V

3 I/O Supply Voltage (medium I/O pads) VDDEH 3.0 5.252 V

4 3.3 V I/O Buffer Voltage VDD33 3.0 3.62 V

5 Analog Supply Voltage VDDA 4.75 5.252 V

6a SRAM Standby Voltage low range VSTBY_LOW 0.955 1.2 V

6b SRAM Standby Voltage high range VSTBY_HIGH 2 6 V

7 Voltage Regulator Control Input Voltage6 VDDREG 2.77 5.52 V

8 Clock Synthesizer Operating Voltage8 VDDSYN 3.0 3.62 V

9 Fast I/O Input High Voltage VIH_F VDDE + 0.3 V

Hysteresis enabled 0.65 × VDDE
Hysteresis disabled 0.55 × VDDE

10 Fast I/O Input Low Voltage VIL_F VSS – 0.3 V

Hysteresis enabled 0.35 × VDDE
Hysteresis disabled 0.40 × VDDE

11 Medium I/O Input High Voltage VIH_S VDDEH + 0.3 V

Hysteresis enabled 0.65 × VDDEH
Hysteresis disabled 0.55 × VDDEH

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 19
Electrical Characteristics

Table 13. DC Electrical Specifications1 (continued)

Spec Characteristic Symbol Min Max Unit

12 Medium I/O Input Low Voltage VIL_S VSS – 0.3 V

Hysteresis enabled 0.35 × VDDEH
Hysteresis disabled 0.40 × VDDEH

13 Fast I/O Input Hysteresis VHYS_F 0.1 × VDDE — V

14 Medium I/O Input Hysteresis VHYS_S 0.1 × VDDEH — V

15 Analog Input Voltage VINDC VSSA – 0.1 VDDA + 0.1 V

9
16 Fast I/O Output High Voltage VOH_F 0.8 × VDDE — V

17 Medium I/O Output High Voltage10 VOH_S 0.8 × VDDEH — V

18 Fast I/O Output Low Voltage9 VOL_F — 0.2 × VDDE V

19 Medium I/O Output Low Voltage VOL_S — 0.2 × VDDEH1 V

0

0.15 × VDDEH
11

20 Load Capacitance (Fast I/O)12 CL

DSC(PCR[8:9]) = 0b00 — 10 pF
DSC(PCR[8:9]) = 0b01 — 20 pF
DSC(PCR[8:9]) = 0b10 — 30 pF
DSC(PCR[8:9]) = 0b11 — 50 pF

21 Input Capacitance (Digital Pins) CIN — 7 pF

22 Input Capacitance (Analog Pins) CIN_A — 10 pF

23 Input Capacitance (Digital and Analog Pins13) CIN_M — 12 pF

24 Operating Current 1.2 V Supplies @ fsys = 180 MHz

VDD (including VDDF current)@1.32 V IDD — 1.016 A
VSTBY14 @1.2 V and 85oC IDDSTBY — 0.10 mA
VSTBY @6.0 V and 85oC IDDSTBY6 — 0.15 mA
VDDF15 (P/E) IDDFPE — 3617 mA
VDDF15 (Read) IDDFREAD — 5017 mA
VDDF15 (RWW) IDDFRWW — 9017 mA
VDDF15 (Standby) IDDplTANDBY — 0.2017 mA
VDDF15 (Disabled) IDDFDISABLED — 0.1017 mA

25 Operating Current 3.3 V Supplies @ fsys = 180 MHz

VDD3318 IDD33 — note18 mA
VDDSYN IDDSYN — 720 mA
VFLASH19 (P/E) IDDFLASHPE — 3221 mA
VFLASH19 (Read) IDDFLASHREADS — 6.421 mA
VFLASH19 (RWW) IDDFLASHRWW — 4021 mA
VFLASH19 (Standby) IDDFLASHSTANDBY — 3.421 mA
VFLASH19 (Disabled) IDDFLASHDISABLED — 0.1021 mA

26 Operating Current 5.0 V Supplies @ fsys = 180 MHz

VDDA IDDA — 5022 mA
Analog Reference Supply Current (Transient) IREF — 1.0 mA
VDDREG IREG — 22 mA

MPC5676R Microcontroller Data Sheet, Rev. 4

20 Freescale Semiconductor
 Electrical Characteristics

Table 13. DC Electrical Specifications1 (continued)

Spec Characteristic Symbol Min Max Unit

27 Operating Current VDDE/VDDEH23 Supplies

VDDE2 IDD2 — mA
VDDEH1 IDD1 — mA
VDDEH3 IDD3 — mA
VDDEH4 IDD4 — note23 mA
VDDEH5 IDD5 — mA
VDDEH6 IDD6 — mA
VDDEH7 IDD7 — mA

28 Fast I/O Weak Pull Up/Down Current24

3.0 V–3.6 V IACT_F 42 158 A

29 Medium I/O Weak Pull Up/Down Current25 IACT_S

3.0 V–3.6 V 15 95 A
4.5 V–5.5 V 35 200 A

30 I/O Input Leakage Current26 IINACT_D –2.5 2.5 A

31 DC Injection Current (per pin) IIC –1.0 1.0 mA

32 Analog Input Current, Channel Off27, AN[0:7], AN38, IINACT_A –250 250 nA
AN39
Analog Input Current, Channel Off, all other analog –150 150 nA
inputs AN[x] = -/+ 150nA

33 VSS Differential Voltage VSS – VSSA –100 100 mV

34 Analog Reference Low Voltage VRL VSSA VSSA + 100 mV

35 VRL Differential Voltage VRL – VSSA –100 100 mV

36 Analog Reference High Voltage VRH VDDA – 100 VDDA mV

37 VREF Differential Voltage VRH – VRL 4.75 5.25 V

38 VSSSYN to VSS Differential Voltage VSSSYN – VSS –100 100 mV

C
39 Operating Temperature Range—Ambient (Packaged) TA (TL to TH) –40.0 125.0

40 Slew rate on power supply pins — — 25 V/ms

41 Weak Pull-Up/Down Resistance28,29 200 k Option RPUPD200K 130 280 k

42 Weak Pull-Up/Down Resistance28,29 100 k Option RPUPD100K 65 140 k

43 Weak Pull-Up/Down Resistance28 (5 k Option) RPUPD5K k

5 V ± 10% supply 1.4 5.2
3.3 V ± 10% supply 1.7 7.7

44 Pull-Up/Down Resistance Matching Ratios RPUPDMATCH –2.5 2.5 %

(100K/200K)
(Pull-up and pull-down resistances both enabled and
settings are equal)
1 These specifications are design targets and subject to change per device characterization.
2
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
3
2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 21
Electrical Characteristics

4
Assumed with DC load.
5
VSTBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode.
6
Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with VDDREG = 4.5 V (min).
7
2.7 V minimum operating voltage allowed during vehicle crank for system with VDDREG = 3.0 V (min). Normal operating voltage
should be either VDDREG = 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected.
8
Required to be supplied when 3.3 V regulator is disabled. See Section 4.5, “PMC/POR/LVI Electrical Specifications.”
9 I
OH_F = {12,20,30,40} mA and IOL_F = {24,40,50,65} mA for {00,01,10,11} drive mode with VDDE= 3.0 V.
10
IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDEH = 4.5 V;
IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDEH = 3.0 V
11
IOL_S= 2 mA
12
Applies to D_CLKOUT, external bus pins, and Nexus pins.
13
Applies to the FCK, SDI, SDO, and SDS_B pins.
14
VSTBY current specified at 1.0 V at a junction temperature of 85 oC. VSTBY current is 700 µA maximum at a junction
temperature of 150 oC.
15
VDDF pin is shorted to VDD on the package substrate.
16 Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization.

1.0 A based on transistor count estimate at Worst Case (wcs) process and temperature condition.
17 Typical values from the simulation.
18 Power requirements for the V
DD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on
the I/O segments. See Section 4.7.2, “I/O Pad VDD33 Current Specifications,” for information on both fast (F, FS) and medium
(MH) pads. Also refer to Table 15 for values to calculate power dissipation for specific operation.
19 VFLSH pin is shorted to V
DD33 on the package substrate.
20 This value is a target that is subject to change.
21 Typical values from the simulation.
22 These value allows a 5 V 20 mA reference to supply ADC + REF.
23 Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O

segment, and the voltage of the I/O segment. See Section 4.7.1, “I/O Pad Current Specifications,” for information on I/O pad
power. Also refer to Table 14 for values to calculate power dissipation for specific operation. The total power consumption of
an I/O segment is the sum of the individual power consumptions for each pin on the segment.
24 Absolute value of current, measured at V and V .
IL IH
25 Absolute value of current, measured at V and V .
IL IH
26 Weak pull up/down inactive. Measured at V
DDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types F and MH.
27 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each

8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types AE and AE/up-down.
28 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics.
29 When the pull-up and pull-down of the same nominal 200 k or 100 k value are both enabled, assuming no interference from

external devices, the resulting pad voltage will be 0.5*VDDEH ± 2.5%.

4.7.1 I/O Pad Current Specifications

The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power
consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from
Table 14 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency,
and load parameters that fall outside the values given in Table 14.
The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”

MPC5676R Microcontroller Data Sheet, Rev. 4

22 Freescale Semiconductor
 Electrical Characteristics

Table 14. VDDE/VDDEH I/O Pad Average DC Current1

Frequency Load2 Voltage Drive/Slew

Spec Pad Type Symbol Current (mA)
(MHz) (pF) (V) Rate Select

1 Medium IDRV_MH 50 50 5.25 11 16.0

2 20 50 5.25 01 6.3

3 3.0 50 5.25 00 1.1

4 2.0 200 5.25 00 2.4

5 Fast IDRV_FC 66 10 3.6 00 6.5

6 66 20 3.6 01 9.4

7 66 30 3.6 10 10.8

8 66 50 3.6 11 33.3

9 66 10 1.98 00 2.0

10 66 20 1.98 01 3.0

11 66 30 1.98 10 4.4

12 66 50 1.98 11 15.1

13 Fast w/ Slew IDRV_FSR 66 50 3.6 11 12.0

Control
14 50 50 3.6 10 6.2

15 33.33 50 3.6 01 4.0

16 20 50 3.6 00 2.4

17 20 200 3.6 00 8.9

1
These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.
2 All loads are lumped.

4.7.2 I/O Pad VDD33 Current Specifications

The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption
is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be
calculated from Table 15 dependent on the voltage, frequency, and load on all F type pins. The VDD33 current draw on medium
pads can be calculated from Table 15 dependent on voltage and independent on the frequency and load on all MH type pins.
Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 15.
The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 23
Electrical Characteristics

Table 15. VDD33 Pad Average DC Current1

Frequency Load2 VDD33 VDDE Drive/Slew

Spec Pad Type Symbol Current (mA)
(MHz) (pF) (V) (V) Rate Select

1 Medium I33_MH — — 3.6 5.5 — 0.0007

2 Fast I33_FC 66 10 3.6 3.6 00 0.92

3 66 20 3.6 3.6 01 1.14

4 66 30 3.6 3.6 10 1.50

5 66 50 3.6 3.6 11 2.19

6 66 10 3.6 1.98 00 0.70

7 66 20 3.6 1.98 01 0.90

8 66 30 3.6 1.98 10 1.08

9 66 50 3.6 1.98 11 1.52

10 Fast w/ I33_FSR 66 50 3.6 3.6 11 0.74

Slew
11 Control 50 50 3.6 3.6 10 0.52

12 33.33 50 3.6 3.6 01 0.36

13 20 50 3.6 3.6 00 0.19

14 20 200 3.6 3.6 00 0.19

1
These are average IDD33 for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input
pins only for the medium pads.
2 All loads are lumped.

4.7.3 LVDS Pad Specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI
module.
Table 16. DSPI LVDS Pad Specification 1, 2
(VDD33 = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH)

Spec Characteristic Symbol Min Typical Max Unit

Data Rate
1 Data Frequency fLVDSCLK — — 40 MHz
Driver Specs
2 Differential Output Voltage VOD mV
SRC=0b00 or 0b11 215 — 400
SRC=0b01 170 320
SRC=0b10 260 480
3 Common Mode Voltage (LVDS), VOS VOS 1.075 1.2 1.325 V
4 Rise/Fall Time tR or tF — — 2.5 ns
5 Delay, Z to Normal (High/Low) tDZ — — 100 ns

MPC5676R Microcontroller Data Sheet, Rev. 4

24 Freescale Semiconductor
 Electrical Characteristics

Table 16. DSPI LVDS Pad Specification 1, 2 (continued)

(VDD33 = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH)

6 Differential Skew between Positive and Negative tSkew — — 0.5 ns

LVDS Pair
I tphla – tplhb I or I tplhb – tphla I
Termination
7 Termination Resistance3 RLoad 95 100 105 ohm
8 Load — — — 32 pF
1
These are typical values that are estimated from simulation.
2
These specifications are subject to change per device characterization.
3
The termination resistance spec is not meant to specify the receiver termination requirements. They are there to establish the
measurement criteria for the specs in this table. As per the TIA/EIA-644A standard, the LVDS receiver termination resistance
can vary from 90 to 132  .

4.8 Oscillator and FMPLL Electrical Characteristics

Table 17. FMPLL Electrical Specifications1
(VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)

Spec Characteristic Symbol Min Max Unit

1 PLL Reference Frequency Range2 (Normal Mode) MHz

Crystal Reference (PLLCFG2 = 0b0) fref_crystal 8 20
Crystal Reference (PLLCFG2 = 0b1) fref_crystal 40 403
External Reference (PLLCFG2 = 0b0) fref_ext 8 20
External Reference(PLLCFG2 = 0b1) fref_ext 40 40

2 PLL Frequency 4
Enhanced Mode fPLL fvco(min)  64 fmax MHz

3 Loss of Reference Frequency5 fLOR 100 1000 kHz

4 Self Clocked Mode Frequency6 fSCM 4 16 MHz

5 PLL Lock Time7 tLPLL — <750 s

6 Duty Cycle of Reference 8, 9 tDC 40 60 %

7 Frequency un-LOCK Range fUL –4.0 4.0 % fsys

8 Frequency LOCK Range fLCK –2.0 2.0 % fsys

9 D_CLKOUT Period Jitter10, 11 Measured at fSYS Max CJitter –5 5 %fclko

Cycle-to-cycle Jitter ut

10 Peak-to-Peak Frequency Modulation Range Limit 12,13 Cmod 0 4 %fsys

(fsys Max must not be exceeded)

11 FM Depth Tolerance14 Cmod_err –0.25 0.25 %fsys

12 VCO Frequency fVCO 192 600 MHz

13 Modulation Rate Limits15 fmod 0.400 1 MHz

14 Predivider Operating Frequency fprediv 4 10 MHz

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 25
Electrical Characteristics

1
All values given are initial design targets and subject to change.
2
Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default
PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.
3
Upper tolerance of less than 1% is allowed on 40MHz crystal.
4
All internal registers retain data at 0 Hz.
5
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
6
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR. This
frequency is measured at D_CLKOUT with the divider set to divide-by-2 of the system clock. NOTE: in SCM, the PLL is running
open loop at a centercode 0x4. The MFD has no effect and the RFD is bypassed.
7
This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
8
For FlexRay operation, duty cycle requirements are higher.
9
Duty cycle can be 20–80% when PLL is used with a pre-divider greater than 1.
10
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval. D_CLKOUT divider set to divide-by-2.
11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
jitter + Cmod.
12 Modulation depth selected must not result in f value greater than the f maximum specified value.
pll pll
13 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in

control register are: 1%, 2%, 3%, and 4% peak-to-peak.

14 Depth tolerance is the programmed modulation depth ±0.25% of F . Initial design target pending silicon evaluation.
sys
15 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz

will result in reduced calibration accuracy.

Table 18. Oscillator Electrical Specifications1

(VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)

Spec Characteristic Symbol Min Max Unit

1 Crystal Mode Differential Amplitude2 Vcrystal_diff_amp | Vextal – Vxtal | — V

(Min differential voltage between EXTAL and XTAL) > 0.4 V

2 Crystal Mode: Internal Differential Amplifier Noise Vcrystal_diff_amp_nr — | Vextal – Vxtal | V

Rejection < 0.2 V

3 EXTAL Input High Voltage VIHEXT ((VDD33/2) + 0.4 V) — V

Bypass mode, External Reference

4 EXTAL Input Low Voltage VILEXT — (VDD33/2) – 0.4 V V

Bypass mode, External Reference

5 XTAL Current3 IXTAL 1 3 mA

6 Total On-chip stray capacitance on XTAL CS_XTAL — 1.5 pF

MPC5676R Microcontroller Data Sheet, Rev. 4

26 Freescale Semiconductor
 Electrical Characteristics

Table 18. Oscillator Electrical Specifications1 (continued)

(VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)

Spec Characteristic Symbol Min Max Unit

7 Total On-chip stray capacitance on EXTAL CS_EXTAL — 1.5 pF

8 Crystal manufacturer’s recommended capacitive CL See crystal spec See crystal spec pF
load

9 Discrete load capacitance to be connected to EXTAL CL_EXTAL — (2 × CL – CS_EXTA pF

4
L – CPCB_EXTAL )

10 Discrete load capacitance to be connected to XTAL CL_XTAL — (2 × CL – CS_XTAL pF

– CPCB_XTAL4)
1
All values given are initial design targets and subject to change.
2
This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In
that case, Vextal – Vxtal  400 mV criterion has to be met for oscillator’s comparator to produce output clock.
3 I
xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
4 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

4.9 eQADC Electrical Characteristics

Table 19. eQADC Conversion Specifications (Operating)

Spec Characteristic Symbol Min Max Unit

1 ADC Clock (ADCLK) Frequency fADCLK 2 16 MHz

2 Conversion Cycles CC 2 + 13 128 + 14 ADCLK cycles

3 Stop Mode Recovery Time1 TSR 10 — s

4 Resolution2 — 1.25 — mV
3
5 INL: 8 MHz ADC Clock INL8 –44 44 LSB5

6 INL: 16 MHz ADC Clock3 INL16 –84 84 LSB

7 DNL: 8 MHz ADC Clock3 DNL8 –34 34 LSB

8 DNL: 16 MHz ADC Clock3 DNL16 –34 34 LSB

9 Offset Error without Calibration OFFNC 04 1004 LSB

10 Offset Error with Calibration OFFWC –44 44 LSB

11 Full Scale Gain Error without Calibration GAINNC –1204 04 LSB

12 Full Scale Gain Error with Calibration GAINWC –44,6 44,6 LSB

13 Disruptive Input Injection Current 7, 8, 9, 10 IINJ –1 1 m

14 Incremental Error due to injection current11, 12 EINJ — +44 Counts

15 TUE value at 8 MHz 13, 14 (with calibration) TUE8 — +44,6 Counts

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 27
Electrical Characteristics

Table 19. eQADC Conversion Specifications (Operating) (continued)

Spec Characteristic Symbol Min Max Unit

16 TUE value at 16 MHz 13, 14 (with calibration) TUE16 — +8 Counts

17 Variable gain amplifier accuracy (gain=1)15 GAINVGA1 Counts17

INL, 8 MHz ADC –4 4
INL, 16 MHz ADC –8 8
DNL, 8 MHz ADC –316 316
DNL, 16 MHz ADC –316 316

18 Variable gain amplifier accuracy (gain=2)15 GAINVGA2 Counts

INL, 8 MHz ADC –5 5
INL, 16 MHz ADC –8 8
DNL, 8 MHz ADC –3 3
DNL, 16 MHz ADC –3 3

19 Variable gain amplifier accuracy (gain=4)15 GAINVGA4 Counts

INL, 8 MHz ADC –7 7
INL, 16 MHz ADC –8 8
DNL, 8 MHz ADC –4 4
DNL, 16 MHz ADC –4 4
1 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time
that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.
2 At V
RH – VRL = 5.12 V, one count = 1.25 mV without using pregain.
3 INL and DNL are tested from V
RL + 50 LSB to VRH – 50 LSB.
4 New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully

included.
5 At V
RH – VRL = 5.12 V, one LSB = 1.25 mV.
6 The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.
7 Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater

than VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions.
8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit

do not affect device reliability or cause permanent damage.

9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the
calculated values.
10 Condition applies to two adjacent pins at injection limits.
11
Performance expected with production silicon.
12 All channels have same 10 k < Rs < 100 kChannel under test has Rs = 10 k, I
INJ=IINJMAX,IINJMIN.
13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.
14 TUE does not apply to differential conversions.
15 Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or

4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated.
16 Guaranteed 10-bit mono tonicity.
17 At V
RH – VRL = 5.12 V, one LSB = 1.25 mV.

MPC5676R Microcontroller Data Sheet, Rev. 4

28 Freescale Semiconductor
 Electrical Characteristics

4.9.1 ADC Internal Resource Measurements

Table 20. Power Management Control (PMC) Specification

Spec Characteristic Symbol Min Typical Max Unit

PMC Normal Mode

1 Bandgap 0.62 V VADC145 0.59 0.62 0.65 V

ADC0 channel 145

2 Bandgap 1.2 V VADC146 1.10 1.22 1.34 V

ADC0 channel 146

3 Vreg1p2 Feedback VADC147 VDD/2.147 VDD / 2.045 VDD/1.943 V

ADC0 channel 147

4 LVD 1.2 V VADC180 VDD/1.863 VDD / 1.774 VDD/1.685 V

ADC0 channel 180

5 Vreg3p3 Feedback VADC181 Vreg3p3 / Vreg3p3 / 5.460 Vreg3p3 / 5.187 V

ADC0 channel 181 5.733—

6 LVD 3.3 V VADC182 Vreg3p3 / 4.996 Vreg3p3 / 4.758 Vreg3p3 / 4.520 V

ADC0 channel 182

7 LVD 5.0 V VADC183 VDDREG / 4.996 VDDREG / 4.520 V

ADC0 channel 183 VDDREG / 7.384 VDDREG / 6.680
— LDO mode VDDREG / 4.758
— SMPS mode VDDREG/7.032

Table 21. Standby RAM Regulator Electrical Specifications

Spec Characteristic Symbol Min Typ Max Unit

Normal Mode

1 Standby Regulator Output VADC194 — 1.2 — V

ADC1 channel 194

2 Standby Source Bias VADC195 150 — 360 mV

ADC1 channel 195

Table 22. ADC Band Gap Reference / LVI Electrical Specifications

Spec Characteristic Symbol Min Typ Max Unit

1 4.75 LVD (from VDDA) VADC196 — 4.75 — V

ADC1 channel 196

2 ADC Bandgap VADC45 — 1.220 — V

ADC0 channel 45
ADC1 channel 45

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 29
Electrical Characteristics

Table 23. Temperature Sensor Electrical Specifications

Spec Characteristic Symbol Min Typ Max Unit

1 Slope VSADC128 1 — 5.8 — mV/ C

–40 C to 100 C ±1.0 C
100 C to 150 C ±1.6 C
ADC0 channel 128
ADC1 channel 128

2 Accuracy — -20 — +20 C

–40 C to 150 C
ADC0 channel 128
ADC1 channel 128
1
Slope is the measured voltage change per °C.

4.10 C90 Flash Memory Electrical Characteristics

Table 24. Flash Program and Erase Specifications (Pending Si characterization)

Initial Lifetime
Spec Characteristic Symbol Typ1 Unit
Max2 Max3

1 Double Word (64 bits) Program Time4 tdwprogram 38 — 500 s

2 Page (128 bits) Program Time4 tpprogram 45 160 500 s

3 16 KB Block Pre-program and Erase Time t16kpperase 270 1000 5000 ms

4 48 KB Block Pre-program and Erase Time t48kpperase 625 1500 5000 ms

5 64 KB Block Pre-program and Erase Time t64kpperase 800 1800 5000 ms

6 128 KB Block Pre-program and Erase Time t128kpperase 1500 2600 7500 ms

7 256 KB Block Pre-program and Erase Time t256kpperase 3000 5200 15000 ms
1
Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 oC. These values are characterized, but not tested.
2 Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase

cycles, nominal supply values and operation at 25 oC. These values are verified at production test.
3 Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values

are characterized, but not tested.

4 Program times are actual hardware programming times and do not include software overhead.

NOTE
The low, mid, and high address blocks of the flash arrays are erased (all bits set to 1) before
leaving the factory.

MPC5676R Microcontroller Data Sheet, Rev. 4

30 Freescale Semiconductor
 Electrical Characteristics

Table 25. Flash Memory AC Timing Specifications1

Value
Symbol Parameter Unit
Min Typ Max

TRES Time from clearing the MCR-ESUS or PSUS bit with EHV = 1 — — 100 ns
until DONE goes low

TDONE Time from 0 to 1 transition on the MCR-EHV bit initiating a — — 5 ns

program/erase until the MCR-DONE bit is cleared

TPSRT Time between program suspend resume and the next program 100 s
suspend request.2 — —

TESRT Time between erase suspend resume and the next erase 10 — — ms
suspend request.3
1
This parameter is guaranteed by characterization before qualification rather than 100% tested.
2
Repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by
completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish (MCR[DONE] = 1 during Program
operation). The minimum time between suspends to ensure this does notoccur is TPSRT.
3 If Erase suspend rate is less than T
ESRT, an increase of slope voltage ramp occurs during erase pulse. This improves erase
time but reduces cycling figure due to overstress.

Table 26. Flash EEPROM Module Life

Spec Characteristic Symbol Min Typical1 Unit

1 Number of Program/Erase cycles per block for 16 KB and 64 P/E 100,000 — cycles
KB blocks over the operating temperature range (TJ)

2 Number of Program/Erase cycles per block for 128 KB and P/E 1,000 100,000 cycles
256 KB blocks over the operating temperature range (TJ)

3 Minimum Data Retention at 85 °C ambient temperature2 Retention years

Blocks with 0–1,000 P/E cycles 20 —
Blocks with 1,001–10,000 P/E cycles 10
Blocks with 10,001–100,000 P/E cycles 1–5
1 Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional
information on the NXP definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for
Nonvolatile Memory.
2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 31
Electrical Characteristics

Table 27. BIUCR1/BIUCR3 Settings

Maximum Frequency
(MHz)
APC =
Spec WWSC DPFEN1 IPFEN1 PFLIM2 BFEN3
RWSC
Core Platform
fsys fplatf

1 180 MHz 90 MHz 0b010 0b01 0b0 0b0 0b00 0b0

0b1 0b1 0b01 0b1
0b1x

Default setting after reset: 0b111 0b11 0b00 0b00 0b00 0b0
1
For maximum flash performance, set to 0b1.
2
For maximum flash performance, set to 0b10.
3
For maximum flash performance, set to 0b1.

4.11 AC Specifications

4.11.1 Clocking Modes

There are two main modes of operating frequency settings:
• Double 2:1 (Core:Platform) Mode—the core is running at the system frequency setting while the platform and eTPU
are running at half the core frequency (system frequency divided by 2).
• eTPU Mode—the core and eTPU are running at the system frequency setting while the platform is running at half the
core frequency (system frequency divided by 2).
Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings.
Table 28. MPC5676R Block Operating Frequency1, 2

Double Mode Freq eTPU Mode Freq

Spec Blocks Symbol
(MHz) (MHz)

1 Cores fsys fsys = 180 fsys = 180

(tcycsys = 1/fsys)
2 Platform fplatf fsys / 2 fsys / 2
(tcyc = 1/fplatf)
3 eTPU feTPU fsys / 2 fsys
4 EBI febi fsys / 4 fsys / 4
1 The values in the table are specified at VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.5 V to 5.5 V, VDD33 and
VDDSYN = 3.0 V to 3.6 V, TA = TL to TH.
2 Up to the maximum frequency rating of the device (refer to Table 1). The f
sys speed is the nominal maximum frequency.

MPC5676R Microcontroller Data Sheet, Rev. 4

32 Freescale Semiconductor
 Electrical Characteristics

4.11.2 Pad AC Specifications

Table 29. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V)1

Out Delay2,4 Rise/Fall3,4 Load Drive

Spec Pad SRC/DSC
L  H/H  L (ns) (ns) (pF)
1 Medium5 00 152/165 70/74 50
2 205/220 96/96 200
3 01 28/34 12/15 50
4 52/59 28/31 200
5 11 12/12 5.3/5.9 50
6 32/32 22/22 200
7 Fast6 00 10
8 01 20
2.5 1.2
9 10 30
10 11 50
11 Fast with Slew Rate 00 40/40 16/16 50
12 50/50 21/21 200
13 01 13/13 5/5 50
14 19/19 8/8 200
15 10 8/8 2.4/2.4 50
16 12/12 5/5 200
17 11 5/5 1.1/1/1 50
18 8/8 2.6 200
19 Pull Up/Down (3.6 V max) — — 7500 50
20 Pull Up/Down (5.25 V max) — 6000 5000/5000 50

1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH.
2
This parameter is supplied for reference and is not guaranteed by design and not tested.
3 This parameter is guaranteed by characterization before qualification rather than 100% tested.
4
Delay and rise/fall are measured to 20% or 80% of the respective signal.
5
Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock.
6 Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock.
Table 30. Derated Pad AC Specifications (VDDEH = 3.3 V)1

Out Delay2,3 Rise/Fall4,3 Load Drive

Spec Pad SRC/DSC
L  H/H  L (ns) (ns) (pF)

1 Medium5 00 200/210 86/86 50

2 270/285 120/120 200

3 01 37/45 15.5/19 50

4 69/82 38/43 200

5 11 18/17 7.6/8.5 50

6 46/49 30/34 200

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 33
Electrical Characteristics

1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH.
2
This parameter is supplied for reference and is not guaranteed by design and not tested.
3
Delay and rise/fall are measured to 20% or 80% of the respective signal.
4
This parameter is guaranteed by characterization before qualification rather than 100% tested.
5
Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock.

VDDEn / 2

Pad VDDEHn / 2
Data Input
Rising Falling
Edge Edge
Output Output
Delay Delay
VOH

Pad VOL
Output

Figure 7. Pad Output Delay

4.12 AC Timing

4.12.1 Generic Timing Diagrams

The generic timing diagrams in Figure 8 and Figure 9 apply to all I/O pins with pad types F and MH. See Table 39 for the pad
type for each pin.

MPC5676R Microcontroller Data Sheet, Rev. 4

34 Freescale Semiconductor
 Electrical Characteristics

D_CLKOUT VDDE / 2

A
B

I/O Outputs VDDEn / 2

VDDEHn / 2

A – Maximum Output Delay Time B – Minimum Output Hold Time

Figure 8. Generic Output Delay/Hold Timing

D_CLKOUT VDDE / 2

B
A

I/O Inputs VDDEn / 2

VDDEHn / 2

A – Minimum Input Setup Time B – Minimum Input Hold Time

Figure 9. Generic Input Setup/Hold Timing

4.12.2 Reset and Configuration Pin Timing

Table 31. Reset and Configuration Pin Timing1

Spec Characteristic Symbol Min Max Unit

1 RESET Pulse Width tRPW 10 — tcyc2

2 RESET Glitch Detect Pulse Width tGPW 2 — tcyc2

3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid tRCSU 10 — tcyc2

4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid tRCH 0 — tcyc2

1
Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA = TL to TH.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 35
Electrical Characteristics

2
See Notes on tcyc on Table 28.

RESET 1

RSTOUT

PLLCFG
BOOTCFG
WKPCFG

Figure 10. Reset and Configuration Pin Timing

4.12.3 IEEE 1149.1 Interface Timing

Table 32. JTAG Pin AC Electrical Characteristics1

Spec Characteristic Symbol Min Max Unit

1 TCK Cycle Time tJCYC 100 — ns

2 TCK Clock Pulse Width (Measured at VDDE / 2) tJDC 40 60 ns

3 TCK Rise and Fall Times (40%–70%) tTCKRISE — 3 ns

4 TMS, TDI Data Setup Time tTMSS, tTDIS 5 — ns

5 TMS, TDI Data Hold Time tTMSH, tTDIH 25 — ns

6 TCK Low to TDO Data Valid tTDOV — 10 ns

7 TCK Low to TDO Data Invalid tTDOI 0 — ns

8 TCK Low to TDO High Impedance tTDOHZ — 20 ns

9 JCOMP Assertion Time tJCMPPW 100 — ns

10 JCOMP Setup Time to TCK Low tJCMPS 40 — ns

11 TCK Falling Edge to Output Valid tBSDV — 50 ns

MPC5676R Microcontroller Data Sheet, Rev. 4

36 Freescale Semiconductor
 Electrical Characteristics

Table 32. JTAG Pin AC Electrical Characteristics1 (continued)

Spec Characteristic Symbol Min Max Unit

12 TCK Falling Edge to Output Valid out of High Impedance tBSDVZ — 50 ns

13 TCK Falling Edge to Output High Impedance tBSDHZ — 50 ns

14 Boundary Scan Input Valid to TCK Rising Edge tBSDST 50 — ns

15 TCK Rising Edge to Boundary Scan Input Invalid tBSDHT 50 — ns

1
JTAG timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and
CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 33 for
functional specifications.

TCK

2 2
3

1 3

Figure 11. JTAG Test Clock Input Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 37
Electrical Characteristics

TCK

TMS, TDI

7 8

TDO

Figure 12. JTAG Test Access Port Timing

TCK

10
JCOMP

Figure 13. JTAG JCOMP Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

38 Freescale Semiconductor
 Electrical Characteristics

TCK

11 13

Output
Signals

12

Output
Signals

14
15

Input
Signals

Figure 14. JTAG Boundary Scan Timing

4.12.4 Nexus Timing

Table 33. Nexus Debug Port Timing1

Spec Characteristic Symbol Min Max Unit

1 MCKO Cycle Time tMCYC 22 8 tCYC

2 MCKO Duty Cycle tMDC 40 60 %
3 MCKO Low to MDO Data Valid3 tMDOV –0.1 0.2 tMCYC
4 MCKO Low to MSEO Data Valid3 tMSEOV –0.1 0.2 tMCYC
5 MCKO Low to EVTO Data Valid3 tEVTOV –0.1 0.2 tMCYC
6 EVTI Pulse Width tEVTIPW 4.0 — tTCYC
7 EVTO Pulse Width tEVTOPW 1 — tMCYC
8 TCK Cycle Time tTCYC 44 — tCYC
9 TCK Duty Cycle tTDC 40 60 %
10 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8 — ns

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 39
Electrical Characteristics

Table 33. Nexus Debug Port Timing1 (continued)

Spec Characteristic Symbol Min Max Unit

11 TDI, TMS Data Hold Time TNTDIH, tNTMSH 5 — ns

12 TCK Low to TDO Data Valid tNTDOV 0 10 ns
13 RDY Valid to MCKO 5
— — — —
14 TDO hold time after TCLK low tNTDOH 1 — ns
1
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified
at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with
DSC = 0b10.
2
The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending
on the system frequency, not to exceed maximum Nexus AUX port frequency.
3
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
4
Lower frequency is required to be fully compliant to standard.
5
The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.

MCKO

3
4
5
MDO
MSEO Output Data Valid
EVTO

6
EVTI

Figure 15. Nexus Timings

MPC5676R Microcontroller Data Sheet, Rev. 4

40 Freescale Semiconductor
 Electrical Characteristics

TCK

10

11

TMS, TDI

14
12

TDO

Figure 16. Nexus TCK, TDI, TMS, TDO Timing

4.12.5 External Bus Interface (EBI) Timing

Table 34. Bus Operation Timing 1

66 MHz (Ext. Bus Freq)2 3

Spec Characteristic Symbol Unit Notes
Min Max
1 D_CLKOUT Period tC 15.2 — ns Signals are measured at 50% VDDE.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 41
Electrical Characteristics

Table 34. Bus Operation Timing 1 (continued)

66 MHz (Ext. Bus Freq)2 3

Spec Characteristic Symbol Unit Notes
Min Max
2 D_CLKOUT Duty Cycle tCDC 45% 55% tC
3 D_CLKOUT Rise Time tCRT — —4 ns
4 D_CLKOUT Fall Time tCFT — —4 ns
5 D_CLKOUT Posedge to Output tCOH 1.0/1.5 — ns Hold time selectable via
Signal Invalid or High Z (Hold Time) SIU_ECCR[EBTS] bit:
EBTS = 0: 1.0 ns
D_ADD[9:30] EBTS = 1: 1.5 ns
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
6 D_CLKOUT Posedge to Output tCOV — 8.5/9.0 ns Output valid time selectable via
Signal Valid (Output Delay) SIU_ECCR[EBTS] bit:
EBTS = 0: 8.5 ns
D_ADD[9:30] EBTS = 1: 9.0 ns
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
7 Input Signal Valid to D_CLKOUT tCIS 5.0/4.5 — ns Input setup time selectable via
Posedge (Setup Time) SIU_ECCR[EBTS] bit:
EBTS = 0; 5.0ns
D_ADD[9:30] EBTS = 1; 4.5ns
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
8 D_CLKOUT Posedge to Input tCIH 1.0 — ns
Signal Invalid (Hold Time)

D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
9 D_ALE Pulse Width tAPW 6.5 — ns The timing is for Asynchronous
external memory system.
10 D_ALE Negated to Address Invalid tAAI 2.0/1.0 5 — ns The timing is for Asynchronous
external memory system.
ALE is measured at 50% of VDDE.

MPC5676R Microcontroller Data Sheet, Rev. 4

42 Freescale Semiconductor
 Electrical Characteristics

1
EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and
CL = 30 pF with DSC = 0b10.
2
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
3
Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency.
The maximum external bus frequency is 66 MHz.
4 Refer to Fast pad timing in Table 29 and Table 30.
5
ALE hold time spec is temperature dependant. 1.0ns spec applies for temperature range -40 to 0 C. 2.0ns spec applies to
temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit.

VOH_F
VDDE / 2
VOL_F
D_CLKOUT

3 2

4
1

Figure 17. D_CLKOUT Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 43
Electrical Characteristics

D_CLKOUT VDDE / 2

6
5

Output
VDDE / 2
Bus

6
5

Output VDDE / 2
Signal

Output
Signal VDDE / 2

Figure 18. Synchronous Output Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

44 Freescale Semiconductor
 Electrical Characteristics

D_CLKOUT
VDDE / 2

Input
VDDE / 2
Bus

Input
Signal VDDE / 2

Figure 19. Synchronous Input Timing

ipg_clk

D_CLKOUT

D_ALE

D_TS

D_ADD/D_DAT ADDR DATA

10

Figure 20. ALE Signal Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 45
Electrical Characteristics

4.12.6 External Interrupt Timing (IRQ Pin)

Table 35. External Interrupt Timing1

Spec Characteristic Symbol Min Max Unit

1 IRQ Pulse Width Low tIPWL 3 — tcyc2
2 IRQ Pulse Width High tIPWH 3 — tcyc2
3
3 IRQ Edge to Edge Time tICYC 6 — tcyc2
1
IRQ timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL
to TH.
2
See Notes on tcyc Table 28.
3 Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

IRQ

1 2

Figure 21. External Interrupt Timing

4.12.7 eTPU Timing

Table 36. eTPU Timing1

Spec Characteristic Symbol Min Max Unit

1 eTPU Input Channel Pulse Width tICPW 4 — tcyc2
2 eTPU Output Channel Pulse Width tOCPW 13 — tcyc2
1 eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH,
and CL = 200 pF with SRC = 0b00.
2 See Notes on t
cyc Table 28.
3 This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

MPC5676R Microcontroller Data Sheet, Rev. 4

46 Freescale Semiconductor
 Electrical Characteristics

eTPU Input
and TCRCLK

eTPU
Output

Figure 22. eTPU Timing

4.12.8 eMIOS Timing

Table 37. eMIOS Timing1

Spec Characteristic Symbol Min Max Unit

1 eMIOS Input Pulse Width tMIPW 4 — tcyc2
2 eMIOS Output Pulse Width tMOPW 13 — tcyc2
1 eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH,
and CL = 50 pF with SRC = 0b00.
2
See Notes on tcyc on Table 28.
3 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 47
Electrical Characteristics

eMIOS Input

eMIOS
Output

Figure 23. eMIOS Timing

4.12.9 DSPI Timing

Table 38. DSPI Timing1,2

Peripheral Bus Freq:

92 MHz
Spec Characteristic Symbol Unit
Min Max

1 DSPI Cycle Time3, 4 tSCK 23.8 1800 ns

Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)

2 PCS to SCK Delay5 tCSC 12 — ns

3 After SCK Delay6 tASC 12 — ns

4 SCK Duty Cycle tSDC 0.4 * tSCK 0.6 * tSCK ns

5 Slave Access Time tA — 25 ns

(SS active to SOUT valid)

6 Slave SOUT Disable Time tDIS — 25 ns

(SS inactive to SOUT High-Z or invalid)

7 PCSx to PCSS time tPCSC 4 — ns

8 PCSS to PCSx time tPASC 5 — ns

MPC5676R Microcontroller Data Sheet, Rev. 4

48 Freescale Semiconductor
 Electrical Characteristics

Table 38. DSPI Timing1,2 (continued)

Peripheral Bus Freq:

92 MHz
Spec Characteristic Symbol Unit
Min Max

9 Data Setup Time for Inputs tSUI

Master (MTFE = 0) 27 — ns
Slave 10 — ns
Master (MTFE = 1, CPHA = 0)7 7 — ns
Master (MTFE = 1, CPHA = 1) 27 — ns

10 Data Hold Time for Inputs tHI

Master (MTFE = 0) –3 — ns
Slave 7 — ns
Master (MTFE = 1, CPHA = 0)7 12 — ns
Master (MTFE = 1, CPHA = 1) –3 — ns

11 Data Valid (after SCK edge) tSUO

Master (MTFE = 0) — 10 ns
Slave — 30 ns
Master (MTFE = 1, CPHA = 0) — 20 ns
Master (MTFE = 1, CPHA = 1) — 10 ns
Master (LVDS) — 5 ns

12 Data Hold Time for Outputs tHO

Master (MTFE = 0) –6 — ns
Slave 2.5 — ns
Master (MTFE = 1, CPHA = 0) 3 — ns
Master (MTFE = 1, CPHA = 1) –7 — ns
Master (LVDS) –5 — ns
1
DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA = TL to TH
2 Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed allowed including
frequency modulation (FM).
3
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two devices communicating over a DSPI link.
4
The actual minimum SCK cycle time is limited by pad performance.
5 The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
6
The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
7
This number is calculated assuming the SMPL_PT bit-field in DSPI_MCR is set to 0b10.

The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.
DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high
speed operation.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 49
Electrical Characteristics

2 3

PCSx

4 1

SCK Output
(CPOL = 0)
4

SCK Output
(CPOL = 1)
10
9

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Figure 24. DSPI Classic SPI Timing — Master, CPHA = 0

2 3

PCSx

4 1
SCK Output
(CPOL=0)
4
10

SCK Output
(CPOL=1)

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Figure 25. DSPI Classic SPI Timing — Master, CPHA = 1

MPC5676R Microcontroller Data Sheet, Rev. 4

50 Freescale Semiconductor
 Electrical Characteristics

3
2
SS

1
SCK Input 4
(CPOL = 0)

4
SCK Input
(CPOL = 1)

5
12 11 6

SOUT First Data Data Last Data

9
10

SIN First Data Data Last Data

Figure 26. DSPI Classic SPI Timing — Slave, CPHA = 0

3
2
SS

SCK Input 4
(CPOL = 0)

SCK Input
(CPOL = 1)
11
5 6
12

SOUT First Data Data Last Data

9
10
SIN First Data Data Last Data

Figure 27. DSPI Classic SPI Timing — Slave, CPHA = 1

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 51
Electrical Characteristics

3
PCSx

4 1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)

9 10

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Figure 28. DSPI Modified Transfer Format Timing — Master, CPHA = 0

PCSx

1
4
2
SCK Output
(CPOL = 0)

4
SCK Output
(CPOL = 1)
10
9

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Figure 29. DSPI Modified Transfer Format Timing — Master, CPHA = 1

MPC5676R Microcontroller Data Sheet, Rev. 4

52 Freescale Semiconductor
 Electrical Characteristics

3
2
SS

SCK Input
(CPOL = 0)
4 4

SCK Input
(CPOL = 1)
11 12 6
5

SOUT First Data Data Last Data

9 10

SIN First Data Data Last Data

Figure 30. DSPI Modified Transfer Format Timing — Slave, CPHA = 0

3
2
SS

1
SCK Input
(CPOL = 0)

4 4

SCK Input
(CPOL = 1)
11
5 6
12

SOUT First Data Data Last Data

9
10
SIN First Data Data Last Data

Figure 31. DSPI Modified Transfer Format Timing — Slave, CPHA = 1

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 53
Electrical Characteristics

7 8

PCSS

PCSx

Figure 32. DSPI PCS Strobe (PCSS) Timing

MPC5676R Microcontroller Data Sheet, Rev. 4

54 Freescale Semiconductor
 Package Information

5 Package Information
5.1 416-Pin Package
The package drawings of the 416-pin TEPBGA package are shown in Figure 33 and Figure 34.

Figure 33. 416 TEPBGA Package (1 of 2)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 55
Package Information

Figure 34. 416 TEPBGA Package (2 of 2)

MPC5676R Microcontroller Data Sheet, Rev. 4

56 Freescale Semiconductor
 Package Information

5.2 516-Pin Package

The package drawings of the 516-pin TEPBGA package are shown in Figure 35 and Figure 36.

Figure 35. 516 TEPBGA Package (1 of 2)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 57
Package Information

Figure 36. 516 TEPBGA Package (2 of 2)

MPC5676R Microcontroller Data Sheet, Rev. 4

58 Freescale Semiconductor
 Product Documentation

6 Product Documentation
This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these
types are available at: http://www.nxp.com.
The following documents are required for a complete description of the device and are necessary to design properly with the
parts:
• MPC5676R RM Microprocessor Reference Manual (document number MPC5676RRM)

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 59
 Appendix A Signal Properties and Muxing
Freescale Semiconductor

The following table shows the signals properties for each pin on the MPC5676R. For each port pin that has an associated SIU_PCRn register to control its pin
properties, the supported functions column lists the functions associated with the programming of the SIU_PCRn[PA] bit in the order: Primary function (P),
Function 2 (F2), Function 3 (F3), and GPIO (G). See Figure 37.
U

Table 2. Signal Properties and Muxing Summar

P/
GPIO/ F/ Pad
PCR1 Signal Name2 G Function3 Function Summary I/O Type
Primary Functions
are listed First 113 TCRCLKA_IRQ7_GPIO113 P TCRCLKA eTPU A TCR clock I 5V M
MPC5676R Microcontroller Data Sheet, Rev. 4

Secondary Functions A1 IRQ7 External interrupt request I

are alternate functions
A2 — — —

GPIO Functions are G GPIO113 GPIO I/O

listed Last

Function not implemented on this device

Figure 37. Supported Functions Example

Table 39. Signal Properties and Muxing Summary

GPIO/PCR1

Package

Pad Type5
Direction

Voltage6
State
P/A/G3

State during Location

Signal Name2 Function4 Function Summary after
RESET7
RESET8

416

516
eTPU_A

113 TCRCLKA_IRQ7_ P TCRCLKA eTPU A TCR clock I MH VDDEH1 —/Up —/Up L1 K4

GPIO113
A1 IRQ7 External interrupt request I
A2 — — —
G GPIO113 GPIO I/O

114 ETPUA0_ETPUA12_ P ETPUA0 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG L2 L6

GPIO114
A1 ETPUA12 eTPU A channel (output only) O
A2 — — —
G GPIO114 GPIO I/O
60
 Table 39. Signal Properties and Muxing Summary (continued)
61

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
115 ETPUA1_ETPUA13_ P ETPUA1 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG L3 J1
GPIO115
A1 ETPUA13 eTPU A channel (output only) O
A2 — — —
G GPIO115 GPIO I/O

116 ETPUA2_ETPUA14_ P ETPUA2 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG L4 J2

GPIO116
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 ETPUA14 eTPU A channel (output only) O

A2 — — —
G GPIO116 GPIO I/O

117 ETPUA3_ETPUA15_ P ETPUA3 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K1 H4

GPIO117
A1 ETPUA15 eTPU A channel (output only) O
A2 — — —
G GPIO117 GPIO I/O

118 ETPUA4_ETPUA16_ P ETPUA4 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K2 J4

GPIO118
A1 ETPUA16 eTPU A channel (output only) O
A2 — — —
G GPIO118 GPIO I/O
119 ETPUA5_ETPUA17_ P ETPUA5 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K3 H1
GPIO119
A1 ETPUA17 eTPU A channel (output only) O
A2 — — —
G GPIO119 GPIO I/O

120 ETPUA6_ETPUA18_ P ETPUA6 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K4 K5

Freescale Semiconductor

GPIO120
A1 ETPUA18 eTPU A channel (output only) O
A2 — — —
G GPIO120 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
121 ETPUA7_ETPUA19_ P ETPUA7 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J1 H2
GPIO121
A1 ETPUA19 eTPU A channel (output only) O
A2 — — —
G GPIO121 GPIO I/O

122 ETPUA8_ETPUA20_ P ETPUA8 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J2 H3

GPIO122
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 ETPUA20 eTPU A channel (output only) O

A2 — — —
G GPIO122 GPIO I/O

123 ETPUA9_ETPUA21_ P ETPUA9 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J3 J3

GPIO123
A1 ETPUA21 eTPU A channel (output only) O
A2 — — —
G GPIO123 GPIO I/O

124 ETPUA10_ETPUA22_ P ETPUA10 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J4 K6

GPIO124
A1 ETPUA22 eTPU A channel (output only) O
A2 — — —
G GPIO124 GPIO I/O
125 ETPUA11_ETPUA23_ P ETPUA11 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H1 G1
GPIO125
A1 ETPUA23 eTPU A channel (output only) O
A2 — — —
G GPIO125 GPIO I/O

126 ETPUA12_PCSB1_ P ETPUA12 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H2 J5

GPIO126
A1 PCSB1 DSPI B peripheral chip select O
A2 — — —
G GPIO126 GPIO I/O
62
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
127 ETPUA13_PCSB3_ P ETPUA13 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H4 G2
GPIO127
A1 PCSB3 DSPI B peripheral chip select O
A2 — — —
G GPIO127 GPIO I/O

128 ETPUA14_PCSB4_ P ETPUA14 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H3 H5

GPIO128
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 PCSB4 DSPI B peripheral chip select O

A2 — — —
G GPIO128 GPIO I/O

129 ETPUA15_PCSB5_ P ETPUA15 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G1 G3

GPIO129
A1 PCSB5 DSPI B peripheral chip select O
A2 — — —
G GPIO129 GPIO I/O

130 ETPUA16_PCSD1_ P ETPUA16 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G2 H6

GPIO130
A1 PCSD1 DSPI D peripheral chip select O
A2 — — —
G GPIO130 GPIO I/O
131 ETPUA17_PCSD2_ P ETPUA17 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G3 G4
GPIO131
A1 PCSD2 DSPI D peripheral chip select O
A2 — — —
G GPIO131 GPIO I/O

132 ETPUA18_PCSD3_ P ETPUA18 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G4 G5

GPIO132
A1 PCSD3 DSPI D peripheral chip select O
A2 — — —
G GPIO132 GPIO I/O
63
 Table 39. Signal Properties and Muxing Summary (continued)
64

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
133 ETPUA19_PCSD4_ P ETPUA19 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F1 F1
GPIO133
A1 PCSD4 DSPI D peripheral chip select O
A2 — — —
G GPIO133 GPIO I/O

134 ETPUA20_IRQ8_ P ETPUA20 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F2 F2

GPIO134
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 IRQ8 External interrupt request I

A2 — — —
G GPIO134 GPIO I/O

135 ETPUA21_IRQ9_ P ETPUA21 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F3 F3

GPIO135
A1 IRQ9 External interrupt request I
A2 — — —
G GPIO135 GPIO I/O

136 ETPUA22_IRQ10_ P ETPUA22 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F4 F4

GPIO136
A1 IRQ10 External interrupt request I
A2 — — —
G GPIO136 GPIO I/O
137 ETPUA23_IRQ11_ P ETPUA23 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E1 E1
GPIO137
A1 IRQ11 External interrupt request I
A2 — — —
G GPIO137 GPIO I/O

138 ETPUA24_IRQ12_ P ETPUA24 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E2 E2

Freescale Semiconductor

GPIO138
A1 IRQ12 External interrupt request I
A2 — — —
G GPIO138 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
139 ETPUA25_IRQ13_ P ETPUA25 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E3 E3
GPIO139
A1 IRQ13 External interrupt request I
A2 — — —
G GPIO139 GPIO I/O

140 ETPUA26_IRQ14_ P ETPUA26 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E4 E4

GPIO140
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 IRQ14 External interrupt request I

A2 — — —
G GPIO140 GPIO I/O

141 ETPUA27_IRQ15_ P ETPUA27 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D1 D1

GPIO141
A1 IRQ15 External interrupt request I
A2 — — —
G GPIO141 GPIO I/O

142 ETPUA28_PCSC1_ P ETPUA28 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D2 D2

GPIO142
A1 PCSC1 DSPI C peripheral chip select O
A2 — — —
G GPIO142 GPIO I/O
143 ETPUA29_PCSC2_ P ETPUA29 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D3 D3
GPIO143
A1 PCSC2 DSPI C peripheral chip select O
A2 — — —
G GPIO143 GPIO I/O

144 ETPUA30_PCSC3_ P ETPUA30 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG C1 C1

GPIO144
A1 PCSC3 DSPI C peripheral chip select O
A2 — — —
G GPIO144 GPIO I/O
65
 Table 39. Signal Properties and Muxing Summary (continued)
66

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
145 ETPUA31_PCSC4_ P ETPUA31 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG C2 C2
GPIO145
A1 PCSC4 DSPI C peripheral chip select O
A2 — — —
G GPIO145 GPIO I/O

eTPU_B
MPC5676R Microcontroller Data Sheet, Rev. 4

146 TCRCLKB_IRQ6_ P TCRCLKB eTPU B TCR clock I MH VDDEH6 —/Up —/Up T23 V25
GPIO146
A1 IRQ6 External interrupt request I
A2 — — —
G GPIO146 GPIO I/O

147 ETPUB0_ETPUB16_ P ETPUB0 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T24 V26
GPIO147
A1 ETPUB16 eTPU B channel (output only) O
A2 — — —
G GPIO147 GPIO I/O

148 ETPUB1_ETPUB17_ P ETPUB1 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T25 U22
GPIO148
A1 ETPUB17 eTPU B channel (output only) O
A2 — — —
G GPIO148 GPIO I/O
149 ETPUB2_ETPUB18_ P ETPUB2 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T26 U23
GPIO149
A1 ETPUB18 eTPU B channel (output only) O
A2 — — —
G GPIO149 GPIO I/O
Freescale Semiconductor

150 ETPUB3_ETPUB19_ P ETPUB3 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R23 T22
GPIO150
A1 ETPUB19 eTPU B channel (output only) O
A2 — — —
G GPIO150 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
151 ETPUB4_ETPUB20_ P ETPUB4 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R24 U24
GPIO151
A1 ETPUB20 eTPU B channel (output only) O
A2 — — —
G GPIO151 GPIO I/O

152 ETPUB5_ETPUB21_ P ETPUB5 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R25 U25
GPIO152
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 ETPUB21 eTPU B channel (output only) O

A2 — — —
G GPIO152 GPIO I/O

153 ETPUB6_ETPUB22_ P ETPUB6 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R26 U26
GPIO153
A1 ETPUB22 eTPU B channel (output only) O
A2 — — —
G GPIO153 GPIO I/O

154 ETPUB7_ETPUB23_ P ETPUB7 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P23 T23
GPIO154
A1 ETPUB23 eTPU B channel (output only) O
A2 — — —
G GPIO154 GPIO I/O
155 ETPUB8_ETPUB24_ P ETPUB8 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P24 T24
GPIO155
A1 ETPUB24 eTPU B channel (output only) O
A2 — — —
G GPIO155 GPIO I/O

156 ETPUB9_ETPUB25_ P ETPUB9 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P25 R22
GPIO156
A1 ETPUB25 eTPU B channel (output only) O
A2 — — —
G GPIO156 GPIO I/O
67
 Table 39. Signal Properties and Muxing Summary (continued)
68

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
157 ETPUB10_ETPUB26_ P ETPUB10 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P26 T25
GPIO157
A1 ETPUB26 eTPU B channel (output only) O
A2 — — —
G GPIO157 GPIO I/O

158 ETPUB11_ETPUB27_ P ETPUB11 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N24 T26
GPIO158
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 ETPUB27 eTPU B channel (output only) O

A2 — — —
G GPIO158 GPIO I/O

159 ETPUB12_ETPUB28_ P ETPUB12 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N25 R23
GPIO159
A1 ETPUB28 eTPU B channel (output only) O
A2 — — —
G GPIO159 GPIO I/O

160 ETPUB13_ETPUB29_ P ETPUB13 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N26 P22
GPIO160
A1 ETPUB29 eTPU B channel (output only) O
A2 — — —
G GPIO160 GPIO I/O
161 ETPUB14_ETPUB30_ P ETPUB14 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M25 R24
GPIO161
A1 ETPUB30 eTPU B channel (output only) O
A2 — — —
G GPIO161 GPIO I/O

162 ETPUB15_ETPUB31_ P ETPUB15 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M24 R25
Freescale Semiconductor

GPIO162
A1 ETPUB31 eTPU B channel (output only) O
A2 — — —
G GPIO162 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
163 ETPUB16_PCSA1_ P ETPUB16 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U26 V24
GPIO163
A1 PCSA1 DSPI A peripheral chip select O
A2 — — —
G GPIO163 GPIO I/O

164 ETPUB17_PCSA2_ P ETPUB17 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U25 T21
GPIO164
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 PCSA2 DSPI A peripheral chip select O

A2 — — —
G GPIO164 GPIO I/O

165 ETPUB18_PCSA3_ P ETPUB18 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U24 W26
GPIO165
A1 PCSA3 DSPI A peripheral chip select O
A2 — — —
G GPIO165 GPIO I/O

166 ETPUB19_PCSA4_ P ETPUB19 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U23 W25
GPIO166
A1 PCSA4 DSPI A peripheral chip select O
A2 — — —
G GPIO166 GPIO I/O
167 ETPUB20_ P ETPUB20 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG V26 W24
GPIO167
A1 — — —
A2 — — —
G GPIO167 GPIO I/O

168 ETPUB21_ P ETPUB21 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG V25 V22
GPIO168
A1 — — —
A2 — — —
G GPIO168 GPIO I/O
69
 Table 39. Signal Properties and Muxing Summary (continued)
70

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
169 ETPUB22_ P ETPUB22 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG V24 V23
GPIO169
A1 — — —
A2 — — —
G GPIO169 GPIO I/O

170 ETPUB23_ P ETPUB23 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG W26 U21
GPIO170
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO170 GPIO I/O

171 ETPUB24_ P ETPUB24 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG W25 Y25
GPIO171
A1 — — —
A2 — — —
G GPIO171 GPIO I/O

172 ETPUB25_ P ETPUB25 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG W24 W21
GPIO172
A1 — — —
A2 — — —
G GPIO172 GPIO I/O
173 ETPUB26_ P ETPUB26 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG V23 Y23
GPIO173
A1 — — —
A2 — — —
G GPIO173 GPIO I/O

174 ETPUB27_ P ETPUB27 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG Y25 Y24
Freescale Semiconductor

GPIO174
A1 — — —
A2 — — —
G GPIO174 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
175 ETPUB28_ P ETPUB28 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG Y24 AA24
GPIO175
A1 — — —
A2 — — —
G GPIO175 GPIO I/O

176 ETPUB29_ P ETPUB29 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG Y23 W22
GPIO176
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO176 GPIO I/O

177 ETPUB30_ P ETPUB30 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG AA24 AB24
GPIO177
A1 — — —
A2 — — —
G GPIO177 GPIO I/O

178 ETPUB31_ P ETPUB31 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG AB24 Y22
GPIO178
A1 — — —
A2 — — —
G GPIO178 GPIO I/O

eTPU_C

440 TCRCLKC_ P TCRCLKC eTPU C TCR clock I MH VDDEH7 —/Up —/Up B26 F22
GPIO440
A1 — — —
A2 — — —
G GPIO440 GPIO I/O

441 ETPUC0_ P ETPUC0 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG C25 C25
GPIO441
A1 — — —
A2 — — —
G GPIO441 GPIO I/O
71
 Table 39. Signal Properties and Muxing Summary (continued)
72

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
442 ETPUC1_ P ETPUC1 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG C26 C26
GPIO442
A1 — — —
A2 — — —
G GPIO442 GPIO I/O

443 ETPUC2_ P ETPUC2 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG D25 D25
GPIO443
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO443 GPIO I/O

444 ETPUC3_ P ETPUC3 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG D26 D26
GPIO444
A1 — — —
A2 — — —
G GPIO444 GPIO I/O

445 ETPUC4_ P ETPUC4 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG E24 E24
PCSE1_GPIO445
A1 DSPI E peripheral chip select
A2 — — —
G GPIO445 GPIO I/O
446 ETPUC5_ P ETPUC5 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG E25 E25
PCSE2_GPIO446
A1 DSPI E peripheral chip select
A2 — — —
G GPIO446 GPIO I/O

447 ETPUC6_ P ETPUC6 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG E26 E26
Freescale Semiconductor

PCSE3_GPIO447
A1 DSPI E peripheral chip select
A2 — — —
G GPIO447 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
448 ETPUC7_ P ETPUC7 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG F23 F23
PCSE4_GPIO448
A1 DSPI E peripheral chip select
A2 — — —
G GPIO448 GPIO I/O

449 ETPUC8_ P ETPUC8 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG F24 F24
PCSE5_GPIO449
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 DSPI E peripheral chip select

A2 — — —
G GPIO449 GPIO I/O

450 ETPUC9_IRQ0_ P ETPUC9 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG F25 F25
GPIO450
A1 IRQ0 External interrupt request I
A2 — — —
G GPIO450 GPIO I/O

451 ETPUC10__IRQ1_ P ETPUC10 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG F26 F26
GPIO451
A1 IRQ1 External interrupt request I
A2 — — —
G GPIO451 GPIO I/O
452 ETPUC11_IRQ2_ P ETPUC11 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG G23 G22
GPIO452
A1 IRQ2 External interrupt request I
A2 — — —
G GPIO452 GPIO I/O

453 ETPUC12_IRQ3_ P ETPUC12 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG G24 G23
GPIO453
A1 IRQ3 External interrupt request I
A2 — — —
G GPIO453 GPIO I/O
73
 Table 39. Signal Properties and Muxing Summary (continued)
74

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
454 ETPUC13_3_IRQ4_ P ETPUC13 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG G25 G24
GPIO454
A1 IRQ4 External interrupt request I
A2 — — —
G GPIO454 GPIO I/O

455 ETPUC14_4_IRQ5_ P ETPUC14 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG G26 G25
GPIO455
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 IRQ5 External interrupt request I

A2 — — —
G GPIO455 GPIO I/O

456 ETPUC15__ P ETPUC15 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG H23 G26
GPIO456
A1 — — —
A2 — — —
G GPIO456 GPIO I/O

457 ETPUC16_FR_A_TX_ P ETPUC16 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG H24 H22
GPIO457
A1 FR_A_TX FlexRay A transfer O
A2 — — —
G GPIO457 GPIO I/O
458 ETPUC17_FR_A_RX_ P ETPUC17 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG H25 H23
GPIO458
A1 FR_A_RX FlexRay A receive I
A2 — — —
G GPIO458 GPIO I/O

459 ETPUC18_FR_A_TX_EN_ P ETPUC18 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG H26 H24
Freescale Semiconductor

GPIO459
A1 FR_A_TX_EN FlexRay A transfer enable O
A2 — — —
G GPIO459 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
460 ETPUC19_TXDA_ P ETPUC19 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG J23 H21
GPIO460
A1 TXDA eSCI A transmit O
A2 — — —
G GPIO460 GPIO I/O

461 ETPUC20_RXDA _ P ETPUC20 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG J24 H25
GPIO461
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 RXDA eSCI A receive I

A2 — — —
G GPIO461 GPIO I/O

462 ETPUC21_TXDB_ P ETPUC21 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG J25 H26
GPIO462
A1 TXDB eSCI B transmit O
A2 — — —
G GPIO462 GPIO I/O

463 ETPUC22_RXDB_ P ETPUC22 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG J26 J22
GPIO463
A1 RXDB eSCI B receive I
A2 — — —
G GPIO463 GPIO I/O
464 ETPUC23_PCSD5_ P ETPUC23 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG K23 J23
GPIO464
A1 PCSD5 DSPI D peripheral chip select O
A2 MAA0 ADC A Mux Address 0 O
A3 MAB0 ADC B Mux Address 0 O
G GPIO464 GPIO I/O

465 ETPUC24_PCSD4_ P ETPUC24 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG K24 J24
GPIO465
A1 PCSD4 DSPI D peripheral chip select O
A2 MAA1 ADC A Mux Address 1 O
A4 MAB1 ADC B Mux Address 1 O
G GPIO465 GPIO I/O
75
 Table 39. Signal Properties and Muxing Summary (continued)
76

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
466 ETPUC25_PCSD3_ P ETPUC25 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG K25 K21
GPIO466
A1 PCSD3 DSPI D peripheral chip select O
A2 MAA2 ADC A Mux Address 2 O
A3 MAB2 ADC B Mux Address 2 O
G GPIO466 GPIO I/O
MPC5676R Microcontroller Data Sheet, Rev. 4

467 ETPUC26_PCSD2_ P ETPUC26 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG K26 J25
GPIO467
A1 PCSD2 DSPI D peripheral chip select O
A2 — — —
G GPIO467 GPIO I/O

468 ETPUC27_PCSD1_ P ETPUC27 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG L23 J26
GPIO468
A1 PCSD1 DSPI D peripheral chip select O
A2 — — —
G GPIO468 GPIO I/O
469 ETPUC28_PCSD0_ P ETPUC28 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG L24 K22
GPIO469
A1 PCSD0 DSPI D peripheral chip select O
A2 — — —
G GPIO469 GPIO I/O

470 ETPUC29_SCKD_ P ETPUC29 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG L25 K23
GPIO470
A1 SCKD DSPI D clock I/O
A2 — — —
G GPIO470 GPIO I/O
Freescale Semiconductor

471 ETPUC30_SOUTD_ P ETPUC30 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG L26 K24
GPIO471
A1 SOUTD DSPI D data output O
A2 — — —
G GPIO471 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
472 ETPUC31_SIND_ P ETPUC31 eTPU C channel I/O MH VDDEH7 —/WKPCFG —/WKPCFG M23 K25
GPIO472
A1 SIND DSPI D data input I
A2 — — —
G GPIO472 GPIO I/O

eMIOS
MPC5676R Microcontroller Data Sheet, Rev. 4

179 EMIOS0_ETPUA0_ P EMIOS0 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE10 AC13
GPIO179
A1 ETPUA0 eTPU A channel O
A2 — — —
G GPIO179 GPIO I/O

180 EMIOS1_ETPUA1_ P EMIOS1 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF10 AB13
GPIO180
A1 ETPUA1 eTPU A channel O
A2 — — —
G GPIO180 GPIO I/O

181 EMIOS2_ETPUA2_ P EMIOS2 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD11 AD13
GPIO181
A1 ETPUA2 eTPU A channel O
A2 — — —
G GPIO181 GPIO I/O
182 EMIOS3_ETPUA3_ P EMIOS3 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE11 AE13
GPIO182
A1 ETPUA3 eTPU A channel O
A2 — — —
G GPIO182 GPIO I/O

183 EMIOS4_ETPUA4_ P EMIOS4 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF11 AF13
GPIO183
A1 ETPUA4 eTPU A channel O
A2 — — —
G GPIO183 GPIO I/O
77
 Table 39. Signal Properties and Muxing Summary (continued)
78

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
184 EMIOS5_ETPUA5_ P EMIOS5 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD12 AF14
GPIO184
A1 ETPUA5 eTPU A channel O
A2 — — —
G GPIO184 GPIO I/O

185 EMIOS6_ETPUA6_ P EMIOS6 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE12 AE14
GPIO185
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 ETPUA6 eTPU A channel O

A2 — — —
G GPIO185 GPIO I/O

186 EMIOS7_ETPUA7_ P EMIOS7 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF12 AD14
GPIO186
A1 ETPUA7 eTPU A channel O
A2 — — —
G GPIO186 GPIO I/O

187 EMIOS8_ETPUA8_ P EMIOS8 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC13 AC14
GPIO187
A1 ETPUA8 eTPU A channel O
A2 — — —
G GPIO187 GPIO I/O
188 EMIOS9_ETPUA9_ P EMIOS9 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD13 AF15
GPIO188
A1 ETPUA9 eTPU A channel O
A2 — — —
G GPIO188 GPIO I/O

189 EMIOS10_SCKD_ P EMIOS10 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE13 AE15
Freescale Semiconductor

GPIO189
A1 SCKD DSPI D clock O
A2 — — —
G GPIO189 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
190 EMIOS11_SIND_ P EMIOS11 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF13 AB14
GPIO190
A1 SIND DSPI D data input I
A2 — — —
G GPIO190 GPIO I/O

191 EMIOS12_SOUTC_ P EMIOS12 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG AF14 AD15
GPIO191
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 SOUTC DSPI C data output O

A2 — — —
G GPIO191 GPIO I/O

192 EMIOS13_SOUTD_ P EMIOS13 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG AE14 AC15
GPIO192
A1 SOUTD DSPI D data output O
A2 — — —
G GPIO192 GPIO I/O

193 EMIOS14_IRQ0_ P EMIOS14 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG AC14 AF17
GPIO193
A1 IRQ0 External interrupt request I
A2 CNTXD FlexCAN D transmit O
G GPIO193 GPIO I/O
194 EMIOS15_IRQ1_ P EMIOS15 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG AD14 AE16
GPIO194
A1 IRQ1 External interrupt request I
A2 CNRXD FlexCAN D receive I
G GPIO194 GPIO I/O

195 EMIOS16_ETPUB0_ P EMIOS16 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF15 AD16
GPIO195
A1 ETPUB0 eTPU B channel O
A2 FR_DBG[3] FlexRay debug O
G GPIO195 GPIO I/O
79
 Table 39. Signal Properties and Muxing Summary (continued)
80

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
196 EMIOS17_ETPUB1_ P EMIOS17 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE15 AB15
GPIO196
A1 ETPUB1 eTPU B channel O
A2 FR_DBG[2] FlexRay debug O
G GPIO196 GPIO I/O

197 EMIOS18_ETPUB2_ P EMIOS18 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC15 AD17
GPIO197
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 ETPUB2 eTPU B channel O

A2 FR_DBG[1] FlexRay debug O
G GPIO197 GPIO I/O

198 EMIOS19_ETPUB3_ P EMIOS19 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD15 AB16
GPIO198
A1 ETPUB3 eTPU B channel O
A2 FR_DBG[0] FlexRay debug O
G GPIO198 GPIO I/O

199 EMIOS20_ETPUB4_ P EMIOS20 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF16 AF16
GPIO199
A1 ETPUB4 eTPU B channel O
A2 — — —
G GPIO199 GPIO I/O
200 EMIOS21_ETPUB5_ P EMIOS21 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE16 AE17
GPIO200
A1 ETPUB5 eTPU B channel O
A2 — — —
G GPIO200 GPIO I/O

201 EMIOS22_ETPUB6_ P EMIOS22 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC16 AC16
Freescale Semiconductor

GPIO201
A1 ETPUB6 eTPU B channel O
A2 — — —
G GPIO201 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
202 EMIOS23_ETPUB7_ P EMIOS23 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD16 AA16
GPIO202
A1 ETPUB7 eTPU B channel O
A2 — — —
G GPIO202 GPIO I/O

203 EMIOS24_PCSB0_ P EMIOS24 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF17 AC17
GPIO203
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 PCSB0 DSPI B peripheral chip select I/O

A2 — — —
G GPIO203 GPIO I/O

204 EMIOS25_PCSB1_ P EMIOS25 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE17 AF18
GPIO204
A1 PCSB1 DSPI B peripheral chip select O
A2 — — —
G GPIO204 GPIO I/O

432 EMIOS26_PCSB2_ P EMIOS26 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD17 AE18
GPIO432
A1 PCSB2 DSPI B peripheral chip select O
A2 — — —
G GPIO432 GPIO I/O
433 EMIOS27_PCSB3_ P EMIOS27 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC17 AD18
GPIO433
A1 PCSB3 DSPI B peripheral chip select O
A2 — — —
G GPIO433 GPIO I/O

434 EMIOS28_PCSC0_ P EMIOS28 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF18 AC18
GPIO434
A1 PCSC0 DSPI C peripheral chip select I/O
A2 — — —
G GPIO434 GPIO I/O
81
 Table 39. Signal Properties and Muxing Summary (continued)
82

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
435 EMIOS29_PCSC1_ P EMIOS29 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE18 AB17
GPIO435
A1 PCSC1 DSPI C peripheral chip select O
A2 — — —
G GPIO435 GPIO I/O

436 EMIOS30_PCSC2_ P EMIOS30 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD18 AF19
GPIO436
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 PCSC2 DSPI C peripheral chip select O

A2 — — —
G GPIO436 GPIO I/O

437 EMIOS31_PCSC5_ P EMIOS31 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AC18 AA17
GPIO437
A1 PCSC5 DSPI C peripheral chip select O
A2 — — —
G GPIO437 GPIO I/O

eQADC

— ANA0 P ANA09 eQADC A shared analog input I AE/up- VDDA_A1 ANA0 ANA0 A4 A4
down

— ANA1 P ANA19 eQADC A shared analog input I AE/up- VDDA_A1 ANA1 ANA1 B5 B5
down

— ANA2 P ANA29 eQADC A shared analog input I AE/up- VDDA_A1 ANA2 ANA2 C5 C5
down

— ANA3 P ANA39 eQADC A shared analog input I AE/up- VDDA_A1 ANA3 ANA3 D6 D6
down

— ANA4 P ANA49 eQADC A shared analog input I AE/up- VDDA_A1 ANA4 ANA4 A5 A5
Freescale Semiconductor

down

— ANA5 P ANA59 eQADC A shared analog input I AE/up- VDDA_A1 ANA5 ANA5 B6 B6
down

— ANA6 P ANA69 eQADC A shared analog input I AE/up- VDDA_A1 ANA6 ANA6 C6 C6
down

— ANA7 P ANA79 eQADC A shared analog input I AE/up- VDDA_A1 ANA7 ANA7 D7 C7
down
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
— ANA8 P ANA8 eQADC A analog input I AE VDDA_A1 ANA8 ANA8 A6 D7

— ANA9 P ANA9 eQADC A analog input I AE VDDA_A1 ANA9 ANA9 C7 A6

— ANA10 P ANA10 eQADC A analog input I AE VDDA_A1 ANA10 ANA10 B7 B7

— ANA11 P ANA11 eQADC A analog input I AE VDDA_A1 ANA11 ANA11 A7 A7

— ANA12 P ANA12 eQADC A analog input I AE VDDA_A1 ANA12 ANA12 D8 D8

MPC5676R Microcontroller Data Sheet, Rev. 4

— ANA13 P ANA13 eQADC A analog input I AE VDDA_A1 ANA13 ANA13 C8 C8

— ANA14 P ANA14 eQADC A analog input I AE VDDA_A1 ANA14 ANA14 B8 B8

— ANA15 P ANA15 eQADC A analog input I AE VDDA_A1 ANA15 ANA15 A8 A8

— ANA16 P ANA16 eQADC A analog input I AE VDDA_A1 ANA16 ANA16 D9 D9

— ANA17 P ANA17 eQADC A analog input I AE VDDA_A1 ANA17 ANA17 C9 C9

— ANA18 P ANA18 eQADC A analog input I AE VDDA_A1 ANA18 ANA18 D10 D10

— ANA19 P ANA19 eQADC A analog input I AE VDDA_A1 ANA19 ANA19 C10 C10

— ANA20 P ANA20 eQADC A analog input I AE VDDA_A1 ANA20 ANA20 D11 D11
— ANA21 P ANA21 eQADC A analog input I AE VDDA_A1 ANA21 ANA21 C11 C11

— ANA22 P ANA22 eQADC A analog input I AE VDDA_A1 ANA22 ANA22 D12 C12

— ANA23 P ANA23 eQADC A analog input I AE VDDA_A1 ANA23 ANA23 C12 D12
— AN24 P AN24 eQADC analog input I AE VDDA_A0 AN24 AN24 B12 B12

— AN25 P AN25 eQADC analog input I AE VDDA_A0 AN25 AN25 D13 C13

— AN26 P AN26 eQADC analog input I AE VDDA_A0 AN26 AN26 C13 D13
— AN27 P AN27 eQADC analog input I AE VDDA_A0 AN27 AN27 B13 B13

— AN28 P AN28 eQADC analog input I AE VDDA_A0 AN28 AN28 A13 A13

— AN29 P AN29 eQADC analog input I AE VDDA_A0 AN29 AN29 B14 A14
— AN30 P AN30 eQADC analog input I AE VDDA_B1 AN30 AN30 C14 B14

— AN31 P AN31 eQADC analog input I AE VDDA_B1 AN31 AN31 D14 C14

— AN32 P AN32 eQADC analog input I AE VDDA_B1 AN32 AN32 A14 B15

— AN33 P AN33 eQADC analog input I AE VDDA_B0 AN33 AN33 B15 D14

— AN34 P AN34 eQADC analog input I AE VDDA_B0 AN34 AN34 C15 C15
83
 Table 39. Signal Properties and Muxing Summary (continued)
84

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
— AN35 P AN35 eQADC analog input I AE VDDA_B0 AN35 AN35 D15 D15

— AN36 P AN36 eQADC analog input I AE VDDA_B1 AN36 AN36 A15 A15

— AN37 P AN37 eQADC analog input I AE VDDA_B0 AN37 AN37 C16 C17

— AN38 P AN38 eQADC analog input I AE VDDA_B0 AN38 AN38 C17 D16

— AN39 P AN39 eQADC analog input I AE VDDA_B0 AN39 AN39 D16 C16
MPC5676R Microcontroller Data Sheet, Rev. 4

— ANB0 P ANB0 eQADC B shared analog input I AE/up- VDDA_B0 ANB0 ANB0 C18 C18
down

— ANB1 P ANB1 eQADC B shared analog input I AE/up- VDDA_B0 ANB1 ANB1 D17 D17
down

— ANB2 P ANB2 eQADC B shared analog input I AE/up- VDDA_B0 ANB2 ANB2 D18 D18
down

— ANB3 P ANB3 eQADC B shared analog input I AE/up- VDDA_B0 ANB3 ANB3 D19 D19
down

— ANB4 P ANB4 eQADC B shared analog input I AE/up- VDDA_B0 ANB4 ANB4 C19 B19
down

— ANB5 P ANB5 eQADC B shared analog input I AE/up- VDDA_B0 ANB5 ANB5 C20 A20
down

— ANB6 P ANB6 eQADC B shared analog input I AE/up- VDDA_B0 ANB6 ANB6 B19 C20
down

— ANB7 P ANB7 eQADC B shared analog input I AE/up- VDDA_B0 ANB7 ANB7 A20 C19
down

— ANB8 P ANB8 eQADC B analog input I AE VDDA_B0 ANB8 ANB8 B20 B20
— ANB9 P ANB9 eQADC B analog input I AE VDDA_B0 ANB9 ANB9 D20 A21

— ANB10 P ANB10 eQADC B analog input I AE VDDA_B0 ANB10 ANB10 B21 B21
Freescale Semiconductor

— ANB11 P ANB11 eQADC B analog input I AE VDDA_B0 ANB11 ANB11 A21 C21
— ANB12 P ANB12 eQADC B analog input I AE VDDA_B0 ANB12 ANB12 C21 A22

— ANB13 P ANB13 eQADC B analog input I AE VDDA_B0 ANB13 ANB13 D21 B22

— ANB14 P ANB14 eQADC B analog input I AE VDDA_B0 ANB14 ANB14 A22 D20

— ANB15 P ANB15 eQADC B analog input I AE VDDA_B0 ANB15 ANB15 B22 C22

— ANB16 P ANB16 eQADC B analog input I AE VDDA_B0 ANB16 ANB16 C22 D21
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
— ANB17 P ANB17 eQADC B analog input I AE VDDA_B0 ANB17 ANB17 A23 D22

— ANB18 P ANB18 eQADC B analog input I AE VDDA_B0 ANB18 ANB18 B23 A23

— ANB19 P ANB19 eQADC B analog input I AE VDDA_B0 ANB19 ANB19 C23 B23

— ANB20 P ANB20 eQADC B analog input I AE VDDA_B0 ANB20 ANB20 D22 C23

— ANB21 P ANB21 eQADC B analog input I AE VDDA_B0 ANB21 ANB21 A24 A24
MPC5676R Microcontroller Data Sheet, Rev. 4

— ANB22 P ANB22 eQADC B analog input I AE VDDA_B0 ANB22 ANB22 B24 B24

— ANB23 P ANB23 eQADC B analog input I AE VDDA_B0 ANB23 ANB23 A25 E20

— VRH_A P VRH_A ADC A Voltage reference high I VDDINT VRH_A VRH_A VRH_A A12 A12

— VRL_A P VRL_A ADC A Voltage reference low I VSSINT VRL_A VRL_A VRL_A A11 A11

— VRH_B P VRH_B ADC B Voltage reference high I VDDINT VRH_B VRH_B VRH_B A19 A19
— VRL_B P VRL_B ADC B Voltage reference low I VSSINT VRL_B VRL_B VRL_B A18 A18

— REFBYPCB P REFBYPCB ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB REFBYPCB B18 B18

— REFBYPCA P REFBYPCA ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA REFBYPCA B11 B11
— VDDA_A0 P VDDA_A Internal logic supply input I VDDE VDDA_A0 VDDA_A0 VDDA_A0 A9 A9

— VDDA_A1 P VDDA_A Internal logic supply input I VDDE VDDA_A1 VDDA_A1 VDDA_A1 B9 B9

— REFBYPCA1 P REFBYPCA1 ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA1 REFBYPCA1 A10 A10
— VSSA_A1 P VSSA_A Ground I VSSE VSSA_A1 VSSA_A1 VSSA_A1 B10 B10

— VDDA_B0 P VDDA_B Internal logic supply input I VDDE VDDA_B0 VDDA_B0 VDDA_B0 A16 A16

— VDDA_B1 P VDDA_B Internal logic supply input I VDDE VDDA_B1 VDDA_B1 VDDA_B1 B16 B16
— VSSA_B0 P VSSA_B Ground I VSSE VSSA_B0 VSSA_B0 VSSA_B0 B17 B17

— REFBYPCB1 P REFBYPCB1 ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB1 REFBYPCB1 A17 A17

FlexRay

248 FR_A_TX_ P FR_A_TX FlexRay A transfer O FS VDDE2 —/Up —/Up AD4 AD4
GPIO248 (–/– for Rev.1 (–/– for Rev.1
A1 — — —
of the device) of the device)
A2 — — —
G GPIO248 GPIO I/O
85
 Table 39. Signal Properties and Muxing Summary (continued)
86

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
249 FR_A_RX_ P FR_A_RX FlexRay A receive I FS VDDE2 —/Up —/Up AE3 AE3
GPIO249 (–/– for Rev.1 (–/– for Rev.1
A1 — — —
of the device) of the device)
A2 — — —
G GPIO249 GPIO I/O

250 FR_A_TX_EN_ P FR_A_TX_EN FlexRay A transfer enable O FS VDDE2 —/Up —/Up AF3 AF3
GPIO250 (–/– for Rev.1 (–/– for Rev.1
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — — of the device) of the device)

A2 — — —
G GPIO250 GPIO I/O

251 FR_B_TX_ P FR_B_TX FlexRay B transfer O FS VDDE2 —/Up —/Up AD5 AD5
GPIO251 (–/– for Rev.1 (–/– for Rev.1
A1 — — — of the device) of the device)
A2 — — —
G GPIO251 GPIO I/O

252 FR_B_RX_ P FR_B_RX FlexRay B receive I FS VDDE2 —/Up —/Up AE4 AE4
GPIO252 (–/– for Rev.1 (–/– for Rev.1
A1 — — —
of the device) of the device)
A2 — — —
G GPIO252 GPIO I/O
253 FR_B_TX_EN_ P FR_B_TX_EN FlexRay B transfer enable O FS VDDE2 —/Up —/Up AF4 AF4
GPIO253 (–/– for Rev.1 (–/– for Rev.1
A1 — — —
of the device) of the device)
A2 — — —
G GPIO253 GPIO I/O

FlexCAN
Freescale Semiconductor

83 CNTXA_TXDA_ P CNTXA FlexCAN A transmit O MH VDDEH4 —/Up —/Up AF19 AE19

GPIO83
A1 TXDA eSCI A transmit O
A2 — — —
G GPIO83 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
84 CNRXA_RXDA_ P CNRXA FlexCAN A receive I MH VDDEH4 —/Up —/Up AE19 AD19
GPIO84
A1 RXDA eSCI A receive I
A2 — — —
G GPIO84 GPIO I/O

85 CNTXB_PCSC3_ P CNTXB FlexCAN B transmit O MH VDDEH4 —/Up —/Up AD19 AC19

GPIO85
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 PCSC3 DSPI C peripheral chip select O

A2 — — —
G GPIO85 GPIO I/O

86 CNRXB_PCSC4_ P CNRXB FlexCAN B receive I MH VDDEH4 —/Up —/Up AC19 AA19

GPIO86
A1 PCSC4 DSPI C peripheral chip select O
A2 — — —
G GPIO86 GPIO I/O

87 CNTXC_PCSD3_ P CNTXC FlexCAN C transmit O MH VDDEH4 —/Up —/Up AF20 AF20

GPIO87
A1 PCSD3 DSPI D peripheral chip select O
A2 — — —
G GPIO87 GPIO I/O
88 CNRXC_PCSD4_ P CNRXC FlexCAN C receive I MH VDDEH4 —/Up —/Up AE20 AE20
GPIO88
A1 PCSD4 DSPI D peripheral chip select O
A2 — — —
G GPIO88 GPIO I/O

246 CNTXD_ P CNTXD FlexCAN D transmit O MH VDDEH4 —/Up —/Up AD20 AD20
GPIO246
A1 — — —
A2 — — —
G GPIO246 GPIO I/O
87
 Table 39. Signal Properties and Muxing Summary (continued)
88

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
247 CNRXD_ P CNRXD FlexCAN D receive I MH VDDEH4 —/Up —/Up AC20 AC20
GPIO247
A1 — — —
A2 — — —
G GPIO247 GPIO I/O

eSCI
MPC5676R Microcontroller Data Sheet, Rev. 4

89 TXDA_ P TXDA eSCI A transmit O MH VDDEH1 —/Up —/Up M2 K2

GPIO89
A1 — — —
A2 — — —
G GPIO89 GPIO I/O

90 RXDA _ P RXDA eSCI A receive I MH VDDEH1 —/Up —/Up M3 K3

GPIO90
A1 — — —
A2 — — —
G GPIO90 GPIO I

91 TXDB_PCSD1_ P TXDB eSCI B transmit O MH VDDEH1 —/Up —/Up P1 K1

GPIO91
A1 PCSD1 DSPI D peripheral chip select O
A2 — — —
G GPIO91 GPIO I/O
92 RXDB_PCSD5_ P RXDB eSCI B receive I MH VDDEH1 —/Up —/Up N1 L5
GPIO92
A1 PCSD5 DSPI D peripheral chip select O
A2 — — —
G GPIO92 GPIO I/O
Freescale Semiconductor

244 TXDC_ETRIG0_ P TXDC eSCI C transmit O MH VDDEH4 —/Up —/Up AF23 AF23
GPIO244
A1 ETRIG0 eQADC trigger input I
A2 — — —
G GPIO244 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
245 RXDC_ P RXDC eSCI C receive I MH VDDEH5 —/Up —/Up AD22 AD22
GPIO245
A1 — — —
A2 — — —
G GPIO245 GPIO I/O

DSPI
MPC5676R Microcontroller Data Sheet, Rev. 4

93 SCKA_PCSC1_ P SCKA DSPI A clock I/O MH VDDEH3 —/Up —/Up AD8 AB8
GPIO93
A1 PCSC1 DSPI C peripheral chip select O
A2 — — —
G GPIO93 GPIO I/O

94 SINA_PCSC2_ P SINA DSPI A data input I MH VDDEH3 —/Up —/Up AF7 AE7
GPIO94
A1 PCSC2 DSPI C peripheral chip select O
A2 — — —
G GPIO94 GPIO I/O

95 SOUTA_PCSC5_ P SOUTA DSPI A data output O MH VDDEH3 —/Up —/Up AD7 AC7
GPIO95
A1 PCSC5 DSPI C peripheral chip select O
A2 — — —
G GPIO95 GPIO I/O
96 PCSA0_PCSD2_ P PCSA0 DSPI A peripheral chip select I/O MH VDDEH3 —/Up —/Up AE6 AD6
GPIO96
A1 PCSD2 DSPI D peripheral chip select O
A2 — — —
G GPIO96 GPIO I/O

97 PCSA1_ P PCSA1 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AC6 AC6
PCSE0_GPIO97
A1 DSPI E peripheral chip select
A2 — — —
G GPIO97 GPIO I/O
89
 Table 39. Signal Properties and Muxing Summary (continued)
90

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
98 PCSA2_ P PCSA2 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AC7 AF6
SOUTE_GPIO98
A1 DSPI E data output
A2 — — —
G GPIO98 GPIO I/O

99 PCSA3_ P PCSA3 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AE7 AD7
SINE_GPIO99
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 DSPI E data input

A2 — — —
G GPIO99 GPIO I/O

100 PCSA4_ P PCSA4 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AE5 AE5
SCKE_GPIO100
A1 DSPI E clock
A2 — — —
G GPIO100 GPIO I/O

101 PCSA5_ETRIG1_ P PCSA5 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AD6 AA8
GPIO101
A1 ETRIG1 eQADC trigger input I
A2 — — —
G GPIO101 GPIO I/O
102 SCKB_ P SCKB DSPI B clock I/O MH VDDEH3 —/Up —/Up AE8 AC8
GPIO102
A1 — — —
A2 — — —
G GPIO102 GPIO I/O

103 SINB_ P SINB DSPI B data input I MH VDDEH3 —/Up —/Up AE9 AB9
Freescale Semiconductor

GPIO103
A1 — — —
A2 — — —
G GPIO103 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
104 SOUTB_ P SOUTB DSPI B data output O MH VDDEH3 —/Up —/Up AF9 AA10
GPIO104
A1 — — —
A2 — — —
G GPIO104 GPIO I/O

105 PCSB0_PCSD2_ P PCSB0 DSPI B peripheral chip select I/O MH VDDEH3 —/Up —/Up AD9 AF8
GPIO105
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 PCSD2 DSPI D peripheral chip select O

A2 — — —
G GPIO105 GPIO I/O

106 PCSB1_PCSD0_ P PCSB1 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AC9 AE8
GPIO106
A1 PCSD0 DSPI D peripheral chip select I/O
A2 — — —
G GPIO106 GPIO I/O

107 PCSB2_SOUTC_ P PCSB2 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AF8 AD8
GPIO107
A1 SOUTC DSPI C data output O
A2 — — —
G GPIO107 GPIO I/O
108 PCSB3_SINC_ P PCSB3 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AD10 AC9
GPIO108
A1 SINC DSPI C data input I
A2 — — —
G GPIO108 GPIO I/O

109 PCSB4_SCKC_ P PCSB4 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AC8 AF7
GPIO109
A1 SCKC DSPI C clock I/O
A2 — — —
G GPIO109 GPIO I/O
91
 Table 39. Signal Properties and Muxing Summary (continued)
92

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
110 PCSB5_PCSC0_ P PCSB5 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up AF6 AE6
GPIO110
A1 PCSC0 DSPI C peripheral chip select I/O
A2 — — —
G GPIO110 GPIO I/O

235 SCKC_SCK_C_LVDSP_ P SCKC DSPI C clock I/O MH+ VDDEH4 —/Up —/Up AD21 AD21
GPIO235 LVDS
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 SCK_C_LVDSP LVDS+ downstream signal positive O

output clock
A2 — — —
G GPIO235 GPIO I/O

236 SINC_SCK_C_LVDSM_ P SINC DSPI C data input I MH+ VDDEH4 —/Up —/Up AE22 AE22
GPIO236 LVDS
A1 SCK_C_LVDSM LVDS– downstream signal negative O
output clock
A2 — — —
G GPIO236 GPIO I/O

237 SOUTC_SOUT_C_LVDSP_ P SOUTC DSPI C data output O MH+ VDDEH4 —/Up —/Up AF21 AF21
GPIO237 LVDS
A1 SOUT_C_LVDSP LVDS+ downstream signal positive O
output data
A2 — — —
G GPIO237 GPIO I/O
238 PCSC0_SOUT_C_LVDSM_ P PCSC0 DSPI C peripheral chip select I/O MH+ VDDEH4 —/Up —/Up AE21 AE21
GPIO238 LVDS
A1 SOUT_C_LVDSM LVDS– downstream signal negative O
output data
Freescale Semiconductor

A2 — — —
G GPIO238 GPIO I/O

239 PCSC1_ P PCSC1 DSPI C peripheral chip select O MH VDDEH4 —/Up —/Up AC22 AC22
GPIO239
A1 — — —
A2 — — —
G GPIO239 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
240 PCSC2_GPIO240 P PCSC2 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up AE23 AE23
A1 — — —
A2 — — —
G GPIO240 GPIO I/O

241 PCSC3_GPIO241 P PCSC3 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up AD23 AD23
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO241 GPIO I/O

242 PCSC4_GPIO242 P PCSC4 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up AF24 AF24
A1 — — —
A2 — — —
G GPIO242 GPIO I/O

243 PCSC5_GPIO243 P PCSC5 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up AE24 AE24
A1 — — —
A2 — — —
G GPIO243 GPIO I/O

EBI

256 D_CS0_ P D_CS0 EBI chip select 0 O F VDDE9 —/Up —/Up — AD9
GPIO256
A1 — — —
A2 — — —
G GPIO256 GPIO I/O

257 D_CS2_D_ADD_DAT31_ P D_CS2 EBI chip select 2 O F VDDE8 —/Up —/Up — U1

GPIO257
A1 D_ADD_DAT31 Address and data in mux mode. I/O
A2 — — —
G GPIO257 GPIO I/O
93
 Table 39. Signal Properties and Muxing Summary (continued)
94

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
258 D_CS3_D_TEA_ P D_CS3 EBI chip select 3 O F VDDE8 —/Up —/Up — T6
GPIO258
A1 D_TEA EBI transfer error acknowledge I/O
A2 — — —
G GPIO258 GPIO I/O

259 D_ADD12_ P D_ADD12 EBI address bus O F VDDE8 —/Up —/Up — R1

GPIO259
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO259 GPIO I/O

260 D_ADD13_ P D_ADD13 EBI address bus O F VDDE8 —/Up —/Up — R2

GPIO260
A1 — — —
A2 — — —
G GPIO260 GPIO I/O

261 D_ADD14_ P D_ADD14 EBI address bus O F VDDE8 —/Up —/Up — R3

GPIO261
A1 — — —
A2 — — —
G GPIO261 GPIO I/O
262 D_ADD15_ P D_ADD15 EBI address bus O F VDDE8 —/Up —/Up — R4
GPIO262
A1 — — —
A2 — — —
G GPIO262 GPIO I/O

263 D_ADD16_D_ADD_DAT16_ P D_ADD16 EBI address bus O F VDDE8 —/Up —/Up — R5

Freescale Semiconductor

GPIO263
A1 D_ADD_DAT16 Address and data in mux mode. I/O
A2 — — —
G GPIO263 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
264 D_ADD17_D_ADD_DAT17_ P D_ADD17 EBI address bus O F VDDE8 —/Up —/Up — T5
GPIO264
A1 D_ADD_DAT17 Address and data in mux mode. I/O
A2 — — —
G GPIO264 GPIO I/O

265 D_ADD18_D_ADD_DAT18_ P D_ADD18 EBI address bus O F VDDE8 —/Up —/Up — T2

GPIO265
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 D_ADD_DAT18 Address and data in mux mode. I/O

A2 — — —
G GPIO265 GPIO I/O

266 D_ADD19_D_ADD_DAT19_ P D_ADD19 EBI address bus O F VDDE8 —/Up —/Up — T3

GPIO266
A1 D_ADD_DAT19 Address and data in mux mode. I/O
A2 — — —
G GPIO266 GPIO I/O

267 D_ADD20_D_ADD_DAT20_ P D_ADD20 EBI address bus O F VDDE8 —/Up —/Up — T4

GPIO267
A1 D_ADD_DAT20 Address and data in mux mode. I/O
A2 — — —
G GPIO267 GPIO I/O
268 D_ADD21_D_ADD_DAT21_ P D_ADD21 EBI address bus O F VDDE9 —/Up —/Up — AB11
GPIO268
A1 D_ADD_DAT21 Address and data in mux mode. I/O
A2 — — —
G GPIO268 GPIO I/O

269 D_ADD22_D_ADD_DAT22_ P D_ADD22 EBI address bus O F VDDE9 —/Up —/Up — AD10
GPIO269
A1 D_ADD_DAT22 Address and data in mux mode. I/O
A2 — — —
G GPIO269 GPIO I/O
95
 Table 39. Signal Properties and Muxing Summary (continued)
96

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
270 D_ADD23_D_ADD_DAT23_ P D_ADD23 EBI address bus O F VDDE9 —/Up —/Up — AE10
GPIO270
A1 D_ADD_DAT23 Address and data in mux mode. I/O
A2 — — —
G GPIO270 GPIO I/O

271 D_ADD24_D_ADD_DAT24_ P D_ADD24 EBI address bus O F VDDE9 —/Up —/Up — AF10
GPIO271
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 D_ADD_DAT24 Address and data in mux mode. I/O

A2 — — —
G GPIO271 GPIO I/O

272 D_ADD25_D_ADD_DAT25_ P D_ADD25 EBI address bus O F VDDE9 —/Up —/Up — AD11
GPIO272
A1 D_ADD_DAT25 Address and data in mux mode. I/O
A2 — — —
G GPIO272 GPIO I/O

273 D_ADD26_D_ADD_DAT26_ P D_ADD26 EBI address bus O F VDDE9 —/Up —/Up — AE11
GPIO273
A1 D_ADD_DAT26 Address and data in mux mode. I/O
A2 — — —
G GPIO273 GPIO I/O
274 D_ADD27_D_ADD_DAT27_ P D_ADD27 EBI address bus O F VDDE9 —/Up —/Up — AF11
GPIO274
A1 D_ADD_DAT27 Address and data in mux mode. I/O
A2 — — —
G GPIO274 GPIO I/O

275 D_ADD28_D_ADD_DAT28_ P D_ADD28 EBI address bus O F VDDE9 —/Up —/Up — AD12
Freescale Semiconductor

GPIO275
A1 D_ADD_DAT28 Address and data in mux mode. I/O
A2 — — —
G GPIO275 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
276 D_ADD29_D_ADD_DAT29_ P D_ADD29 EBI address bus O F VDDE9 —/Up —/Up — AB12
GPIO276
A1 D_ADD_DAT29 Address and data in mux mode. I/O
A2 — — —
G GPIO276 GPIO I/O

277 D_ADD30_D_ADD_DAT30_ P D_ADD30 EBI address bus O F VDDE9 —/Up —/Up — AE12
GPIO277
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 D_ADD_DAT30 Address and data in mux mode. I/O

A2 — — —
G GPIO277 GPIO I/O

278 D_ADD_DAT0_ P D_ADD_DAT0 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — P25
GPIO278 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO278 GPIO I/O
279 D_ADD_DAT1_ P D_ADD_DAT1 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — P26
GPIO279 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO279 GPIO I/O

280 D_ADD_DAT2_ P D_ADD_DAT2 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — N24
GPIO280 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO280 GPIO I/O

281 D_ADD_DAT3_ P D_ADD_DAT3 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — N25
GPIO281 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO281 GPIO I/O
97
 Table 39. Signal Properties and Muxing Summary (continued)
98

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
282 D_ADD_DAT4_ P D_ADD_DAT4 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — N26
GPIO282 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO282 GPIO I/O

283 D_ADD_DAT5_ P D_ADD_DAT5 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — M25
MPC5676R Microcontroller Data Sheet, Rev. 4

GPIO283 Address and data in mux mode.

A1 — — —
A2 — — —
G GPIO283 GPIO I/O
284 D_ADD_DAT6_ P D_ADD_DAT6 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — N22
GPIO284 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO284 GPIO I/O

285 D_ADD_DAT7_ P D_ADD_DAT7 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — M24
GPIO285 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO285 GPIO I/O

286 D_ADD_DAT8_ P D_ADD_DAT8 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — M23
GPIO286 Address and data in mux mode.
A1 — — —
Freescale Semiconductor

A2 — — —
G GPIO286 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
287 D_ADD_DAT9_ P D_ADD_DAT9 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — M22
GPIO287 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO287 GPIO I/O

288 D_ADD_DAT10_ P D_ADD_DAT10 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — L26
MPC5676R Microcontroller Data Sheet, Rev. 4

GPIO288 Address and data in mux mode.

A1 — — —
A2 — — —
G GPIO288 GPIO I/O
289 D_ADD_DAT11_ P D_ADD_DAT11 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — L25
GPIO289 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO289 GPIO I/O

290 D_ADD_DAT12_ P D_ADD_DAT12 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — L24
GPIO290 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO290 GPIO I/O

291 D_ADD_DAT13 P D_ADD_DAT13 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — L23
_GPIO291 Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO291 GPIO I/O
99
 Table 39. Signal Properties and Muxing Summary (continued)
100

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
292 D_ADD_DAT14_GPIO292 P D_ADD_DAT14 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — L22
Address and data in mux mode.
A1 — — —
A2 — — —
G GPIO292 GPIO I/O

293 D_ADD_DAT15_GPIO293 P D_ADD_DAT15 EBI data only in non-mux mode. I/O F VDDE10 —/Up —/Up — K26
MPC5676R Microcontroller Data Sheet, Rev. 4

Address and data in mux mode.

A1 — — —
A2 — — —
G GPIO293 GPIO I/O
294 D_RD_WR_GPIO294 P D_RD_WR EBI read/write O F VDDE10 —/Up —/Up — R26
A1 — — —
A2 — — —
G GPIO294 GPIO I/O

295 D_WE0_GPIO295 P D_WE0 EBI write enable O F VDDE8 —/Up —/Up — N1

A1 — — —
A2 — — —
G GPIO295 GPIO I/O

296 D_WE1_GPIO296 P D_WE1 EBI write enable O F VDDE8 —/Up —/Up — P5

A1 — — —
A2 — — —
G GPIO296 GPIO I/O
Freescale Semiconductor

297 D_OE_GPIO297 P D_OE EBI output enable O F VDDE10 —/Up —/Up — P23
A1 — — —
A2 — — —
G GPIO297 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
298 D_TS_GPIO298 P D_TS EBI transfer start O F VDDE9 —/Up —/Up — AE9
A1 — — —
A2 — — —
G GPIO298 GPIO I/O

299 D_ALE_GPIO299 P D_ALE EBI Address Latch Enable O F VDDE10 —/Up —/Up — P24
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO299 GPIO I/O

300 D_TA_GPIO300 P D_TA EBI transfer acknowledge I/O F VDDE9 —/Up —/Up — AF9
A1 — — —
A2 — — —
G GPIO300 GPIO I/O

301 D_CS1_GPIO301 P D_CS1 EBI chip select O F VDDE9 —/Up —/Up — AB10
A1 — — —
A2 — — —
G GPIO301 GPIO I/O
302 D_BDIP_GPIO302 P D_BDIP EBI burst data in progress O F VDDE8 —/Up —/Up — M2
A1 — — —
A2 — — —
G GPIO302 GPIO I/O

303 D_WE2_GPIO303 P D_WE2 EBI write enable O F VDDE8 —/Up —/Up — N2

A1 — — —
A2 — — —
G GPIO303 GPIO I/O
101
 Table 39. Signal Properties and Muxing Summary (continued)
102

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
304 D_WE3_GPIO304 P D_WE3 EBI write enable O F VDDE8 —/Up —/Up — N3
A1 — — —
A2 — — —
G GPIO304 GPIO I/O

305 D_ADD9_GPIO305 P D_ADD9 EBI address bus O F VDDE8 —/Up —/Up — P1

MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO305 GPIO I/O

306 D_ADD10_GPIO306 P D_ADD10 EBI address bus O F VDDE8 —/Up —/Up — P2

A1 — — —
A2 — — —
G GPIO306 GPIO I/O

307 D_ADD11_GPIO307 P D_ADD11 EBI address bus O F VDDE8 —/Up —/Up — P3

A1 — — —
A2 — — —
G GPIO307 GPIO I/O

Reset and Clocks

— RESET P RESET External reset input I MH VDDEH1 RESET/Up RESET/Up R2 N5

230 RSTOUT P RSTOUT External reset output O MH VDDEH1 RSTOUT/Low RSTOUT/ A3 A3

High

211 BOOTCFG0_IRQ2_ P BOOTCFG0 Boot configuration I MH VDDEH1 BOOTCFG/ —/Down — L4

Freescale Semiconductor

GPIO211 Down
A1 IRQ2 I
A2 — — —
G GPIO211 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
212 BOOTCFG1_IRQ3_ P BOOTCFG1 Boot configuration I MH VDDEH1 BOOTCFG/ —/Down N2 L3
GPIO212 Down
A1 IRQ3 External interrupt request I
A2 — — —
G GPIO212 GPIO I/O

213 WKPCFG_NMI_ P WKPCFG Weak pull configuration input I MH VDDEH1 WKPCFG/Up —/Up N3 M5
GPIO21310
MPC5676R Microcontroller Data Sheet, Rev. 4

A1

A2 — — —
G GPIO213 GPIO I

208 PLLCFG0_IRQ4_ P PLLCFG0 FMPLL mode configuration input I MH VDDEH1 PLLCFG/Up —/Up R3 M3
GPIO208
A1 IRQ4 External interrupt request I
A2 — — —
G GPIO208 GPIO I/O

209 PLLCFG1_IRQ5_GPIO209 P PLLCFG1 FMPLL mode configuration input I MH VDDEH1 PLLCFG/Up —/Up P2 L1
A1 IRQ5 External interrupt request I
A2 SOUTD DSPI D data output O
G GPIO209 GPIO I/O
— PLLCFG2 P PLLCFG2 FMPLL mode configuration input I MH VDDEH1 PLLCFG/ —/ P3 L2
Down Down

— XTAL P XTAL Crystal oscillator output O AE VDD33 XTAL XTAL AC26 AC26
— EXTAL P EXTAL Crystal oscillator input I AE VDD33 EXTAL EXTAL AB26 AB26

229 D_CLKOUT P D_CLKOUT EBI system clock output O F VDDE9 CLKOUT/ CLKOUT/ — AF12
Enabled Enabled

214 ENGCLK P ENGCLK EBI engineering clock output O F VDDE2 ENGCLK/ ENGCLK/ AD1 AD1
Note: EXTCLK (External clock input) Enabled Enabled
selected through SIU register)

JTAG and Nexus

(see footnote11 about resets)

— EVTI –12 EVTI Nexus event in I F VDDE2 —/Up EVTI/Up T4 V1

103
 Table 39. Signal Properties and Muxing Summary (continued)
104

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
227 EVTO –12 EVTO Nexus event out O F VDDE2 ABS/Up EVTO/HI U1 V2
(the BAM uses this pin to
select if auto baud rate is on
or off)

219 MCKO –12 MCKO Nexus message clock out O F VDDE2 O/Low Disabled13 T2 U4

220 MDO0_GPIO220 –12 MDO014 Nexus message data out O F VDDE2 See Note15 See Note15 U3 V3
A1 — — —
MPC5676R Microcontroller Data Sheet, Rev. 4

A2 — — —
G GPIO220 GPIO I/O
221 MDO1_GPIO221 – 12
MDO114 Nexus message data out O F VDDE2 O/Low —/Down U4 W6
A1 — — —
A2 — — —
G GPIO221 GPIO I/O

222 MDO2_GPIO222 – 12
MDO214 Nexus message data out O F VDDE2 O/Low —/Down V1 V4
A1 — — —
A2 — — —
G GPIO222 GPIO I/O
–12 14
223 MDO3_GPIO223 MDO3 Nexus message data out O F VDDE2 O/Low —/Down V2 V5
A1 — — —
A2 — — —
G GPIO223 GPIO I/O
75 MDO4_GPIO75 –12 MDO414 Nexus message data out O F VDDE2 O/Low —/Down V3 W1
Freescale Semiconductor

A1 — — —
A2 — — —
G GPIO75 GPIO I/O
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
76 MDO5_GPIO76 –12 MDO514 Nexus message data out O F VDDE2 O/Low —/Down V4 W2
A1 — — —
A2 — — —
G GPIO76 GPIO I/O

77 MDO6_GPIO77 – 12
MDO614 Nexus message data out O F VDDE2 O/Low —/Down W1 W3
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO77 GPIO I/O

78 MDO7_GPIO78 – 12
MDO714 Nexus message data out O F VDDE2 O/Low —/Down W2 Y1
A1 — — —
A2 — — —
G GPIO78 GPIO I/O

79 MDO8_GPIO79 –12 MDO814 Nexus message data out O F VDDE2 O/Low —/Down W3 W5
A1 — — —
A2 — — —
G GPIO79 GPIO I/O
80 MDO9_GPIO80 – 12
MDO914 Nexus message data out O F VDDE2 O/Low —/Down Y1 Y2
A1 — — —
A2 — — —
G GPIO80 GPIO I/O

81 MDO10_GPIO81 – 12
MDO1014 Nexus message data out O F VDDE2 O/Low —/Down Y2 Y3
A1 — — —
A2 — — —
G GPIO81 GPIO I/O
105
 Table 39. Signal Properties and Muxing Summary (continued)
106

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
82 MDO11_GPIO82 –12 MDO1114 Nexus message data out O F VDDE2 O/Low —/Down Y3 Y4
A1 — — —
A2 — — —
G GPIO82 GPIO I/O

231 MDO12_GPIO231 – 12
MDO1214 Nexus message data out O F VDDE2 O/Low —/Down AA1 Y5
MPC5676R Microcontroller Data Sheet, Rev. 4

A1 — — —
A2 — — —
G GPIO231 GPIO I/O

232 MDO13_GPIO232 – 12
MDO1314 Nexus message data out O F VDDE2 O/Low —/Down AA2 AA1
A1 — — —
A2 — — —
G GPIO232 GPIO I/O

233 MDO14_GPIO233 –12 MDO1414 Nexus message data out O F VDDE2 O/Low —/Down AA3 AA2
A1 — — —
A2 — — —
G GPIO233 GPIO I/O
234 MDO15_GPIO234 – 12
MDO1514 Nexus message data out O F VDDE2 O/Low —/Down Y4 AA3
A1 — — —
A2 — — —
G GPIO234 GPIO I/O

224 MSEO0 – 12
MSEO014 Nexus message start/end out O F VDDE2 O/Low MSEO/HI U2 U6
Freescale Semiconductor

225 MSEO1 – 12
MSEO114 Nexus message start/end out O F VDDE2 O/Low MSEO/HI T3 U5
226 RDY –12 RDY Nexus ready output O F VDDE2 O/Low RDY/HI R4 U3
12
— TCK – TCK JTAG test clock input I F VDDE2 TCK/Down TCK/Down AB2 AB2
12
— TDI – TDI JTAG test data input I F VDDE2 TDI/Up TDI/Up AC2 AC2

228 TDO –12 TDO JTAG test data output O F VDDE2 TDO/Up TDO/Up AB1 AB1
12
— TMS – TMS JTAG test mode select input I F VDDE2 TMS/Up TMS/Up AB3 AB3
 Table 39. Signal Properties and Muxing Summary (continued)
Freescale Semiconductor

GPIO/PCR1
Package

Pad Type5
Direction

Voltage6
State

P/A/G3
2 4 State during Location
Signal Name Function Function Summary after
RESET7
RESET8

416

516
— JCOMP –12 JCOMP JTAG TAP controller enable I F VDDE2 JCOMP/Down JCOMP/Down R1 U2

— TEST — TEST Test mode select (not for customer I F VDDEH1 TEST/Down TEST/Down B4 B4
use)

— VDDSYN — VDDSYN Clock synthesizer power input I/O VDDE VDDSYN VDDSYN VDDSYN AD26 AD26

— VSSSYN — VSSSYN Clock synthesizer ground input I VSSE VDDSYN VSSSYN VSSSYN AA26 AA26

— VSTBY — VSTBY SRAM standby power input I VHV VDDEH1 VSTBY VSTBY M4 M4
MPC5676R Microcontroller Data Sheet, Rev. 4

— REGSEL — REGSEL Selects regulator mode I AE VDDREG REGSEL REGSEL W23 W23
(Linear/Switch mode)

— REGCTL — REGCTL Regulator controller output to O AE VDDREG REGCTL REGCTL Y26 Y26
base/gate of power transistor
— VSSFL — VSSFL Tie to VSS I VSS VDDREG VSSFL VSSFL AB25 AB25

— VDDREG — VDDREG Source voltage for on-chip regulators I VDDINT VDDREG VDDREG VDDREG AA25 AA25
and Low voltage detect circuits
1
The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not
have GPIO functionality, this number is the PCR number.
2
The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices
and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.
3
P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.
4 Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions
are designated in the PA field of the SIU_PCRn registers except where explicitly noted.
5 MH = High voltage, medium speed
F = Fast speed
FS = Fast speed with slew
AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)
VHV = Very high voltage
6 VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V
(+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.
7 All pins are sampled after the internal POR is negated. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak
pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side
of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down
enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled.
8 The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin
are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.
107
 9
During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the
Freescale Semiconductor

system clock propagates through the device.

10 NMI function is selected using the SIU_IREER/SIU_IFEER registers and has priority over any other function on this pin.
11 Nexus reset is different than system reset; MDO0-11 are enabled in RPM or FPM trace modes, while MDO12-15 are enabled in FPM trace mode only. MSEO

and MCKO are also dependent on trace (RPM or FPM) being enabled.
12 The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU

values have no effect on the function of these pins once enabled.

13 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register).
14 Do not connect pin directly to a power supply or ground.
15 While JCOMP is negated, the MDO0 pad is pulled up because of the default values in its SIU PCR. When JCOMP is asserted, the MDO0 pad is enabled as an

output and goes low when the system clock is present.

MPC5676R Microcontroller Data Sheet, Rev. 4
108
 Revision History

Appendix B Revision History

Table 40 describes the changes made to this document between revisions.
Table 40. Revision History

Revision Date Description

Rev 1 5 Aug 2011 Initial customer release

Rev 2 21 Dec 2011 Added information about specs 1a through 1d in the PMC Electrical Specifications table.

Updated the footnote reference (changed from 13 to 14) of spec 18 of the PMC Electrical
Specifications table.

Updated the Operating Current 5.0 V Supplies @ fsys = 180MHz VDDA Max value
(changed from 30 to 50).

Updated footnote 1 of the VDD33 Pad Average DC Current table (changed IDDE to
IDD33).

Updated the pF value of 11 SRC/DSC Fast with Slew Rate (changed from 2.6 to 200) in
the Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V) table.

Added a footnote for ANA0-ANA7 (9) functions in the “Signal Properties and Muxing
Summary” table.

Added a footnote for MDO0-MDO15 (14) and MSEO0 functions in the “Signal Properties
and Muxing Summary” table.

Updated figure numbers 25, 27, 29, and 31: Added specs 1-4.

Changed the title of the “PFCPR1 Settings” table to “BIUCR1/BIUCR3”.

Added a new row “Load” under “Termination” in the “DSPI LVDS Pad Specification” table.

Updated the “Max” and “Typical” values of “Delay, Z to Normal”, “Rise/Fall Time”, and “Data
Frequency” in the “DSPI LVDS Pad Specification” table.

Changed “VDDE” to “VDDEH” in footnote 10 of the “DC Electrical Specifications” table.

Made the following changes in the “DSPI Timing” table:

• Update the minimum peripheral bus frequencies for “Data Setup Time for Inputs” and
“Data Hold Time for Outputs”.
• Updated the maximum peripheral bus frequencies for “Data Valid (after SCK edge)”.
• Added “Master (LVDS)” information for “Data Valid (after SCK edge)” and “Data Hold
Time for Outputs”.

Changed the minimum voltage value of the “I/O Supply Voltage (fast I/O pads)” from
“1.62 V” to “3.0 V” in the “DC Electrical Specifications” table.

Changed “VDDE” values from “1.62 V to 1.98 V” to “3.0 V to 3.6 V” in footnote 1 of the “Pad
AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V)” table.

Removed voltage ranges “1.62 V–1.98 V” and “2.25 V–2.75 V” from “Fast I/O Weak Pull
Up/Down Current” in the “DC Electrical Specifications” table.

MPC5676R Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor 109
Revision History

Table 40. Revision History (continued)

Revision Date Description

Rev 3 10 August 2012 Added minimum and maximum “Nominal bandgap reference voltage” values in the “PMC
Electrical Specifications” table.
Updated the maximum “Medium I/O Output Low Voltage” value (changed from 0.2 x VDDEH
to 0.2 x VDDEH and 0.15 x VDDEH ) in the “DC Electrical Specifications” table, moved
reference to the footnote 10 (IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O
with VDDEH = 4.5 V; IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDEH
= 3.0 V) to “0.2 x VDDEH”, and added a new footnote 11(IOL_S=2 mA) to “0.15 x VDDEH”.
Updated footnote9 (IOH_F = {12,20,30,40} mA and IOL_F = {24,40,50,65} mA for
{00,01,10,11} drive mode with VDDE = 3.0 V): Removed “IOH_F = {7,13,18,25} mA and
IOL_F = {18,30,35,50} mA for {00,01,10,11} drive mode with VDDE = 2.25 V;
IOH_F = {3,7,10,16}mA and IOL_F = {12,20,27,35} mA for {00,01,10,11} drive mode with
VDDE = 1.62 V”.
Added minimum and maximum values to all rows of the “Power Management Control
(PMC) Specification” table.
Updated the “Accuracy” temperature values in the “Temperature Sensor Electrical
Specifications” table: Changed “–40 C to 100 C to 40 C to 150 C, removed the
correspnding “Typ” value, removed “100 C to 150 C, and added minimum (10) and
maximum (+10) values.
Added a new section “ADC Internal Resource Measurements” and moved “Power
Management Control (PMC) Specification”, “Standby RAM Regulator Electrical
Specifications”, “ADC Band Gap Reference / LVI Electrical Specifications”, and
“Temperature Sensor Electrical Specifications” tables to the section.
Changed “Minimum Data Retention at 25 °C ambient temperature” to “Minimum Data
Retention at 85 °C ambient temperature” in the “Flash EEPROM Module Life” table.
Added the following note after “Flash Program and Erase Specifications (Pending Si
characterization)” table in the “C90 Flash Memory Electrical Characteristics” section:
“The low, mid, and high address blocks of the flash arrays are erased (all bits set to 1)
before leaving the factory.
Updated the “DSPI LVDS Pad Specification” table: Changed maximum “Load” value from
“25” to “32”; minimum values for “Differential Output Voltage SRC=0b00 or 0b11,
SRC=0b01, SRC=0b10” from “150, 90, 160” to “215, 170, 260”; “Transmission lines
(Differential) to “Termination Resistance”; “Zc” to “RLoad”; and added the following
footnote: “The termination resistance spec is not meant to specify the receiver
termination requirements. They are there to establish the measurement criteria for the
specs in this table. As per the TIA/EIA-644A standard, the LVDS receiver termination
resistance can vary from 90 to 132  .

Rev 4 21 January 2016 Added a table “Flash Memory AC Timing Specifications”.

Updated the min and max values from -10 and +10 to -20 and +20 for “Accuracy” in the
“Temperature Sensor Electrical Specifications” table.

MPC5676R Microcontroller Data Sheet, Rev. 4

110 Freescale Semiconductor
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Document Number: MPC5676R

Rev. 4
16 Feb 2016