EEPROM Technology

ROCHESTER INSTITUTE OF TECHNOLOGY

MICROELECTRONIC ENGINEERING

CMOS Process Variations

EEPROM Fabrication Technology

Dr. Lynn Fuller

Webpage: http://people.rit.edu/lffeee
Microelectronic Engineering
Rochester Institute of Technology
82 Lomb Memorial Drive
Rochester, NY 14623-5604
Tel (585) 475-2035
Email: Lynn.Fuller@rit.edu
Department Webpage: http://www.microe.rit.edu

2-22-2012 EEPROM.PPT
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© February 22, 2012 Dr. Lynn Fuller, Professor Page 1

 EEPROM Technology

OUTLINE

Introduction
Tunneling Gate Oxide EEPROM
Programming
Reading
Test Specification/Results
Fowler-Nordheim Tunneling
Process Variation
Tunnel Oxide Recipe
Test Chip Layout
Step-by-Step Process

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 EEPROM Technology

INTRODUCTION

In certain applications, data must be electrically entered and erased from Read
Only Memory (ROM). The procedure can involve the entire ROM sections or
one memory cell at a time. From the various technologies available, we have
chosen the design of a FLOTOX EEPROM (FLOating-gate Tunneling Oxide
Electrically Erasable Programmable ROM, Figure 1.

This EEPROM cell has double polysilicon gates, with the top polysilicon as the
control gate and the lower polysilicon as the floating gate. A thin tunneling
oxide is formed above the drain in the FLOTOX Transistor.
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 EEPROM Technology

TUNNELING GATE OXIDE EEPROM

Another form of the FLOTOX Transistor is shown below. The

structure is simpler and smaller but is more difficult to manufacture
because of the problems associated with diffusion of phosphorous
from the gate poly through the tunnel oxide into the transistor channel
region. Most modern EEPROM devices use this structure.
Source Gate Drain

n+ n+

P-well or P substrate

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 EEPROM Technology

INTRODUCTION

The EEPROM is programmed by transferring electrons between the floating-gate

and the substrate, through the tunneling oxide, by means of Fowler-Nordheim
tunneling. There are two modes of programming the EEPROM: write and erase.
First, in the write mode, the floating-gate is charged negatively by electrons that
tunnel from the drain to the floating gate. The charging is done by applying a
+15V voltage to the control gate and connecting both the drain and source to
ground.

The negative charge stored on the floating gate has the effect of shifting the
threshold voltage towards a more positive value. When the floating gate is
charged, the normal +5V applied to the control gate during a read operation will
not be sufficient for the transistor to conduct channel current. Only when the
floating gate is uncharged, will the transistor be able to conduct with +5V on the
control gate.

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 EEPROM Technology

PROGRAMMING THE EEPROM CELL

0V Bit 15V Bit 15V Bit

Word Word Word
15V 15V 0V

Ctrl Ctrl Ctrl

15V 0V 0V

Precharge Floating Write a 0 Write a 1

Gate with Electrons Remove Electrons Leave Electrons
From Floating Gate on Floating Gate

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 EEPROM Technology

READING THE CELL

5V
If the floating gate is charged with
electrons the 5 volts on the control line
will not be enough to turn that transistor R
on. Thus the output will be high. Bit
Word Line
5V
If the floating gate is uncharged with
electrons the 5 volts on the control line
will turn that transistor on. Thus the Control
output will be low. 5V

Read Output
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 EEPROM Technology

TEST SPECIFICATION

Specification
Can FLOTOX Transistor be programmed
Charge the Floating Gate
Measure the subthreshold characteristics
Discharge the Floating Gate
Measure the subthreshold characteristics
Can the FLOTOX Transistor hold the charge
Charge the Floating Gate
Measure the subthreshold characteristics
Wait 1hours, 10 hours, 100 hours, 1000hours
Measure the subthreshold characteristics
Can the FLOTOX Transistor be cycled many times
How much time does it take to charge and discharge
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 EEPROM Technology

FOWLER-NORDHEIM TUNNELING

J = C1 Ec2 exp(-Eo/Ec) VP
CG
C1 = q3 m / (8πhφb m*) VFG =
= 9.625E-7 A/V2 Vp C G /(CG + CFG)
Ec = VFG/tox CFG
Eo = 8π(2m)1/2 φb3/2 /(3hq)

Example: let CFG=0.3 pF, CG=0.2 pF, Vp=25 volts, tox = 100 Å, m*=.5me , φb = 3.2
where me=9.11E-31, h=(6.625E-34)/2π, q=1.6E-19

so Eo=2.765E8 V/cm and Ec = 10/100E-8 V/cm

J = 9.625E-7 (Ec)2 exp (-2.765E8/Ec)=94.4 µA/cm2

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 EEPROM Technology

CMOS PROCESS MODIFICATIONS

The fabrication of a FLOTOX EEPROM involves a three modifications to

the present CMOS process. An additional n+ drain implant is performed
before the polysilicon layers are deposited. A thin 100 Å tunneling oxide is
grown above the additional n+ implant region. A second polysilicon layer is
deposited for the control gate.

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 EEPROM Technology

TUNNEL OXIDE RECIPE FOR ~120 Å SiO2

Step Gas Flow Temperature Time Boat

0 Load Tube N2 @ 15 lpm 650 °C ? Out
1 Push N2 @ 15 lpm 650 °C 15 min In
2 Stabilization N2 @ 15 lpm 650 °C 15 min
3 Ramp Up N2 @ 15 lpm 650 to 950 °C 30 min
4 First Oxide N2 @ 15 lpm + O2 @ 5 lpm 950 °C 15 min
5 First Anneal N2 @ 15 lpm 1050 °C 30 min
6 Ramp Down N2 @ 15 lpm 950 °C 20 min
7 2nd Oxide N2 @ 15 lpm + O2 @ 5 lpm 950 °C 10 min
8 2nd Anneal N2 @ 15 lpm 950 °C 30 min
9 Ramp Down N2 @ 15 lpm 950 to 650 °C 60 min
10 Pull N2 @ 15 lpm 650 °C 15 min Out

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 EEPROM Technology

Entire Test Chip

EEPROM Transistor
EEPROM plus Select
EEPROM Memory Array
Variable Programmable
Resistor
Binary-weighted Variable
Programmable
Resistor
Resistors
Capacitors

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 EEPROM Technology

Drain
EEPROM Transistor

Basic transistor with two layers

poly, tunnel oxide, and
3 connections.

Gate

Source
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 EEPROM Technology

Drain EEPROM Transistor + Select

Basic transistor with two layers

poly, tunnel oxide, and
4 connections.

Gate

Select

Source

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 EEPROM Technology

EEPROM

5V
R R R R

Word Line 0

Control/Read
Word Line 1

Control/Read
Word Line 2

Control/Read
Word Line 3

Control/Read
Bit Lines
B3 B2 B1 B0
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 EEPROM Technology

Memory array of four-by-

four EEPROM cells

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 EEPROM Technology

A variable programmable resistor

with equal 1000 ohm resistors in
series.

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 EEPROM Technology

A variable programmable
resistor with binary-weighted
resistors, 1k, 2k, 4k, 8k .. ..
..64 k ohms

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 EEPROM Technology

TEST RESULTS

Programmed with 3 seconds of +25 volts on gate

Erase with 4 seconds of 25 volts on the Drain
Id (Amps)
Id 10 -2
10 -3 After
Sub Vt Swing (Amps)
10 -4 erase
+ 10 -5 After
D
10 -6
G Vgs=Vds
10 -7 programming
10 -8
- 10 -9
S 10 -10
10 -11
10 -12 Vt
Vgs
Lights On
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 EEPROM Technology

REFERENCES

1. “Flash EE PROM Device”, Keith Zawadski, Senior Desing Project, May

1996.
2. “EEPROMs”, Edward Storbeck, Visiting Scholar from South Africa,
1996-97.
3. Device Electronics for Integrated Circuits, Richard S. Muller, Theodore
I. Kamins, John Wiley and Sons, Inc.
4. Nonvolatile Semiconductor Memory Technology, Edited by William D.
Brown and Joe E. Brewer, IEEE Press

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 EEPROM Technology

HOMEWORK - EEPROM

1.0 Calculate the current that would flow through a 10 by 10

µm tunnel oxide of 100 Å, at a control gate voltage of 10, 15 and
20 Volts, assume CFG=0.3pF and CG=0.2 pF

2.0 How long would it take to charge the floating gate to 2.5
volts. Assume the floating gate is 0.3 pF floating gate and the
currents are as found in problem 1.0.

3.0 Describe the exact procedure that you would use to test the
FLOTOX transistor.

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 EEPROM Technology

HOMEWORK - EEPROM

1.0 Calculate the current that would flow through a 10 by 10

µm tunnel oxide of 100 Å, at a control gate voltage of 10, 15 and
20 Volts, assume CFG=0.3pF and CG=0.2 pF

2.0 How long would it take to charge the floating gate to 2.5
volts. Assume the floating gate is 0.3 pF floating gate and the
currents are as found in problem 1.0.

3.0 Describe the exact procedure that you would use to test the
FLOTOX transistor.

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 EEPROM Technology

NOR AND NAND FLASH

Flash memory is a non-volatile computer storage that can be electrically erased and
reprogrammed. It is a technology that is primarily used in memory cards and USB flash drives
for general storage and transfer of data between computers and other digital products. It is a
specific type of EEPROM (Electrically Erasable Programmable Read-Only Memory) that is
erased and programmed in large blocks; in early flash the entire chip had to be erased at once.
Flash memory costs far less than byte-programmable EEPROM and therefore has become the
dominant technology wherever a significant amount of non-volatile, solid state storage is
needed. Example applications include PDAs (personal digital assistants), laptop computers,
digital audio players, digital cameras and mobile phones. It has also gained popularity in console
video game hardware, where it is often used instead of EEPROMs or battery-powered static
RAM (SRAM) for game save data.
Since flash memory is non-volatile, no power is needed to maintain the information stored in the
chip. In addition, flash memory offers fast read access times (although not as fast as volatile
DRAM memory used for main memory in PCs) and better kinetic shock resistance than hard
disks. These characteristics explain the popularity of flash memory in portable devices. Another
feature of flash memory is that when packaged in a "memory card," it is extremely durable,
being able to withstand intense pressure, extremes of temperature, and even immersion in water.
Although technically a type of EEPROM, the term "EEPROM" is generally used to refer
specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because
erase cycles are slow, the large block sizes used in flash memory erasing give it a significant
speed advantage over old-style EEPROM when writing large amounts of data.

Rochester Institute of Technology Wikipedia contributors. "Flash memory." Wikipedia, The Free Encyclopedia.
Microelectronic Engineering
Wikipedia, The Free Encyclopedia, 3 Feb. 2010. Web. 11 Feb. 2010.

© February 22, 2012 Dr. Lynn Fuller, Professor Page 23

 EEPROM Technology

NOR AND NAND FLASH

NOR and NAND flash differ in two important ways: the connections of the individual memory cells are
different the interface provided for reading and writing the memory is different (NOR allows random-
access for reading, NAND allows only page access) These two are linked by the design choices made in
the development of NAND flash. A goal of NAND flash development was to reduce the chip area
required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase
maximum chip capacity so that flash memory could compete with magnetic storage devices like hard
disks. NOR and NAND flash get their names from the structure of the interconnections between memory
cells. In NOR flash, cells are connected in parallel to the bitlines, allowing cells to be read and
programmed individually. The parallel connection of cells resembles the parallel connection of
transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND
gate. The series connections consume less space than parallel ones, reducing the cost of NAND flash. It
does not, by itself, prevent NAND cells from being read and programmed individually. When NOR flash
was developed, it was envisioned as a more economical and conveniently rewritable ROM than
contemporary EPROM, EAROM, and EEPROM memories. Thus random-access reading circuitry was
necessary. However, it was expected that NOR flash ROM would be read much more often than written,
so the write circuitry included was fairly slow and could only erase in a block-wise fashion. On the other
hand, applications that use flash as a replacement for disk drives do not require word-level write address,
which would only add to the complexity and cost unnecessarily. Because of the series connection and
removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60%
of the area of equivalent NOR cells (assuming the same CMOS process resolution, e.g. 130nm, 90 nm,
65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be
further reduced by removing the external address and data bus circuitry. Instead, external devices could
communicate with NAND flash via sequential-accessed command and data registers, which would
internally retrieve and output the necessary data. This design choice made random-access of NAND
flash memory impossible, but the goal of NAND flash was to replace hard disks, not to replace ROMs.
Rochester Institute of Technology
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Wikipedia contributors. "Flash memory." Wikipedia, The Free Encyclopedia. Wikipedia, The Free Encyclopedia, 3 Feb. 2010. Web. 11 Feb. 2010.
© February 22, 2012 Dr. Lynn Fuller, Professor Page 24
 EEPROM Technology

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132GBit NAND FLASH

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 EEPROM Technology

RIT EEPROM PROCESS

λ = 2.5 Micrometer Design Rules

9 Design Layers
12 Photolithography Layers
LOCOS
Extended n+ drain
n-Type Poly Floating and Control Gate
100A Tunneling Oxide over Drain

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 RIT P-WELL CMOS PROCESS
CROSSECTION
PMOSFET NINE PHOTO LEVELS
6000Å n+ Poly NMOSFET 3000Å CVD Ox
0.75 µm Aluminum

10,000Å Field Ox p+ p+ n+
p+ n+ n+
LVL 1 - WELL LVL 6 - P+ D/S
field Vt adj 8e13
p-w ell B11, 100KeV Bare
p+ D/S 2e15, 150 KeV
BF2 thru gate oxide
n+ D/S 4e15, 100KeV Vt adj nmos 1.2e12, 60 KeV
P31 thru gate Oxide B11, 1000Å Kooi Vt adj pmos 1e11, 60 keV
Blanket, 1000Å Kooi
p-w ell 4e12, 50 keV, B11, 1123 C, 20 hr LVL 2 - ACTIVE LVL 7 - N+ D/S

n-type substrate 10 ohm-cm (100)

SIX LAYOUT LEVELS
POLY LVL 3 - FIELD VT LVL 8 - CC

+V ACTIVE P SELECT

LVL 4 - NMOS VT LVL 9 - METAL

CC METAL
WELL
LVL 5 - POLY Vin Vout
 EEPROM Technology
CROSS-SECTION

EEPROM NMOS

p+ n+ n+ n+ n+

field Vt adj 8e13

p-well 4e12, 50 keV, B11, 1123 C, 20 hr B11, 100KeV Bare
n+ D/S 4e15, 100KeV
P31 thru gate Oxide
p+ D/S 4e15, 120 KeV n+ D/S 4e15, 100KeV
Vt adj blanket and nmos
BF2 into bare silicon P31 thru gate Oxide
e , 60 KeV B11, 1000Å Kooi

Three extra layers: Drain Extension

Tunnel Oxide
Floating Poly

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 EEPROM Technology
IDENTIFY AND FOUR POINT PROBE

F960417
D1
I
V

N-TYPE WAFER, 10 OHM CM

Rho = V / I * Pi / ln 2 ohm-cm

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 EEPROM Technology
ALIGNMENT OXIDE
EEPROM NMOS

Well Oxide, 5000 Å

Push, 12 in/min at 900 C, 5 lmp N2
Ramp to 1100 C, 5 lpm Dry O2
Soak for 48 min, 5 lpm wet O2
Ramp to 1000 C, 5 lpm N2
Pull, 12 in/min, 5 lpm N2
n-type substrate, 5-15 ohm-cm, (100)
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 EEPROM Technology
LEVEL 1 PHOTO - WELL
EEPROM NMOS

Photoresist

well Oxide, 5000 Å

n-type substrate, 5-15 ohm-cm, (100)

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 EEPROM Technology
OXIDE ETCH
EEPROM NMOS

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WELL IMPLANT
EEPROM NMOS

p-well implant, 4e12, 50 KeV, B11

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 EEPROM Technology
STRIP RESIST
EEPROM NMOS

p-well implant, 4e12, 50 KeV, B11

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 EEPROM Technology
POST WELL DRIVE
EEPROM NMOS

5800 Å Oxide (increase by 800 Å)

2850 Å Oxide, 4 hours Dry O2

p-well, 4e12, 50 KeV, B11, 1125 C, 20 hrs

xj = 4.5 µm
Rhos = 3000 ohms

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 EEPROM Technology
OXIDE ETCH
EEPROM NMOS

925 Å alignment step height

p-well

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 EEPROM Technology
GROW PAD OXIDE
EEPROM NMOS

Well Oxide, 500 Å p-well

Push, 12 in/min at 900 C, N2
Ramp to 1100 , Dry O2
Soak for 8 min, Dry O2
Ramp down to 1000 C, N2
Pull, 12 in/mi, N2

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 EEPROM Technology
LPCVD SILICON NITRIDE
EEPROM NMOS

p-well

500 Å Oxide
1500 Å Nitride, 810 °C, 20 min

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 EEPROM Technology
LEVEL 2 PHOTO - ACTIVE
EEPROM NMOS

10,000 Å photoresist

p-well

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 EEPROM Technology
NITRIDE PLASMA ETCH
EEPROM NMOS

p-well

SF6, 300 mTorr, 30 sccm

50 W, 60 seconds
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 EEPROM Technology
STRIP RESIST
EEPROM NMOS

p-well

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 EEPROM Technology
LEVEL 3 PHOTO - CHANNEL STOP / FIELD VT ADJ
EEPROM NMOS

p-well

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 EEPROM Technology
IMPLANT CHANNEL STOPS
EEPROM NMOS
B
11

p-well

11B, 100 keV, 8E13

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 EEPROM Technology
STRIP RESIST
EEPROM NMOS

p-well

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 EEPROM Technology
OXIDE ETCH
EEPROM NMOS

p-well

1 min in BOE HF
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 EEPROM Technology
GROW FIELD OXIDE
EEPROM NMOS

p-well

Push in 900C, ramp to 1100C in O2,

soak 210 min wet O2,
ramp down to 1000C and pull.

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 EEPROM Technology
NITRIDE ETCH
EEPROM NMOS

p-well

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 EEPROM Technology
OXIDE ETCH
EEPROM NMOS

p-well

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 EEPROM Technology
GROW KOOI OXIDE
EEPROM NMOS

p-well

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 EEPROM Technology
IMPLANT BLANKET Vt ADJ
EEPROM NMOS

11B, 60 keV, 0e12

p-well

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 EEPROM Technology
LEVEL 4 PHOTO - NMOS Vt ADJ
EEPROM NMOS

p-well

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 EEPROM Technology
IMPLANT - NMOS Vt ADJ
EEPROM NMOS

11B, 60 keV, 1.2e12

p-well

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 EEPROM Technology
STRIP RESIST
EEPROM NMOS

p-well

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 EEPROM Technology
LEVEL 5 PHOTO - N+ DRAIN
EEPROM NMOS

p-well

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 EEPROM Technology
IMPLANT N+ DRAIN
EEPROM NMOS

31P, 100 keV, 4e15

p-well

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 EEPROM Technology
STRIP RESIST
EEPROM NMOS

n+

p-well

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 EEPROM Technology
OXIDE ETCH
EEPROM NMOS

n+

p-well

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 EEPROM Technology
GROW GATE OXIDE
EEPROM NMOS

n+

TCA tube clean during warm up

Push at 900 C, 12 in/min, N2
Ramp up to 1100 °C, dry O2
Soak 1100 C, dry O2, 8 min
Pull at 900 C, 12 in/min, N2
Xox desired = 500 Å
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 EEPROM Technology
PHOTO 6 - TUNNEL OXIDE
EEPROM NMOS

n+

p-well

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ET06 NMOS
EEPROM

n+

p-well

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ET07 NMOS
EEPROM

n+

p-well

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 EEPROM Technology
OX06-TUNOX NMOS
EEPROM

n+

p-well

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 EEPROM Technology
POLYSILICON DEPOSITION
EEPROM NMOS

n+

p-well
LPCVD Polysilicon
0.6 micrometers
610 °C, 60 min

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 EEPROM Technology
POLYSILICON DOPING
EEPROM NMOS

n+

Spin-on n-type Dopant

p-well 1000 °C, 20 min, N2

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 EEPROM Technology
ET06
EEPROM NMOS

n+

Spin-on n-type Dopant

p-well 1000 °C, 20 min, N2

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 EEPROM Technology
LEVEL 5 PHOTO - POLYSILICON
EEPROM NMOS

n+

p-well

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 EEPROM Technology
PLASMA ETCH POLYSILICON
EEPROM NMOS

n+

p-well

SF6 + O2, 30 sccm + 3 sccm, 75 mT, 75 watts

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 EEPROM Technology
ET07
EEPROM NMOS

n+

p-well

SF6 + O2, 30 sccm + 3 sccm, 75 mT, 75 watts

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 EEPROM Technology
ET06 NMOS
EEPROM

n+

p-well

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 EEPROM Technology
CL01 & OX06 NMOS
EEPROM

n+

p-well

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 EEPROM Technology
CV01 NMOS
EEPROM

n+

p-well

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 EEPROM Technology
DI04 NMOS
EEPROM

n+

p-well

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 EEPROM Technology
ET06 NMOS
EEPROM

n+

p-well

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 EEPROM Technology
PHOTO 8 - SECOND GATE
EEPROM NMOS

n+

p-well

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 EEPROM Technology
ET08 NMOS
EEPROM

n+

p-well

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 EEPROM Technology
ET07 NMOS
EEPROM

n+

p-well

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 EEPROM Technology
LEVEL 6 PHOTO - P+ D/S, OXIDE ETCH
EEPROM NMOS

n+

p-well

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 79

 EEPROM Technology
ION IMPLANT P+ D/S
EEPROM NMOS

11B, keV, e

n+
4e15, 120 KeV, BF2 into bare silicon

p-well

4e15, 120 KeV, BF2 into bare silicon

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 80

 EEPROM Technology
ET07
EEPROM NMOS

p+ n+
4e15, 120 KeV, BF2 into bare silicon

p-well

4e15, 120 KeV, BF2 into bare silicon

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 81

 EEPROM Technology
LEVEL 7 PHOTO - N+ D/S
EEPROM NMOS

p+ n+
4e15, 120 KeV, BF2 into bare silicon

p-well

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 82

 EEPROM Technology
ION IMPLANT N+ D/S
EEPROM NMOS

11B, 60 keV, 1.2e12

p+ n+

p-well

4e15, 100KeV, P31 thru gate Oxide

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 83

 EEPROM Technology
ET07
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

4e15, 100KeV, P31 thru gate Oxide

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 84

 EEPROM Technology
ANNEAL, 950 °C, 30 MIN, N2
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 85

 EEPROM Technology
CVD (LTO) GLASS DEPOSITION
EEPROM NMOS

6000Å LTO CVD Oxide

p+ n+ n+ n+ n+

p-well

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 86

 EEPROM Technology
LEVEL 8 PHOTO - CONTACT CUT
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

Etch in BHF 7min

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 87

 EEPROM Technology
CONTACT CUT ETCH
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 88

 EEPROM Technology
STRIP RESIST
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 89

 EEPROM Technology
METAL DEPOSITION
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

1µm Aluminum

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 90

 EEPROM Technology
LEVEL 9 PHOTO - METAL
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

1µm Aluminum

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 91

 EEPROM Technology
ETCH METAL AND STRIP RESIST
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 92

 EEPROM Technology
SINTER
EEPROM NMOS

p+ n+ n+ n+ n+

p-well

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 93

 EEPROM Technology
EEPROM NMOS
EEPROM
1 µm Aluminum

p+ n+ n+ n+ n+

p-well 4e12, 50 keV, B11, 1123 C, 20 hr

field Vt adj 8e13
n+ D/S 4e15, 100KeV B11, 100KeV Bare
P31 thru gate Oxide

p+ D/S 4e15, 120 KeV Vt adj blanket and nmos n+ D/S 4e15, 100KeV
BF2 into bare silicon e , 60 KeV B11, 1000Å Kooi P31 thru gate Oxide

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 94

 EEPROM Technology

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 95

 EEPROM Technology

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 96

 EEPROM Technology

Rochester Institute of Technology

Microelectronic Engineering

© February 22, 2012 Dr. Lynn Fuller, Professor Page 97