NAU8220

2Vrms Audio Line Driver

1 GENERAL DESCRIPTION

The NAU8220 is a high quality 2Vrms analog input and output line driver. This device includes an integrated charge
pump enabling true ground referenced inputs and outputs and full 5.6Vpp output levels, while operating from only a
single 3.3V positive supply voltage.

Additionally, the NAU8220 includes pop/click elimination features and high immunity to power supply and other system
noise. This enables fast and efficient system integration while minimizing external component costs.

The NAU8220 is specified for operation from -40°C to +85°C, It is packaged in a cost-effective and space-saving 14-
lead SOP and TSSOP packages.

2 FEATURES

 Operating voltage: 3.0-3.6V

 Full 2Vrms output using only 3.3Vdc supply
 True Ground Referenced analog outputs
 Low cost, small footprint package
 Automatic pop/click elimination and output muting for power-on
 108dB SNR A-weighted performance
 >90dB THD+N
 114dB Mute Attenuation
 < 1mV Output Offset
 110dB channel separation at 1kHz
 Low external parts count
 High system noise immunity
 Packages: Pb free 14-pin SOP and TSSOP
 Operating temperature range: -40 to +85°C
 ±8 kV HBM protection on line outputs

NAU8220 Datasheet Rev2.0 Page 1 of 21 Jun, 2012

3 Block diagram

RINN

RINP
ROUT

CP
MUTEB Mute Charge
Logic CN
Pump

VEE
LINP
LINN
LOUT

NAU8220

4 Pin Configuration

1 RINP LINP 14

2 RINN LINN 13

3 ROUT LOUT 12

4 GND NAU8220 UVP 11

5 MUTEB GND 10

6 VEE VDD 9

7 CN CP 8

NAU8220 Datasheet Rev2.0 Page 2 of 21 Jun, 2012

5 Pin Description

Pin No. Pin Name Type Description

1 RINP AI Right Channel Positive Input
2 RINN AI Right Channel Negative Input
3 ROUT O Right Channel Line Output

4 GND P Ground
5 MUTEB I Mute Bar
6 VEE IO Charge Pump Decoupling Output (Negative Voltage)
7 CN IO Charge Pump Capacitor Negative Node
8 CP IO Charge Pump Capacitor Positive Node
9 VDD P Positive Voltage Supply
10 GND P Ground
11 UVP I Under Voltage Protection
12 LOUT O Left Channel Line Output
13 LINN AI Left Channel Negative Input
14 LINP AI Left Channel Positive Input

Table 1 Pin Description

NAU8220 Datasheet Rev2.0 Page 3 of 21 Jun, 2012

 6 Table of Contents

1 GENERAL DESCRIPTION .................................................................................................................................1

2 FEATURES .........................................................................................................................................................1
3 BLOCK DIAGRAM .............................................................................................................................................2
4 PIN CONFIGURATION .......................................................................................................................................2
5 PIN DESCRIPTION .............................................................................................................................................3
6 TABLE OF CONTENTS ......................................................................................................................................4
7 ABSOLUTE MAXIMUM RATINGS .....................................................................................................................5
8 RECOMMENDED OPERATING CONDITIONS ..................................................................................................5
9 ELECTRICAL CHARACTERISTICS ..................................................................................................................6
10 FUNCTIONAL DESCRIPTION ............................................................................................................................7
11 AMPLIFIER CIRCUITS .......................................................................................................................................8
12 LOW PASS FILTER CIRCUIT ............................................................................................................................9
13 TYPICAL APPLICATION DIAGRAM ................................................................................................................ 12
14 TYPICAL CHARACTERISTICS ........................................................................................................................ 14
15 PACKAGE SPECIFICATION ............................................................................................................................ 17
15.1 SOP-14 Package ....................................................................................................................................... 17
15.2 TSSOP-14 Package (14L 4.4X5.0 MM^2) .................................................................................................. 18
16 ORDERING INFORMATION ............................................................................................................................. 19
IMPORTANT NOTICE ................................................................................................................................................. 21

NAU8220 Datasheet Rev2.0 Page 4 of 21 Jun, 2012

 7 Absolute Maximum Ratings

DESCRIPTION SYMBOL CONDITION MINIMUM MAXIMUM UNIT

VDD supply voltage VDD VDD−GND -0.3 +4.0 V
Digital Input Voltage
DVIN DVIN− GND GND – 0.3 VDD + 0.30 V
range
Analog Input Voltage AVIN AVIN− VEE VEE – 0.3 VDD + 0.30 V
Operating
TA -40 +85 °C
Temperature
Storage Temperature Tst -65 +150 °C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such
Conditions may adversely influence product reliability and result in failures not covered by warranty. Follow IC
handling procedures to avoid ESD damage.

8 Recommended Operating Conditions

DESCRIPTION SYMBOL MINIMUM TYPICAL MAXIMUM UNIT

Supply voltage VDD 3.0 3.3 3.6 V
Ground GND 0 V

NAU8220 Datasheet Rev2.0 Page 5 of 21 Jun, 2012

9 Electrical Characteristics
Test Conditions VDD = 3.3V, TA = +25°C, 1 V rms 1 kHz signal, R1 (IN) = 15kΩ, R2 (FB) =
30kΩ, CP = 1µF, RL = 10kΩ unless otherwise stated.

Parameter Sym Test Conditions Min Typ Max Unit

Full Scale Output Voltage Vout 2.0 - Vrms
Signal to Noise Ratio SNR A-weighted 90 108 - dB

Dynamic Range DNR A-weighted 90 108 - dB

Total Harmonic Distortion + THD+N 20 kHz LPF 90 102 - dB

Noise

Power Supply Rejection Ratio PSRR VDD = 3.0 V to 3.6 V 100 dB

AC 100Hz - 90 - dB
Power Supply Rejection Ratio1
1kHz 75 - dB
PSRR
20kHz - 60 - dB
Channel Separation 1kHZ - -110 - dB
Noise Voltage VN A-weighted - 8 - µV

Mute Noise Voltage VN A-weighted - 4 - µV

MUTEB=GND
Output Offset -1 0.5 +1 mV

Output Impedance when muted ZM MUTEB = GND 0.6 Ω

Input to output attenuation MdB MUTEB = GND 114 dB

when muted

UVP detect voltage VUVP 1.2 Volts

UVP feedback current IUVP 5 µA

Current Limit ILIMIT Output = GND 30 mA AC

Supply Current IDD VDD = 3.3 Volts 15 mA

Charge pump switching FCP Pin CP 300 kHz
frequency
Low input level VIL MUTEB 40 % VDD
High input level VIH MUTEB 60 % VDD
Input current IIN MUTEB GND or VDD -1 +1 µA

Load Resistance RL Maximum signal 600 10k Ω

Load Capacitance Cload LOUT,R OUT 0 - 200 pF

Notes
1. The performance of AC PSRR depends upon the board layout.

NAU8220 Datasheet Rev2.0 Page 6 of 21 Jun, 2012

 10 Functional Description

The NAU8220 uses charge pump mechanism to get the full output signal swing. The charge pump uses
the charge pump capacitor to put a negative voltage onto VEE, the charge pump decoupling node. An
additional capacitor is needed from VDD to GND, pin 10. A low resistance one micro-farad capacitor is
recommended for each of these capacitors. All of these connections need to be short. The negative
voltage developed on pin 6 VEE enables the outputs to swing both positive and negative from GND.

Signal gain is set by the ratio of external resistors. The input signal can be either single ended or
differential. The typical single ended application diagram is shown in figure 1 and differential in figure 2.
For single ended inputs, the signal polarity of the output is inverted. A gain of two using R1 = 15 K Ohms
and R2 = 30 K Ohms is recommended for good performance. R3 of 10 K Ohms helps to reject unwanted
signals by balancing the inputs. For larger gains, R2 can be increased. R1 can also be decreased, but 10
K Ohms is the minimum recommended. For example, a gain of three could use R1 = 10 K Ohms, R2 = 30
K Ohms, and R3 = 7.5 K Ohms. For better performance R3 and R6 should be approximately equal to
R1||R2 and R4||R5. Gains larger than ten are not recommended. Large gains will have more noise and
distortion than the nominal gain of two. The following table shows the R1 and R2 resistance values for
different gain settings.

Gain Input Resistance, R1 Feedback Resistance, R2

-1 10k Ohms 10k Ohms
-2 15k Ohms 30k Ohms
-3 10k Ohms 30k Ohms
-10 10k Ohms 100k Ohms

Table 2 Recommended resistor values for different gain settings

Load of the line driver outputs is from 600 Ohms minimum to 10 K Ohms nominal. With VDD at 3.3 Volts,
the maximum output signal is 2 Volts RMS. Capacitive loads up to 200 pF can be driven. If larger
capacitive loads such as 2.2 nF (CPC) need to be driven, then a resistance of at least 33 Ohms (RPC)
should be added in series to provide both stability and protection. RPC and CPC are resistance and
capacitance of the protection circuit as shown in Figure 1 and Figure2. If this resistor and capacitor are
added for protection, then the components need to be properly rated. For example, 100 volts rating for
the capacitor may be needed to survive an output surge.

For best output offset voltages, the inputs can be AC coupled.

Upon the application of power to the VDD pin, the part will enter into a pop reduction mode which applies
a resistive loading to the two outputs. After the VEE pin reaches more than about 1.5 Volts, a power up
sequence begins that places the outputs into the Mute condition. This condition is held until both the
MUTEB pin is held high and the UVP pin exceeds about 1.25 Volts. When the MUTEB pin rises, the
outputs will follow the input signals. This pin should not be raised until a valid signal is available. The
MUTEB pin is driven by a logic signal to GND or VDD.

The MUTE condition can be entered from normal operation by pulling MUTEB low. If power is interrupted,
the UVP pin can be used to force the part into the MUTE condition.

The UVP pin can force the part into the Mute condition when the power supply voltage drops below the
desired voltage. If this function is not needed, the UVP pin should be connected to VDD. Feed back is
provided by a nominal 5 µA current developed across the external resistors applied. The turn on voltage
sets the ratio of R11 and R12 compared to the internal 1.22 Volt reference. The formula for turn ON

NAU8220 Datasheet Rev2.0 Page 7 of 21 Jun, 2012

voltage is VON = 1.22V * (R11 + R12)/R11 and the formula for the turn off voltage is VOFF= VON - (5uA *
R12).

For example, for a turn on voltage of 3.0 Volts and a turn off voltage of 2.5 volts, the calculated resistors
are R11 = 68.5kΩ and R12 = 100kΩ, or using standard values, R11 = 68kΩ and R12 = 100kΩ.

Important note: When using a LDO, the turn-on and turn-off voltages for the UVP should be set higher
than the sum of 3.3V and the minimum required voltage drop across the LDO, to ensure proper operation.

11 Amplifier circuits
NAU8220 can be used to implement the amplifier configurations in single ended and differential mode.
The following diagram shows the NAU8220 in single ended (inverting) and differential amplifier
configuration modes. Notice the similarities between these two configurations. The differential input
function is accomplished by duplicating the values used in single ended configuration. The required gain
can be achieved by properly selecting the R1 and R2 values as per the Table 2.

An ac coupling capacitor (Cin) is used to block the dc content from the input source. The input resistance
of the amplifier (Rin) together with the Cin will act as a high pass filter. So depending on the required cut
off frequency the Cin can be calculated by using the following formula

𝐶𝐶𝐶𝐶𝐶𝐶 = 1/2𝜋𝜋𝜋𝜋𝜋𝜋𝜋𝜋𝜋𝜋𝜋𝜋 where 𝑓𝑓𝑓𝑓 is the desired cut off frequency of the High pass filter.

R2

Input -
R1
Cin
NAU8220 Output

Rin(Input Resistance)

Inverting Amplifier Configuration

NAU8220 Datasheet Rev2.0 Page 8 of 21 Jun, 2012

 R2

Cin
R1

Input- -

NAU8220
Output
Cin
R1
Input+ +

R2

Differential Amplifier Configuration

12 Low Pass Filter Circuit

Many of the today’s Digital to Analog Converters (DACs) requires low pass filter circuit to remove the out
of band noise produced by the sigma-delta modulator. Most commonly used filter is multiple feedback
(MFB) 2nd order low pass filter. The advantage of the MFB filter is, it requires fewer components
compared to the other filter configurations. The following diagrams show the 2nd order Low pass filter in
single ended and differential mode.

The transfer function for the MFB filter (single ended mode) is

1
𝑉𝑉𝑉𝑉 𝐶𝐶1𝐶𝐶2𝑅𝑅1𝑅𝑅3
= − 1 1 1 1 1
𝑉𝑉𝑉𝑉 𝑆𝑆² + 𝑆𝑆 � � � + + � + ( )
𝐶𝐶2 𝑅𝑅1 𝑅𝑅2 𝑅𝑅3 𝐶𝐶1𝐶𝐶2𝑅𝑅3𝑅𝑅2

By comparing this equation with following the standard 2nd order Low pass filter equation, the component
values can be calculated for a given cut off frequency (𝑓𝑓𝑓𝑓) and 𝑄𝑄 (Quality factor) value.

NAU8220 Datasheet Rev2.0 Page 9 of 21 Jun, 2012

 𝑉𝑉𝑉𝑉 (2𝜋𝜋𝜋𝜋𝜋𝜋)2 𝐾𝐾
=
𝑉𝑉𝑉𝑉 𝑆𝑆 2 + 2𝜁𝜁(2𝜋𝜋𝜋𝜋𝜋𝜋)𝑆𝑆 + (2𝜋𝜋𝜋𝜋𝜋𝜋)²

Where 𝑄𝑄(𝑄𝑄𝑄𝑄𝑄𝑄𝑄𝑄𝑄𝑄𝑄𝑄𝑄𝑄 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓) = 1/2𝜁𝜁(𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟)

𝑅𝑅2
𝐾𝐾(𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺) = − 𝑅𝑅1

R2

C1

R3

Input -
R1
Cin
NAU8220 Output
C2

Single ended 2nd order Low pass filter

Example1: Design a second order single ended MFB Low pass filter with following specifications. Cut off
Frequency = 50 kHz, Quality factor, Q= 0.707 and Gain, K = -2.

Step 1: Find R1 and R2 depending on the gain. By assuming R1 = 10kOhms and using the equation
𝑅𝑅2
𝐾𝐾 = − 𝑅𝑅1 the value of the R2 = 20kOhms.

NAU8220 Datasheet Rev2.0 Page 10 of 21 Jun, 2012

 2𝜋𝜋𝜋𝜋𝜋𝜋 1 1 1 1
Step2: Using the equation = ( )( + + ) , Calculate R3 by assuming C2 = 1000pF
𝑄𝑄 𝐶𝐶2 𝑅𝑅1 𝑅𝑅2 𝑅𝑅3

R3 = 3.3kOhms

1
Step3: Using the equation(2𝜋𝜋𝜋𝜋𝜋𝜋)2 = 𝐶𝐶1𝐶𝐶2𝑅𝑅3𝑅𝑅2, the C1 = 150pF

Example2: Design a second order differential mode MFB Low pass filter with following specifications. Cut
off Frequency = 50 kHz, Quality factor, Q= 0.707 and Gain, K = -2.

The differential mode configuration can be achieved by duplicating the above example 1 values except
the C2. The C2 value in this configuration is half of the value of the single ended configuration.

R2

C1

Cin
R1 R3

Input- -
C2
NAU8220
Output
Cin R1 R3

Input+ +

R2 C1

Differential 2nd order Low pass filter

NAU8220 Datasheet Rev2.0 Page 11 of 21 Jun, 2012

13 Typical Application Diagram

Right Left
Input Input
R3 R6
C1 C2
1 RINP LINP 14
R1 R4
2 RINN 13
R2
LINN R5

3 ROUT LOUT 12
2.2 nF(Cpc) 2.2 nF (Cpc)
33 (Rpc) 33 (Rpc)
Right Output 4 GND NAU8220 UVP 11 Left Output

5 MUTEB GND 10

R11
6 VEE VDD 9
MUTEB 1uF
1uF R12
logic input
7 CN CP 8

Linear low System

Dropout
Regulator Supply
10 uF
1uF

R1 = R4 = 15 KOhms
R2 = R5 = 30 KOhms
R3 = R6 = 10 Kohms
C1 = C2 = 2.2 uF

Figure 1 Single Input Amplifier Configuration

NAU8220 Datasheet Rev2.0 Page 12 of 21 Jun, 2012

 Right Left
Input Input
- + + -

C1 C2 C3 C4

R1 R3 R7 R5

R4 R8
1 RINP LINP 14

2 RINN 13
R2
LINN R6

3 ROUT LOUT 12
2.2 nF (Cpc) 33 (Rpc) 2.2 nF (Cpc)
33 (Rpc)
Right Output 4 GND NAU8220 UVP 11 Left Output

5 MUTEB GND 10

R11
MUTEB Logic 6 VDD 9
1uF VEE
Input 1uF R12
7 CN CP 8
System
Linear low
Dropout Supply
Regulator

10 uF
1uF

R1 = R3 = R5 = R7= 15 KOhms
R2 = R4 = R6 = R8 = 30 KOhms
C1 = C2 = C3 = C4 = 2.2 uF

Figure 2 Differential Input Amplifier Configuration

NAU8220 Datasheet Rev2.0 Page 13 of 21 Jun, 2012

14 Typical Characteristics
Test Conditions VDD = 3.3V, TA = +25°C, 1kHz signal, R1 (IN) = 15kΩ, R2 (FB) = 30kΩ, CP =
1µF, RL = 10kΩ, CPC = 2200pF, RPC= 33 Ohms unless otherwise stated.

Total Harmonic Distortion + Noise Vs Frequency

RL = 10k Ohms
RL= 600 Ohms With out RPC and CPC
0.01
2V RMS 0.01
2V RMS
0.008 1V RMS
0.008 1V RMS

0.006
THD+N (%)

0.006

0.004 THD+N (%)

0.004

0.002 0.002

0 0
10 100 1000 10000 100000 10 100 1000 10000 100000
Frequency (Hz) Frequency (Hz)

Total Harmonic Distortion + Noise Vs Output Voltage

RL=10k Ohms, F = 100 Hz RL=600 Ohms, F= 100 Hz
100 100

10 10

1 1
THD+N (%)

THD+N (%)

0.1 0.1

0.01 0.01

0.001 0.001

0.0001 0.0001
0 1 2 3 0 1 2 3
Vout RMS (V) Vout RMS (V)

NAU8220 Datasheet Rev2.0 Page 14 of 21 Jun, 2012

 RL=10k Ohms, F = 1kHz RL=600 Ohms, F = 1kHz
100 100

10 10

1 1
THD+N (%)

THD+N (%)
0.1 0.1

0.01 0.01

0.001 0.001

0.0001 0.0001
0 1 2 3 0 1 2 3
Vout RMS (V) Vout RMS (V)

RL=10k Ohms, F = 10kHz RL=600 Ohms, F = 10kHz

100 100

10 10

1 1
THD+N (%)

THD+N (%)

0.1 0.1

0.01 0.01

0.001 0.001

0.0001 0.0001
0 1 2 3 0 1 2 3
Vout RMS (V) Vout RMS (V)

NAU8220 Datasheet Rev2.0 Page 15 of 21 Jun, 2012

Cross talk Vs Frequency

Crosstalk
0
Right->Left
-20
Left -> Right
-40

-60
Crosstalk (dB)

-80

-100

-120

-140

-160
10 100 1000 10000 100000
Frequency (Hz)

NAU8220 Datasheet Rev2.0 Page 16 of 21 Jun, 2012

15 Package Specification
15.1 SOP-14 PACKAGE

14 8 c

E HE

1 7
O
D 0.25

Y
SEATING PLANE e GAUGE PLA
b A1

Cont r ol demens i ons ar e i n mi l met er s .

DIMENSION IN MM DIMENSION IN INCH

SYMBOL
MIN. MAX. MIN. MAX.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
b 0.33 0.51 0.013 0.020
c 0.19 0.25 0.008 0.010
E 3.80 4.00 0.150 0.157
D 8.55 8.75 0.337 0.344
e 1.27 BSC 0.050 BSC
HE 5.80 6.20 0.228 0.244
Y 0.10 0.004
L 0.40 1.27 0.016 0.050
θ 0 8 0 8

NAU8220 Datasheet Rev2.0 Page 17 of 21 Jun, 2012

 15.2 TSSOP-14 PACKAGE (14L 4.4X5.0 MM^2)

NAU8220 Datasheet Rev2.0 Page 18 of 21 Jun, 2012

16 Ordering Information

Part Number Dimension Package Package

Material
NAU8220SG 8.75x4 mm SOP-14 Green
NAU8220WG 5x4.4 mm TSSOP-14 Green

NAU8220 _ _

Package Material:
G = Pb-free Package

Package Type:
S = 14-Pin SOP Package
W = 14-Pin TSSOP Package

NAU8220 Datasheet Rev2.0 Page 19 of 21 Jun, 2012

Revision History
VERSION DATE PAGE DESCRIPTION
Added application circuit diagram with differential
1.8 Feb 2012 9
configuration.
1.9 March 2012 14 Added TSSOP package dimensions information
1. Corrected Application circuit diagram. Changed value
of input DC blocking capacitors to 2.2 uF.
6,8-
2.0 June, 2012 2.Added Load resistance and Load capacitance column
11,12,13
in the Electrical characteristics table
3.Added amplifier circuit and 2nd order LPF circuit

NAU8220 Datasheet Rev2.0 Page 20 of 21 Jun, 2012

 Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
any malfunction or failure of which may cause loss of human life, bodily injury or severe
property damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.

NAU8220 Datasheet Rev2.0 Page 21 of 21 Jun, 2012