Combinational ircuits

A
Po
Combinational Circuit
3 ou3 FuN
adder CusFu 8dder
Cp Cn Full
adder Cino1

use as
ubtracto 's
3.1: Adders andthelr Fig. Q.2.1 4-bt parallel subtractor
4-bit parallel adder using full-adders Q.3 Draw and explaln the operation of 4-blt
a.1 Design a
subtractor. parallel adder |
3[SPPU: June-22,
Mar Makh
Ans.:
shows
Fig Q1.1 position,
least significant
diagram
the block
carry input of full-adder
for 4-bit
is adder.
maHen H
.
Ans.Hg
Ans.: Fig. Q3.1 shows 4-bit parallel adder /
subtractor circuit.
The mode input M controls the operation of the circuit. When
M 0, the circuit is an. adder, and when M
The carry output of each adder 1s connected to the -
1, the circuit
carry inpe
aTy inpu becomes a subtractor.
the next higher-order adder.
B Ag B2 2 2 A

Full
adder
oua adder
Full CouFul n Cou Full
adder adder
Out3 Cina Cou2
Full Full ina out
s
S s adder adder
Full
adder
Couo Fu
addar
S0
Fig. Q.1.1 Block diagram of 4-bit
full-adder
Q.2 Draw and write S3
the expresslon for S
using full adder. a 4-bit parallel subtract
Flg. Q.3.1 4-bit adder-subtractor
OR Draw and Each exclusive OR gate receives
explain the operation of 4-bit
-

input M and one of the inputs

Ans.: The parallel subtracto. of B. When M -
0, we have B 0 B. The full-adders
subtraction of binary value of B, the receive the
conveniently by means of numbers can be done input carry is 0 and the circuit
performs A plus B.
The
subtraction A B cancomplements.
of B and be done
.When M 1,
have B 1
we B and C 1. The B inputs are
-

by all complemented and a 1 is added through the input carry. The

adding it to A. taking the 2's comp
The 2s circuit performs the
operation A plus the 2's complement of B,
complementcomplement can ie. A - B.
and be obtained by taking the
The 1's adding one taking a.4 What is BCD
one can complement can
to theleast significant pa" bits
significant pair 4what
Decimal adder.
/ Decimal adder ? Design one digit BCD
[SPPU: Dec.-04, May-12,13, Marks 8]
be be
in the added to
Fig. Q21. the sum implemen with inverters ant

through input carry

as sho

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 Combinational Circuit. Digital Crcuits
3-4
3-3
Digital Circuits
circuit
that
adds
two BCD di
BCD digits and Combinational Circuits

is a

Ans.:A BCD adder

also in BCD. B, B B, Bg Ag Az A Ap
a sum digit :
produces
adder we require
BCTD
T o implement addition
adder for initial IC 7483
binary out 4-bit binary adder Cin
4-bit

circuit to
detect sum Inputs Output Combinational
Logic
greater
than 9 and
sSS S Y circuit SS2SSg
One

0110,
more

in the
4-bit adder
sum
to add
if sum is 00
0 0
0
1 0 Output
A-bit add
1. 0
than 9 or carry is carry
greater 0 1 0
sum
circuit to detect
The logic be 0 1 1
greater than 9 can
the 01L0
determined by simplifying
boolean expression of given 0 1 0
IC 7483
truth table. 0 1 |1|0 Cout 4-bit binary adder
(lgnored )
,S 00 01 11 10 011
1 |0 0
1 0
S3 S2 S, So
01 0 0 0 10
1 0 Fig. Q.4.1 (b) Block diagram of BCD adder
11
1 1
B3 B2 B Bo As AA Ap B BB, Bo
10 0 1110 A Az A, Ap

Y SS2+SgS
11 1 4-bit binary adder

Fig. Q4.1 (a) K-map

1 1 11 1 Out (IC74LS283)
in
COut
4-bit binary adder
IC74LS283)
n

simplification Table Q.4.1 S S SS SSS,S

Table Q4.1
shows the truth table for BCD adder.
Fig. Q4.1 (a) shows the K-map
and Fig. Q4.1 (b) shows the blocksimplification for the logic circul
(Refer Q4.1 (b) on next diagram of BCD adder.
Q.5 Design an page).
8-bit BCD adder
using 4-bit binary adder. Out 4-bit binary adder Cn0 C 4-bit binary adder
(Ignored) (IC74LS283) (IC74L$283)
Ans.: To U[SPPU: May-05, 10, 12, Marks 8] gnored

BCD adders.implement 8-bit

In cascade BCD adder we have to Digit 2
S3 S2 S
So S3 S S S
cascade 4-bit
position (digit) is connectedconnection carry
two ower
(digit). Fig. Q5.1 shows the as a carry input ofoutput of the Digit 1 Digit 0

the
block higher P0 sition
diagram of 8-bit BCD adder. Flg. Q.5.1 8-bit BCD adder using IC 74283
 Combinational.
Circuity Digital Circuits 3-6 Combinational Circuits
Dnital Cirwis bin.
converter
using
sing binary parallt
code
Er
BCD to . G is called a carry generate and it produces on carry when both
a
Q6 Designm
sdder. A and B; are one, regardless of the input carry.
Ans Add $ BCDinput is called a
.P carry propagate because it is term associated with
the propagation of the carry from G; to Ci1 Now Ci1 can be
As A Ay Ao expressed as a sum of products function of the P and G outputs
-Dit biner adder Cin 0 of all the preceding stages.
For the carriers in a four stage carry-lookahead adder
sSSS example,
are defined as follows
Excess 3 output
C GotPo Cin
Fig. Q.6.1
C G+P, C - G,+ P,G +P, Po i n
3.2: Adder
Look Ahead Carry
Q7 Explain in detail look ahead carry generator.
SPPU : Dec.-07,09, Marks 4
Ans.: One method of speeding up this process by eliminating
nter stage carry delay is called lookahead-carry addition. This =
method utilizes logic gates to look at the lower-order bits of the
Gg + Pa +Pa P2 G
augend and addend to see if a higher-order carry is to be +Pg P2 P Go +PaPa Pi P% Cin
generated. It uses two functions Carry generate arnd carry shows the general form of a carry-lookahead adder
Fig. Q7.2
propagate circuit designed in this way.
.Consider the circuit of the full adder shown in Here
we define
Fig. Q.7.1.
two hunctions Carry generate and carry propagate. Cn Carny lookahead generator
P A, B
Pn-11-1 Pn-2o2
The output sum and carry can be
expressed as
Sn-1 -2 So
1-bit -bit
adder addar addar
n-1 C
D C1
An-1n-1 An-2 Ba2
Flg. Q.7.2 General form of a carry-lookahead adder circult
Flg. Q.7.1 Full
adder circuit
QIcOD A Guide for Engineering Studens
DEcoDE
A Gulde f o r E n g i n e e r i n g Tudens
 Combinationai Circui
Digital Circuits 3-8 Combinational Circuits
Unit (ALU)
Arithmetic
Logic The output MUX (multiplexer) is controlled by S input andit
3.3: decides the final output. When S - 0, the output of arithmetic
ALU. 10, Dec.-12, Marks
short note
on
SPPU: May-05, 6] circuit is transferred as a final output; otherwise, the output of
G.8 r i t e a
logic circuit is transferred as a final output.
The arithmetic and
Unit (ALU)* ogic
Ans:Arithmetic Logic arithmetic and logical operations
ut ertorms all the
neressary
wNcn it operates
3.4 Digital Comparator
or tvo operands upon and
I t requines one Q.9 What is magnitude comparator?
produes a result.
combinational logic circuit. Ans. A magnitude comparator is a Inputs
multifunction
I t is basicall a
special combinational circuit designed
it provides select input to select the particular operation. primarily to compare the relative
the arithmetic unit of the magnitude of two binary numbers.
Arithmetic unit: The basic component of
11e can use parallel adder fo
this for Fig. Q9.1 shows the block diagram
simplest ALU s a parallel adder. of an n-bit comparator n-bit
addition and 2s complement subtraction operation. comparator
I t receives two n-bit numbers A and
unit: The logic unit consists of logic gates, such as OR gate,
Logie B as inputs and the outputs are
XOR gate AND gate and NOT gate. Proper gate is selected to
A>B, A= B and A < B.
perform desired logic operation. A>B A=8 AS
Depending upon the relative
Selection logic: The selection logic provides select inputs.
of ALU Outputs
These inputs allow us to select the operation to be performed.
magnitudes of the two number, one
Fig. Q.9.1 Block diagram of
of the outputs will be high. n-bit comparator
The Fig. Q5.1 shows the typical block diagram of ALU. Q.10 Design 2-bit comparator using gates.
Operand1 Operand2 SPPU : Dec.-12, Marks 8]

Ans.: The truth table for 2-bit is given in Table Q.10.1.

Operation
seiect Arithmetic Cout
signals
circuit Cin Inputs Outputs

A A B A BA BA<B
0 0 0 0
Operand1 Operand2 MUX -Y
0
0
Logic 0
circuit 0
0
Fig. Q.8.1 Block
diagram of a typical ALU 0 0
oBCODE
A Guide OECODE A Guide for Engineering Students
for Engineering Students
 Combinational Cireuits
Digital Circuits 3-10 Combinational Circuits

Loglc dlagram
A Ao Bo
A Ao

0
0
1

D-
Table Q.10.1
D
AS
AB
A
A<B
D-Aes
01 11 10 D»
o
D-A
ooo
Fig. Q.10.2
Fig. Q.10.1
| 3.5 Parity Generator / Checkers
K-map simplification
Q.11 What is parity generator and checker ? Show
parity generator
truth table for 3-bit message with even
(A-B) A, BB +AA B,B parity and odd parity.
SPPU : Dec.-07, Marks 6]
AA B,Bo A,A, B,o Ans.: Parity Generator and Checker: A parity bit is used for
K,5, Ao +AgP) the purpose of
information.
detecting errors during transmission of binary
+A,B, (AgBo +Ag) A parity bit is an extra bit included with a
binary message to
(A, B)A OB) make the number of 1s either odd or even.
(AB) A,
B, A, B,B,+ A,B, The message,
checked at the
including the parity bit is transmitted and then
receiving end for errors. An error is detected if the
checked parity does not correspond with the one transmitted.
The circuit that generates the
parity bit in the transmitter is called
a
parity generator and the circuit that checks the parity in the
receiver is called a parity checker.
QIcoD
A DECOD A Guide for Engineering Students
Guide for Englneering Studens
 Combinational Circuit.
Digital Circuits 3-12
Digitel C r i s
make the
the total number
tot- Combinational Circuits
bit will
addei nant
in even parit.
the
amount
3.6 Multiplexers and their use in Combinational
ot is an even
bit will make the total ns
Logic Designs, Multiplexer Trees
the added parity
i n odd panit.
Q.13 What is multiplexer ?
is an odd
amount.

message
with even parity aand odd
shows the 3-bit Ans.
Tabie Q11.I

parit odd parity bit Even parity bit

In digital systems, many times it is necessary to select single data
-bit message line from several data-input lines, and the data from the selected
data line should be on the
available The
B C circuit
output. digital
which does this task is multiplexer.
a

The selection of a particular input line is controlled by a set of

selection ines.

Data input, P2 Y (Output

ines 2": 1 -Y (Output)
Multiplexer 2:1
Multiplexer
Table Q11.1 Parity generator truth table for even and odd parity Da
Enable
Q12 Design an even parity generator with 3 message bits. input

Ans.: Reie Table Q11

P ABC +ABT+A BC+ AB C Selet inputs
(a) Block diagram of 2": 1 mutiplexer
ABC-B )+ A(B+ BC) (b) Equivalent circuit
Fig. Q.13.1
A(BC)+A(B C) Normally, there are 2" input lines and n selection lines whose bit
A(BC)+A (BOC) AB(BGC) =

combinations determine which input is selected. Therefore,

Kemap simplification
Logic diagram multiplexer is 'many into
one and it provides the digital
00 01 11 equivalent of an analog selector switch.
Q.14 Draw and explain the logic diagram of 4 : 1 ine multiplexer
Ans.:
Fig. Q.14.1 (a) shows 4-to-1 line multiplexer.

Fig. Q12.1 ta)

Simplification ch even
LD Each of the four lines, D,o to Dy is applied to
AND gate.
one input of an

parity bit Fig. Q12.1 (b) Selection lines are decoded to select a particular AND gate.

ECODE A
DECODED A Guide for Engineering Students
Guide for Engineeriug Studen
 Combinational Cireits Digital Circuits 3-14
Combinational Circuits

Show how 4-input multiplexer can be realize using 2-input

a.15
multiplexers.

to expand range of inputs for multiplexer

Ans.It is posible
the available range by interconnecting several multiplexers
beyond
-Y =
ES, S, D,+ in cascade.

ES, SD.+
ES,SD2 D D2 D Do
E S, So DD

2:1
Select (So 2:1 MUX
MUX
Y

E
S(a) Logic diagram
Fig. Q.14.1

Select (S)- 2:1

For example, when S,S, =0 1, the AND gate associated with data MUX

input D. has
of its inputs equal to 1 and the third input
two
Y
have at least one
conected to D. The other three AND gates
input equal to 0, which makes their outputs equal to 0. The OR Output
gate output is now equal to the value of D, thus we can say
data bit D, is routed to the output when S, S% = 0 1. Fig. Q.15.1
The circuit with two or more multiplexers connected to obtain the
E multiplexer with more number of inputs is known as multiplexer
10 inputs 4x1 tree.
2 -Output
MUX
1D Enable
3 Q.16 Explain the process of implementation of combinational
circuit using multiplexer.
_110 D2 S So
input Ans. Let us implement F(A, B, C) = 2m (1, 3, 5, 6) Boolean
11 D function using 4 1 multiplexer.
o xX0 Select inputs
(c) Logic symbol Step 1: Connect least significant variables as select inputs of
(b) Function table multiplexer. Here, connect C to So and B to S1
Fig. O.14.1 4 to 1 line Step 2 Derive inputs for multiplexer using implementation
multiplexer
table

OIcODED A
OECODE A Guide for Engineering Students
Gulde for Engineering Studen
 3 15
Combinafional ircuits Digital Cireuits
3 16 Combinational Circuits
Digital Cnwis
Po Stop 2: Connect the most significant select lines
4:1 MUX 5.
(S and S2) to the
MUX
row 1 stop 3:Connect the outputs Yo Y, Yz and Y of four
2 multiplexers
7
row2 S EN as data
inputs for the MUX 5, as shown in the Fig. Q.17.1.

AMostsignifice/nt A A
DIS D12 D
variebe (a) Implementation table
(b) Multiplexer Implemontatln
Fig. Q.16.1 4:1 4:1
41 4:1
MUX 1 S4 MUX 2 1S MUX 4
implementation table is MSX 3
As shown in the Fig. Q.16.1 (a)
the

the multiplexer
nder
and und them list hing
the inputs of of
but the list of all those mir those minterms
The first row lists
in two rows.
all the minterms
and the second r o w lists all the
where A is complemented
The minterms given in given in the S 4:1
MUX 5
A uncomplemented.
minterms with column is inspected separatels S2
function are circled and then each
as follows Output

I f the two minterms in a column are not circled, 0 is applied t Fig. Q.17.1
column 0).
the corresponding multiplexer input (see Q.18 Implement the following Boolean function with 8 1
1f the two minterms in a column are circled, 1 is applied to the multiplexer F(A, B, C, D) = t M (0, 3, 5, 8, 9, 10. 12. 14).
corresponding multiplexer input (see column 1). Ans.

If the minterm in the second row is circled and minterm in the

first row is not circled, A is applied to the
corresponding
multiplexer input (see column 2).
I f the minterm in the first row is circled and minterm in the
second row is not circled, A is
applied to the corresponding Do D2 D Dr
multiplexer input (see column 3).
8:1
a.17 Design 16 1 5
multiplexer using 4:1 multiplexers. AMUX
B[SPPU : May-11, Marks 8 9 10 12 O |4

Ans. : Since there are

16-inputs for the A A A A
multiplexers to satisfy input needs.multiplexers
we require
four 4: 1
The four outputs of
DS S So
4 1 multiplexers
are again multiplexed by 4 1
generate final output. to multiplexer 8 C D
Step 1:Connect the select (o) Imptemontatlon table (b) Multiplexer Implomentation
parallel.
lines (S and Sa) of four
multiplexers " Flg. Q.18.1

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A Giulde far Euglneering Studen
 Combinatlonal Clreu
-17 DigltalCirnults 3-18 Combinational Circuits
Thua
DitnlCYwits are
ipecifled,
we hw
m a x t e r m n

of
minterms,
included in the Boolean funti
instead
Here, which are not olean function
Boolean functlon with
m a x t e r m s
of
circde
implementation

Q18.1
shows the
Fig convert
code
multiplexer. to
excess-3

mplement BCD gates.

and loglc
Q.19 Deslgn and some
(SPPU : May-13, Marks i
multiplexers
dual 4: 1 19 19 13 14
for truth table of
u.
2 D 1
Table Q.34.1 of chajpter
Ans.: Reter
Excess-3 code conversion. Hota :Dot care rirterms 11, 12 an 1 a
nsidsre1 as 1,

Da 10
1D o) implementation tabe for E,
Y

Logia1 1D3
2100

202
20 D Fig. Q.19.3

203
10 11 12 1EN Q.20 Implement the following hunction using singie 8 1 MUX
FA, B, C, D) = Z m (1, 4, 6, 8, 10, 11, 13. 14)
0 1 1 2EN
D 00 LSPPU : May-15, Marks 6]
Don't care minterms 13, 14 8nd 15 are
Note : considered as logic 1.
Ans.
D Do
(a) Implementation table for Eg (b) Implementation
Implementationtable
Fig. Q.19.1

1 Do
1D1 Oo D D2 D
D2
* wwwwawww..mwww
oO 2 s MUX
Logic 1 2
Do D D2 D D4 Dg Dg D
20 A 12® 15 Logic

EO00DO
************A ***

5 6 2 D2 A A A A 1
******************** ** 2 D3
wwwwwve
13
.20
14
wwwwwwwwwwwvwewww.wwwwwve
15
EN S S
11 1 1
0

Note: Dont care minterms

SSo 8CD

10, 11 and 12 are

considered as logic 1
D Do Fig. Q.20.1
(o) Implementatlon table for E
(b) Implomentatlon
Fig. Q.19.2
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OECODE A Guide for Engineering Students
 3-19
Combinational Cireuit, wwe
Combinational Circuits
single 4:1 3-20
DcrtalCini
function
usina

(SPPU : Dec.-15, Marks UX. Digital Circuits

1
the
following

7, 10,
14)
and implement following function using 4
4, 5, a.23 Design : May-14, Marks 4]
Implement

(2, (SPPU
0.21
D)
=
Xm
multiplexer. F
= 2m (1, 3, 4, 5)
F4.
B. C,

Ans.: F 2m(1, 3, 4, 5)
Ans.

A 4:1
MUX A Do
Do D D2 D
D 4:1
8.5-AB S 0 MUX
'A A 0 O 2 D2

21315 C D
A 6 7 A
Da S So
rwwwww

1 0 A
Fig. Q.21.1 B

expression using single R..

1
the followlng logic Flg. Q.23.1
a.22 Design
+ d (12,13)
multiplexer. functions using single 8: 1 MUX :
Q.24 Implement the following
(0,2,3,6,8,9,14)
FA.B,C.D)
= Em UP [SPPU : Dec.-13, Marks 6
mM (0, 3, 5, 7, 12, 15) + d (2, 9).
f(A, B, C, D) =

Dec.-14, Marks 6]
Ans.: Implementation Table U [SPPU
www.wwww.wwAVwwwwwwww** w****v

D D4 D5 D6 D7 Ans.: f(A, B, C, D) =
TM (0, 3, 5, 7, 12, 15) + d(2, 9)
Do D, D,
- m (1, 4, 6, 8, 10, 11, 13, 14) + d (2, 9)
0 4 5 7
********eg************ttni

A 10 11 12 13 1 15
Logic 1
*****""***ervv**v**.

Do
1A A A 0 1
Note: Don't care minterms are considered as zeroes.
Do D D D3 D4 D5 Dg D7
Fig.Q.22.1 (a) Y 8 1
Implementation A 0 3 5
7 MUX

Logic 1 A D 12 15

A 1 1 A A A 1

S2 S So
8:1
MUX
TTTBCD

(a) Implementatlon table (b) Implementatlon

Fig. Q.24.1
C D

Fig. Q.22.1 (b)

OICOD udent
A Guide for Engineerngu DECODE) A Guide for Engineering Students
 Combinational reuits
21
Digital Cireuits
multiplexer
er. 3-22 Combinational Circuits
using 8 : I
F(SPPU : Dec.-19, June-22, Mar.
circuit
adder
full
.28
Imphement
The selection of specific output line is controlled
n selection lines.
by the values of

Solution Outputs The Fig. Q,26.1 shows the block diagram of a demultiplexer. It
Inputs
Sum
has one input data line, 2" output lines, n select lines and one
Carry enable input.
Cin 0
0

Data input Din

0
1:2 Data input
DEMUX

Enable-
0
0 Y
sSn-1 , s
Select inputs
(a) Block diagram (D) Equivaiant circuit
Logic 1
Fig. Q.26.1
0
Q.27 Draw and explain the logic diagram of one line to 8 line
demultiplexer.
Ans. The Fig. Q27.1 shows 1 8 demultiplexer.
-Cary 8:1 Sum
M MUX

Din
SS5,DoYo
S2 S So
TT Data
E3,5.S, PY,
AB Cin AB Cin input Din

Fig. Q.25.1
1:8
3.7: Demultiplexers and their use in Combinational DEMUX ES.5, 2oY.
Logic Designs, Demultiplexer Trees Enable ESSS DnoYs
Q.26 What is
de-multiplexer ? SS ESSS noYe
Ans.A demultiplexer is
circuit that receives
a ESS9 DngY,
single line and transmits this information on Select inputs
Enabla o-
output lines. information on one of 2" poss1 (a) Block schematic (b) Loglc diagran
Fig. Q.27.1
OECODE A Guide for Engineering Studen DECODE A Guide for Engineering Students
 3 23
Combinational Circuie Digital Crcuits 3 24
Combinational Circuits
Deeirn Cnmits
to all eight o u t p u t
has a path the Stop 2 Connect select lines B and C to select lines
data 1)n of the o output
r lines S, and S of
single input
one
only the both
7he
is
directed
to
demultiplexers, respectively.
Stop 3: Connect most significant select line (A) such that when
i n t o r m a t i o n

input select nputs.

the demultlplas.
depending
on
subtractor
using a 1: 8 lexer. A - 0 DEMUX 1 is enabled and when A 1 DEMUX 2 is -

the full subtractor.

enabled.
Q.28 Impiement
the truth
table for full
Ans.: Table shows
Outputs
Inputs
Din Din 1:4
A B B DBout
0 0
DEMUX 1
-Y2
0
Select
1 inputs
S
1
01

1 0 0 0
Dn 1:4 s
1 0 0
DEMUX 2
11 0 | 0 0
11 1 |1
Table Q.28.1 Truth table
for full-subtractor
Fig. Q.29.1 Cascading of demultiplexers
D m (1, 2, 4, 7) and Bout 2m (1, 2, 3, 7)

3.8 Decoders
Logic D a.30 What is decoder ? draw and explain a 2 to 4 line decoder.

A decoder
Ans.: is a multiple-input, multiple-output logic
which converts coded inputs into coded outputs, where the input
circuit
1:8
De-MUX
and output codes are different.

Bout
Enabie
n-data
inputs
Possible
2 S So n:2
Decoder 2" outputs
AB 5n Enable
Fig. Q.28.1 Implementation inputs

Q.29 Design 1: 8
demultiplexer using two 1 4demultiplexers. Fig. Q.30.1 General structure of decoder
Ans.: Step 1 Connect D signal to D input of both the
demultiplexers.
CECODE A Guide for Eugineeriug Studens
PECODED A Guide for Engineering Studeno
 3-25
Combinational rcuits
D g i t a l Cinwi?s
Digital Cicuits 3-26 Combinational Circuits
Outputs
Inputs logic 1. In such case to
ENAB 1,Y,Yo A- A
implement SOP function B B
0xxo o00 we have to take sum of c-
0 product terms
0 Yo AB selected
1 0 0 0
3:8
01 0 0 generated by decoder. Decoder

10 0 100 Let us see the

Implementation of

table for a
Y2AB Boolean
function F-m(1,2,3, 7 Fig. Q.31.1
Table Q.30.1 Truth
2 to 4 decoder
using 3: 8 decoder.
Ys*AB
2-to-4
T Step 1: Connect function variables as
inputs to the decoder.
Fig Q30.2 shows Enable (EN)
Step 2 Logically OR the outputs correspond to
decoder. 2 inputs are decoded obtain the
present minterms
into four outputs, each output
Fig. Q.30.22 to 4 line decoder to output.
representing one of the minterms of the 2 input variables. Q.32 Design and implement a full adder circuit
decoder. using a 3 8
The two inverters provide the complement of the inputs, and D[SPPU: Dec.-08,15, May-10, Marks 10)
each one of four AND gates generates one of the minterms. Ans.: Truth table for full adder is as shown in the Table Q32.1.
The Table Q.30.1 shows the truth table for a 2-to-4 decoder.
Inputs Outputs
f enable input is 1 (EN=1), one, and only one, of the
Y to Yy is active for a given input.
outputs A
B Cn Carry Sum
0 0 0O 0 A
The output Y is active, i.e. Yo =1 when inputs A =
B 0, the 00 1 1
A
3:8
B
output Y, is active when inputs A =0 and B =1. 01 0 Decoder Y -Cary

If enable input is 0, i.e. EN =0, then all the

01 1 1 0
outputs are 0. | 1 |0 |0 1
Q.31 Explain the
decoder with the help of
procedure
implement combination circuit using
to 10 1 Sum
example. 1 10 1
Ans. The combination of
used to implement decoder and external logic gates can be Table Q.32.1 Truth table for
single or multiple output functions. Fig. Q.32.1
When decoder full-adder
output is active high, it generates minterms Q.33
(product terms) for input variables; i.e. it makes selected write
Implement full subtractor
using a decoder (1C 74138) and
a truth table.
output SPPU : May-15, Dec.-05, 15, Marks 8]
Ans.: IC 74138 is a 3:8 decoder with active-low outputs. For
OECODL active-high outputs, we use OR gate to
implement the function. We
A Guide
for Engineering Studens
OECODE A Guide for Engineering Students
 Combinational Circit Digital Crcuits 3 28 Combinational Circuits
-27

eita nwits for

active-lou -low outputs a.34 Design a 2 bit magnitude comparator using sultable decoder
1Thus, We
is
OR
function. The t, (SPPU: Dec.-13, 14, Marks 6
bubbled-NAND

implement
the
able
know
that
NAND gate
to
Table
Q.33.1. Ans.: Refer Table Q.10.1. From table we have
have to
use
shown
in A >BXm (4, 8, 9, 12, 13, 14)
subtractor
is as
for full
Outputs A B : 2 m (0, 5, 10, 15)
Inputs A <BZm (1, 2, 3, 6, 7, 11)
D out
B Bin
0 0

1
-A>B
0
1 A A(MSB)
0 AB Y14-
B C
1 0
0
0
BoD (LSB)
4:16
-A = B
0 Decoder Y10
1 1 1 9 Y15-
10
Y11
for full subtractor Y12
Table Q.33.1 Truth table

Y -A< B
Y15
Y11

D Fig. Q.34.1

5 V
3 8
Decoder
END...
G
Boul
7
G28

Fig. Q.33.1
Implementation
3:8
of full subtractor using
decoder (IC 74138)
OECODE DECODE A Guide for Engineeriug Students
A Guide for Engineering Students
 gebal Crcwits Saguential Logic Desigm
Unit IV
QDierentiate between combinational logic circuits and
sequential logic circuits K S P : May-10, Marks 4]

Sequential Logic Design Ans

4 a t e d u r t i o n
S. Na Cembinational cìrcuis
n combinational cirvuis the
ouput variadles are at all
tines dependant on the
SequentiaB circuits
In sequential circuits, the output
variables depend not otly on
tthe present input variables but
nbinadon of input
variabies they also depend upon the past
history of these input variables
Nenay unit is not quired Menory unit is required to
in combinadonal circuis storr the past history of input
variables àn the equential

Combinational ireuis are Squential ireuis are slower

aster in speed becaus the than the ovambinational cirvui
delar betaen input and
output is due o propagatin
emoy delay of a s
Combinational ireuis are sasv Sequential ireuis are
tdesign onparatdvely harder to design
Parael adder is a Serial adder is
cobinational ireut nuit
a
quential
F Scck ziæagram f sequental cireuiti FSM

4.2: Flip - Flops

Q3 Name the two
storage elements.
Ans: 1. Latches
2 Flip-Flop.
Q4What is flip-Bep?
Ans:
Fip-flop is a
sequential circuit driven by cdock input either
Osiive eige or
negative edge. R is a binary storage device
Capaie oi storing one bit ot inkormation.
Q5 What is level
riggering and
edge triggering?
pies Ans. Level triggering In the level
wed to change triggering. the output state is
according to input(s) when active ievel (either
4-19 coo
4Guide fr Engineerirg &dens
 3
Sequential ogie esign
diai
Deitel Ynw enable input
ble input. The
al the ere Digital Circuits
maintaned

are 4-4
ANitive or
negative)
is
latehes
Sequential Logic Design
triggerd
of level
wo pes
output of
ot flip-tlop
responds
tnp-tlop respond. to the .Negative edge trig88ering : Here, the output responds to the
triggened: The
Positive level enable input
is 1 (HIGH) changes in the input only at the negative edge of the clock
when its
changes only Flip-Flop is enabled at the clock input. pulse
input
only when the level
of E input is HIGH Output resoonds
onity at a negaiv
Clock
Enable 1t

L input
9dges of he pulse

Q.5.1 Positive
level triggering
Fig. Fig. Q.5.4 Negative edge triggering9
level triggened: Ihe output tup-riop responds to tha
or
the Q.6 Give the comparison between latch and flip-flop.
Negative
changes only when its enable input is 0 (LOW).
input Latch
Flip-flop
Latches are controlled by signal Flip-Flop are controlled by clock
levels. transitions.
Enabie
nput Latches are level triggered. Flip-Flops are edge triggered.
E
Gated SR ach
Flip-Flop is enabled
only when the level
of E input is LOW Positve
EN- adge
Ceector AY
Fig. Q.5.2 Negative level triggering

Edge Triggering: In the

DD DD
edge triggering, the output responds to SR latch with enable
the the input using NAND gates
changes in
input only at the positive or negative edge of SR fip-fiop using NAND gates
the clock pulse at the clock
input. There are two types of edge Q.7 Draw and explain the
working of SR flip-flop. Give the truth
trggerng table and characteristic
equation of SR flip-flop.
Positive edge triggering : Here, the output responds to the SPPU: Dec.-95, 99, 11, May-98, 99,13,14, Marks 8, June-22, Marks 5]
changes in the input only at the OR Realize SR flip-flop using NAND gates and explain
at the dock positive edge of the clock pulse operation.
its
input
C Ans. Fig. Q.7.1 shows the positive edge triggered clocked SR
nput flip-flop.
Gated SR latch

Po8dge
Positive
S
DD -Q
UPositna
DDD
Output responds delecto CPo- dge
delertr
only at the positive Lcicuit Cr
Fig. Q.5.3 Positive edges of the puise DRD- D D
edge triggering (a) SR flip-lop using NAND gates
ecoDE (b) SR fip-tlop using NOR gates

A Gulde for Fig. Q.7.1 Clocked SR flip-flopp

Engineering Studenb
DECOD AGuide for Engineeriug Students
 Scquential Logie Desi. Digltal Circuits 4 6 Seguential Logic Design
45
Digital Yrnwits
Truth Table

Operation clock
pulse
is applied.
the ou .The truth table
for D flip-flop consider only these two conditions
S R -0andthe This is indicat
ed in the shown in the Fig. Q,8.1 (b).
1 n it is
-

as
Case 1 : ie. Qn and
do not change, table. CP
truth
of the
tirst row
clock
Ise
pulse is applied, Q
and the
0. R 1 of the truth t * 0
2 S the
secona
row
table. CP
Case
indicated in
This is X
pulse is applied, o
0 and the lock ta+ 1 Truth table of D flip-flop
Case 3
- in the third
S -1,.indicated R r o W of the truth
Fig. Q.8.1 (a) Logic
symbol Fig. Q.8.1 (b)
This is

clock pulse is applied, tho .Qn+1 function follows D input at the positive going edges of the
the
Case 4 If S -R =1 and undefined and therefore is indicatod Hence the characteristic equation for D flip-flop is
of the flip-flip is
ot the truth table
as clock pulses.
row
indeterminate in the tourth Qn+1 D .

and give the characteristic table of JK

CP S R ,n*1 State Q.9 Draw the logic diagram
flip flop.
0 0 0 No Change(NC)
1
OR Explain the operation of Jk Flip Flop.
Reset
01 0 Ans. Fig. Q.9.1 shows the logic diagram, symbol and truth table
Set
1 of positive edge triggered JK flip-flop.
Indeteminate
101
No Change(NC) neS+R
nww

(a) Logic symbol (b) Truth table for positive edge clocked (c) Characteristic equatlon
SR flip-floP
Positive edge
CP detector
Fig. Q.7.2 circuit

Q.8 Draw and explain the working of D flipSPPU:

flop. Give truth table
and characteristic equation.
OR Draw a positive edge triggeredD flip
June-22, Marks 5]
flop using NAND gates
D
and explain its function.
Fig. Q.9.1 (a) Clocked JK flip-flop
Ans.:In SR Flip-Flop, when both inputs the
are same output
either does not change or it is invalid K
(Inputs 00, no
change and inputs >11, invalid).
.These input conditions can be avoided by
complement of each other. This making them
CP-
D flip-flop
modified SR flip-flop is knoWn as

.The D input goes directly to the S

applied to the R input. Due to input, and its complement 1s
these connections, only
conditions exists, either S= 0 and R
two np Truth table
=
1 or S 1 and R = 0. Fig. Q.9.1 (b) Logic symbol Fig. Q.9.1 (c)

PIcODE A Guide for Eigineering Students

A Gulde for Engineering Stulen OECODED
 -7
Sequential Logic Desig Digital Circuits 4 8
Sequential Logic Desig
Dgtel Ciruis
10 Discuss the race around
condition and its solution.
a00 01 11 10
OR What is race around condition ? Explain in brief.

OR How can race condition be avoided in flip-flop.

[SPPU May-06,07, Dec.-08,09,13, Marks 8]
+KQ,
J+Qn K=J, Ans.In JK flip-flop,
Qn
equation
when J K = 1, the =

output toggles (output

Characteristics
changes either from 0 to 1 or from 1 to 0).
Fig. Q.9.1 (d)
flip-flop .Consider that initially Q = 0 and J = K = 1. After a time interval
Operation of JK
At equal to the propagation delay through two NAND gates in
0
Case 1: JK = =

to series, the output will change to Q = 1 and after another time

R =0 and according truth tahia
able o
When J =
K 0, S =

intervalof At the output will

SR flip-flop there is no change in the output. change back to Q=0. This toggling
will continue until the flip-flop is enabled and J = K = 1. At the
K 0, output does not change.
inputs J
= =
iWhen end of clock pulse the flip-flop is disabled and the value of Q is
Case 2 J =1 and K =
0 uncertain. This situation is referred to as the race-around
Q 0, Q= 1: When J =1, K 0 and Q 0, S =1 and =

condition. This is illustrated in

R 0. According to truth table ot Sk flip-tlop it is set Fig. Q.10.1.
state and the output Q will be 1. This condition exists when t, 2At. Thus by keeping tp <At we
Q 1. Q = 0 : When J - 1, K = 0 and Q = 1, S = 0 and

R 0. Since SR can avoid race around condition.

=
00, there is no change in the output
and therefore, Q =1 and Q 0. =

We keep tp
purs j = 1 and K = 0, makes Q = 1, i.e. set state.
can
< At by keeping the duration of edge less than
At.
Case 3 J =0 and K =1
A more practical method for this
Q 0, 1:
Q =

When J 0, K =1 and Q 0, S overcoming difficulty is the use

=0
= =
and of the Master-Slave
R 0 Since SR =
00, there is no
change in the (MS) configuration.
and herefore, Q =
and Q =
1.
output
Q 1, Q 0: When J 0, K
=
1 and = =
Q 1, S =0 and
According
to truth table of SR
flip-flop it is a reset
CLK
sta and he ouput Q will be 0.
e nous = and K = i, makes Q 0, i.e., =

reset state.
Case 4 } =K =1
K-
, Q = 1: When J K =1 and Q 0, S =

1
b
and
=

According to truth table of SR flip-flop it

sr2te ad re
utput Q will be 1.
is a se
iL M -Propagation delay
1 , Q = 0: WhenJ K 1 and Q
According to truth table of SR =
1, S =0 ar
The
stae 2nd he output Qwill be 0.
flip-flop it is a
ze Fig. Q.10.1 Input and output waveforms for clocked JK flip-flop
ng K 1,
toggles fhe fip-flop output
=

ICOD 4 Guide for Engineering Students

A Guide for
Engineering Stuáer
 Sequential Logic esign DigitalCircuits 4-10 Sequential Logic Design
4-9

D i g i t a lC i r a stext of
SR/RS
of SR flip-flop. the second
flip-flop follows the first one, it is referred to as
c o n t e x t

Since
in
raceco
condition

are logic (s R the slave

and the first one as the master.
the inputs
both
Q.11 Explain when of the
tip-flop, the
state
is Inmaster-slave JK flip-flop state change occurs when flip-flop
to
and Q try
SRRS
Ans: In is applied ome 1. boeh positive transition (first half) of clock and
pulse goes through
outputsQ

the
ciock
both
the
and )
of the
t flip-flop
and
(Q are of the clock (second half). Thus, race-around
known ac
case,

undeined.
in this
that the
outputs
is known as the
is gative transiti
violates
the rule Such
condition
race condition does not exist in the master-slave JK flip-flop.
his other.
of each tlop.
/RS flip
-

complement
of SR
ondition in
context

flip-flop with
nee

cessary On+1
master
JK
slavediagram.
of
Explain
working and state SPPU: Dec.-19, Marks 6
Q.12 state
equation
logic diagram,

MS J-K flip-flop.
OR Explain
the
ter-slave JK
master-slave flip-flop. Posi
JK flip-flop. Positive
Ans.: Fig.
Q121
shows
flip-flop
and inverrerted (negative)
to first
dock pulses are applied
to second flip-flop.
dock pulses are applied Table Q.12.1 Truth table
Prese
Slave Characteristics equation : Qn+1QnJ+ Qn K JQn -
+ KQ,n
Master

- State Diagram
JK = 10, JK = 11

JK= 000) 00
DDu
JK 01
JK = 11

Ceer Fig. Q.12.2

Fig. Q.12.1 Master slave JK flip flop Q.13 Explain the operation of T flip flop.
When CK =1, the first flip-flop is enabled and the outputs QM Ans.: T flip-flop is also known as Toggle flip-flop
and Qy responds to the the T flip-flop is obtained from a JK
inputs of J and K according to tne As shown in Fig. Q.13.1,
Table Q.12.1. At this time, the J and K together.
second flip-flop is inhibitea tlip-flop by connecting both inputs,
because its clock is low, CK= 0.
When T =
0, J =
K =
0 and hence there is no change in the
When CK goes Low (CK= K 1 and hence output toggles.
1), the first flip-flop is inhibited output. When T 1, J = =

second flip-flop is enabled. At

this time, the output of
a
flip-flop (Q and Q)follow the outputs Q and seco
Ou, respective
OICOD A Guide for Engineering Students
A Guide for Engineering Studens
OECOD
 SeguentialLo Design
-11 Digital Circuits 4 12 Sequential Logic Design
Piital Cinwis

|4.4 Hold and Setup Time and Metastability

setup and hold times.

a.15 Define
ULEdge G:Setup time The setup time is the minimum time required
K detector
CP fip-tlop CP circuit maintain a constant voltage levels (data) at the excitation inputs
to
of the flip-flop device prior to the triggering edge of the clock
of
ulse in order for the levels to be reliably clocked into the flip-flop.
puls
It is denoted as tsetup
NAND gates
Q.13.1 T flip-flop using Hold time: The hold time is the nminimum time for which the
Flg.
truth table and the characteristi at the excitation inputs must remain constant
shows logic symbol, voltage levels (data)
Fig. Q.13.2 edge of the clock pulse in order for the levels to
equation for T flip-tlop. after the triggering
he reliably clocked into the flip-flop. It is denoted as thold
50 %
T Nogative
dge triggerad
CA- cloCK

Data can
n TQ,TO, Flipeflop
Data must be stable
change
(a) Logic symbol b) Truth table (c) Characterlstic equation nputs

Fig. Q.13.2
5etp nold
4.3: Use of Preset and Clear Terminals
Fig. Q.15.1 Setup and hold timings
Q.14 What are preset and clear ?
a.16 Write a detail note on flip flop metastability.
Ans.: When power is turn ON, the state of to flip-flops.
the tlip-tlop is Ans.: We have seen various timing parameters related
uncertain. lt may come to set (Q- 1) or reset within safe limits, i.e,, under normal
(Q= 0) state. In many When these parameters are
applications, it is necessary to
initially set or reset the tlip-tlop. conditions, a flip-flop has -o Vo
Such initial state ot tlip-tlop can be two stable states, logic 1
evieoien

direct or asynchronous accomplished by using the

inputs of the tlip-flop. These inputs are and logie 0. The third stale,
Preset (P) and Clear
(C). They can be
elock pulses and are not in applied at any time between metastable state exists in
synehronism with the clock. he flip-flop if the output
voltage is about haliway
between a valid logic 1
valid 0
Voltage and a logic V2
Vi2
voltage Cross coupled Inverters
rcop Fig. Q.16.1
A Studens
Guide for Engineering Sudens 4 Guide for Engineering
PEcOD
 4-113 Sequential Logle Desi Digltal Circuits 4-14
Seguential Logic Desig
D i g i t a lC i r w i t k

shown in Logic0
cross-connected
inverters,
as

fed back to the

Fig Q161 Vcc
Undefined
Consider

Because
two
the outputs
of the
inverters
are

inputs
inverter
w e have,
other
o1 2 Metestable state

o2
voltages be graphicall
be graphically
can plotted
relationship
between these Undefined
The relationship is
as shown
in Fig. Q.16.2.
This graphical known as
of cross led
coupled inverter
ontal axis shows The
characteristics
transfer Vo1Vi2
voltage and the horizzon
vertical axis shows Vol and Viz
and o2
Vcc
Logic 0 Undefined Logic 1 VoaV
Fig. Q.16.2 (b) Voltage transfer curve for inverter 2
Voc
Logic 1 The metastable state occurs in the flip-lop when setup arnd hold
parameters are not met. Flip-flop also can enter into metastable
Metastable state
state when a stray glitch occurs at the input at wrong time. The
flip-flop will remain in the metastable state for indeterminate time
Undefined depending on the input conditions. For reliable operation of the
digital system it is necessary to avoid metastable state.
VoV2
Fig. Q.16.3 (a) shows how delayed clocking of flip-flop 2 avoids the
Logic metastable state in the flip-flop. Here, the first
flip-flop accepts the
Vcc asynchronous excitation inputs. The output of first flip-flop is
Vo2Vi
Fig. Q.16.2 (a) Voltage transfer
curve for inverter 1 AtB
When Vi increases from 0 volts D -Output
toward
Vc Vstays within the
range of permissible
logical 1 voltages until about the middle of the CLK CLK2
graph. The Vo then
remains there. But drops toward a
voltage level and logic 0
while
through voltage levels whichdropping
are not
toward logic 0, it passe a
This part of defined as logic 1 or
voltage transíer curve
See Fig. Q.16.2 (a). Fig. indicates the metastablelogicte Clock- Delay
for inverter 2. Q16.2 (b) shows the sta
rve voltage transfer cu
Fig. Q.16.3 (a) Circuit to avoid metastable state

DECOD
OIcoDE A Guide for Engineering Students
A Guide for
Engineering Studen
 4-15
Sequential Logic Design
D i g i t a lC t r c u i t s 4-16 Sequential Logic Design
second flip-flop. Because first
an
ingut
of the
seco

it can go into
ip-le
flop metastak
input,
n a n d '
ds e x c i t a t i o n

n+1 S R Qn Qn+ 1 J K
a s V n c h r o n o u s

Qn
X
has
leave
he metastable state betote 0 0 X 0 0 0
stae to 0 0 1 X
flip-flop
for the
lip-lop
Secos
first clock
the the 1 1
0
To
allow

the
second
flip-flop, ld be greater than the Der 0 1
1 x
should 0
1
clocking

delaved.
The delay
introduced

completely
avoid metastab
This X0
state to Q.16.3 (b). JK excitation table
metastable
wavefornm
shown in Fig. SR excitátion table
illustrated in
the Table Q.17.1 Table Q.17.2

n an+ 1 D Qn Qn+ 1 T

0 0

0 1 1 1

0 0 0

A+B

D excitation table T excitation table

Table Q.17.3 Table Q.17.4
Negatve edge
triggered clock
4.6 Conversion of Flip-Flop
-Metastable state a.18 Explain how T is converted into D FF.
0 [SPPU: Dec.-11, 15, May-13, Marks 6

Ans.: The excitation table for above conversion is as shown in

Table Q.18.1.
Delayed clock

Input Present state Next state Flip-flop input

Fig. Q.16.3 (b) Waveforms D T

0 0
4.5: Excitation Tables
Q.17 What do
tables of SR, JK,youD mean
excitation table ? Give citation by
and Tflip-flops? exe
Ans.: Table that gives the
given change of state required
is known as inputs of the for a Table Q.18.1
flip-flop. flip-tiOP the
an
excitation tadie
OIcOD
A Guide for Engineering Struden
DECODE A Guide for Engineering Students
 4-1 Sequential Logic Design
-17
Sequential Logic Desi D i g i t a lC i r c u t s

hou JK FPF is converted to D FF.

Logic diagram .20
Explain
D[SPPU : May-2000, 02, 06, 10, 12, Dec.-08, 09, Marks 3)
R m a p simplification
excitation table for above conversion is as shown in
The
Ans.: The
Table Q.20.1.
For T

| Present state Next state Flip-flop inputs

Input
K
D Qp+1
0 0 X
0

T=D+Da,
0

Fig.
Q.18.2 T to D flip-flop conversion
Fig. Q.18.1
converted to JK FF.
is 19, May-12, Marks 4 1 X
a.19 Explain
how
SR-FF
F SPPU: Dec.-07, 1 1
is as shor..
table for
above
conversion
nown in Table Q.20.1
excitation Logic diagram
Ans. : The
K map simplification
Table Q.19.1.
Present Next Flip-flop inputs For
For
Inputs state
D
state D
R D
K
X
oX Y ca
0 0
1 0
0 11 X
0
0 X K=D
JD
0 Fig. Q.20.2 JK to D
Fig. Q.20.1 flip-flop c o n v e r s i o n

0 X 0
1 is converted to T FF.
1 1 Q.21 Explain how D FF : Dec.-11,15, May-13,15,
Marks 4]
DS [SPPU
0 0 table for above
conversion is as
shown in
Ans. The excitation
Table Q.19.1
Table Q.21.1.
K-map simplification Logic diagram
Present state Next state| Flip-flop input
For S For R Input
KOn D
00 01 11 10 00 01 11 10 0
oox1o10
S JO
R=KOn JK flip-flop

Fig. Q.19.1 Fig. Q.19.2 SR to JK fIip-1p

Table Q.21.1
conversion
Engineering Students
A Guide for
OECODE
OECODE
A Guidefor Eugineering Sue
 Digital Circutts 4 - 20
Sequential Logic Desig
-19
Sequential Logic Desi
Logic diagram K map simplification Logic diagram
DieitelCnw

For J For K
K m a p s i m p l i f i c a t i o n

On On
SR
0 SR
For D
00 00x S
o 01 ox o1

11
11 X
CP

Fig. Q.21.2 D to T flip-flop converslon

x
Fig. Q.21.1 J S K R
TQn +TQn T®Qn
=

D Fig. Q.22.1 Fig. Q.22.2 JK to SR

SR flip-flop ?
JK flip-flop to to convert T to SR flip-flop ?
how to
convert
Dec.-03,12, May-05,11, Marks 61 a.23 Explain how flip-flop
a.22 Explain (SPPU: SPPU: Dec.-12, Marks 4]

SR Flip-Flop Ans.: T Flip-Flop to SR Flip-Flop

Ans.: ]K Flip-Flop to conversion 1s as shown in SR FF is
The excitation table for conversion of T FF
above into as
The excitation table for an

Table Q22.1 shown in Table Q.23.1.

Inputs Present Next state Flip-flop Present state Next state Flip-flop input
inputs Inputs
state
T
K
S R Qn Q+1
S R Qn An+ 1 J
0 0
0 0 0 0 0 X
0
0 1 1 0
0 0
01 0 0 0 X
0 0 X 1
0 1

0 1 1 X 0 0
1 0 1 1
X 0 0
1
X X X
11 X X X
Table Q.22.1 Excitation
table for JK to SR conversion
conversion Table Q.23.1 Excitation table for T to SR

PucoDE)
A Guidefor Engineering Students
DECODE
A Guide for Engineering Stuae
 21
Sequential Logic Des
Logic diagram Unit IV
K m a ps i m p l i f c a t i o n

RO SC
D

(b)
SR flip-flop
5 Shift Registers

5.1: Register and Shift Registers

shift registers
a.1 What are

Fig. Q.23.1
Ans. A group of flip-tlops can be used to store a word, which is
called register.
Flops
4.7:Applications of Flip The binary information (data) in a register can be moved from
stage to stage within the register or into or out of the register
of flip-flop.
Q24 List the applications upon application of clock pulses. Such registers are called 'shift
Ans.: Some of the important applications
of flip-flops are registers'.

It car be used as a memory element. Q.2 Explain the operational types of shift register.
K SPPU : June-22, Marks 5]
It can be used to eliminate key debounce.
Ans.: Fig. Q.2.1 gives the symbolical representation of the different
It is used as a basic building block in sequential circuits such as types of data movement in shift register operations.
counters and registers. Data bits- E +-DataData bits
t can be used as a delay element.
(a) Serial shift right, then out (b) Serlal shift left, then out
Data bits
END..

Data bits
(c) Parallel shlft in (d) Parallel shift out (e) Rotate right () Rotate teft

Fig. Q.2.1 Basic data movement in registers

Q.3 Explain the operation of SISO shift register.
L[SPPU : June-22, Marks 5]
Ans.: Fig. Q.3.1 shows serial-in serial-out shift-left register.
(Serlal dataouA
output) DPA (Serial data input)

CP
DECODL Fig. Q.3.1 Shift-left register
4 Guide for Eugineerlng Sue
(5 1)
 Shift Registen D i g i t a lC i r c u l t a
5-3 Shift Registers
5-2

shift
register
is
hifted lef
bit
DigitalCincuits

data
within
the
lhe
data
input is loaded in Onetho SHIFT/LOAD
register, pulse.
shift cock
this each
In
position
at hift-right register.
shift-
bit
right most fip-tlop. s e r i a l - o u t

serial-in

shows

Q3.2
Fie

CP
tt
register
Parallel In Serial Out (PISO) shift register
Fig. Q.5.1
Shift-right

Fig.
Q.3.2
register is shif enabled,
data
within
the shift
right SHIFT/LOAD is low, gates G, G G are

shift register, The data input bit is

is iloadedi .When to D input of its
data bit to be applied
In this
at each
clock pulse.
allowing each input
bit position
one respective flip-flop.
most flip-flop. 1 will SET
the ieft register. with D
operation
of SIPO
shift
P SPPU :Dec.-19, Marks 61 When a pulse clock is applied, the flip-flops
the
Q4 Explain
those with D = 0 will RESET.
and
the data CP stored simultaneously.
All four bits
are
Ans.: In SIPO, disabled and
serially NC | NC
high, gates G, G, Gz
entered NC are
NC is
When SHIFT/LOAD
bits are
but the data bits to shift
register enabled. This allows the
into the
taken in parallel.
D D2 D Do gates G Gz, G;
are

output is to the next.

Table Q.4.1 Truth table right from one stage
data are stored, allow either the
Once the D-inputs of the flip-flops
on its The OR gates at the
each bit appears depending on
or shift operation,
available simultaneously as
and all bits parallel data entry operation
are
respective output line enabled by the level on
the SHIFT/LOAD
shown in Fig. Q4.1. which AND gates are
Data
nput
Po input.
out shift register.
a.6 Explain parallel in parallel
Ans. Parallel data inputs
CP

Fig. Q41 A Sorial In Parallel Out (SIPO) shift register

Q.5 Explain the operation of PISO shift register. P
Ans.:Fig Q5.1 illustrates a four-bit parallel in serial out registe
There are four
input lines Aay A, A, Ap for enterin8 data n CP-

parallel into the register.

Parallel data outputs
SHIFT/COAD is the control input which allows shift or ding shift register
data operation of the o Q.6.1 Parallel In
Parallel Out (PIPO)
register. Fig.
Engineering
Students
A Guide for
pCODE5 dents
QEcODE
A Gulde for Eugineering >u
 5-4
shift Registen gital Circuits 5-5
Shift Registers
simultaneou
DyiteiCin
paralleiout
register,
ther
on parallel entry of .ttconsists of four flip-flops and four multipexers.
outputs
appear
in bits
paralle' the
In and
bits
have two
.The four multiplexers common selection inputs and
data
all S,
mutaneNIST

register. Sand they select appropriate input for D fip-flop

shons
this tpe of
7 shift register usir JK
Fie serial-in-serial-out
shows the
4bt Table Q8.1 Mode control
07Design
a
operation Register
shic register
ip ops serial-out
S operation
Ans Q3 we
have seen
4-bit

D
serial-in

tip-tlop using eau

registers depending8 on the
Fup-Flops By replacing
HtSISÓ shift register using JK flip-lon selection inputs of No
change
usng D SISO shift.
can use it Alops. Shift right
can implement
i-fiops e
to JK TIp-tlops we can use as a multiplexers.
inputs D
Br ging compiemer:t When SSo = 00, input
Srift left
fp-flop Parallel load
of universaB shift register 0 is selected and the
Q Drev and explain the working Table Q.8.1 Mode control and register
value of the
shifts (right shift and left shif-and present
Ans: the register has bothreterred shift regis is applied to
operation
parallel loa capabilites, it is fo as universal
er register
of the This results change in the
shift register. the D inputs flip-flops. no

Fig Q6.1 shows the 4-bit universa

register value.
Perale inputs

When SS =
01, input 1 is selected and circuit connecions are
Sene Serial
input for such that it operates as a right shift register.
shin left

When S,So =
10, input 2 is selected and cireuit connections are

such that it operates as a left shift register.

8210 3210 3 2 10 3 210 information the paralle!
4 4x 4x1 Finally, when S,S 11, the binary on

MUX MSX MUX and it is

input lines is transferred into the register simultarneousBy
a parallel load operation.

5.2: Applications of Shift Registers

Q.9 What are the applications of shift register ?
used to
Ans. (SISO) shift register can be
A Serial-ln-Serial-Out
introduce time delay At in digital signals.
be used to
A Serial-In-Parallel-Out (SIPO) shift register can
parallel form.
Convert data in the serial form to the
be used to
Parallel output A Parallel-In-Serial-Out (PISO) shift register can
Fig. Q.8.1 4-bit the parallel form to the serial
form.
universal shift convert data in

OECOD register
Students
A Guide for Engineering
A Guide for Engineering Stude OECODE
 5-6
Shift Registerg
DigitalCircuits
counter.

used as a

can
also be Unit IV
A
register
shift p s e u d o - r a n d o m
bina sequence rator. wwwwwwwwwwwwww.www

registeris
a
enerate a particular bit

6
generat
to
Shift

can
be
used
pattem
shift register
The

repetitively.
detect the desired
tect the desired sequence
son
Counters
to
can be used
The shift register
END...
6.1 Introduction
01 What is counter ? Give the difference between synchronous
and asynchronous counters. [SPPU: May-07, Dec.-07, Marks 2]

Ans.A counter is a register capable of counting the number of

clock pulses arriving at its clock input.
are two types of counters :
Synchronous counter and
.There
asynchronous counter.

Asynchronous counters Synchronous counters

Sr. No.
1. In this type of counter flip-flops In this type there is no
are connected in such way that| connection between output of
a

output of first flip-flop drives first flip-flop and clock input

the clock for the next flip-flop. of the next flip-flop.

2 All theflip-flops are not clocked All the flip-flops are clocked
simultaneously. simultaneously.
3.
Logic circuit is very simple even | Design involves complex logic
for more number of states. circuit as number of states
increases.

4. Main drawback of these counters| As clock is simultaneously

is their low speed as the clock is given to all flip-flops there is
propagated through number of no problem of propagation
flip-flops before it reaches last delay. Hence they are high
flip-flop. speed counters and are
preferred when number of
flip-flops increases in the givern
design.
counterss
Table Q.1.1 Synchronous Vs asynchronous
pICOD
A
Guide for Engineering Studen (6-1)
 62 Countes D i g i t a lC t r e u i t a 3 Counters
D i g i t a l
C i n u i t s

(RIpple)
Counter
Counters

A s y n c h r o n o u s

a.3 Explain the working of 4-blt asynchronous down counter.

6.2:
6.2
of 2-bit asynchrono
of 2.

expiain
the
working
binary that
ram
OR Draw diagrar
trigger on
of a 4-bit binary ripple counter using flip flops
negative edge transition. Also draw a timing
and
a.2 Drau counter counter.
a s y n c h r o n o u s

of the
2-Dit diagram
counter showS

. Fe Q21
(a)
Fig. Q.3.1 shows the 4-bit asynchronous down counter

to the clo lock input of only using JK flip-flops.

flip-flops
is
connected
stage
clock signal HIGH
The
HIGH LSB
fip-flop LSE
The clock input
secondcpLUUL
CP-
of the
stage flip-fiop i5 L
trggered by the Fig. Q.3.1 4-bit asynchronous down counter
(a) A two-bit asynchronous binary first
Qoutput of Fig. Q.2.1 is connected to the clock input of only
counter The clock signal
the first stage.
flip-flop the Q
is triggered by
Because
of the
The clock input of the remaining flip-flops
CPTU2UUML instead of Q output of the previous
inherent
output of the previous stage
propagation delay stage.
time through a
LSB O
flup-flop, MSBOg
transition of the
Count
TTiuTeriuriu
input dlock pulse stage
and a transition of
the Q output of Fig. Q.2.1 (b) Timing dilagram for the counter of
first stage can
Flg. Q.2.1 (a)
never OCcur at
exactly the same
time. Therefore, the two flip-flops are never simultaneou
triggered, which results in asynchronous counter operation.
Fig Q21 (b) shows the timing diagram for two-bit
asynchron |0
0 0 0 0 0

counter. t illustrates the changes in the state of the

outputs in response to the clock.
flip-o
and K input of JK 1101/110010111010/1001/1o0o|ot1/0110/lo1010100/0011 001o/0001 o000
fip-flops are tied to logic HGn
output will toggle for each
hence
Count
111 1110 counter
negative edge of the clock inpu of 4-bit
asynchronous
down

ig. .3.2 Tlmlng dlagram Students

Eugineering
A Giulde for
PPCODE
AGutde for EnglneeriugSuen PIcoDD
 6-3
Counterss

-
7
a n d m u s r K i t p d

zegave
c p

ge
e ge o he
of ciocik
e cioce D
uut
oil agpefr eact aKmag simplfication 3 Lgic diayam

c n t e .
D Fig. a42
hinary ap
tos P : Dec4, 12, a e
e i g n : i i t

CR
,243 shows the -bit up down counter dhat wll count fro
1 1 1 when te mode controi nvur M s i and from 11
te oyerzti he po po wher mode controi inpt Mist

* t dOn and wher M

henM- se coter the M input shod
wl cot p To actoere tris
cer

comt he orual ipfp oatput ()

wheter
ed v. drrve the ciock sigadt
ierted figog oaytis
5 shert iy A1(a
sucTessivestagg fisp,
The truth tatleis shaswn n iy A1 )

Fig aA3 1st ssynchanos aitw sutar

MGT
j 1o M eneities ASD zates 1 ard 2 md isaties A
ps 3 ad 4. Thas allws #e 2, ad 2, vtputs 7 ze

isc'k irepats of heis esypeve 1ert stay #at urer w

h e r M is korje 0, AD zates 1 ard 2 are disabled and AD

te 3 ard 4 ate eratied. Tis aiows te , and 2, oputs to
drive the doxk irputs t heir respective rert stazes so ha

anher itl cmurt dow

A uide fur E ngin erriug Hstrnts

ACmlde for Lngureng Mude
 6-6 Counters DigltalCircuts
6-7 Counters

BCD (mod-10) rlpple

Digital
Cinwis

a.5 Design
a n BCL counter using JK filp-flop.
Step
1: Determine the number of flip-flops needed. The
Ans. :
counter goes hrough states 0-9, i.e. total 10 states. Thus,
p10 and for 2" 2 N, we need n =4, ie. 4 flip-flops required.
N=

Type of flip-flops to be used: JK

step 2

Step 3 Write the truth table for the counter.

1

Output of Note The reset input

A
CLK D C B
.
reset logicY (CLR) of each Flip-Flop
1 is active-low input.
1
By making CLR input
ofall Flip-Flaps iogicC0,
010
011foo 101110 11 1
we can reset the counter.

o 00 Thus reset logic is

designed such a way
that for invalid
0 Valid states, Y = 0 and
states
0 1 counter resets.

0 0 0
CLK

010 0

0 0 Invalid
states
O 1

counter
Table Q.5.1 Truth table for BCD

Step 4: Derive reset logic

c BA 11 10
DC,00 01,
00 1 11-
Count
000 11 110 101
01 11 1
Y D+BBC
100 011
SNEARAMAANAATAYAAAAONANAA

010 O01 000

Fig. Q4.4 Timing diagram for
3-blt UP/
11 0 0 0
DOWN ripple count -BT
Fig. Q44 shows the 10 1 1 O 1
timing diagram
Counter.
for 3-bit
up/doW ipple Fig. Q.5.1

Students
OECOD A Guide for Engineering
A Guide for Engineering Studen OECODE
 Digital Circuits
6-8
Counters DigitalCircuits 6-9
Counters

Draw logic
diagram. Stop 5 : Draw logie diagram.
5:
Step
Logk 1
(MSB) Logic 1
LSB
MSB
CLK
Taa CLK
B
LcR CLR CLR
Reset logic

diagram of BCD ripple couter

Fig. Q.5.2 Logic Reset logic
ripple counter using T flip-flops.
Q.6 Design mod 6
Fig. Q.6.3
Ans.: Step Determine the number ot flip-floP required. Has
1
total 6 states. Thus N Q.7 Design ripple counter for state diagram shown.
counter goes through 0 5 states, 1.e., 66
-
=

for 2" 2 N we need n = 3, i.e. 3 flip-flops.

and
Step 2: to be
Type of flip-flopsused : T - -
Step 3 Write the truth table for counter

CLK B A
Output of
resetiogic
Fig. Q.7.1
Ans.: Step 1: Deternmine the number of flip-flops needed.
Valid We know that 2" 2 N. Here, N = 8 n
=3 i.e. 3 flip-flops
states needed.

Step 2: Type of flip-flops to be used JK

Invalid Step 3 Write truth table for counter.

wwwwww.eve states
**wwwww.wwwwww.wwww.vwwwwww
CLK B Output of reset logic Y
Fig. Q.6.1
Step 4: Derive
reset logic.
A5A
C 00 01 11 10
0

Y=C+B
Fig. Q.6.2
OECOD Table Q.7.1 Truth table
A Guide for
Engineering Studen
OECODE A Guide for Engineering Studenis
 DiytalCircuits 6-11 Caranters
D g i t a lC o n w i t

A
Dertve preset
0 01 11 10
Step4 down

Sirceif
ka
logikc need to
dertve

e r
we

instead of reset
preset logc Y BA+C
logkc Fig. Q.7.2
Timing dilagram for 3-tit synchronous binary cwundar
Fig Q.8.4 (bj
for this counter is shorwn in Table QB.1.
diagram The state sequence
Step &: Draw kogic

MS

Prése PrOS

D-D 1
Prosot logic
Fig. Q.7.3
Since it is down counter, the clock of the next Table Q.8.1 State sequence for 3-bit binary counter
a
flip-flop is given each
by the Q output of the previous flip-flop. Looking at Fig. Q8.1 (b), we can see that QA changes on

clock pulse as we progress from its original state to its final state
6.3:Synchronous Counters and then back to its original state.
Q.8 Drew and
explain the working of 3-bit
Ans.
synchronous counter Flip-flop A is held in the toggle mode by connecting J and K
Fig Q8.1 (a) shows 3-bit synchronous binary counter and
its timing diagram. inputs to HIGH

HIGH Flip-flop B toggles, when Qa is 1.

B is in the no-change mode and remains

When QA is 0, flip-flop
in its present state.

at Table notice that flip-flop C has to

Looking Q,8.1 we can
This
CP
change its state only when Qß and Qa both are at logic 1.
AND gate and applied to the J and K
Fig. Q.8.1 (a) A three-blt
condition is detected by
Q and Qn HIGH, the
synchronous binary nputs of flip-flop C. Whenever both are

OICOD counter
A Guide for Engineerlng Students
Gulde for Englneering Sudens DECOD
 6 3
herel i t
6 -12
ovten Pertal Crrwite

makes
the and K
inputs
K inputs of
flip-fop
K-ma simplification

outut
of the AND gate on the ollowing clock pulse At
C oggles hat
and fip-fiop of flip-tlop C are
HIGH

other times
the and
K inputs
fip-flop
does not chanee
OW by
and
AND gate output uste
the
tmplement
bit nchronous counter
ynchronous
counter using JK eBA
a.s Design and (SPPU May-12,
E
June-22, Narks
S-bit
synchronous binary pcounter
Ans :Design of

See Number of flip-flops -it

counter so we requine KA A
Fig. Q.9.1
fip-iops to be used JKK Draw logic diagram.
Types of flip-fiops step 5:
Step 2 HIGH
Present state Next state Flip-ops inputs

Decoder C BA C.BA JcKcJK

0

CP
1 1
Fig. Q.9.2 (a) A three-bit synchronous binary counter

0 0 T-flip-lops. Write state

Q.10 Design divide by 6 counter using
table and reduce the expression using
K-map.
[SPPU: Dec.-09, May-14, Marks 81

1
Ans.: Step 1: Determine number flip-flops needed.
the of
1 x 0 x the formula
For designing mod 6 counter using
00 0 2 2 N
Table Q.8.1 Excitation table required.
Here N 6 n 3 ie. 3 flip-ilops are

Step used: T
of flip-flops to be
3
Determine the excaitation table for the counter. Step 2 Type
Step 3 Determine the excitation table for counter
- 1

0
table for T-ftip-Rop
Table Q.9.2 JK Table Q.10.1 Excitation
flipfiop excitation table Sudenss
OECODED 4 Guide for Engiueering
DECOD
4 Guide for Enginering Sade
 6-14
Digital Ciraits

Digital Cireuits
6 15
iueuiit that goes in Counters
The circuit
lockout condition
is called bushless
circuit.

3 01
0
O
0 1

0 0
o O
Table Q.10.2 Excitation table for (a) Desired sequence
counter (b) Unused stata
Step4 K-map simplification. forming lockout
Fig. Q.11.1
For Tc For Ts 12 Design synchronous
For T step, using JK counter which will go through
flip-flop. (Avoid lock out the
01 10 conditlon.). following
01
10
[SPPU: May-11, Marks 3]

TA= 1
-0-0-0-0
Fig. Q.10.1 Ans. Fig. Q.12.1 shows the
Step 5: Draw the logic diagramn. state diagram for the given n
counter. To avoid
COo
condition states 1, 4 and 6 lock-out -0-0-0-
areforce to enterinto state 3.
Flip-flop excitation table is as
shown below Fig. Q.12.1
(LSB)
Qp Present state
Qc(MSB) Next state
Fig. Q.10.2 utputs B
C
Q.11 What
Ans. : In a
is
lock-out condition
Logic
and
diagram 0 A BL C1
an counter if the
unused state next state
bushless circuit ? 1
in and if of
the
unused states by chance the some unused state
counter is said and counter is a8
Fig Q11.1. The to be in the never arrived at a happens to ina elf
called self counter lockout used state
starting counter.which neverconditions. This is then in
ECODE
goes in
lockout illustrated
conaiuition is L 0

0
Table Q.12.1
A
Gulde for Engineering
Studena OECODED 4
Guide for Eugineering Students
 17 COunters
/'i wit

For D

iwoeoomoki

Step 3 K - m a p sinplification

For Ta For Tc
Fl. a.12.2
For Ta
0 11 10 00 O 11 00 01
Logie dapram

TA BC TaC
Fig. Q.13.1

LogicDiagram:
Fig. Q.12.3

mod 8 synchronous counter using T flip-flop. LS8

a13 Desisn (MSB)
SPPU: Dec.-19, Marks 6

Ans.: Step 1: Determine the number ot tlip-flops needed.

LO
ClocK
For desijgning mod S counter the formula
22N
Here. N 8 n =3 ie. 3 flip-flops are required. Fig. Q.13.2
Step 2: Determine excitation for counter
using JK flip-flop
Q.14 Design the sequence generator Marks 6)
0 K SPPU: Dec.-19,
Present state 02 4 6
Next state Flip-Flop inputs
Ans.: Excitation table
A BC
ABC Ta T Flip-Flop inputs
0 00 0 0 Present state Next state

0
001 B c*JA Kg JcKc
01 0 0 BCA* X 0
X
0 0 0 0
0 X
0 0 1 1 x X X

111 1
Lo
0 0
xxxxxx
0 X X

Students
OECODE A Guide for Engineering
A Guide for Engineering Studens OECODES
 -19
Dgital Cireuits

Counters

D i e i h e lC n w i t s
T 01X
Counters
X -p.o
FFO rFF1 FF2 FF3 FFA PFS
XXX CLR
CLK-

Kmapsimplification:
For Ka For Jp
CLR-

Fig. Q.16.1 Six stage ring countor

For a
10
00 01 11 10 A00 01 10 Ooratlon: Fig Q15.2 shows the operation of
six stage
ring
00 81 11
oxxX oTXX counter. On preset, FFO (tlip-tlop 0) is set and FFI to FF5 are reset.
lling
After each falli edge of the clock contents of ring courter are
xx shifted 1 bit from LSB to MSB.
KA=5 ds1
For K Forc For Kc CLR CLK% 4 , g Operation
0BC
0 01 11 100 AB O0
01 11 10 01 1110
Ux 1| 0 0 0 0 o Preset
0 0
1 1 0 0 0 0 1Bit
follows a
xx Oxxo XXx 1 01 0 0 circular
path to form

Fig. Q.14.1
K1 1
|o00|1 00 ring counter

Logic diagram
1

(MSB)
1g 1 0oo o o
B - (LSB)
Cioc
Flg. Q.15.2 llustrating operation of six-stage ring counter

Q.16 Draw and explain the operation of 4-bit Johnson counter

twlsted counter.
Fig. Q.14.1 (a) L [SPPU: May-12, Marks 3
64: Ring and
a.15 Draw
Twisted Ring Counters Ans,: In a Johnson counter, the Q output of each stage ot
a sx
stage ring counter
Mention about the use tlip-flop is connected to the D input of the next stage.
of and explain its ation
presetting the counter. opeta The single exception is that the complement output of the last
Ans.: Fig.
Q15.1 shows the [SPPU: May-12, Marks 3 lip-flop is connected back to the D-input of thhe first flip-tlop as
present to sin
S1X
value (00000), by stage ring counter. The counter 1s
bits 0. shown in Fig. Q.16.1.
setting bit
bit 0
0 1 and
remainir
pICODE
A Gulde for
pEcODED Giuide for Engiuveriug Studens
Englneerlng Studens
 er stats the sae sequene is repeated

rbit
ttis case four-i register is used. So the our-tit nequetice
ha
tt

& tal of eight states

.16.2 gives the timing sequence for a four-bit lohrison
Fi Ql6
Vnder
r i t Johson countsr

epiemented with SR or . UUUUUUUL

s i dback rom the righs.
As shou m Fg CA
iement cugt he emost tip-ilop input. This
of states.
produces a i u e sequEnce
the g s e r l piops) is deared. So all the outputs

QA ae zera.
Oc
The ouput af last stage p is zero. Therefore complement
ourpur of last stage. n is one. This is connected back to the D
ampur of irst stage. So D, is one

The firsfaling diock edge produces QA= 1 and QB =0, Qc =0, Fig. Q.16.2 Timing sequence for a four-bit Johnson countar
Qp0 snce D De D are zero. If we design a counter of five-bit sequence, it has a total of ten
The next
ciock puise produces Q 1, Q, 1, Qc0, Qp states.
The sequence of states
is summarized in Table An n-stage Johnson counter will produce a modulus of 2xn
Q.16.1.
where n is the number of stages (i.e. flip-flops) in the counter.
Ciock pulse OA Qg c Op
Jonnson counter requires only half the number of tlip-tlops
00 compared to the standard ring counter. However, it requires
1 0 0 0
1
0 0
more
flip-flop than binary counter.
1 6.5: Clock Skew and Clock Jitter
1

1
a.17 What is clock skew and clock Jittering in synchronous
clrcuits? (SPPU: May-14, Marks 21

Table Q16.1 001

Four-bit Johnson
Clock skew :. Synchronous system using edge trigger
Pops gives desired output only it all tlip-tiops
see the

CECODD sequence 4 Guide for Engineering S?uden

A Guide for Engineering Sue
pECODD
 t e a m e time
Unit V
ter
fiir-finpe
are docked by t
theoreticaily

iteitioh
whee
ya FF2 is delayed
to the dok signal
seen by F

7 State Machines
relatfve

giftca m
wtvwen arriva
timee of the clock at different devi
evene

delfied a the
temporal variation of the ciock
. o k ter i (reference ede
wl regerc the
reference transifion
edge) s 7.1 Mealy and Moore Machine Representation
Coci Hter represents edge-to-edge variation
cie sigrna
Mealy and Moore medele ?
ekek gnel ir time Q What are
9 9, 10, kay- 2, Macs
END. Ans.: The synchronous or cuc ked Siertia Cirea:ts
tepresented by two models
when the output of the sequential cireit deperds oniy on e
ctesent state of the tlip-tlop, the sequent.al circuut s Festerte
Moore model.

on both the
When the output of the sequential circut depends
present state of flip-flopts) and on the inputi he t u e t a
arcit is referred to as Mealy model
a2 Compare Mealy and Moore models ?
(SPPU :
Dac. 10, 12, 15, May-12, 15. Mavka
Ans.

Sr. No. Moore mnodet saly odel

Its output is a function of

present state only
inpu
ic
nput changes does not atet nput hage ay Test
the ourput
Moore model requires mure
Bunber of states to
LImplemernting sane kuntior

3 Draw and explain the block diagram of Noare ode.

P P : May-1, Marka 4}

ns. Yflen the output of the sequernmai circuit depeis uniy O

circuit is reterrecd to
PEesent state of the fhp-tlop, the sequentia!
Moore model Let us see otis Exampie ot Moore modet
ECOD
 DigitalC i r c u i t
7-2 State Machines D i g i t a lC i r c u i t s 7-3
State Machines
rcuit which consists ofof two K
circuit after the application of a clock
shows a
sequential
has one
p-flop
ction gives the values of pulse, and the output
inpu the output
Fig. Q.3.1
flip-flops
and AND gate.
The circuit
Xand one present state.
variables during the
output Y.
state diagram.
Q5 Explain SPPU : Dec.-12, May-13, Marks 2
B
State diagram is a pictorial representation of
bahaviour of a

CP
Aential
a sequential circuit.
The state is
represented by the circle, and the
sition between states is indicated
by directed lines
icles. A directed line connecting a circle with itselfconnecting
indicates
at
a t next state
is same as present state. The
binary number inside
of Moore model ch circle identifies the state represented by the circle. The
Fig. Q.3.1 Example
As shown in the
is used to determine the
Fig. Q.3.1, input irectedlines are labelled with two binary numbers
separated by a
used to determine the output. The ot inputs eumbol /'. The input value that causes the state transition is
the flip-flops. It is not
derived using only present states of the flip-flops or combinafio labelled first and the output value during the present state is
it (in this case Y =Q4QB) labelled after the symbol /'.

In general form the Moore model can be represented with its blo k 7.3: Basic Design Steps
schematic as shown in Fig. Q.3.2.
Excitation variables
a.6 State the steps for design of clocked sequential circuits.
Ans.: Steps for design of clocked sequential circuits
Input
variables Next Output The recommended steps for the
state Memory decoder Output design of a clocked synchronous
decoder elements (Combinatlor varlables sequential circuit are as follows
circult)
1. It is necessary to first obtain the state table from the given
circuit information such as a state diagram, a timing-diagram, or
State variables
other pertinent information.
Fig. Q.3.2 Moore circuit model with 2. The number of states may be reduced by state reduction
an output decoder technique if the sequential circuit can be categorized by
7.2: State Diagram and State Tables input-output relationships independent of the number of states.
.
Q.4 Explain state table? Assign binary values to each state in the state table, i.e. state
[SPPU: Dec.-12, May-13, Marks 2 assignment.
Ans.: It is convenient .Determine the number of flip-flops needed and assign a letter
to translate
state the information contained in u symbol to each.
diagram into a tabular form called state
simply state table. synthesis table 0 5. Choose the
type of flip-flop to be used.
It 6.
represents
It consists of relationship between input, From the state table, derive the circuit excitation and output
output and tates tables.
labeled present state, flip-flop sta
three
Output. The present sections
state next stareand USing the K-map or any other simplification method, derive the
the
occurrence of aclock designates the state of flip-flops circuit output functiohs and the flip-flop input functions.
pulse. The Deefore
next state is
8. Draw the
state the logic diagram.
OECODE
A Guide for Engineering Sruue OHCODDD A Guide for Engineering Students
 Digitni C i w i s
State Machines D g i t a lCireuits 7 5
State Machines
7:4:State
Reduction and State Assignn
nt gtop 2
Find equivalent ates
technique. at the state table for two
explain state
reduction
May-13, Marks 3, L present states that go
a.7 Briely
SPPU: Dec-10,
13,
e-22, Marks 4 xt state and have the sarne to the
in sequential circutt sa we
output for both input
reduction can easily find hat states
OR Wite a note on state combinations, and e are
Ans.:The state reduction equivalent.

avoids the oo O0
/0
technigue basically raia is because, c and e both states go to states c and d
introduction of redundant and have
outs of 0 and 1 for X 0 and X 1,
respectively. Therefore,
states.
state e can be removed and replaced by c.
The reduction in
redundant
1/0
states reduce the
number of 0/0
The final reduced table is shown in
Table Q7.1 The state diagramn
required flip-flops and logic 1/1
gates, reducing the cost
of for the reduced table consists of only four states and is shown in
the final circuit. 1/1 Fig. Q.7.2.
1/0
The two states are said to be
Fig. Q.7.1 State
redundant or equivalent, if diagram Present Next state Output
every possible set of inputs generate exactly same output state

same next state. and

When two states are

X =0 X=1 X =0 X 1 oro
without
equivalent, one or tnem can be removed
altering the input-output relationship. a b C 0

Example b d 0
We start with
the state
a
sequential circuit whose
specification is given in C d 1
diagram of Fig. Q.7.1. a d
Step 1: Determine the state table for Fig. Q.7.2 Reduced stata
Table Q.7.1 shows the state given state diagram.
table for Table Q.7.2 Reduced state table diagram
given state diagram.
Present state Next state
Q.8 What is state assignment ? State the rules for state
Output assignment. [SPPU: Dec.-12, 13. Marks 3, June-22. Marks 4]
X 0
X =
1 X =0 X1 Ans. To determine the
b to
flip-flop input functions, it is necessary
C 0 represent states in the state diagram using binary values instead
d of alphabets.
e

This procedure is known state

as assignment.
w e must
1S
assign binary values
to the states in such way that it a

possible to implement flip-flop input functions using minimum

1
Table Q.7.1 State logic gates.
table
CICODL There are two basic rules for making state assignments.
A Guide for Eugineerlng Sudens DECODES A Guide for Engineering Students
 7-6 State Metkines 7-7
State Machines
DgitalCircuits

DipitelCii for
NEXT STATES for a
the same given
having
Rule : States should have assignments
whiich can be inpu Q/0
cmdihon
adjacent
cels in a K-map. groupe
nto logically
example
Rule 1.
for Rul As
hown 19
shows the in the
Fig Q82
there are
Fig Q81,
foar states whose
100 101 110 1 O/1
1/1
same.
next state is
states
for
(
assigntnerits 1/0
these states are 100, 1/0

30 130 and 111

which Can be 000 Fig. Q.9.1
grouped nto
Fig. Q.8.1 Example of using Rule 1
iogically adjacent Ans.: The state table for the given state diagram is as follows
oels in a K-map
Rule 2 States that are the NEXT STATES of a single Input Present Next Output
stato
should have assignment which can be X State State Y
grouped into
iogically adjacent cells in a K-map.
Fig Q8.2 shows the 0
example for Rule 2
0 S
As shown in the 000
Fig Q.8.2, ior state
000, there are four
next states. These
states are
assigned as
S2 So
100, 101, 110 and 111
1 S3 0
so that
they can be 100 101 S
gouped into logically 110 111
ASsigning states So 00, S = 01, S2 10 and S, - 11 we have,
adjacent cells in a Fig. Q.8.2 Example of
K-map and table using Rule2
Input Present Next State Flip-Flop Excitation Output
shows the state
table with State Table
Q.9 Design the assigned
states.
diagram shown insequentlal circuit using JK A B A B,
Fig. Q.9.1. fllp-flops, for state K Kg
(SPPU: Dec.-10, May-05, 0 0 0 X
11, Marks 8
DECODE 1

4 Guide for Englneerlng Studens

DECODE A Guide for Engineering Studens
 State Machines D i g i t a lC i r c u i t s 7-9
State Machines
D i i h e lC i r a

X
11 x Logic diagram

1X
0010 X1 AD
o111 XX
1000Xx ox
1X X o Clock
K-map simplification

For da For KA

11 01 Output
AR
D
Ka1 Fig. Q.9.3
For For KB
AS AB a.10 Reduce following state diagram. [SPPU: May-14, Marks 6]
x00 01 111 00 01 11 10
oox
N 0/0
g XA+X Kg 1/0 O/0
AX
0/0 0/0
For output
AS 1/0
001 11 10 1/0
0/0

1/1
1/1

Output XB AB 0/0 1/1

Fig. Q.9.2
1/1

Fig. Q.10.1

QEcOD
A Guide for Engineering wden
QEcODE A Guide for Engineering Stwdents
 7-10 State Machines D i g i t a lC i r u i t s 7-11
State Machines
DigitalCnwits

table
given state diaga: 3 : The reduced state diagram willbe as follows
1: Drawstate
Ans. Step
Next state Output
Present state
X-0X-1X-0X 1 1/0
a b 0 0 0/0 1/0

d 0 0

0 0 1/0 1/1 0/0

d

d 0 1
O/0
e 0 1 O/0
01 Fig. Q.10.1 (a)
0
a.11 Implement the following state diagram using D flip-flop.
Step 2: Reduce the state table by replacing redundant states [SPPU: Dec.-12, Marks 10]

(stateg replaced by state e).

is
O00
Present state Next state Output
X 0X 1 X = 0X = 1| 0/0 O/011/1 1/1
a b 0 0 1/1
o00)010
Cd 0 0 110 1/0
001
d 0
a 0 o/0
a 0

(100
Now state d and f are
redundant replace so state f by state d.
Fig. Q.11.1
Present state Next state Output
Ans. The excitation table for the given state diagram is shown in
X0X 1X =0X1| Table Q.11.1. Since D flip-flops are used, flip-flop excitations are
b 0 0 same as next states.
C d 0 0
a d
0 Input Present state Next state Output
e d
X B CA
a d 0
OECODES 0 0 000 1L 1 0
A Guide for Engineering Studens A Gulde for Euglneering Students
DECODE9
 .12 $tate Malinrs myltal Crult
7-11 State Machines
Digitnl Cwis
ede
nplomontatlon

PiDE
0
Fig. O.11.3
0

0.12 Design a cireult to generate ssquernce 02-5-4.7.3 using T FP

1 SPPU s Dec8,1, May-12,43, Marks 6

1 X X Ann.: Excitatlon tabls

0

Prerent state Next state Flip-1lop inputs

Table Q.11.1 Excitation table

Komap simplification aB cOA1 B1 Qc.1 TA T TT

for DA for Dg
00 11 10 00 01 11 10 1

oOZ o
) 1 1

Dg7K CKAB 1
For D
ForY
11 1 0
0 1 11 10

1 0

Fig G.11.2

A tuda
fur ngneerny Mulen 4 tutde fur fngliegring Studen
 7-14 State Machines Digita Circuits
7-15
State Machines
D i i t e lC i n i
Ans.:he minimum number of
flip-flops can be gjven as
K-map simplification

NS 2n-
For Te For Tc
Since max (0s, 1s) 4, N 4, therefore n
=
3. Table Q14.1 shows
0 01 11 10 o00 01 11 state
encoding
for given sequence using 3 flip-flops.
oX FF O/Ps
CP States

Te QA Qc
Fig. Q.12.1 1 1 7

Implememtation

3 0 1 1

0 0
5 1 0

6 1 1

Table Q.14.1
Therefore, design a circuit to get above state. In case of D flip-flop
Fig. Q.12.2 next states.
flip-flop inputs are same as

7.5:Sequence Generator Excitation table

213 Find the numbea of flip-flops required to generate the Present state Next state/Flip-flop
sequence 1101011.
Ans.: The gven inputs
sequence number of Os are 2 and number of 1s
aze5 Tnerefore
equation becomes,
max(2 5) 2 QA c QA Qc
0 0 0
2 0 0 0

Once the number of 1

fip-fops are
decided, we have to
uugue sates asSTg
nat corresponding each bit in the given
to 1 X

up-iop representing least sequence Su 0 0

sequence. (Usually, the output significant
of the
bit generates
the gve
signihicant bit is used to flip-flop representing least 0 1 1
generate the given
Q14 Design a
110011.. usingpulse-train
sequence). 1 0 0
D
flip-flop.generator to generate a PMarks se train
01 1
[SPPU: May-06, Marks 881
DECODE
A Guide for Engineering Students
OECODED A Guide for Engiueering Students
 7-16 State Machines D i g i t a i
C i r c u i t s
7-17
State Machines
D i g i t a lC i r c u i t s

K - m a p s i m p l i f i c a t l o n

For D
CP Flip-flop outputs Din States
For DA
01 11
10
00 01 1110 Qc
OA00 x x 1 0

DA Oc 3 0 1 0
DA OgQ,Oc
0 1 0
For Dc
5 4
O00 01 11 10 1
The required sequence is 0 6
ooxx
generated at the output of flip-flop A
7 0
State is repeated
Table Q.15.1 (a)

seventh state is repeated, n =3 is not sufficient. Let us try with

Logic diagram AS
Table Q.15.1 (6) shows sequence generation with
4 flip-flops. The
Desired
puise ran four flip-flops.

DE D CP Flip-flop outputs Preset States

Qc
1 1 0 15
CLK 7
0
0 1
Fig. Q.14.1 1 0 1 3

Q.15 Design a pulse train generator circuit using shift register for
the following pulse train. 4 0 0 0
1 0 0 0 1l
********* ...

0..... . 9
[SPPU Dec.-08, May-12, Marks 8] 0 0
Ans.: The minimum number
1 12
of 1 1
flip-flops n, required to generare
sequence of length N is given by
7 0 1 11 6
N s 2" 1 X 011
-

Preset flip-flop| 0 1
Here, N =
7, thereforen =3. The Table Q.15.1 (a) shows
11
generation with three seque 1 1 1 1 0 1 1 15
flip-flops.
Table Q.15.1 (b)

OICODD A Guide for Engineering

Students
A Guide for Engineering ents OICODES
 ngial irells

simplifhioation
tor n
Kmap

a,
)

Pebel
tlip flop
Fig. Q.16.1

Talle Q.16.1
Logic diagram

K-map
simplification for D
00 01 11 1

Frecel Loglc diagram

Fig. Q.16.1 (a)

Vcc
Preset
A Dc
PL
in Stat
Fig. Q.15.2
Q.16 Design a pulse train generator to
sequence 10110 generate the following
using shift register.
Ans.: The minimum
(SPPU : Dec.-14, Marks 6] C
number of flip-flops be
n can given as

Here N
N2h-1
5, therefore n 3. The

La4
=

generation with three Table 3 showS S

flip-flops.
Fig. Q.16.1 (b)
OECODE Studens
A Gulde for Engineering Studen A Guidefor Eugineering
DICODES
 State Machines u g i t a lCircutts
7-21 State Machines
. 20
DigvtelC i n w i

7 . 6 Sequence
: Detector is 0, we have tected the second bit
in the
hen i n p u t
sequence,
have
We
to go to the next state
detect the next bit in the to

sequence
detector to deto.
ect a erlal hen When input is 1, we have to remain in state b because 1
pe
DesignMealy E SPPU :Dec.-13, Marks etected may
dete start the
a.17
sequence
of 101. 61 ich we
have
sequence. Output is sti
input
the number of states in ero.

Ans. : In a Mealy type design of bits in the desired state

do 3. State c
the number
diagram are equal to have three in the
bits in the sequenc nput ed for state a and state b, if desired bit is detected we
we As explained
this exampie,
sequence. n diagranm. Once the
so
the number of otherwise we have to go to the previcus
three states in
the state
have to go for next state
we have
we have to
draw the airection lines with statee ate from where we can continue the desired sequence When
states are known of state
inputs and outputs. Let us start drawing direction lines, assuming have to make
eomplete sequence is detected we output HIGH and
state 'a as an initial state.
20 to the
initial state. This is illustrated in Fig. Q17.1 (c
1. State a 010
State a checks for 1. When input is 1, we have detected the first bit First bit in
n the sequence, hence we have to go to the next state to detect the sequence
10 detected
next bit in the sequence
Incorrect
When input is 0, we have first bit Third bit and 10
to Temain in the state 'a Oj0 may be fist
bit in the
because bit 0 is not the O10 next overlapped
first bit in the sequence. Initil
First biin sequence
seguence
in both cases output is 0 state
110 detected Third incorrect
Sinoe we have not
yet
detected al the bits in the
bithence
sequence has
to start from
O Secoi bit

sequence beginning
2. State b Fig. Q.17.1 (a) Fig. Q.17.1 (c)

From the above state diagram we can determine the state table as

First bit in shown in Table Q.17.1 (a).

6uerce
Geected
Incorect socond bit Present Next state Output
but may b state
0orrect firgt bf in X-
X 0 X0

b
b
cond bit in
Setnoe b
delecded
iv KIaheeere

Fig. Q.17.1 (b) Table Q.17.1 (a) State table

4uide for Lngneoring Siudents

A Gulde for Lnglnvertng Stinden coD
 7 2.1
i t u l( h r u a

State Machines
state Mahines
a 10 D r a
a Moore ype equenee detector tn detet a serial
velwi
tnO flip- flops of 101.
1PPy Dec.13, Marvs 6
Ant
minegnintheg
hevt
we" weguence

staes
thw 10 we can dete uput
Se
there
av

01 and
state
lna Moore type
Mo output design
eniy t n depends flip-flup
state Q171 (6). Therefor, in the state
statea
table as
shown in Table
Ann,
diagtam of More machire, the
Mal ritten with the state instead of with the
Output 7 transitiot
ettation

Next state
Present s t e Apart from this the proress of determining the
the states.
to that used for Mealy machtre iet us
I r t w e n

dgram is simil.
stuat initial state.
ith state '
8 an
N-1X 0 X-I slart

1 .Stato a
0

input is 1,
we
When
0 huve
detected

bit in
thencorrect
the first bit
-CO Corrac
first
Table Q.17.1 (b) Excitation table sequence, hence we

g0 to the
K-map simplification have to
For A For B For Z state to detect
next
Fig. Q.18.1 (a)
bit in the
AB
the next
is 0, we have to remain in the state 'a
Sequence. When input
not the first bit in the sequence. In both cases
00 0 because bit 0 is
output is 0 since we have not yet detected all the bits in the
01 0 0 sequence.
11 X b: When input is 0, have detected the second bit in
2.State we

10 the sequence,
hence we have to First bit in
ABX B X Z AX the next sequence
80 to
Fig. Q.17.2 (a) detected
Logic diagram state to detect
the next bit in
the sequence.
D When input is 1,
we have to
Sacend bit
remain in state b in the sequeNcE
delectet
because 1 which
CLK we have detected
Fig. Q.18.1 (b)
may start the

Fig. Q.17.2 (b) D Sequence. Output is still zero.

A Guide for Engineering Studens
(5-1) OECODE
 7-24 State Machine Digital
Circuits 7-25
Digital Circuits State Machines
occurs, the 101 seo
the sequence above state
ate di¡
when a 1 input From the diagram we can
determine the
3. State c:Now,
must equal
ot ongo
to 1. Here, we cannot
back
s
in Table Q.18.1 (a). state table as
and output
completed
state b (since output
in state b is zero)
and hence we have
to have createto s h o w n

1.
Present state Next state
new state d with a output Output Z
0
X=0 X=1
Fist bitin
seguence
detected
*Wwwww0w
C

C d
d C
b
Table Q.18.1 (a) State table
Second bit
in the sequence
detected there are four
Thirdbif Since Present state Next state A" B"
inthe we need two |Output
states
sequernce
detected flip-flops. Assigning ABX=0X=1 Z
Fig. Q.18.1 (c) b =01,
state a00, 0 0 1
0
10 and d =
11
c 1 0 01
we can determine
the excitation table 0 0 1|1 0

as shown in 011
Table Q.18.1 (b). Table Q.18.1 (b) Excitation table
0
K-map simplification
For A For B For Z
X
AB 0 1 AB 0 4 0
Second bit in
Overlapped 00 00 0
Sequence detected
Fig. Q.18.1 (d) o1 01
In caseif input is zero, we
have to restart
sequence and hence we have to return to state checking of input 11 0 0
11 0
a.
4. State d : Since
the
When input is 1, we
sequence is detected, this is the last state.
have detected the first
bit in the next
1 10

Z AB
sequence, hence we have to go to state b. A = ABX B X
When input is 0, we have detected the
sequence, hence second bit in the (AB +AB)
we haveto go to state overlapped
c. (A B) Fig. Q.18.2
DECODE
Students
A Guide
for Engineering Students ORCODE
A Guidefor Engineering
 7-26 State Machines Digital
Circuits 7-27
State Machines
Digital Circuits
When input is 0, we
State c : have O/0
Logic diagram detected the last bit in the sequence,
we have to go to the initial state,
hence w e

B next sequence and make

next /0
A Dg detect
the

to high indicating sequence is O/0

x- output

ted. When
letected. w input is 1, we have to
the state b' because 1 which we
0/1
to
e
have dete detected may start the sequence. 10
Assumingsta assignments as a = 0,
K Fig. Q.18.3 and = 10,c we can determine
01
tation table for above state diagram (c)
Q.19 Design a sequence detector to detect the following so.

using JK flip-flops. (Use Mealy

Machine) ... 110 equence shown in
Table Q,19.1. Fig. Q.19.1 State diagram
(SPPU May-07, 14, Dec.-08, Marks 4 as

state Next state Output

O/0 Input |Present Flip-flop inputs
Ans.: The given sequence has 3-bit, so
BAnB, Y
8
we require 3 states in the state
direction
X 0 0
diagram. Let us start drawing 0 X 0X
lines, assuming state 'a' is an initial
state.
1/0 1 0 0 0 0X X1
0 0 0 1
1 X 1 0
State a: When input is 1, we have 0 0 0 0 X1 X
detected the first bit in the sequence, 0 0 0
1XX1
hence we have to go to the next state (a) 1 0 0
X1
to detect the next bit in the
1X
sequence. 0/0 Table Q.19.1 Excitation table
When input is 0, we have to remain in
the state 'a' because bit 0 is K-map simplification
not the
first bit in thè In
For JA For Ka For a
sequence. both cases 1/0 AB AB AB
output is 0, since we have not X00 01 1110 X00 01 11 10 00 01 11 10
detected all the bits in the yet oo xx
sequence. 0/0
State b: When xxx
input 1, we have
is A XB
detected the second bit KA1
in the
sequence, hence we have to go to 1/0
next state to the For Kg

detect the next bit AS

sequence. When input is 0, we in

X00 01 11 10
the
have to ox1x x
go to the state 'a' to
in the detect the first bit
sequence, i.e. 1. () Kg 1

OECODE Fig. Q.19.2

A Guide
for Engineering Students OECODE A Guide for Engineering Students
 Digital Circuits
7-28
State Machtne Digital
Circuits

7-29
Loglc dlagram K-map simplificatlon State Machines
For dA
X
AB For hA
A B 00 01 11 10
X
X 11
x 10

JAXB
x
CP
Flg. Q.19.33
For a
machine for For Ka
Q.20 Design sequential circult using Mealy
a
JK
1011.... Use flip-flop. etectlig 00 01 11 10
00 01 11
the sequence . . .

(SPPU: Dec.-12, Marks an 10

xx oX 11
Ans.: State diagram 1 Xx
0/0
X
1/0
Fig. Q.20.2
1/0 Logic diagram

0/0 0/0 1/1

0/0
1/0
Flg. Q.20.1
B

Clock-
D -Y

State table
InputPresent Next StateOutput Flip-flop inputs
State
X
A
BAB,Y KA Fig. Q.20.3
0 0 0xX
END...
1 0 1 Xx
00 0 0 0 X
0 0 0
0 1 0 X 1X
0 1 0 0 X X
1 0 1
1 0 X 0 1 S.
11 1011 X X0 A Guide for Engineering
 D i g i t a lC i r c u i t g

Unit V 8-2
State
name
Entry
Coding of
Algorithmic State Machtnes
tlip-lop
Algorithmic State values for
yYy hls slate

8 8.1 Introduction to Algorithmic

Machines
State Mac
Reglster operation
or Output

| Exlt

(a) Goneral descriptlon

2 1

(b) Spocilflic oxamplo

chart ? (SPPU: Dec.-08,10,15, May-11,13. Fig. Q.3.1 State box
Q.1 What is ASM The
D e c i s i o n
box decision box describes
that has isbeen developed the effect of
Ans.: A special flowchartalgorithms
define digital hardware
called an specifically
Algorithmic
on the control

more exit ths,

hrol subsystem. It has a
diamond shape box an input
as shOwn in
Fig. with two or
Machine (ASM) chart. State more written inside the diamondQ32.
tested is written
The input
condition to be
from conventional floueh. tethat may be assumed by an box. Each value
Q.2 How does ASM chart differ either 0 or
(SPPU: May-o-09,12, Dec. art? input or expression in a
Marka associated with an exit path from that diamond. diamond is
Ans.: The ASM chart resembles a conventional flow chat z he These lead paths
blocks corresponding
interpreted somewhat differently. A conventional flow but to to the next
states of the circuit
following the next clock pulse.
describes the sequence of procedural steps and decision paih chart
paths
an algorithm without concern for their time relationship. An
chart describes the sequence of events as well as the Iiput
relationship between the states of a sequential controller and timing Condition
events that occur while going from one state to the next.
Eit path 1 Ealt path 2 Exit palh 1
Exit palh 2
Q.3 State and explain basic components of ASM chart.
P [SPPU: Dec.-11,13, (a) Gonoral doscription
(6) Speclftc 9xampla
May-13,15,16, Marks 61
Ans.: An ASM chart consists of three basic elements Fig. Q.3.2 Decision box
The state Conditional box
box, the decision box, and the conditional box.
State box : A state in the control The state and decision boxes are
From exit path of decision box
sequence is indicated by a state familiar from use in conventional
box, as shown in Fig. Q3.1.
flowcharts. The third basic element, the
As shown in Fig. Q.3.1,
rectangle shape is used to represent state conditional box, is unique to the ASM
LIst of
box. (At the left of this box is the name of the chart. It is an oval shape box. Its
state, such as A, B conditional outputs
Q On the right hand top corner of the box is a list
of the rounded corners differentiate it from
tlip-tlop values that define that state. The ircuit that the state box. The input path for the
occur whenever the circuit is in the outputs can

corresponding state regardless conditional box always comes from one

of input values are listed within Conditlonal box
the box.) Finally, a line drawn of the exit of a decision box. The Fig. Q.3.3
paths
from state box, known as when the path to a
exit, indicates the path to the next state. outputs that occur
within the box.
Conditional output box is satisfied are listed
udens
A Gukde for Engineering
(8- 1) OECOOD
 Digital Cirwits
-3
Algorithmic Statei
llsted in either the D i g l t a lC l r e u t t a

The outputs
that are no

ASM chart are alre state box eeisuevpr

conditional box in a particular ways Imactive Alyorithmic State Machines

that state.
the circuit is in CP
[SPPU
of ASM chart,
May-12,15,16, Marks
Ma.
the features Inputs

Q.4 Llst

ASM chart describes

the sequence of
Ans.An
between the states of a events
sequen
as
Co well a
the timing relationship
while going from one
and the events that occur
block in an ASM chart specifies the
state to
controlle
the next.
01

Every
one common clock pulse,
operations that 1
be performed during are t
The operations specified within the state and conditio 1 1
the block are performed in the datapath subsystem. boxes in Flg. Q.6.1 Output
wavetorms
The change from one state to next is perfe Ans. The ASM chart can be
erformed in the states, one for each clock
drawn for above
waveform with
subsystem. ntr of
For each state the
cycle the waveforms four
period. with the
output will be conditional
An ASM chart consists of one or more
input lines in effect
longest
interconnected bloc.
ocks.
of the at that time. Let on the values
An ASM block has one entrance and
conditions at different states. us observe the different
any number of evit
represented by the structure of the decision boxes. paxths 1.State Q In the first state,
Q, ie. in the first
clock cycle, all
Each block in the ASM chart describes the
state of the waveforms are at logie .
Iherefore, the output, Z 1 =
and is listed
during one clock-pulse interval. su.
system in the state box for the first state, Q
Q.5 Mentlon applicatlon of ASM chart 2.State Q: In the second state,
Q, i.e. in the second clock cycle,
(SPPU May-13, Dec.-15,
:
the output is 1 except for the waveform
Ans.: ASM chart is used to Marks 2 to corresponding inputs
circuit with the represent state
machine/sequential xX -
11. This condition can be
tested by expression x, AX, in the
description of sequence of events and timine
relation between the states. decision box. When the result of expression is 0, the
inputs are
other than xx, 11 and hence output Z =1. This is
=

decision box and conditional box in state

represented by
8.2: Construction of ASM Chart and Q,
Realization for Sequential 3. StateQ During the third state Q ie.
in the third clock

Q.6 Develop an ASM

Circuits| pulse, the output will be 1, if x, = 1 The condition of x is checked
chart for a and accordingly output is made 1 by decision box and conditional
that will
output any one of the fourcontrollable waveform generator
as
determined by the values of waveforms given in Fig. box in state Q. Looking at Fig. Q6.2 we can realise that the output
period of the first two waveforms is two inputs x, and X2.Q.6.l,
its
The of third waveform in state Q, and state Q, is same, ie. logic 1. In
the third is three, and the four clock cycles, the
clock of period period ot
the fourth other words, in state Q, the third waveform starts new cydle.
cycles, waveform
waveform respectively.
ls
new When an
input change does ttne not used and line goes
may begin at occur, herefore, when x,x, 10, the fourth state is
=

any point in its period. back to first state to start the new cycle

OECOD A Guide for Engineering

Studens
A Guide for Engineering Stdems OECODE
 D i g t a lC l r c u i t s

Algorithmic State Machine Aigritemie State Machines

8-5
example,
the ASM chart
of
inputs 1, and 1Fie,ia,GA2
Consider,

and two control

Digital C w i t s
state
t consiss
in the
the
00
four
consists two
nplementation. stcws there
t Q7.3
4State Q ie.n
leve

register with two lip-fios,

2 moitipieers,
a MI d
fourth state Q, the
21 M

com
U

ircuit to determine the

X

nbinational circuít
A
and , nd
the fourth cycle,
01 registe are used to select the
output. Tre cstyats of the
0. inputs o he
register is used multipjæsars.
is always in s
output state of the
the the present to eiect e
From state Q4 way

inputs f r o ach multiplexer. The outputs of the te

circuit
returns to Q so
1 to the D inputs of A and B The mlpiesers arz
sf eaxc
then a p p l i e d

waveforms
0
1A X2 is to produce an input to its
purpoe
the
that iplexer correspon.dang ac-ia
qual to the binary vaueeof the next state
multi;

may be repeated.
us express the
Let puts of the ultiplexers are determuned from the decsio
ASM chart
as a

that
state

in
O-01 The
boxes and
annd state transitions given in the A5M charts Reter
know
table. We O.6.2). The present states, next states and conditons or
list Fig
the state tables
we
ansition
can be tabulated for ASM chart gven in Fig Q2 as
with
the outputs along Table Q.7.1.
in the
shown in
states
the next
No.
Present state Next state Condiion
columns
corresponding to each
L 21
combination of input (Q10 0 Q
values. 0 010
1 0(Q)0
(Q3)
Q
(Q)1 1 ) 0
Table Q.7.1
waveform generator
chart for
Fig. Q.6.2 ASM Inputs for Multiplexers
with
with the suitable
controller
method MUX2
the MUX Dec.-08,15 May-11, Marks 8] MUX 1
a.7 Explain [SPPU:
example. realisation of 01
forward method
for 00
It is simpler and
straight method, the gates 10
Ans.: controller. In
this
1 1
combinational circuit for any and registers,
registers,
multiplexers
are replaced by components. 2 +
and flip-lops three levels of
In this method there are
next state
30
respectively. the
consists of multiplexers that determine
the 30
The first level that holds
level contain a register Table Q.7.22
second
of the register. The the decoder that provides
The third level has
Sudents

state. Engineering

present binary state. Sometimes

cômbinationa 4 Guidefor
for each control
a separate output
of decoder.
circuit is used in place DIcoDE)

udents
 8-7 Algorithmic State Mar D i g i t a lC i r c u i t s
8-8
Digital Circuits
uX 22 genee Algorithmic State Machirs
input for
flip-jlop A and MUK
generates input r
1 generates
Note MUX multiplexer inprt can be
determinea
by nehdino uding condition
Aip-flop B. The
in the next state o
coresponding
to logic 1
bit position
A the next state
Consider the
ner hence
ransition

from Q
to Q2 For flipfiop For fip-fiop B the
transition s 9
multiplerer given conditions1,
coresponding input of multiplexerI
s the given
the
corresponding input of
hence the
transition, ie. 1.
In this ca
from Q3 to Q1 or Q4. e, the nex
the transition
Consider
state for flip-flop
A is 0 for Q1
and 1
corresponding to is the
Q4 Therefore,
taken 2ss ASM chart fo
Fig. Q.7.1 (b)
condition of transition 1 i.e. xix2 +x,.
an
a 2-bit binary counter
a.8
corresponding input
of muliplexer line E tch that:E
such = l (counting enabled) E 0 having enable
(hold present
=

The equation for output

Z can directly derived from ASMM
be chart count). SSPPU: Dec-98, May-12, Marks 6
ASM chart and find the.
For this we have to
observe the condit
1 thereforeons Ans.: The output represents the output of the counter
in state Q, Z
=

when output is 1. For example, AfterZ.

appear in the equation
for output collecting
all the
conditions where Z=1we get
Z + 9 MA +09 *2 *AB*AB x2 +AB1

Logic diagram

M
(1)

1 4:1
MUX
(2)

CP
Fig. Q.7.1 (a) ASM Chart
Fig. Q.8.1
 8-9 Algorithmic State Machih. D i g i t a lC i r c u i t s

8-10
DigitelC i n i t
Algorithmic State Machins
state table
for a
2-bit UP-DON
2-his
ASM chart for the
tth output Q1 following
a.10 Draw A S
and
M 1:Up counting state
and enzble machine
chart
M 1:
=

Draw an
ASM
input: counter A o-bit
two-bit
a9
having mode
control
co at lesign. I f
X = 0, Counterhe sta
r e s the state changes signal X
ignal is to be
counter
M= 0:DOWN counting output 1
whenever
beco Counter should remain n
as 00-01-10-11-00.
a
PPU: May-05,14, Dec-12, 1, present state.
The circalt
should
generate
Marks using
circuit
JK-FF and suitat
Design
May-6,37,14, VarksyourT]
: ASM chart:
Ans: State diagram Ans.

-O-
a B-0A

Fig. Q9.1

ASM chart
01
B-0,A

10
B-1.A0

11
8-1, A1

Fig. Q.9.2
Fig. Q.10.1 ASM chart
ECOO
A Guide for Students
Engineering Students A Guide for Engineering
OICODE
 Algorithmic State Macki, 8-12
D i g i t a lC t r c u i t s
8-11

input
conditin
Madntnes D i g i t a l
C i r c u i t s

Algorthmic State Machines

multiplexer
the
gven
A n s .

shows
Q10.1
The Table
example Next state
Input Multiplexer input
Present state ndition MUX 1 MUX2
condition
001
A B C 0,B 0.A 1
B X 0
A
0
0
X |0

X
0
X
T X X
011
X
0
Table Q.10.1
C 0,8 1,A=1
Logic diagram

X
MUX 1

101
C 1,B 0, A=1

L7.
0

B
MUX 2

111
CLK C 1,B 1,A=1
Fig. Q.10.2
Q.11 Design a sequence generator circuit to
multiplexer controller based ASMgenerate
1-3-5-7 using sequence the
Consideration i) If control input C approach.
circuit in the same state. ii) If 0, the sequence generator
=

control input C= 1, the

generator circuit goes into next state. sequence
[SPPU: Dec.-13, Marks 7] Fig. Q.11.1

OECODES A Guide for Engineering

Stiudents

A Guide for Engineering Studens

ECOD
 State Mathi
DigielC w i s

Present
Next state
nput
Multiplexer input
state
condition

MUX 1 MUX 2 MUX Unt V1

BC A
X
1
X
9 Programmable
Logic Devices
0 1 1 0 1
1 X
1 9.1 ROM
101111 X as PLD
111
11 Draw and explain structure of ROM
OR matriz PROM wth the
11001 Q.1

AND
matrix and heio
of
rhe ROM/PROM 15 a two level
Logic diagram Ans.

minterms form.
implementation in sum ot

AND
matrix
-

It is used to form product terms.

OR matrix is provided produce the to
The
logical sum of the
term outputs of the AND matrix.
roduct
P r o ,

Address input

MUX 1
MUX 2 MUX
Einterms

S S, S0 AND
matrix

TTTT Fus8s
OR
natrix

AND-OR gates
PROM with
Q.1.1 4x2 circuitaccepts
Fig. ROM. The to
equal
circuit using number
c o m b i n a t i o n a l binary
a an
output
CLK 2Design
and
generates
number
-DIt
Fig. Q.11.2 of input
number.
square

END...
(9-1
Guida far Fupiugering Studen
 Digiel Cinwits

Ans.
9-2
Programmable Logic Devicessi
D i g i h a lC i r c u i t s

9-3
Binary Square of numt
input on
address
on data lines mber t
consists

terms, mn sum
of
n-inputs, output buffer
terms, input and
Programmable Logic TDevices
lines
vith m
oduct constitu aoutput 'busfers utputs, m product
terms

numbers
Biney- 86 F2 Square
BB,FFP
0 0 0
00
sum terms constitute a

Fuses are inser

gtoup oi goup
between
to each of the AND
al
m OR
of m
gates,
AND
called zates
gates n-inputs and theit
and
OR matri the
atru
ROM F3Outputs
o o 1 are also provided
Os 00001 0
01 0000
Fuses
and the inputs of the OR
between the
gates. ourguts oí the
AND zaes
o 1 1 0 01 The third set of fuses in the
0o tion to be generated either
output inverters allows
100010 000
1 0 AND-OR-NVERT form.
in the re
ANDOR torm c output
1o 1 1 0o Input buffers provided
m te
1 10 1
are
in the PLA
001o0
1 1 11100o1
sources that drive the inputs. imit
loading oi te
(a) Biock diagram The driving capacity of PLA is
increased. by
(b) ROM truth table the output. providing biets at
Fig. Q.2.1 o4 A combinational circuit is
9.2: defined by the functions
Programmable Logic Array (PLA), F. m (3, 5, 7), F2 2m (4, 5, 7). Implement the citcutt
Programmable Array Logic (PAL), ith a PLA having 3 inputs, 3 product tems and two outputs.
Designing Combinational Circuits using PLDs SSPPUDec.-10, May-1i, Marks S
Ans. Step 1: Simplify the given Boolean functions.
Q.3 Explain the block diagram of a PLA. The Boolean functions are
simpliied, as shown in the Fig Q41
(SPPU: Dec.-10, May-11, Marks 6, June-22, The simplified functions in sum of products are ootaired from the
Ans. PLA stands for Marks 10]
Programmable Logic Array: maps are
In PLA, both AND and OR F AC BC, FA AC
gates have fuses
therefore in PLA both AND and at the
inputs, For F For F
OR gates ACO01 111
Fig. Q.3.1 shows the block
are
programmable. 00 01 11 10

diagram of PLA.
o o
Fo BC
F AS AC
F, AC +

inpts inp AND OR

buer ratr inver Flip-tlaps/ Fig. Q.4.1
matrix output Outpuis
non-inven
matrix buter there are three
St table: Therefore,
p Write PLA program The
| m-1
BC and AB,
and two sum terms.
m-1 terms: AC,
(output enable) C t Pproduct consists of three columns
shown in Table Q4.1 first column
TLA program table outputs.
The
and
Fig. Q.3.1 Block diagram of a PLA Specifying product terms, inputs
Srudens
1
Guide for Engineering
 Programmable L.ogic Deviees Digltal
Cireult 9-5
Dieihal C w s
Programmable logie Devices
terms numerically.
The
secon colux clreult la defined by the
c o m b l n a t l o n a l

ists of product a.6 A functons,

gives the paths
ts and AND
inputs
between
m (1, 3, 0 ) 2
the circuit with a
m (5, 6,7
PLA
specifies the required
the required paths
between the gates, f ent having 3 inguts, 3
ieseach ble, we writeAND (5P9 May-15, product terms
and two outpute.

third column specifies

and the OR gates.
Under each output
o
variabl
a' gates Ans K-map simplification Dec.13, Marks 31
înverter is to
be bypassed
be
and c for For F
true) if the
complement) if
output
the function
to be
complemented
is ted with
ool the
BC
inverter. The product terms listed on of
the left of first column
first output
are not
A 00 01 11 10

table they are ded

include for
referenc only
the part of PLA program

Product Inputs Outputs

term F BC+
FA3AC
Fig. Q.5.1
A BCF: F To implement For F
AC 1 111 functions Fand BC
1 1 A 00 01 11 10
BC 2
we require
C 1 11 1
AB 3x4x2 PLA and
o

TT TIC 1 we
have to 1
Table Q.4.1 PLA program table implement them
F C+AB
3x3x2
Step3: Implementation using
PLA. There we
Fig. Q.5.2
A BB cT

have to examine product terms by grouping 0s instead of 1. That is

function.
product terms for complement of a
Looking at function outputs, functions Fi and Fh have one common

they
term. Thus have total 3 product terms and can be
product
using 3x3x2 PLA.
3 Product terms implemented
AC PLA program table

BC Product terms Inputs Outputs

A B C F F2
AB
C
AB
2 Sum
terms AC
C

Table Q.5.1
Fig. Q.4.2
 7
e mmable tngic r i t a l C i r e u i t s

Deri Programmable Logic Devices

mpiementatkon

ThPe
-
-

3 P r d u c tenns

AB

AC

ww ww

2 Sum
erms
*** Fig. Q.6.1 (b)
Link open
to get
Link close
D e s i g n the following multiple output function using PLA.
complemented
Output o get F1 (a,b,c,d)
=
2m (3, 7, 8, 9, 11, 15)
uncomplemented
Output (a.b.c.d) = 2m (3, 4, 5, 7, 10, 14, 15) S P : Dec.-13, Marks 7

3 Ans.
2 Outputs

Fig. Q.5.3 For F1 For F2

Q.6 A combinational circuit is
defined
Implement th circuit with PLA having by3
the following
functions.
00 01 11 10 ac
and 2 outputs : input, 4 product terms 00
F (A, B,
F2 (A, B, C)
=
Em (1,
C) = Em (0, 2,
1, 3, 4) 5)
3, 4,
D[SPPU : Dec.-14, Marks 8] 01
Ans.: K-map simplification
11
For F
4
BC BC For F2
1,
00 01 11 10 A 00 01 1 1 10
1011
Fabc*cd F, =abc+acd+abc+acm
1
Fig. Q.7.1 (a)

F, BCAc
F2 AB + +
Fig. Q.6.1 (a)
OECOD
A Guide for A Guide for Engineering-
Engineering Studens RcoDE
 9-9
Digite! Cinwiis
Programmable Logic Derira igttalCreuita

Programmable Logie Drvices

implementation Using PLA
01 1
011

011 11
10 01
9 1 0 01 1 16
6 Product terms
simplification
2: K-map
Step

For a

11 10
CO

01
AB

00

01 o
11

1 x
a A+C+BD+Bb

For d For
CD CD
AB00 01 11 10 AB00

00
2 sum 01
terms
11 X x
B3 B2
Fig. Q.7.1 (b)
Q.8 Design seven-segment decoder
using PLA. d B CD BCo Bc+A fzA-C-8-e
SPPU: May-14, Marks 7]
Ans.: Step 1: Draw For
truth table for
7 segment decoder.
BCD-to-common cathode
00
Digit A
0
BCD a bcd e
efg
00 0
0 1 1 11
1
2
00 0
1 0 1 1
110 11

0 0 00 0 0
3
00
10|1
1
1 0 11 0
1 1 11 1
9 A+8C+BC+C5

00 Fig. Q.8.1
OFCOO
 Digitel Ciwis
9-10
Programmable Logie Devir D i g l t a l
C l r c u l t s

9-11
table. evttey Programmable Logic Devices
Write PLA program Step
, 4 : Implementation
Step 3:

Product terms Inputs Outputs A-

B cD a b C d
15 produo
terrng
1 1

BD 3
30
BD 4

B 5 0
CD
CD 0 0
CD

CD 1 1

C 9 0

D 10 D
CD 11 1 0
D
BC

BCD 12 0 1

BC 13

B 14
1 0

BD 15
Fig. Q.8.2

Q.9 Implement following function using PLA. 4, 5).

Em (0, 2, 5, 7), F, (A,
B, C) =
2m (2, 3, 6)
(A, B, C) =
[SPPU Dec.-09, May-14,
Marks

Students
Engineering
DECODD A Guide for Engineering Studens
A Guide for
ORCOD
 9-12
Programmable Logie De D i g i t a i
C i r e u i t g

9 13
simplification Prog ammabie
Ans.: Step 1:K-map
PAL
with the help lrgi Detves
F,(A. C)
B. Em(0. 2 5,7) F (A, B, C) Xm (2, 3, .10
Explain
sest
diagem
BC 4,5 Ans.:PAL (Programmable Array Logc
0 0 01 11 0
00 01 11 10 that PLA is
0 We have
,we a deise w a seen

d prograrmmable OR array
array and Howe ptogame
*****
?AL AND
array
prograrmmable 1
logic is
progratate a

AND array.programma

FAB,C)= AC :FalA,B,C) = +AB and a ecaxe oniy

prograrmmable,
the PAL is
easier ANzates are
Step 2: Write PLA program table flexible
the PLA. proigaa
as s ts
Product terms Inputs Outputs shows the array logc s a
Q10.1

four outputs. Each inout ypa ?A

Fig
has
A B C F FE inputs
and has uffer ard a ior
It is important to note that w
1 gate.
gate.
zates ate so
1
posite graphic symbo witn nomal and compiemert woa
AC 2
There are
four sections. ach secticn has
ree
AB 3 1 AND gates and one fixed OR zate he ouro oiprogamn ga
AB 4 1 0 connected to a uffer-inverter gate and en tei baxk
inputs of the ND gates, throuzh huses Tis aas
Step 3: Implementation
er to feed an output functon back äs a
g t var
create new function a Suc PALs ar
eed a s
Programmable I/O PALs
A- C
For
AB
- 4 product
1efms
01

D
AC

AB
D Fo
AG

2 t5

yAEC c* AT
Fig. Q.9.1
Su e=
Engineering
A Guidefor
A iulde fur Euglarerlug Smdents
 Programmable Logie Debire
Dieitnl Crewits
W
D M g i l a lC i r e u i t s

9-15
Prodvct step2 Implementation Prozrammable Logic Devices
terms
A BcTo

All fuses intact

always 0)

10
Fig. Q.11.1 (a)
11

12
a.12 Design BCD to
Excess-3 SPPU:
converterDec.-07.
using PAL
12. ,
May-13. Marks 3
D- X Fuse intact
Ans.: Step 1: Derive the truth table of BCD to Excess-3 converter

Fuse blown Decimal BCD code Excess-3 code

Fig. Q.10.1 Array loglc for typical PAL
Q.11 Implement the
following ustng PAL B, B BBEy Ez EE
F(A, B,C, D) = m (0,1,3,15) 0
(SPPU: Dec.-19, Marks 6 0 0
Ans. :
K-map simplification 0
For F
A C o

0 0
AB 00 01 11 10 0
oo 0

10

FABCTEo+ABCD Excess-3 code

converter
Flg. Q.11.1 Table Q.12.1 Truth table for BCD to
PICODED A Gulde for
Engneering
5Students
A Gulde for Englnrerng Studets retna

paco
 Pvogvammabie Legi r H g i t a lC r e u i t a
17

finetions for Excess-3 coda

theeiesn 8, , 8 , a, 3, 3, a
Programmable togte Dettee
Step Simplify the Bovlean
Fer

00
01

E,,8, 9,8 B

For Eo
01 11 10
0o
x

Fig. Q.12.1 K-map simplification

Fig. Q.12.2 Logic diagra
Step 3: mplementation
9.3: Diference between PROM, PLA and PAL
Product terms Inputs Outputs a.13 What is the difference between PLA, PAL and PROM
SPPU: Dec.-04, 08. 09, 10, 13, ay-06. 22. 24 15 ars
B B B BE E E Eo
Ans.

Sr. PROM PLA PAL

BB No.
0 0 1
AND array is fived Boh AND nd OR Crar is txed
, Bo 1
and OR arrav is arraare
01 rammse ae
programmatle.
00
2 Cheaper and
than A and ROs sp
1 1 simple ta use.
9
All minterms are

TT TTIc decodei
Cesire rnter
Cesred mrtEs
Table Q.12.2 PAL
program table
ECODE w
4Guide for Fagineering Stsdenh A Guiie for
Ëngineeing
tuderm
 9-18 Programmable Logic n Digital
Cicuits
9-19
Programmahie Logic Devices
Digihel C i n w i s

Any Boolean functions

Any Boolean
Devas the look-up table
used
is in FPGAs
be
It.is
hat c
can be programmed to pertorm logic functions.
be actually a memory
Only Boolean

runctions in
in SOP
form can

implemented using
functions in SOp
form can be
LUT:

that
an

Each logic block

standard SOP form
device
The logic blo block: in a
generic FPGA contains
can
e
implemented using
PLA.
implemented usino
PLA.
severa logic elements.

gic element: It ,contains an LUT, associated logic, and a

PROM. The

Architecture FPGA and

of FPGA an CPLI flip-flop

9.4:General and explain the block diagram of CPLD

and
Draw
the structural block
diagram
FPGA of a. 15 [SPPU: May-14, Marks
and explain SPPU: Dec.-05, May-07, 08, Marks
Q.14 Draw genera architecture of CPLD.
the
4 Explain
short note
on
FPGA. SPPU: Dec-11, Marks 61 OR
SPPU: Dec-13, Marks 6
OR Write a
of in detail the architecture of CPLD.
of FPGA consists
an

The basic
architecture of logi Explain
Ans. programmable roOW and
column inter OR F|SPPU: Xay-15, Marks 6]
blocks
channels
with
surrounded by programmable I/0 blocks as shor in
based
necing Block Diagram: The Fig. Q.15.1 shows the block diagramof
Complex Programmable Logic Device (CPLD). It consists of
architectures are on Ans.
a
Fig. Q.14.1. Many FPGA rather han on (sum of product
type of PAL like blocks, IO blocks and a set of
called LUT (look-up table)
a
collection of
memory are. Anoth
SOP AND/OR arrays
as CPLDs approach found on interconnection wires, called programmable intercon1nection
some FPGAs is the use of multiplexers to generat logic functions
cture. The PAL like blocks are connected to the programmable
InputiOutput interconnect structure and to the 1/0 blocks. The chip input-output
block
attached to the I/O blocks.
are
pins

Row PAL-E
Logic PAL-like
Logic Logic LOgic
block
interconnect block biock
blook block block
block

Logic LOgIC Logic Logic

block block block block

Programmable interconnect strUcture

o
Logic Logic Logic LOgIC
block block block block

1/0H PALike
block block
PAL-e
biccx
10

Column
interconnect CPLD
Q.15.1 Block diagram of
Flg. Q.14.1 Basic architecture of FPGA Fig.
Students
Engineering
A Guide for
OECODD A Guide for Engineering Stmdenis OECOD
 9-20 Programmable Logie Deviee,
Digital Crcwits

the
CPLD usually consists
consists
ot
PAL ike block in
the acrocell in CD
macrocell CPLI abou
flip-flconsi
op, sts
A macrocells,

Like other EX-OR

EX-OR gate,
gate, a
a
16 m a c r o c e l l s . an
configuration,
AND-OR
of
of
tri-state
buffer.
multiplexer,
and a

between FPGA and CPLD

Comparison
9.5:
between
FPGA
and CPLD.
Q.16 Explain
diference
[SPPU: Dec.-15, Marks 5
Ans.
FPGA
CPLD
No.
basic Fig. Q.14.1 shows the basic
1. Fig. Q.15.1 shows architecture of FPGA.
architecture of CPLD.

like They consist of Configurarable

2. They consist of PAL Logic Blocks (CLBs), I/O blocks,
blocks, 1/O blocks and
row interconnect and column
programmable
interconnect structures. interconnect.

They use AND/OR arrays They use memory called LUT

3 (Look-up Table) or multiplexers
to generate logic
functions. to generate logic functions.

They are programmedfor They are programmed for

a specific function by the specific function by the user.
manufacture of the device.

5. It is more suitable in It is more suitable in high gate

small gate count designs. count designs since it has ver
high logic capacity.
6. Lesscomplex architecture. More complex architecture.

7. Delays are more Delays are quite urnpredictable.

predictable.
8. CPLD contains a few FPGA contains upto 100 000 of
blocks of logic that tiny logic blocks.
reaches up to a few
thousands.

DECODD A Guide for Engineering Students

 rtalCircwits
19-2
Semicomdactor Memaries
Unit VI Q.1.1 shows
T h e Fig.

the
block diagran of
nit. Then data
ra ines
emory unit

10 Semiconductor Memorie hunes

nformation

memory
provide
o be stored
and the k
the
k-address
ines

Read
Memory
in
address
lines specify the
Write
2word
n-bit per word
particular word chosen
10.1: Memory Organization and Operation pa

the many Fig. Q.1.1 Block

semiconductor memory.
diagram of
memory unit
Q.1 Explain the structure of a
among

The two
a v a i l a b l e .

Ans.: Semiconductor memnories are made up of registers direction transfer.

Each control inputs specify the
register in the memory is one storage
location also called me When there are k address lines we can access 2 memory words
location. Each memory location is identified by an address For example, fk =10 we can access 2 = 1024 memory words
The number of storage locations can
vary from a few in son Q.2 A certain memory has a capacity of 4 Kx 8. How many
memories to hundreds of thousand in others. Each me data
and data output lines does it have? How many address lines
location can
accommodate one or more bits. it have ?
What is its capacity in bytes?
doe

Generally, the total number of bits that a memory can store is Ans.:Since memory is specified as 4KxS it has $ data input
its
capacity. Most of the types the capacity is specified in terms and data output lines.
of
bytes (group of eight bits). locations. Since 4096 4K t has
Memory has 4K memory
=

Each 12 address lines.

register consists of storage elements (flip-flops
capacitors), each of which stores one bit of data.
A storage The memory capacity is 4 Kbytes.
element is called a cell.
lines and input-output data lines
Q.3 How many. address
are

A unit ?
memory unit stores
binary information in groups of bits called needed in 64 Kx8 memory
words. A word in memory is an Ans. 20 16 K 16 address are needed and S input-output
out of
entity of bits that moves in and
storage as a unit. A word having group of 8-bits is called data lines are needed.
a byte.

Most 10.2 Classification and Characteristics of Memories

computer memories use words that are
bits in length. Thus, a 16-bit word contains wo
multiples of eight of operation,
bytes and a 32-bit memories on the basic of principle
word is made of Q.4 Classify access and
fabrication technology.
4-bytes. physical characteristics, mode of
SPPU: Dec.-04, Marks
.The communication between a
memory and its environment is of memory.
achieved through data lines, address Ans. Fig. Q4.1 shows the
classification

selection lines, and control

lines that specify the direction of (Refer Fig. Q4.1 on next page.)
transfer.
Srudens
(10 1) A Guidefor Engineering
QECODE
 Digital Cireuits 10-3
Semiconductor Memories DigitaC
l ircuits
10-4
Semiconductor Memories
CS
Classification of Memory| ories in which the stored data
erasable
can be erased and
new data can
be stored.

Based on ,The semiconductor memories are also ssified

principle of operation
MOSs memories depending upon
upo
Bipolar
the type of transistors usedandto
as

Read only memory (ROM)

Read/write memory (RAM) t h e individ
cell.
c o n s t r u c t

between volatile
a.5 Distinguish be and non-volatile
memories.
Masked PROM EPROM EEPROMM Static SPPU: May-12, 13, Dec-04, Marks 2
ROM RAM
Dynami
RAM
c nouish between volatile and
Based on physical non-volatile memories
characteristics Ans.

Erasable Non erasable Volatile

Nonvolatile Volatile memory Non-volatile memory
Sr.
Based on No.
mode of access Volatile memory requires Non-volatile memory can hold the
Sequential Random
1. constant power to stored information even when there is
maintain the stored no power supply to the
memory or

Based on information.
storage device.
terminology
used for Volatile memory is Non-volatile memory is typically used
fabricatlon 2. for for the task of secondary storageor
Bipolar MOS typically
used only
primary storage. long-term persistent storage
Fig. Q.4.1
Type of volatile Examples of non-volatile memory
Broadly semiconductor memories are classified as
volatile
3.
memories are include Read-Only Memory, flash
memories and non-volatile memories. Volatile memories memory, most types of magnetic
can i) Random Access
retain their state as long as power is
applied. On the other hand computer storage devices (e.g. hard
Memory (RAM) disks, floppy disk drives and magnetic
non-volatile memories can hold data even if
power is turned off. tape), optical disc drives, and early
Read/Write Memories (RWMs) are those memories, which allows i) Static RAM (SRAM)
i ) Dynamic RAM computer storage methods such as
both read and write operations. They are used in type and punch cards.
where data has to change continuously.
applications (DRAM) paper
are also used They for
iv) Fast Page Mode
temporary storage of data. ROM memories allow only read
DRAM (FPM DRAM)
operation. They are used to store monitor
programs and
constants used in the program. v)Extended Data Output
RAM (EDO RAM)
.The volatile memories which can hold data as vi) Synchronous DRAM
long as power is
ON are called Static RAMs (SRAMs). (SDRAM)
Dymamic RAMs (DRAMs)
stores the data as a charge the vii) Double Data Rate
on
capacitor and they need
refreshing of charge on the capacitor after every few milliseconds (DDR) SDRAM

to hold the data even if

power is ON. EPROM and EEPROM are

OECODE Engineering Stud-

A Guide for Engineering Students A Guide for
QECODE
 Digitel Crewits 10 -5 10-6

10.3
Semiconductor Memorie D i g l t a lC i r c u i t s

Sense line
Semiconductor Memories
RAM, ROM, EPROM, EEPROM, NVRAM, SRAM Q.6.2 shows the
Q.6 Draw circuits of
SRAM, DRAM dynamic
Fi& RAM cell. A
one cell of static and dynamic RA. dynamic RAM contains
explain its working. [SPPU: Dec.-12, 15, May-13, M such
Ans. There
Mart.nd
Aar thousands
of Storage
are two types of RAMs memory cells. capacitor
Static RAM
Dynamic RAM LUMN (Sense)
Static RAM COL
When

lines ine
ROW (Control)
Memories that consists of circuits capable of and MOSFET
as
long retaining their high,
the Fig. Q.6.2 Dynamic RAM
power is applied are known as static
as
memoriess. state
go
and charges the
are Random onducts
combinely These
Access Memory (RAM) and hence
static RAM memories. cal.
alled
capacitor.

When the COLU LUMN and ROW lines go low, the MOSFET opens
Fig. Q6.1 shows the one-bit memory cell for
static RAM. retains its charge. In this way, it stores 1 bit.
the capacitor
storage part of the cell is modeled by an SR latch with The and

gates to form a D latch. associa lated

Ceonly a single MOSFET and capacitor are needed, the
RAM contains more memory cells as compared to static
dnamic
Select
RAM per unit
area.
Select
dynamic of RAM is that it needs refreshing of
The disadvantage
inpul -Output input charge on the capacitor
after every few milliseconds. This
Output the
complicates the system design, since it requires extra

hardware to control refreshing of dynamic RAMs.

Read/ Write
Read/Write RAMs and dynamic RAMs.
a.7 Compare static
(a) Logic diagram [SPPu May-05, 0, 14, Dec.-06, 10, 19, Marks 4]
(b) Block diagram

Fig. Q.6.1 One-bit binary cel Ans.

.The binary cell is capable of storing one bit in its internal latch. Sr. No. Static RAM Dynamic RAM
The select input enables the cell for reading and
read/write input determines the operation of thewriting, and the 1. Static RAM contains less Dynamic RAM contains more

compared to
cell when it is memory cells per unit area. memory cells as

selected. static RAM per unit area.

.When Read/Write input is logic 1, read operation 2. It has less access time hence Its access time is greater than
is performed;
otherwise, write operation is performed. faster memories.
static RAMs.

stores the data

Dynamic RAM 3. Static RAM consists of number Dynamic RAM
as a charge on the capacitor. It
of flip-flops. Each ílip-flop the
Dynamic RAM stores the data as a
charge on the capacitor. stores one bit.
consists of MOSFET and

capacitor for each cell.

Students
PEcODE A Gulde for Engineering Students A Guide for Engineering
pecoDD
 10
10 7 Semicmductun Memaries
Digitat Cireits Semiconduetu Dgtal
Creuito

Refreahing circuitry is not

Refrenhing the is Tequ
to maintain clreuitry
Bit lins

required eharge onquired

capacitors after every the
miloeconds. few
Extra hardware Word ine
required to control
Thls makes system refreshir
design
complicated,
Open:Data stred (o 1)
5. Cost is more. Cost is less.

Q.8 What ie ROM ? Llst the types of ROM.

(SPPU: June-22, Marks gi Fig. a.8.1 ROM cell

Ans. We can't write data in read only memories a short note on PROM. SPPU une-22, Marks 8)
Write
It a.9
non-volatile memory i.e. it can hold data even if power i .PROMs are programmed by user. To provide the
off. Generally, ROM is used to store the binary codes
for Ans.:

facility, each address select and data line intersection

sequence of instructions you want the computer to carry out the
programming

and its o w n
fused OSFET or transistor. When the fuse is intact,
data such ás look up tables. This is because this
tyD of has
cell is configured as a logic 1 and when fuse is blown
information does not change. thememory the cell is logical 0. Logical 0s are
memory
I t is en circuit),
important to note that although we give the name RAM. by selecting the appropriate select line and then
static and dynamic read/write memory devices, that to p r o g r a m m e d

does not VpD

mean that the ROMs that we are using are also not
random
access devices. In fact, most ROMs are accessed
randomly with Address
select line
unique addresses.
The Fig. Q,8.1 shows the typical configuration of a ROM cell. It
consists of a transistor T and switch P. The transistor T is
driven MOSFET
by the word line. The contents of cell can be read from the cell switch
-Data line
when word line is logic 1. A logic value 0 is read if the transistor
is connected to ground through switch P. If switch P is open, a
logic value 1 is read. The bit line is connected through a resistor
to the power supply. A sense circuit at the end of the bit line
generates the proper output value. Data is stored into a ROM Output
Fuse
when it is manufactured. (Refer
Fig.
Q.8.1 on next page) - bit

There are four

types of ROM : Masked ROM, PROM, EPROM
and EEPROM or E°PROM.
PROM cell
Fig. Q.9.1 Single fused
Students
Engineering
A Guide for
QECOD
OECODE A Guide for Engineering Students
 Digital Circuits 10-9 10-10
Semiconductor Memories
driving the vertical data line with
Semiconductor Memo.ories DigtalCircuits

locations.Although
lthough ornly Os will be programmed, both 1s and Os
Fig. Q.9.1
a
pulse of high cur
shows a PROM fused MOSFET
memory cell. rrent. The C a nb epresented
in the data.

Q.10 Explain address and data

in brief
EPROM.
puring p r o g r a m m i n g a d d r e s
are
applied to address and
SPPU May-08,:
Marks 6, of the ROM. When the address and data are stable,
June-22, Mari ta pi e is applied to the program input of the EPROM. The
OR Write a short note EPROM. arks
SPPU:
d a t a

on
May-12, 13, Marks program duration is around 50 ms and its
amplitude
OR What is meant by EPROM ?
4141 ram
pulse
IC. It is typically 11.5 V to 25 V. In EPROM, it
State
disadvantages. its
advantages
prOB

ds
depends
on
EPROM

SPPU: May-15, Marksand to program any location at any time either

Ans. Erasable
programmable ROMs use MOS
61 is
possible
sequentialy, or
at random.
store 1s and Os circuitry, dividually,
T
as a
packet of
They
i n d i v

chip. EPROMs can be charge

layer in a buried of tho
Advantages o f EPROM

EPROM programmed by the user with a IC 1, Non-volatile memory.

programmer. The important point is that we special

the stored data in and pro8rammable memory.
the EPROMs can 2Erasable
erase
light through its quartz window byforexposing the chip to
ultraviolet possible to program any location at any time - either
the Fig. Q.10.1. 15 to 20
minutes, as shown in 3Itis or at random.
individually, sequentially,
Disadvantages of EPROM
Quartz window Colective erasing is not possible. When erased the entire
Ultraviolet light
information is lost.

to erase the EPROM.

Needs ultraviolet light
source
2.

3. Requires 15 to 20 minutes for erase operation.

and ROM. [SPPU: June-22, Marks 4
a.11 Compare RAM

Ans.

Fig. Q.10.1 EPROM RAM ROM

Parameter
It is not
possible to erase
selective information, when erased It is a read/ write memory. | It is a read only memory.
entire information is lost. The the Definition
is
chip can be reprogrammed. This
memory ideally suitable for product It is a volatile memory, its It is a non-volatile memory
projects, and development, experimental Volatility retained
college laboratories, since this chip can be reused
contents are lost when the its contents are
after the power is switched
ever

many times, over. power is turned off.

off.
EPROM Programming
include
When erased each cell in the Types The two main types of RAM| The types of ROM
EPROM contains Data is 1. static RAM and dynamic| PROM, EPROM and
introduced by selectively programming Os into the desired bit
are

RAM EEPROM.

DECODD A Guide for OECODE) A Guide for Engineering

Stu=
Engineering Student