System Verilog

INTRODUCTION, DATA
TYPES
 What is SV?

 System Verilog is a hardware description and

Verification language (HDVL).

 The bulk of the verification functionality is based on the

OpenVera language.

 System Verilog (IEEE Standard 1800-2005) is an

extensive set of enhancements to IEEE 1364 Verilog-
2001 standards.

 It inherits features from Verilog, VHDL, C and C++.

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 Features of SV

Constrained
Randomization

OOPS Improved
Data Types

System Verilog

Functional
Synchronization
Coverage
Assertions

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 Regions in SV

Preponed Continuous, Blocking and RHS of

Active
Non Blocking Assignment. $display,
Sample Data $write.
before entering Inactive Execute statements with #0 delay
current time
slot (#1step) NBA Non Blocking Assignments

From Current Time Observed Assertions are evaluated

Slot

To Next Time Pass/ Fail code of concurrent

Re-Active assertions
Slot
Blocking Statement in Program
$strobe,
$monitor, PLI Re-Inactive #0 StatementsBlock
in Program Block
Calls
Postponed Re-NBA NBA inside Program Block

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 Data Type

 System Verilog offers following Data Types:

o 4-State Type o Structures

o 2-State Type o Unions
o Real o Strings
o Arrays o Enumerated Type
o User Define o Class

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 4-State Type

 Allowed values are 0, 1, X and Z.

 Following 4-State types are included from Verilog:

o wire //Size: 1-bit Value: Z
o reg //Size: 1-bit Value: X
o integer // Size: 32-bit Value: X
o time // Size: 64-bit Value: X

 User can define size for wire and reg.

 integer is signed, all others are unsigned.

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 4-State Type

 Addition to System Verilog

o logic //Size: 1-bit Value: X

 User can define size for logic.

 Logic is improved reg data type.

 Logic can be driven by continuous as well as

procedural assignments.

 Logic has a limitation that it cannot be driven by

multiple drivers in such case use wire.
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 Logic

Example4:

module example4 ( input logic a, b, ctrl,

output logic c);
assign c= ctrl?a:1’bZ; //driving logic using continuous
assignment

assign c= !ctrl?b:1’bZ; //driving logic using continuous

assignment
endmodule

Compilation error, use wire to achieve this functionality.

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 2-State Type

 Allowed values are 0 and 1.

 System Verilog offers following 2-State Data Types :

o shortint //Size: 16-bit Value: 0
o int //Size: 32-bit Value: 0
o longint //Size: 64-bit Value: 0
o byte //Size: 8-bit Value: 0
o bit //Size: 1-bit Value: 0

 User can define size for bit.

 All are signed except bit which is unsigned.

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 Example1

module example1;
int a;
int unsigned b; //unsigned integer
bit signed [7:0] c; //same as byte
initial
begin
a=-32’d127;
b=‘1; //SV offers un-sized literal to fill all
c=‘0; // locations with given number
end
endmodule
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 Example2

module example2;
int a;
logic [31:0] b=‘Z; //b=32’hzzzz_zzzz
initial
begin
a=b; //a=32’h0000_0000
b=32’h123x_5678;
if($isunknown(b)) $display(“b is unknown”);
else $display(“b is known”);
end
endmodule
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 Real Type

 Included from Verilog

o real //Default Value : 0

 real is same as double in C.

 Addition to System Verilog

o shortreal //Default Value : 0
o realtime //Default Value : 0

 shortreal is same as float in C.

 realtime and real can be used interchangeably.

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 Void

 void data type represents non existing data.

 It can be used as return type of functions to indicate

nothing is returned.

Example: Usage:

function void display; void=display;

$display(“Hello”);
endfunction

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 Arrays

 Arrays are used to group elements of same type.

 Arrays can be categorized as following:

o Fixed Array
o Dynamic Array
o Packed Array
o Unpacked Array
o Queues
o Associative Array

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 Fixed Array

 Array whose size is fixed during compilation time is

called as Fixed Array.

 Size of fixed array cannot be modified during run time.

Examples
int array1 [15]; //array of int containing 15
elements
//Equivalent to int array1 [0:14]
int array2 [0:14];
logic array3 [7:0]; //array of logic containing 8
elements
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 Unpacked Array

 Unpacked Arrays can be declared by adding size after

array name.

 Unpacked Arrays can be made of any data type.

Example:
int array1 [16] [8]; //16 rows , 8 columns
bit array2 [3:0] [7:0]; //4 rows , 8 columns
bit [7:0] array3 [4]; //4 rows each containing 8 bits

 System Verilog stores each element of an unpacked

array in a longword (32-bit).

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 Unpacked Array

bit [7:0] array1 [4];

Unused
array1 [0] 7 6 5 4 3 2 1 0
Memory
array1 [1] Unused 7 6 5 4 3 2 1 0
Memory
array1 [2] Unused 7 6 5 4 3 2 1 0
Memory
array1 [3] Unused 7 6 5 4 3 2 1 0
Memory

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 Unpacked Array

Initializing Array:
int array1 [2] [4] = ‘{ ‘{ 1, 2, 3, 4 } , ‘{ 5, 6, 7, 8 } };

int array3 [0:5] = ‘{1:5, 3:1, default: 0};

// same as ‘{0, 5, 0, 1, 0, 0}

int array4 [0:2] [1:4] = ‘{3 { ‘{ 2 {1, 2} } } };

// same as ‘{ ‘{1, 2, 1, 2} , ‘{1, 2, 1, 2} , ‘{1, 2, 1, 2} }

int array5 [2] [2] [2] = ‘{ ‘{ ‘{4, 5}, ‘{3, 1} }, ‘{ ‘{1, 7}, ‘{2, 5} }
};

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 Unpacked Array

Accessing Array
int array1 [2] [4];
int array2 [0:5];
byte array3 [0:2] [1:4];
int a, b;
byte c;

a= array1[1] [3];
b= array2[4];
c= array3[1] [2];

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 Basic Array Operation

 Arrays can be manipulated using for and foreach loop

bit [7:0] array1[10], array2[10] ;

initial
begin
for ( int i=0; i <$size(array1); i++) //$size returns size of
array
array1[ i ]= 0;
foreach(array2[ k ]) //k is defined implicitly
array2[ k ]=$random;
end
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 Basic Array Operation

Example:
bit [7:0] array1[10] [20];

initial
begin
array1=‘{10 { ‘{0:2, 1 : 0 , default:$random} } };

foreach(array1[i ,k])
$display(“array1[%0d] [%0d]=%0d”, i, k, array1[i] [k]);
end

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 Packed Array

 Packed Arrays can be declared by adding size before

array name.

 One dimensional packed arrays are also referred as

vectors.

 Packed array is a mechanism of subdividing a vector

into subfields which can be accessed as array elements.

 Packed array represents contiguous set of bits.

 Packed array can be made of single bit data (logic, bit,

reg), enumerated type or other packed arrays.
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 Packed Array

bit [3:0] [7:0] array1;

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

array1[3 array1[3:2] array1[1 array1[0][4]

] ]
array1 a=array1[3];
bit [7:0] a, b;
b=array1[1];
bit [15:0] c;
c=array1[3:2];
bit d;
d=array1[0][4];
bit [31:0] e;
e=array1;
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 Packed Array

Mixture of Packed and Unpacked Array

bit [3:0] [7:0] b [4];

b[0] 76543210765432107654321076543210
b[0] [2] b[0] [1] [4:0]
b[1] 76543210765432107654321076543210
b[1]
b[2] 76543210765432107654321076543210
b[2] [2] [2]
b[3] 76543210765432107654321076543210

b[3] [0]
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 Packed vs. Unpacked Array

 Packed arrays are handy if user wants to access array

with different combination.

 If user want to wait for change in array(i.e. @), in that

case packed array will be preferred over unpacked
array.

 Only fixed size arrays can be packed. Therefore it is not

possible to pack following arrays:
o Dynamic Arrays
o Queues
o Associative Arrays

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 Dynamic Array

 Dynamic arrays are unpacked arrays whose size can be set

and changed during simulation time.

 new constructor is used to set or change size of Dynamic

Array.

 size() method returns current size of array.

 delete() method is used to delete all elements of the array.

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 Dynamic Array

module top;
int dyn1 [ ]; //Defining Dynamic Array (empty subscript)
int dyn2 [4] [ ];

initial
begin
dyn1=new[10]; //Allocate 10 elements
foreach (dyn1[ i ]) dyn1[ i ]=$random; // Initializing Array
dyn1=new[20] (dyn1); // Resizing array and
// Copying older values
dyn1=new[50]; // Resizing to 50 elements Old Values are lost
dyn1.delete; // Delete all elements
end
endmodule

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 Dynamic Array

int dyn1 [ ]= ‘{5, 6, 7, 8} ; //Alternative way to define size

initial
begin
repeat (2)
if (dyn1.size != 0)
begin
foreach(dyn1 [ i ] ) $display(“dyn1[%0d]=%0d”, i, dyn[ i ] );
dyn1.delete;
end
else
$display(“Array is empty”);
end

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 Queue

 A Queue is a variable size, ordered collection of

homogenous elements.

 Queues support constant time access to all its

elements.

 User can Add and Remove elements from anywhere in

a queue.

 Queue is analogous to 1-D array that grows and shrinks

automatically.

 0 represents 1st element and $ represents last element.

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 Queue Methods

int A [$] = ‘{ 0, 1, 2, 3, 4, 5, 6 }; A 0 1 2 3 4 5 6
int x, y, z;

 size() method returns number of elements in a queue.

x=A.size(); x 7
 insert(index, item) method is used to insert item at a
given index.
A.insert(3, 7); A 0 1 2 7 3 4 5 6
 delete(index) method is used to delete a queue if index
is not specified else it is used to delete item at given
index.
A 0 1 2 7 3 5 6
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 Queue Methods

 pop_front() method removes and returns 1st element of the

queue.
y=A.pop_front();
y 0 A 1 2 7 3 5 6
 pop_back() method removes and returns last element of the
queue.
z=A.pop_back(); z 6 A 1 2 7 3 5

 push_front(item) method inserts item at the front of the

queue.
A 9 1 2 7 3 5
A.push_front(9);
 push_back(item) method inserts item at the back of the
queue.
A 9 1 2 7 3 5 8
A.push_back(8);
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 Associative Array

 In case size of data is not known or data space is

sparse, Associative array is a better option.

 System Verilog allocates memory for an associative

element when they are assigned.

 Index of associative can be of any type.

 If index is specified as * , then the array can be indexed

by any integral expression of arbitrary size.

 real and shortreal are illegal index type.

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 Associative Array

int array1 [ * ];
int array2 [ int ];
//Array can be indexed by any integral expression.

int array3 [ string ];

//Indices can be strings or string literals of any length.

class xyz; …
int array4 [ xyz ];
//Indices can be objects of xyz.
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 Associative Array

int xyz [ * ];

5 7 2 1 3 9
0 1 2 3 7 10
xyz[0]=5; //Memory allocated during assignment
xyz[1]=7;
xyz[2]=2;
xyz[3]=1;
xyz[7]=3;
xyz[10]=9;

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 Associative Array Methods

 num() and size() method returns number of elements in associative

array.

 delete(index) deletes element at given index if index is specified

else deletes entire array.

 exists(index) checks whether an element exists at the specified

index.

 first(index) method assigns to the given index variable the value of

the first (smallest) index. It returns 0 if the array is empty; otherwise,
it returns 1.

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 Associative Array Methods

 last(index) method assigns to the given index variable the value of

the last (largest) index in the associative array. It returns 0 if the
array is empty; otherwise, it returns 1.

 next(index) method finds the smallest index whose value is greater

than the given index argument. Returns 1 if new index is different
as old index else 0.

 prev(index) function finds the largest index whose value is smaller

than the given index argument. Returns 1 if new index is different
as old index else 0.

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 Associative Array Methods

int a [string]= ‘{“Jan”: 1, “Feb”: 2, “Mar”: 3, “April”: 4, “May”:

5};
string index;

initial
begin
a.first(index); //index=Jan //\\
$display(a[index]);
while(a.next(index)) //Go through all index
$display(a[index]);
end
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 User Defined

 System Verilog allows user to define new data types

using typedef keyword.

typedef byte unsigned uint8; //Defining uint8

typedef bit [15:0] word; //Defining word

uint8 a, b;
word c, d;

a=8’d10;
c=16’d25;
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 Structures

 Structure and Unions are used to group non-

homogenous data types.

Declaration :

struct { bit [7:0] opcode; struct {bit [7:0] r, g, b;} pixel;

bit [15:0] addr; } IR;

struct {int a, b; real b;} mix;

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 Structures

Initializing : Accessing :

IR=‘{opcode : 7’d8, addr : 15’d1}; int x;

pixel=‘{ 128, 255, 100}; bit [7:0] y;
pixel=‘{ r :128, g : 255, b :100}; pixel.r=200;
pixel=‘{ int :0}; mix.a=3;
mix=‘{ 3, 5, 5.6}; mix.c=4.5;
mix=‘{ int : 1, real : 1.0}; x=mix.b;
mix=‘{ default : 0}; y=pixel.g;

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 Unions

 Union represents a single piece of storage element that

can be accessed by any of its member.

 Only one data types in union can be used at a time.

Example :

union
{ real a;
int b;
bit [7:0] c; } exam1;

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 Unions

Example :
typedef union
{ shortint a;
00 00 00 00
int b;
bit [7:0] c; } my_un;
my_un un1; 00 00 F0 F0
un1.a=16’hf0f0;
$displayh(un1.b);
00 00 F0 AA
un1.c=8’b1010_1010;
$displayh(un1.b);
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 Structures vs Unions

Structure Union

Memory is allocated to each Common memory is allocated

and every element. for all the members.

Size of structure is sum of size Size of union is equal to size of

of each member or more. largest member

Modifying value of one member Modifying value of one member

has no effect on other members modifies value of all members

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 String

 System Verilog string type is used to store variable

length strings.

 Each character of string is of type byte.

 There is no null character at the end of string.

 String uses dynamic memory allocation, so size of string

is no longer a concern.
Example :
string s=“hello”;

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 String Operators

 str1 == str2 checks whether strings are equal or not.

 str1 != str2 checks for inequality of strings.

 Comparison using lexicographical ordering of strings.

o str1 < str2
o str1 <= str2
o str1 > str2
o str1 >= str2

 {str1, str2, str3, .. , strn} concatenation of strings.

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 Enumerated Type

 An enumeration creates a strong variable type that is

limited to a set of specified names.
Example :
enum { RED, GREEN, BLUE } color;
typedef enum { FETCH, DECODE, EXECUTE } operation_e;
 enum are stored as int unless specified.
typedef enum bit [2:0] { RED, GREEN, BLUE } color_e;
 First member in enum gets value 0, second value 1 and
so on.
 User can give different values to member if required.

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 Enumerated Type

Example :
enum { RED, GREEN, BLUE } color;
//RED=0, GREEN=1, BLUE=2

enum { GOLD, SILVER=3, BRONZE} medals;

//GOLD=0, SILVER=3, BRONZE=4

enum {A=1, B=3, C, D=4} alphabet;

//Compilation error C and D have same value

enum logic [1:0] {A=0; B=‘Z, C=1, D} exam;

//A=00, B=ZZ, C=01, D=10 Default value of exam is X

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 const

 const keyword is used to define constants in System

Verilog.

 localparam constants are set during elaboration time.

 const constants are set during simulation time.

Example:
const byte colon= “:”;
const real pi=3.14;

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 Casting

 Casting is used convert data from one type to other.

 There are two ways to perform casting :

o Static Casting: destination = return_type’ (source). This
type of casting always succeeds at run time and does not
give any error.
o Dynamic Casting: using $cast system task or function.

Example :
int a;
initial a=int’(3.0 * 2.0);

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 Casting

 System Verilog provides the $cast system task to assign

values to variables that might not ordinarily be valid
because of differing data type.

 $cast can be called as either a task or a function.

$cast used as a function
if ($cast(destination, source)) //destination and
source
// should be singular
$cast used as a task
$cast(destination, source);
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 Casting

int a;
real b=3.0;

if($cast(a, b)) //Returns 1 if casting succeeds else 0

$display(“casting success”);

$cast(a, b); //If casting fails run time error occurs

In both cases if casting fails then destination value

remains unchanged.

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 Casting

Example :
int a=-10;

initial
begin
$display(a>>>1); // -5
$display(unsigned’(a)>>>1); // positive value
const’(a); // changing to constant
a=3; //Runtime error
end

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