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Circuit Descriptions: EN 34 QM16.4E LA 7

This document contains circuit descriptions for various components in a front-end system, including: - A tuner and scaler for analog and digital TV reception - Additional components like a demodulator for DVB-T2 and ISDB-T reception - HDMI input configuration with 4 HDMI ports - An overview of the main audio and video processor, the MT5593FPIJ, which handles tasks like decoding, display processing, and audio coding.

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100% found this document useful (1 vote)
204 views3 pages

Circuit Descriptions: EN 34 QM16.4E LA 7

This document contains circuit descriptions for various components in a front-end system, including: - A tuner and scaler for analog and digital TV reception - Additional components like a demodulator for DVB-T2 and ISDB-T reception - HDMI input configuration with 4 HDMI ports - An overview of the main audio and video processor, the MT5593FPIJ, which handles tasks like decoding, display processing, and audio coding.

Uploaded by

avrelec
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EN 34 7. QM16.

4E LA Circuit Descriptions

U102 Pin1,CI_VCC

20050_208.eps

Figure 7-5 Power SSB Bottom View

7.4 Front-End Analogue and DVB-T/T2, DVB-C;


DVB S/S2, ISDB-T reception TDSY-G480D

7.4.1 Front-End Analogue and DVB T/C reception I2C


I2C

The Front-End for analogue tuner consist of the following key IF


components:
IF_AGC
IF_AGC
• TUNER EUROPE TDSY-G480D
• SCALER MT5593FPIJ HSBGA-900 Processor RF_AGC

MT5593
Below find a block diagram of the front-end application for
analogue part.
20050_203.eps

Figure 7-6 Front-End Analogue block diagram

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Circuit Descriptions QM16.4E LA 7. EN 35

7.4.2 DTV T2 reception 7.5 HDMI


Refer to figure 7-9 HDMI input configuration for the application.
The Front-End for DVT part consist of the following key
components:

• TUNER EUROPE TDSY-G480D I2C


RX
• SCALER MT5593FPIJ HSBGA-900 Processor TX
• DEMODULATOR Si2168-C50-GMR QFN-48 MT5593
TX RX
I2C
Below find a block diagram of the front-end application for DTV
part. TX

I2C RX I2C CN501


CN505 RX
TDSY-G408D HDMI4
I2C HDMI1
I2C
CN504 CN502
IF HDMI2 HDMI3
DECODER
IF-AGC Si2168 20050_206.eps
IF_AGC
TS DATA
RF_AGC Figure 7-9 HDMI input configuration
I 2C
MT5593
The following HDMI connector can be used:
• HDMI 1: HDMI input ( TV digital interface support
HDMI1.4/HDCP1.3) with digital audio/PC DVI input/ARC
20050_204.eps
• HDMI 2: HDMI input ( TV digital interface support HDCP)
with digital audio/PC DVI input/ARC
Figure 7-7 Front-End DVB-T2 DTV block diagram • HDMI 3: HDMI input ( TV digital interface support
HDMI1.4/HDCP1.3) with digital audio/PC DVI input/ARC
7.4.3 Front-End DTV-S2 reception • HDMI 4: HDMI input ( TV digital interface support
HDMI1.4/HDCP1.3) with digital audio/PC DVI input/ARC
The Front-End for ISTB part consist of the following key • +5V detection mechanism
components: • Stable clock detection mechanism
• HPD control
• CEC control
• TUNER EUROPE TDQS-A701F
• SCALER MT5593FPIJ HSBGA-900 Processor
• DEMODULATOR Si2166-C50-GMR QFN48
7.6 Video and Audio Processing - MT5593FPIJ
The MT5593FPIJ is the main audio and video processor (or
System-on-Chip) for this platform. It has the following features:
Below find a block diagram of the front-end application for DTV
part.
• ATSC /DVB-T /DVB-C/DTMB demodulators
• Ture 120HZ Full HD MJC
• Power CPU core
• 3D graphic support OpenGL ES 1.1/2.0
S2 function
• A muti-standard video decoder
• A transport de-multiplexer
System I2C • One HDMI 2.0 receiver with 3D support
S2 tuner LNB power
• MHL2.0& Standby charging
• 2D/3D converter
MT5593
Tuner I2C
• Rich format audio codec
S2 Demond • Local dimming (LED backlight)
SI2169
IP/IN/OP/ON • Ethernet MAC+PHY
Tuner I2C • TCON
TS DATA • Panel overdrive control
• Four-link LVDS, mini-LVDS,V-by-one, EPI
20050_205.eps
The MT5593FPIJ family consists of a DTV front-end
demodulator, a backend decoder and a TV controller and offers
Figure 7-8 Front-End DVB-S2 DTV block diagram high integration for advanced applications. It integrates a
transport de-multiplexer, a high definition video decoder, an
audio decoder, a four-link LVDS transmitter, a mini-LVDS
transmitter, a V-by-one transmitter, an EPI transmitter, and an
NTSC/PAL/SECAM TV decoder with 3D comb
filter(NTSC/PAL).
The MT5593FPIJ enables consumer electronics
manufacturers to build high quality, low cost and feature-rich
DTV.
The MT5593PFIJ family supports Full-HD
MPEG1/2/4/H.264/VC1/RM/AVS/ and H.264/HEVC video
decoder standards, and JPEG. The MT5593FPIJ also supports
Media Tek MDDi de-interlace solution which can reach very
smooth picture quality for motions. A 3D comb filter added to
the TV decoder recovers great details for still pictures. The
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EN 36 7. QM16.4E LA Circuit Descriptions

special color processing technology provides a natural, deep


colors and true studio quality video. Moreover, the MT5593
family has built-in high resolution and high-quality audio codec.
The MT5593FPIJ family provides consumers with and Full-HD
120Hz experience. It integrates high-quality Full-HD ME/MC
technology.
The MT5593FPIJ family supports ASTC,DVB-T and
DVB-C,DTMB demodulation functions. It reserves transport
stream inputs for external demodulators for other countries or
areas.TV maker can easily port the same UI to worldwide TV
models. First-class adjacent and co-channel rejection
capability grants excellent reception. Professional
error-concealment provides stable, smooth and mosaic-free
video quality

For a functional diagram of the MT5593FPIJ, refer


to Figure 8-1.

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