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SN65LVDS93A
SLLS992B – AUGUST 2009 – REVISED MARCH 2015

SN65LVDS93A FlatLink™ Transmitter

1 Features 2 Applications
•
1 Industrial Temperature Range –40°C to 85°C • LCD Display Panel Drivers
• LVDS Display Serdes Interfaces Directly to LCD • UMPC and Netbook PCs
Display Panels With Integrated LVDS • Digital Picture Frames
• Package Options: 4.5-mm × 7-mm BGA, and 8.1-
mm × 14-mm TSSOP 3 Description
• 1.8 V up to 3.3-V Tolerant Data Inputs to Connect The SN65LVDS93A LVDS SerDes
Directly to Low-Power, Low-Voltage Application (serializer/deserializer) transmitter contains four 7-bit
and Graphic Processors parallel load serial-out shift registers, a 7 × clock
synthesizer, and five low-voltage differential signaling
• Transfer Rate up to 135 Mpps (Mega Pixels Per (LVDS) drivers in a single integrated circuit. These
Second); Pixel Clock Frequency Range 10 MHz to functions allow synchronous transmission of 28 bits of
135 MHz single-ended LVTTL data over five balanced-pair
• Suited for Display Resolutions Ranging From conductors for receipt by a compatible receiver, such
HVGA up to HD With Low EMI as the SN65LVDS94 (SLLS928).
• Operates From a Single 3.3-V Supply and 170 When transmitting, data bits D0 through D27 are
mW (Typical) at 75 MHz each loaded into registers upon the edge of the input
• 28 Data Channels Plus Clock In Low-Voltage TTL clock signal (CLKIN). The rising or falling edge of the
to 4 Data Channels Plus Clock Out Low-Voltage clock can be selected through the clock select
(CLKSEL) pin. The frequency of CLKIN is multiplied
Differential
seven times and then used to serially unload the data
• Consumes Less Than 1 mW When Disabled registers in 7-bit slices. The four serial streams and a
• Selectable Rising or Falling Clock Edge Triggered phase-locked clock (CLKOUT) are then output to
Inputs LVDS output drivers. The frequency of CLKOUT is
• ESD: 5-kV HBM the same as the input clock, CLKIN.
• Supports Spread Spectrum Clocking (SSC) Device Information(1)
• Compatible With all OMAP™2x, OMAP3x, and PART NUMBER PACKAGE BODY SIZE (NOM)
DaVinci™ Application Processors TSSOP (56) 14.00 mm × 6.10 mm
SN65LVDS93A BGA MICROSTAR
7.00 mm × 4.50 mm
JUNIOR (56)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

RGB Video System Using Discrete LVDS TX

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 9.1 Overview ................................................................. 16
2 Applications ........................................................... 1 9.2 Functional Block Diagram ....................................... 16
3 Description ............................................................. 1 9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 18
4 Revision History..................................................... 2
5 Description (continued)......................................... 3 10 Application and Implementation........................ 19
10.1 Application Information.......................................... 19
6 Pin Configuration and Functions ......................... 3
10.2 Typical Application ................................................ 20
7 Specifications......................................................... 6
11 Power Supply Recommendations ..................... 27
7.1 Absolute Maximum Ratings ..................................... 6
7.2 ESD Ratings.............................................................. 6 12 Layout................................................................... 27
12.1 Layout Guidelines ................................................. 27
7.3 Recommended Operating Conditions....................... 7
12.2 Layout Example .................................................... 29
7.4 Thermal Information .................................................. 7
7.5 Electrical Characteristics........................................... 7 13 Device and Documentation Support ................. 31
7.6 Timing Requirements ................................................ 8 13.1 Documentation Support ........................................ 31
7.7 Switching Characteristics .......................................... 9 13.2 Trademarks ........................................................... 31
7.8 Typical Characteristics ............................................ 11 13.3 Electrostatic Discharge Caution ............................ 31
13.4 Glossary ................................................................ 31
8 Parameter Measurement Information ................ 12
9 Detailed Description ............................................ 16 14 Mechanical, Packaging, and Orderable
Information ........................................................... 31

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (August 2011) to Revision B Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Original (August 2009) to Revision A Page

• Deleted all maximum values from ICC - Supply current (average).......................................................................................... 8

• Changed ten - Enable Time, unit value From: 6 ns To: 6 µs................................................................................................... 9

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5 Description (continued)
The SN65LVDS93A device requires no external components and little or no control. The data bus appears the
same at the input to the transmitter and output of the receiver with the data transmission transparent to the
users. The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling
edge with a low-level input and the possible use of the shutdown/clear (SHTDN) signal. SHTDN is an active-low
input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this
signal clears all internal registers at a low level.
The SN65LVDS93A is characterized for operation over ambient air temperatures of –40°C to 85°C.

6 Pin Configuration and Functions

DGG Package
56-Pin TSSOP ZQL Package
(Top View) 56-Ball BGA MICROSTAR
(Top View)
1 56 D4 6 5 4 3 2 1
IOVCC
D5 2 55 D3
D6 3 54 D2 K
D7 4 53 GND D8 D7 D5 D4 D2 D1

GND 5 52 D1
J
D8 6 51 D0 D9 GND D6 D3 D0 D27
D9 7 50 D27
H
D10 8 49 GND D11 VCC D10 GND Y0P Y0M

VCC 9 48 Y0M
G
D11 10 47 Y0P D13 D12 GND Y1P Y1M
IOVCC
D12 11 46 Y1M
F
D13 12 45 Y1P
D14 GND GND LVDSVCC
GND 13 44 LVDSVCC
GND E
D14 14 43
D16 D15 Y2P Y2M
D15 15 42 Y2M
D16 16 41 Y2P D
D17 D18 CLKSEL GND CLKP CLKM
CLKSEL 17 40 CLKOUTM
D17 18 39 CLKOUTP C
D19 GND IOVCC GND Y3P Y3M
D18 19 38 Y3M
D19 20 37 Y3P B
GND 21 36 GND D20 D21 D25 SHTDN PLLVCC GND

D20 22 35 GND A
D21 23 34 PLLVCC D22 D23 D24 D26 CLKIN GND

D22 24 33 GND
D23 25 32 SHTDN
IOVCC 26 31 CLKIN
D24 27 30 D26
D25 28 29 GND

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Pin Functions - TSSOP

PIN
I/O DESCRIPTION
NAME NO.
Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock
CLKSEL 17 I trigger
(CLKSEL = VIL).
CLKIN 31 I Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
CLKOUTM 40 O Differential LVDS pixel clock output.
CLKOUTP 39 O Output is high-impedance when SHTDN is pulled low (de-asserted).
D0 51
D1 52
D2 54
D3 55
D4 56
D5 2
D6 3
D7 4
D8 6
D9 7
D10 8
D11 10
D12 11 Data inputs; supports 1.8-V to 3.3-V input voltage selectable by VDD supply. To connect a
D13 12 graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not
I necessarily intuitive).
D14 14 Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16,
D15 15 D17, D23, and D27 to GND
D16 16
D17 18
D18 19
D19 20
D20 22
D21 23
D22 24
D23 25
D24 27
D25 28
D26 30
D27 50
5, 13, 21, 29,
GND 33, 35, 36, Supply Ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
43, 49, 53
Power
IOVCC 1, 26 Supply (1) I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing)
LVDSVCC 44 3.3-V LVDS output analog supply
PLLVCC 34 3.3-V PLL analog supply
Device shut down; pull low (de-assert) to shut down the device (low power, resets all
SHTDN 32 I
registers) and high (assert) for normal operation.
Power
VCC 9 3.3-V digital supply voltage
Supply (1)

(1) For a multilayer pcb, TI recommends keeping one common GND layer underneath the device and connecting all ground terminals
directly to this plane.
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Pin Functions - TSSOP (continued)

PIN
I/O DESCRIPTION
NAME NO.
Y0M 48
Y1M 46
Y2M 42 Differential LVDS data outputs.
O
Y0P 47 Outputs are high-impedance when SHTDN is pulled low (de-asserted)
Y1P 45
Y2P 41
Y3M 38 Differential LVDS Data outputs.
O Output is high-impedance when SHTDN is pulled low (de-asserted).
Y3P 37 Note: if the application only requires 18-bit color, this output can be left open.

Pin Functions - BGA MICROSTAR

BALL
I/O DESCRIPTION
NAME NO.
CMOS IN with
CLKIN A2 Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
pulldn
CLKM D1 Differential LVDS pixel clock output.
LVDS Out
CLKP D2 Output is high-impedance when SHTDN is pulled low (de-asserted).
Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input
CMOS IN with
CLKSEL D4 clock trigger
pulldn
(CLKSEL = VIL).
D0 J2
D1 K1
D2 K2
D3 J3
D4 K3
D5 K4
D6 J4
D7 K5
D8 K6
D9 J6
D10 H4
D11 H6
D12 G5 Data inputs; supports 1.8-V to 3.3-V input voltage selectable by VDD supply. To
D13 G6 connect a graphic source successfully to a display, the bit assignment of D[27:0] is
CMOS IN with
critical (and not necessarily intuitive).
D14 F6 pulldn
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11,
D15 E5 D16, D17, D23, and D27 to GND.
D16 E6
D17 D6
D18 D5
D19 C6
D20 B6
D21 B5
D22 A6
D23 A5
D24 A4
D25 B4
D26 A3
D27 J1

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Pin Functions - BGA MICROSTAR (continued)

BALL
I/O DESCRIPTION
NAME NO.
A1, B1, C3,
GND C5, F2, F5, J5, Supply Ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
D3, G3, H3

IOVCC C4, G4 Power Supply (1) I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal
swing)
LVDSVCC F1 3.3-V LVDS output analog supply
PLLVCC B2 3.3-V PLL analog supply
CMOS IN with Device shut down; pull low (de-assert) to shut down the device (low power, resets all
SHTDN B3
pulldn registers) and high (assert) for normal operation.
VCC H5 Power Supply (1) 3.3-V digital supply voltage
Y0M H1
Y1M G1
Y2M E1 Differential LVDS data outputs.
LVDS Out
Y0P H2 Outputs are high-impedance when SHTDN is pulled low (de-asserted)
Y1P G2
Y2P E2
Y3M C1 Differential LVDS Data outputs.
LVDS Out Output is high-impedance when SHTDN is pulled low (de-asserted).
Y3P C2 Note: if the application only requires 18-bit color, this output can be left open.
-- E3, E4, F3, F4 – Not connected

(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.

7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
Supply voltage, VCC, IOVCC, LVDSVCC, PLLVCC (2) –0.5 4 V
Voltage at any output terminal –0.5 VCC + 0.5 V
Voltage at any input terminal –0.5 IOVCC + 0.5 V
Continuous power dissipation See Thermal Information
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND terminals.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±5000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±500 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6
LVDS output supply voltage, LVDSVCC 3 3.3 3.6
PLL analog supply voltage, PLLVCC 3 3.3 3.6 V
IO input reference supply voltage, IOVCC 1.62 1.8 / 2.5 / 3.3 3.6
Power supply noise on any VCC terminal 0.1
IOVCC = 1.8 V IOVCC/2 + 0.3 V
High-level input voltage, VIH IOVCC = 2.5 V IOVCC/2 + 0.4 V V
IOVCC = 3.3 V IOVCC/2 + 0.5 V
IOVCC = 1.8 V IOVCC/2 – 0.3 V
Low-level input voltage, VIL IOVCC = 2.5 V IOVCC/2 – 0.4 V V
IOVCC = 3.3 V IOVCC/2 – 0.5 V
Differential load impedance, ZL 90 132 Ω
Operating free-air temperature, TA –45 85 °C

7.4 Thermal Information

SN65LVDS93A
ZQL (BGA DGG (TSSOP)
THERMAL METRIC (1) UNIT
MICROSTAR)
56 PINS 56 PINS
RθJA Junction-to-ambient thermal resistance 67.1 62.1
RθJC(top) Junction-to-case (top) thermal resistance 25.2 18.4
RθJB Junction-to-board thermal resistance 31.0 31.1 °C/W
ψJT Junction-to-top characterization parameter 0.8 0.8
ψJB Junction-to-board characterization parameter 30.3 30.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VT Input voltage threshold IOVCC/2 V
Differential steady-state output voltage mV
|VOD| 250 450
magnitude
RL = 100 Ω, See Figure 7
Change in the steady-state differential
Δ|VOD| output voltage magnitude between 1 35 mV
opposite binary states
Steady-state common-mode output
VOC(SS) 1.125 1.375 V
voltage See Figure 7
Peak-to-peak common-mode output tR/F (Dx, CLKin) = 1 ns
VOC(PP) 35 mV
voltage
IIH High-level input current VIH = IOVCC 25 μA
IIL Low-level input current VIL = 0 V ±10 μA
VOY = 0 V ±24 mA
IOS Short-circuit output current
VOD = 0 V ±12 mA
IOZ High-impedance state output current VO = 0 V to VCC ±20 μA

Input pulldown integrated resistor on all IOVCC = 1.8 V 200

Rpdn kΩ
inputs (Dx, CLKSEL, SHTDN, CLKIN) IOVCC = 3.3 V 100
Disabled, all inputs at GND;
IQ Quiescent current 2 100 μA
SHTDN = VIL

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
SHTDN = VIH, RL = 100 Ω (5 places),
grayscale pattern (Figure 8)
VCC = 3.3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 51.9
I(IOVCC) with IOVCC = 3.3 V 0.4 mA
I(IOVCC) with IOVCC = 1.8 V 0.1
SHTDN = VIH, RL = 100 Ω (5 places), 50%
transition density pattern (Figure 8),
VCC = 3. 3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 53.3
I(IOVCC) with IOVCC = 3.3 V 0.6 mA
I(IOVCC) with IOVCC = 1.8 V 0.2
SHTDN = VIH, RL = 100 Ω (5 places), worst-
case pattern (Figure 9),
VCC = 3.6 V, fCLK = 75 MHz
ICC Supply current (average) I(VCC) + I(PLLVCC) + I(LVDSVCC) 63.7
I(IOVCC) with IOVCC = 3.3 V 1.3 mA
I(IOVCC) with IOVCC = 1.8 V 0.5
SHTDN = VIH, RL = 100 Ω (5 places), worst-
case pattern (Figure 9),
fCLK = 100 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 81.6
I(IOVCC) with IOVCC = 3.6 V 1.6 mA
I(IOVCC) with IOVCC = 1.8 V 0.6
SHTDN = VIH, RL = 100 Ω (5 places), worst-
case pattern (Figure 9),
fCLK = 135 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC) 102.2
I(IOVCC) with IOVCC = 3.6 V 2.1 mA
I(IOVCC) with IOVCC = 1.8 V 0.8
CI Input capacitance 2 pF

7.6 Timing Requirements

MIN MAX UNIT
Input clock period, tc 7.4 100 ns
w/ modulation frequency 30 kHz 8%
Input clock modulation
w/ modulation frequency 50 kHz 6%
High-level input clock pulse width duration, tw 0.4 tc 0.6 tc ns
Input signal transition time, tt 3 ns
Data set up time, D0 through D27 before CLKIN (See Figure 6) 2 ns
Data hold time, D0 through D27 after CLKIN 0.8 ns

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7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS MIN TYP (1) MAX UNIT
Delay time, CLKOUT↑ after Yn valid
t0 (serial bit position 0, equal D1, D9, –0.1 0 0.1 ns
D20, D5)
Delay time, CLKOUT↑ after Yn valid
1 1
t1 (serial bit position 1, equal D0, D8, /7 tc – 0.1 /7 tc + 0.1 ns
D19, D27)
Delay time, CLKOUT↑ after Yn valid
2 2
t2 (serial bit position 2, equal D7, D18, /7 tc – 0.1 /7 tc + 0.1 ns
D26. D23)
Delay time, CLKOUT↑ after Yn valid
See Figure 10, tC = 10 ns, 3 3
t3 (serial bit position 3; equal D6, D15, /7 tc – 0.1 /7 tc + 0.1 ns
|Input clock jitter| < 25 ps (2)
D25, D17)
Delay time, CLKOUT↑ after Yn valid
4 4
t4 (serial bit position 4, equal D4, D14, /7 tc – 0.1 /7 tc + 0.1 ns
D24, D16)
Delay time, CLKOUT↑ after Yn valid
5 5
t5 (serial bit position 5, equal D3, D13, /7 tc – 0.1 /7 tc + 0.1 ns
D22, D11)
Delay time, CLKOUT↑ after Yn valid
6 6
t6 (serial bit position 6, equal D2, D12, /7 tc – 0.1 /7 tc + 0.1 ns
D21, D10)
tc(o) Output clock period tc ns
tC = 10 ns; clean reference clock,
±26
see Figure 11
tC = 10 ns with 0.05UI added noise
±44
(3)
modulated at 3 MHz, see Figure 11
Δtc(o) Output clock cycle-to-cycle jitter ps
tC = 7.4 ns; clean reference clock,
±35
see Figure 11
tC = 7.4 ns with 0.05UI added noise
±42
modulated at 3 MHz, see Figure 11
High-level output clock pulse 4
tw /7 tc ns
duration
Differential output voltage transition
tr/f See Figure 7 225 500 ps
time (tr or tf)
Enable time, SHTDN↑ to phase lock
ten f(clk) = 135 MHz, See Figure 12 6 µs
(Yn valid)
Disable time, SHTDN↓ to off-state
tdis f(clk) = 135 MHz, See Figure 13 7 ns
(CLKOUT high-impedance)

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed
over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.

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Dn

CLKIN
or
CLKIN

CLKOUT

Previous cycle Current cycle Next

Y0 D0-1 D7 D6 D4 D3 D2 D1 D0 D7+1

Y1 D8-1 D18 D15 D14 D13 D12 D9 D8 D18+1

Y2 D19-1 D26 D25 D24 D22 D21 D20 D19 D26+1

Y3 D27-1 D23 D17 D16 D11 D10 D5 D27 D23+1

Figure 1. Typical SN65LVDS93A Load and Shift Sequences

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7.8 Typical Characteristics

100 800
Output Jitter
90 700
ICC - Average Supply Current - mA

600

Period Clock Jitter - ps-pp

80
Input Jitter
VCC = 3.6V
70 500

60 400

50 VCC = 3.3V 300

200
40
VCC = 3V
100
30
0
20 0.01 0.10 1 10
10 30 50 70 90 110 130
f(mod) - Input Modular Frequency - MHz
fclk - Clock Frequency - MHz
Total device current (using grayscale pattern) over pixel clock CLK frequency during text = 100 MHz
frequency

Figure 2. Average Grayscale ICC vs Clock Frequency Figure 3. Output Clock Jitter vs Input Clock Jitter

CLKL Signal PRBS Data Signal

V - Voltage - 80mV/div

tk - Time - 1 ns/div
Clock signal = 135 MHz

Figure 4. Typical PRBS Output Signal

Over One Clock Period

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8 Parameter Measurement Information

LVDSVCC

IOVCC

5W
D or YnP or
50W YnM
SHTDN 10kW

7V 7V
300kW

Figure 5. Equivalent Input and Output Schematic Diagrams

tsu thold
Dn

CLKIN

All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.
CLKSEL = 0V.

Figure 6. Setup and Hold Time Definition

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Parameter Measurement Information (continued)

49.9W ± 1% (2 PLCS)
YP

VOD

YM VOC

100%
80%
VOD(H)

0V
VOD(L)
20%
0%
tf tr

VOC(PP)

VOC(SS) VOC(SS)

0V

Figure 7. Test Load and Voltage Definitions for LVDS Outputs

CLKIN

D0,8,16

D1,9,17

D2,10,18

D3,11,19

D4-7,12-15,20-23

D24-27
The 16 grayscale test pattern test device power consumption for a typical display pattern.

Figure 8. 16 Grayscale Test Pattern

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Parameter Measurement Information (continued)

T
CLKIN

EVEN Dn

ODD Dn
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.

Figure 9. Worst-Case Power Test Pattern

t7
CLKIN

CLKOUT

t6
t5
t4
t3
t2
t1
t0
Yn

VOD(H)
~2.5V CLKOUT
1.40V or Yn 0.00V
CLKIN
~0.5V VOD(L)
t7 t0-6
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.

Figure 10. SN65LVDS93A Timing Definitions

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Parameter Measurement Information (continued)

Device
Reference + VCO Under
Test
+

Modulation
v(t) = A sin(2 pfmodt)

HP8656B Signal HP8665A Synthesized Device Under DTS2070C

Generator, Signal Generator, Test Digital
0.1 MHz-990 MHz 0.1 MHz-4200 MHz TimeScope

RF Output CLKIN CLKOUT Input

RF Output Modulation Input

Figure 11. Output Clock Jitter Test Set Up

CLKIN

Dn

ten
SHTDN
Invalid
Yn Valid

Figure 12. Enable Time Waveforms

CLKIN

tdis
SHTDN

CLKOUT

Figure 13. Disable Time Waveforms

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9 Detailed Description

9.1 Overview
FlatLink™ is an LVDS SerDes data transmission system. The SN65LVDS93A takes in three (or four) data words
each containing seven single-ended data bits, and converts this to an LVDS serial output. Each serial output runs
at seven times that of the parallel data rate. The deserializer (receiver) device operates in the reverse manner.
The three (or four) LVDS serial inputs are transformed back to the original 7-bit parallel single-ended data.
FlatLink devices are available in 21:3 or 28:4 SerDes ratios.
• The 21-bit devices are designed for 6-bit RGB video for a total of 18 bits in addition to 3 extra bits for
horizontal synchronization, vertical synchronization, and data enable.
• The 28-bit devices are intended for 8-bit RGB video applications. Again, the extra 4 bits are for horizontal
synchronization, vertical synchronization, data enable, and the remaining is the reserved bit. These 28-bit
devices can also be used in 6-bit and 4-bit RGB applications as shown in the subsequent system diagrams.

9.2 Functional Block Diagram

Parallel-Load 7-bit
Shift Register
D0, D1, D2, D3, 7 Y0P
A,B,...G
D4, D6, D7 SHIFT/LOAD Y0M
>CLK

Parallel-Load 7-bit
Shift Register
D8, D9, D12, D13, 7 Y1P
A,B,...G
D14, D15, D18 SHIFT/LOAD Y1M
>CLK

Parallel-Load 7-bit
Shift Register
D19, D20, D21, D22, 7 Y2P
A,B,...G
D24, D25, D26 SHIFT/LOAD Y2M
>CLK

Parallel-Load 7-bit
Shift Register
D27, D5, D10, D11, 7 Y3P
A,B,...G
D16, D17, D23 SHIFT/LOAD Y3M
>CLK

Control Logic
SHTDN

7X Clock/PLL
7XCLK
CLKOUTP
CLKIN >CLK
CLKINH
CLKOUTM
CLKSEL RISING/FALLING EDGE

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9.3 Feature Description

9.3.1 TTL Input Data
The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video
information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The
data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the
CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the SN65LVDS93A and can connect directly to low-
power, low-voltage application and graphic processors. The bit mapping is listed in Table 1.

Table 1. Pixel Bit Ordering

RED GREEN BLUE
LSB R0 G0 B0
R1 G1 B1
R2 G2 B2
4-bit MSB R3 G3 B3
R4 G4 B4
6-bit MSB R5 G5 B5
R6 G6 B6
8-bit MSB R7 G7 B7

9.3.2 LVDS Output Data

The pixel data assignment is listed in Table 2 for 24-bit, 18-bit, and 12-bit color hosts.

Table 2. Pixel Data Assignment

8-BIT 6-BIT 4-BIT
SERIAL
DATA BITS NON-LINEAR STEP LINEAR STEP
CHANNEL FORMAT-1 FORMAT-2 FORMAT-3
SIZE SIZE
D0 R0 R2 R2 R0 R2 VCC
D1 R1 R3 R3 R1 R3 GND
D2 R2 R4 R4 R2 R0 R0
Y0 D3 R3 R5 R5 R3 R1 R1
D4 R4 R6 R6 R4 R2 R2
D6 R5 R7 R7 R5 R3 R3
D7 G0 G2 G2 G0 G2 VCC
D8 G1 G3 G3 G1 G3 GND
D9 G2 G4 G4 G2 G0 G0
D12 G3 G5 G5 G3 G1 G1
Y1 D13 G4 G6 G6 G4 G2 G2
D14 G5 G7 G7 G5 G3 G3
D15 B0 B2 B2 B0 B2 VCC
D18 B1 B3 B3 B1 B3 GND
D19 B2 B4 B4 B2 B0 B0
D20 B3 B5 B5 B3 B1 B1
D21 B4 B6 B6 B4 B2 B2
Y2 D22 B5 B7 B7 B5 B3 B3
D24 HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC
D25 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC
D26 ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE

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Table 2. Pixel Data Assignment (continued)

8-BIT 6-BIT 4-BIT
SERIAL
DATA BITS NON-LINEAR STEP LINEAR STEP
CHANNEL FORMAT-1 FORMAT-2 FORMAT-3
SIZE SIZE
D27 R6 R0 GND GND GND GND
D5 R7 R1 GND GND GND GND
D10 G6 G0 GND GND GND GND
Y3 D11 G7 G1 GND GND GND GND
D16 B6 B0 GND GND GND GND
D17 B7 B1 GND GND GND GND
D23 RSVD RSVD GND GND GND GND
CLKOUT CLKIN CLK CLK CLK CLK CLK CLK

9.4 Device Functional Modes

9.4.1 Input Clock Edge
The transmission of data bits D0 through D27 occurs as each are loaded into registers upon the edge of the
CLKIN signal, where the rising or falling edge of the clock may be selected through CLKSEL. The selection of a
clock rising edge occurs by inputting a high level to CLKSEL, which is achieved by populating pullup resistor to
pull CLKSEL=high. Inputting a low level to select a clock falling edge is achieved by directly connecting CLKSEL
to GND.

9.4.2 Low Power Mode

The SN65LVDS93A can be put in low-power consumption mode by active-low input SHTDN#. Connecting pin
SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-
level on this signal clears all internal registers to a low-level. Populate a pullup to VCC on SHTDN# to enable the
device for normal operation.

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section describes the power up sequence, provides information on device connectivity to various GPU and
LCD display panels, and offers a PCB routing example.

10.1.1 Power
The SN65LVDS93A does not require a specific power-up sequence.
The device is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and
connected to GND. The input level of the SHTDN during this time does not matter as only the input stage is
powered up while all other device blocks are still powered down.
The device is also permitted to power up all 3.3-V power domains while IOVCC is still powered down to GND.
The device will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of
their true input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the
LVDS output stage will turn on. The power consumption in this condition is significantly higher than standby
mode, but still lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power-up sequence (SN65LVDS93A SHTDN input initially low):
1. Ramp up LCD power (maybe 0.5 ms to 10 ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Enable video source output; start sending black video data.
4. Toggle LVDS83B shutdown to SHTDN = VIH.
5. Send >1 ms of black video data; this allows the LVDS83B to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power-down sequence (SN65LVDS93A SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set SN65LVDS93A input SHTDN = GND; wait for 250 ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.

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10.2 Typical Application

J1

U1H J2
C3 sma_surface
GND1
C5
GND2
D3
GND3
F5 J3
GND4 sma_surface
G3 U1A
GND5
H3 D1
GND6 CLKM
J5 D2
GND7 CLKP
A1
PLLGND sma_surface J4
B1 H2
LVDSGND1 Y0P
F2 H1
LVDSGND2 Y0M

G2 J5
Y1P sma_surface
SN65LVDS93A-Q1ZQL G1
Y1M

E1
Y2P
E2 sma_surface J6
Y2M
IOVCC
C2
Y3P
R4 R5 R6 R7 R8 R9 R10 C1
4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k Y3M
J7 sma_surface

U1B JMP1 SN65LVDS93A-Q1ZQL

J2 D0
D0 1 2
K1 D1 J8
D1 sma_surface
K2 D2
D2
J3 D3
D3
K3 D4
D4
J4 D6 J9
D6 sma_surface
K5 D7
D7 14

Header 7x2
SN65LVDS93A-Q1ZQL J10
IOVCC sma_surface

R11 R12 R13 R14 R15 R16 R17

4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k
sma_surface
U1C JMP2
K6 D8
D8 1 2
J6 D9
D9 IOVCC IOVCC
G5 D12
D12
G6 D13
D13
F6 D14
D14
E5 D15
D15
D5 D18
D18 14
R1 R2
Header 7x2 4.7k
SN65LVDS93A-Q1ZQL

IOVCC

R18 R19 R20 R21 R22 R23 R24

4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k
U1G JMP6
JMP3 B3 SHTDN
U1D SHTDN 1 2
C6 D19 D4 CLKSEL
D19 1 2 CLKSEL 3 4
B6 D20
D20 Header 2x2
B5 D21
D21 SN65LVDS93A-Q1ZQL
A6 D22
D22
A4 D24
D24
B4 D25
D25
A3 D26
D 26 14 U1J
E3
NC1
Header 7x2 E4
SN65LVDS93A-Q1ZQL NC2
F3
NC3
F4
NC4
IOVCC
R25 R26 R27 R28 R29 R30 R31 SN65LVDS93A-Q1ZQL
4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k

JMP4
U1E
K4 D5
D5 1 2 VCC IOVCC
H4 D10
D10 U1I
H6 D11
D11 G4
E6 D16 VCC
D16 B2
D6 D17 PLLVCC
D17 F1
A5 D23 LVDSVCC
D23
J1 D27
D27 14 H5
IOVCC1
C4
IOVCC2
Header 7x2
SN65LVDS93A-Q1ZQL
SN65LVDS93A-Q1ZQL

VCC VCC
VCC IOVCC

C31 C32 C33 C34 C35 C36 C40 C41 C42 C37 C38 C39
1uF 0.1uF 0.01uF 1uF 0.1uF 0.01uF
1uF 0.1uF 0.01uF 1uF 0.1uF
0.01uF

PLACE UNDER LVDS93A-Q1

(bottom pcb side)

Figure 14. Schematic Example (SN65LVDS93A Evaluation Board)

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Typical Application (continued)

10.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VCC 3.3 V
VCCIO 1.8 V
CLKIN Falling edge
SHTDN# High
Format 18-bit GPU to 24-bit LCD

10.2.2 Detailed Design Procedure

10.2.2.1 Signal Connectivity

While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the
industry has aligned over the years on a certain data format (bit order). Figure 15 through Figure 18 show how
each signal should be connected from the graphic source through the SN65LVDS93A input, output and LVDS
LCD panel input. Detailed notes are provided with each figure.

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24-bpc GPU SN65LVDS93A

FORMAT1 FORMAT2 (See Note A)
R0(LSB) D0 D27
R1 D1 D5
R2 D2 D0
R3 D3 D1
R4 D4 D2 Y0M 100
R5 D6 D3 Y0P
R6 D27 D4 to column
driver
R7(MSB) D5 D6 Y1M 100
G0(LSB) D7 D10 Y1P

Main board connector

FPC
G1 D8 D11

Panel connector
Cable
G2 D9 D7 Y2M LVDS
100 timing
G3 D12 D8 Y2P Controller
G4 D13 D9 (8bpc, 24bpp)
G5 D14 D12 Y3M
100
G6 D10 D13 Y3P to row driver
G7(MSB) D11 D14
B0(LSB) D15 D16 CLKOUTM 100
B1 D18 D17 CLKOUTP
B2 D19 D15
B3 D20 D18
B4 D21 D19
B5 D22 D20 24-bpp LCD Display
B6 D16 D21
B7(MSB) D17 D22
HSYNC D24 D24
VSYNC D25 D25
ENABLE D26 D26
RSVD (Note C) D23 D23
CLK CLKIN CLKIN
VDDGPUIO

LVDSVCC
CLKSEL

PLLVCC
SHTDN
IOVCC
GND

GND

VCC

4.8k 3.3V 3.3V

1.8V or 2.5V C1 C2 C3
Rpullup
or 3.3V
Rpulldown

(See Note B)

Main Board

Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each
color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of
each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by
checking the LCD display data sheet.
• Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the
dominate data format for LCD panels.
• Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
• C1: decoupling capacitor for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling capacitor for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
Note D. RSVD must be driven to a valid logic level. All unused SN65LVDS93A inputs must be tied to a valid logic
level.

Figure 15. 24-Bit Color Host to 24-Bit LCD Panel Application

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18-bpp GPU SN65LVDS93A

R0(LSB) D0
R1 D1
R2 D2
R3 D3
R4 D4 Y0M 100
R5(MSB) D6 Y0P
D27 to column
driver
D5 Y1M 100
G0(LSB) D7 Y1P

Main board connector

FPC
G1 D8

Panel connector
Cable
G2 D9 Y2M LVDS
100
G3 D12 Y2P timing
Controller
G4 D13 (6-bpc, 18-bpp)
G5(MSB) D14 CLKOUTM
100
D10 CLKOUTP to row driver

D11
B0(LSB) D15
B1 D18
B2 D19
B3 D20
B4 D21
B5(MSB) 18-bpp LCD Display
D22
D16
D17 Y3M
(See Note A)
HSYNC D24 Y3P
VSYNC D25
ENABLE D26
RSVD D23
CLK
LVDSVCC

CLKIN
VDDGPUIO

CLKSEL

PLLVCC
SHTDN
IOVCC
GND

GND

VCC

4.8k 3.3V 3.3V

1.8V or 2.5V C1 C2 C3
Rpullup
or 3.3V
Rpulldown
(See Note B)

Main Board
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
• C1: decoupling capacitor for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling capacitor for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.

Figure 16. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application

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12-bpp GPU SN65LVDS93A

(See Note B)
R2 or VCC D0
R3 or GND D1
R0 D2
R1 D3
R2 D4 Y0M 100
R3(MSB) D6 Y0P
D27 to column
driver
(See Note B) D5 Y1M 100
G2 or VCC D7 Y1P

Main board connector

Panell connector
FPC
G3 or GND D8 Cable

t
G0 D9 Y2M LVDS
100
G1 D12 Y2P timing
G2 Controller
D13 (6-bpc, 18-bpp)
G3(MSB) D14 CLKOUTM
100
D10 CLKOUTP to row driver
(See Note B) D11
B2 or VCC D15
B3 or GND D18
B0 D19
B1 D20
B2 D21
B3(MSB) 18-bpp LCD Display
D22
D16
D17 Y3M
HSYNC (See Note A)
D24 Y3P
VSYNC D25
ENABLE D26
RSVD D23
CLK
LVDSVCC

CLKIN
VDDGPUIO

CLKSEL

PLLVCC
SHTDN
IOVCC
GND

GND

VCC

4.8k 3.3V 3.3V

1.8V or 2.5V C1 Rpullup C2 C3

or 3.3V
Rpulldown

(See Note C)

Main Board
Note A. Leave output Y3 N.C.
Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of
the entire color space at the expense of nonlinear step sizes between each step. For linear steps with less dynamic
range, connect D1, D8, and D18 to GND.
R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color
space at the expense of nonlinear step sizes between each step. For linear steps with less dynamic range, connect
D0, D7, and D15 to VCC.
Note C.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
• C1: decoupling capacitor for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling capacitor for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.

Figure 17. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application

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24-bpp GPU SN65LVDS93A

R0 and R1: NC
(See Note B) R2 D0
R3 D1
R4 D2
R5 D3
R6 D4 Y0M 100
R7(MSB) D6 Y0P
D27 to column
driver
G0 and G1: NC
(See Note B) D5 Y1M 100
G2 D7 Y1P

Main board connector

Panell connector
FPC
G3 D8 Cable

t
G4 D9 Y2M LVDS
100
G5 D12 Y2P timing
G6 Controller
D13 (6-bpc, 18-bpp)
G7(MSB) D14 CLKOUTM
100
D10 CLKOUTP to row driver
B0 and B1: NC
(See Note B) D11
B2 D15
B3 D18
B4 D19
B5 D20
B6 D21
B7(MSB) 18-bpp LCD Display
D22
B0 and B1: NC D16
(See Note B)
D17 Y3M
HSYNC (See Note A)
D24 Y3P
VSYNC D25
ENABLE D26
RSVD D23
CLK
LVDSVCC

CLKIN
VDDGPUIO

CLKSEL

PLLVCC
SHTDN
IOVCC
GND

GND

VCC

4.8k 3.3V 3.3V

1.8V or 2.5V C1 Rpullup C2 C3

or 3.3V
Rpulldown

(See Note C)

Main Board
Note A. Leave output Y3 NC.
Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down
to18-bit per pixel.
NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
• C1: decoupling capacitor for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling capacitor for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling capacitor for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.

Figure 18. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application

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10.2.2.2 PCB Routing

Figure 19 shows a possible breakout of the data input and output signals on two layers of a printed-circuit-board.
D27
D5
D10
D11
D16
D17
D23
Y0M
Y0P
D19
D20 Y1M
D21 Y1P
D22
D24
D25 Y2M
D26 Y2P

D8 CLKINM
D9 CLKINP
D12
D13 Y3M
D14 Y3P
D15
D18

D0
D1
D2
D3
D4
D6
D7

CLKIN
Figure 19. Printed-Circuit-Board Routing Example (See Figure 14 for the Schematic)

10.2.3 Application Curve

250

200
Pixel Value (dec)

150

100

50

0
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Pixel Samples

Figure 20. 18b GPU to 24b LCD

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11 Power Supply Recommendations

Power supply PLL, IO, and LVDS pins must be uncoupled from each.

12 Layout

12.1 Layout Guidelines

12.1.1 Board Stackup
There is no fundamental information about how many layers should be used and how the board stackup should
look. Again, the easiest way the get good results is to use the design from the EVMs of TI. The magazine
Elektronik Praxis has published an article with an analysis of different board stackups. These are listed in
Table 4. Generally, the use of microstrip traces needs at least two layers, whereas one of them must be a GND
plane. Better is the use of a 4-layer PCB, with a GND and a VCC plane and two signal layers. If the circuit is
complex and signals must be routed as stripline, because of propagation delay and/or characteristic impedance,
a 6-layer stackup should be used.

Table 4. Possible Board Stackup on a Four-Layer PCB

MODEL 1 MODEL 2 MODEL 3 MODEL 4
Layer 1 SIG SIG SIG GND
Layer 2 SIG GND GND SIG
Layer 3 VCC VCC SIG VCC
Layer 4 GND SIG VCC SIG
Decoupling Good Good Bad Bad
EMC Bad Bad Bad Bad
Signal Integrity Bad Bad Good Bad
Self Disturbance Satisfaction Satisfaction Satisfaction High

12.1.2 Power and Ground Planes

A complete ground plane in high-speed design is essential. Additionally, a complete power plane is
recommended as well. In a complex system, several regulated voltages can be present. The best solution is for
every voltage to have its own layer and its own ground plane. But this would result in a huge number of layers
just for ground and supply voltages. What are the alternatives? Split the ground planes and the power planes? In
a mixed-signal design, for example, using data converters, the manufacturer often recommends splitting the
analog ground and the digital ground to avoid noise coupling between the digital part and the sensitive analog
part. Take care when using split ground planes because:
• Split ground planes act as slot antennas and radiate.
• A routed trace over a gap creates large loop areas, because the return current cannot flow beside the signal,
and the signal can induce noise into the nonrelated reference plane (Figure 21).
• With a proper signal routing, crosstalk also can arise in the return current path due to discontinuities in the
ground plane. Always take care of the return current (Figure 22).
For Figure 22, do not route a signal referenced to digital ground over analog ground and vice versa. The return
current cannot take the direct way along the signal trace and so a loop area occurs. Furthermore, the signal
induces noise, due to crosstalk (dotted red line) into the analog ground plane.

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: SN65LVDS93A
SN65LVDS93A
SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com

Figure 21. Loop Area and Crosstalk Due to Poor Signal Routing and Ground Splitting

Figure 22. Crosstalk Induced by the Return Current Path

12.1.3 Traces, Vias, and Other PCB Components

A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner, and the
characteristic impedance changes. This impedance change causes reflections.
• Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any
impedance change, the best routing would be a round bend (see Figure 23).
• Separate high-speed signals (for example, clock signals) from low-speed signals and digital from analog
signals; again, placement is important.
• To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route
them with 90° to each other.

28 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: SN65LVDS93A

 SN65LVDS93A
www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015

Figure 23. Poor and Good Right-Angle Bends

12.2 Layout Example

6507548
EVM REV
SN65LVDS93A-Q1

Figure 24. SN65LVDS93A EVM Top Layer – TSSOP Package

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Links: SN65LVDS93A
SN65LVDS93A
SLLS992B – AUGUST 2009 – REVISED MARCH 2015 www.ti.com

Layout Example (continued)

Figure 25. SN65LVDS93A EVM VCC Layer – TSSOP Package

30 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated

Product Folder Links: SN65LVDS93A

 SN65LVDS93A
www.ti.com SLLS992B – AUGUST 2009 – REVISED MARCH 2015

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation
For related documentation see the following:
LVDS SerDes Receiver, SLLS928

13.2 Trademarks
OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 31

Product Folder Links: SN65LVDS93A
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Jan-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN65LVDS93ADGG ACTIVE TSSOP DGG 56 35 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS93A

SN65LVDS93ADGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LVDS93A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Jan-2021

OTHER QUALIFIED VERSIONS OF SN65LVDS93A :

• Automotive: SN65LVDS93A-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS93ADGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS93ADGGR TSSOP DGG 56 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN65LVDS93ADGG DGG TSSOP 56 35 530 11.89 3600 4.9

Pack Materials-Page 3
 PACKAGE OUTLINE
DGG0056A SCALE 1.200
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
8.3 SEATING PLANE
TYP
7.9
PIN 1 ID 0.1 C
A
AREA 54X 0.5
56
1

14.1 2X
13.9 13.5
NOTE 3

28
29
0.27
6.2 56X 1.2 MAX
B 0.17
6.0
0.08 C A B

(0.15) TYP

0.25
SEE DETAIL A GAGE PLANE

0.15
0 -8 0.75 0.05
0.50

DETAIL A
TYPICAL

4222167/A 07/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGG0056A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X (1.5) SYMM

1
56

56X (0.3)

54X (0.5)

(R0.05)
TYP
SYMM

28 29
(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4222167/A 07/2015
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGG0056A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

56X (1.5) SYMM

1
56

56X (0.3)

54X (0.5)

(R0.05) TYP
SYMM

28 29

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4222167/A 07/2015
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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