4.4 Introduction : In chapter 3. we had already developed microprocessor. It was our version. The same should ‘be replica of Inte! 8085. So let’s start study of the same. Features of Intel 8085 : features of 8085 include It is an 8 bit microprocessor ice. it can accept or provide 8 bit data simultaneously. It is a single chip, NMOS device implemented with 6200 wansistors. It requires a single +5V power supply. It provides on chip clock generator, hence it does not require extemal clock generator, but it requires external tuned circuit like LC, RC or crystal. It requires two phase, 50% duty cycle, TTL clock. These clock signals are generated by an intemal clock generator. (Refer Fig. 4.1), The maximum clock frequency is 3. MHz and minimum clock frequency is 00 KHz. ss It provides 74 instructions with the following addressing modes : register, te direct, immediate, indirect and implied. Fig. 4.1; 2 Phase TTL clock The data bus is multiplexed with address bus, hence it requires external hardware to separate data lines from address lines.(This is the drawback of 8085). ) It provides 16 address lines, hence it can access 2'“= 64 K bytes of memory.' nr erga . (1) tt pemeratcs § bit LO address, hence at can access 2 (1) performs the following anthmenc ant logical oper aE nay § bit 16 ba burury addsnon 2 dipt BCD xian, # bt Bin AND. OR. EXOR, complement anil sit CPEENOS AST 65, RST 7.5, (12) Tt peovades § hardware interrupts (13) By providing extemal hardware one can Increase (14) 808S has capability to share ts bus with om > | Wecreg tay = 156 Ing POS 208 2565 any igs bin, my subtraction lapyeoy re interrupt capability of 1. ermal bus controller (Direct from memory to WO and vice aig es 6 general pumpose registers ars 1, controller). for transfernng large amour of data (15) It provides one accumulator, one flag mpser, eg Purpose reaisters (16) th providss seams for advanced control signals. (Advanced control sigrats are uaeg 5, . te sysem) (17) It cam be used to implement three chip microcomputer (0065, #155 and #355) (18) It provides neo seris! 10 lines viz SOD and SID, hence serial penpherals con be ieetiag with $085 directly 4.3 Pin Diagram of 8035 : The £985A is an % bit general purpose x) microprocessor having 40 pins and works on +5V x single power supply. Fig. 4.2 stows the pin diagram pecey our cf S085A To study the pin diagram, we group the 500 signals as shown in Fig. $3. They are as follows : a G) Address bus THARP (2) Data bus RST7S G) Status signals RST6S (3) Convo! signais ie (5) Power supply eile (6) Clock signals 4D, (7) Interrupt signals 1D, (8) Serial input output signals AD, (9) DMA request signals ADs (10) Reset signals, AD, ADS ADe AD, ss, Fig, 4.2 : Pin diagram of 8085 functionvise identical with our microprocessor. Note : Observe pin configuration carefully. it matches with our microprocessor. Obviously,yr 8085 Microprocessor yee os hed serial sio—4 ie YO ports igher ordor UID Re soD«—} address bus TRAP —> RST7.5 AD; ~ AD, Multiplexed 7 address / data bus Interrupt m signals §\ PSTES RSTS.S | INTR—) saga | Le INTA*—] Ls Status 0 signals — S| DMA request) HOLD Signal 7 signals) HLDA hil ES Control preset | RESETIN—> |. WA signals signals RESET OUT <—} — READY XM CLK ouT Clock signals Fig, 4.3 : Groups of 8085 signals Symbol Name and function () Ay- Aig, Address bus : These are output, tri-state signals used as higher order 8 bits of 16 bit address. These signals are unidirectional meaning that the address is given by 8085 to select a memory or an I/O device. (0) ADy-AD, Multiplexed address/data bus : These signals are VO wistatable signals. These pins provides multiplexed or time, shared address and data bus. Address is lower onder of total 16 bit address i.e. A7— Ag, Refer Fig. 4.4, as shown the bus ‘works in conjuction with ALE. In earlier part it will output address. Address will remain there for finite time. After that it will vanish. In later part it is used as data bus;,ie. either for reading or writing. 1, (ae a) — —— Fig. 44: Multiplexed address/data busa | 60n5 Moropvonesnn Techniques a4 Open, seponato address ntl data . Wt extemal peripherals requires scp" MW the DMO TEP A wor we ester ttch This avantape oF nuttpgenc wo @) (5) © ALE tom S, and Sy ‘ her of pins But disndyintay AMicrMprOcessor requires less HUH a " } lemultiplesing Second ext IC (Lath) for : oe rnltiplesing, tittle bit more tine required for read/write oy Address lated enable ¢ This isan output st asitive potty ADy= AD, contents, I isa posi jermpiocessor, When pulse is HIGH, it ingiee ie Al by av aniernpto Micateg ADy ae adress, When It is LOW, it indicates tn the al, used (0 jive int on; twilse, peered Whey ion op operation is starte the contents of ADp omens ane data, (Refer Bish) The ALA signat is used! to separate ADy = ADy (Le, denttiptexy ig 4 and Do Dy. ‘To do this separation a tateh is connected 0 AD, ~ apy The latch is controlled by ALE signal Input Outpuvimenory This is aH Out MS SHE, Ye Gg ie et c vi C1 Biv information of operation to be performed with memory or yo, devi aA, lines Whew 1OMMt = 0 the microprocessor fs performing & meMOFY telaed open and when [OAL © L the microprocessor is performing an VO deyieg ms operation. This is the sigtal which separes memory and VO dayiggg TMM signal is combined with read and write contro} implement this; Signa nals ane generated; one for memory and other for VO gee and vo sets of ovicg, The function performed by IO/M can also be performed by using one aug, Tine, Bur in this case the number of VO devices and memory which As connected to $085 rwill be halved, Instead of haying 1O/M tine, the manufacturer could have increased one line, But the main problem with (his approach is that the total nun address fines wow becomes 17, AIL the internal sources of adldess fines are ogy 16 bits 80 itis not possible to generate 17 bil address Using 16 bits, So inde of adding one addess ine for 1O/M, itis used (0 address. Wo separate section, ie, memory and 1/0 ports. Status signals Sy and S1 : These are output status signals used to gig information of operation performed by microprocessor. These are generally ng, used in small systems but can be used to generale advaniced control signals for large systems, The Sy and S; lines specifies four different conditions of 8085 machine cycles These 4 cycles are as follows : (1) OPCODE felch (Instniction read from memory) Sy 2) Read (Data read from memory) Sy =0, S; = | 3) Write Sy=1, 8,20 (4) Halt Sy =0, S, When So and S; is combined with IO/M we get status of all the machine cycles (operations) performed by 8085 as shown in Table 1 Read : This is an active low, output control signal used to read data from memory or an YO device. To read data from device, microprocessor selects 2 device, make data bus available for data transfer and then generates signal RD CaM be address Nber ofTechniques, a 8085 M to teal data thom selected device ES Meroprocissn Write: This is a Sis an act memory’ oF an VO ten Bi "Ys Output control signal used to site data to sn 0 W , device a tases st on danny an ee MFOEACN eects 3 WR indicates that the contents er Interrupt acknowledge | | o Halt T Pz | X | Xx [How X_ |X {Reset [Note : READY TRAP RST 7.5, RST 6.5 and RST 5.5 INTR au INTA Z-Tristate (High impedance) condition X-Unspecified condition \ This is an active high input control signal. It is used by microprocessor to detect whether a peripheral has completed the data transfer or not. If ready pin is HIGH, the microprocessor will complete the operation and proceed for next operation. But if ready pin is LOW (ie. peripheral has not yet completed the operation), microprocessor will WAIT until it goes HIGH. The main function of this pin is to synchronize slower peripheral to the faster microprocessor. This is an active high level, edge triggered, non maskable, highest. priority interrupt. When TRAP line is active microprocessor performs intemal restart automatically at address 0024. The net effect of TRAP is, it transfers program control at address 0024. Restart interrupts : These are active high, edge (RST 7.5) or level (RST 6.5 and RST 5.5) triggered maskable interrupt. The priorities of these are TRAP, RST 7.5, RST 6.5, RST 5.5. When RST 75, RST 6.5, RST 5.5 is active microprocessor performs intemal restart automatically at address 003C, 0034, 002C respectively. The net effect is, it transfers program control at address, specified above. Interrupt request : INTR is an active high, level triggered general purpose interrupt. When INTR_ is active, microprocessor generate an interrupt acknowledge signal INTA. The INTR and INTA signals are basically used to expand interrupt system to more than 56 Microprocessor Techniques The details of TRAP, RS chapter 10, Note : d by other controll yh, input signal used by a (12) HOLD HOLD is an active high of address, data and control buses, Wheat ut use : i microprocessor 1¢* tn use of the bus. TO implement this, the micro Ching | cyele and will relinquis tcrOpTO ces ‘i ristate its address, data and control signals (RD, WR and TO/My, 4.4 will tristate its address, i in response to HOLD generates a gig, “P Jing them, The microprocessor t sees the requesting A2vc® by HILDA signal, When HLDA jg ao, hat aenowiedss Mapes has eceved HOLD Yous and will ming = is next clock cycle. The other controller will use buses ang completion of work will deoctvate HOLD signal, because op ‘ft microprocessor will also make HLDA LOW. The microprocessor takes coy = of buses half clock cycle after HLDA goes eae — (13) RESET — This is an active low, input reset signal. When RESET IN = 0, it ey, his is a7 er ie, 0000 aed makes address, data and conte tines yigaet ‘ter reset the status of internal register and_flags are unpredictable, The cpiy held in the reset condition as along as RESET IN is applied. After eset te rnicroprocessor stais executing instructions from 2000 H ortwards. Thus 09g ff rere a6 RESET aes of MHCTOEESSOE ( i i igh, output signal used to indi Ca : (1) RESET This i an ce Na ol as aye fest, te Mer devices comes the system. : 7 (is) SID Serial input data : This is an active high, serial input port pin, used to acoge Sern pit dala under software control. When a RIM instruction is execuey the SID pin data is loaded in bit Dy of accumulator iat output data : This is an active high, serial output port pis ne Serial output #90 “sata under Software conrol. When a SIM instutin @ varsted the SOD pin is set or reset depending on Dz and De bit of sccumulator, The details of SID and SOD are covered in chapter 14 (17) X,Xz___ These are clock inpot signals, connected to crystal, LC or RC network. The X and X; pins drive the interal clock generator circuit: ‘The frequency is divide ty 2 and used as operating frequency. Generally, the 6.014 MHz crystal is connected to X, and Xp, So the operating frequency is 3.07 MHz, ie, (+2) (18) CLK OUT This is an output signal, used as a system clock. ‘The intemal operat frequency ie(+2), is available on CLK. OUT pin, (19) Vee and — Power supplty Vec - +5V, Vss Vos ~ Ground reference ZI 4.4 8085 CPU Architecture : ‘Alas | we have reached to architecture, Hold your breath and observe it carefully. .- Aa you have won the game. Except few points you are acquainted with cach and every block. Compt Fig, 3.23 in chapter 3, with Fig, 4.5.sssor $808 Jo weadeyp yr0Iq [UONDUNY = s*p “BLT 3| 8 | snqueg, ssanpy nq sseuppy 170 3| ‘avSay Sty-ty VOTH MOH UM Gy WOT 's °s Sry Apeay iasoy UIIeSeH 1s t Pitttite it 4 s (8) 2044 (@) 20314 = LS -— eee 4no 710 eg / sseuPpY sseuppy * Jonuos pue Buy, ee x 10 Ly Aiddns somog*— ON + As I | | (e1)seunosumibag | D | é Supooue | (91) so1w10d ses z etka 2 euyoou sl (@)-601 se |S pur Jepooep 1 H gs uogonysuT (@) Ber (te |S 7 a oe (@) 631 (@) Bei | 2 a | ‘Berdue, | Bei -dwo, (9) s0ys{601 | @z oronnsur a JoyejnWINDoyee 8085 Mi Mictoprocossor Techniques att Vo cen replaced by temporary topisigg—— (1 Output store register in our microprocessor, Has oe oe ne monty Tepister Q) Wo more temporary registers Le, W and Z are ads | Q)__ Remaining fat ecture is same. Se ars = again go through each and every block yao Eventhongh we know everything, we wil And yi make ont concepts, more strony pee ‘The architecture is divided in different groups as follows : 2 3) Interrupt (1) Atithmetic and logical group (2) Register BOP y(t timing and je | (Serial VO contrat prop (5) Instruction register, : SOMO eon | 4.5 Arithmetic and Logical Group : This group consists of ALU, accumulator or A register, Cemporary register and flag repiieg 4.5.4 ALU: ‘The ALU performs arithmetic operations such as addition patie ae ope such as ANDing, ORing, EXORing, cle, This block can be wel visnlce Dy Unie ALU IC 74igh In it the arithmetic and logical operations are performed on input cepreraes en A and 5 inputs are 4 bits cach. The data is provided at A and B inputs anc sovided ee ited is select, by using select fines. Similarly in 8085, to ALU the inputs are pt YY ACCUMUaLOT ng ations ¥ formed on these data bytes x temporaty registers; both are of 8 bits. The operation to be pe : tes is Selecta by control logic, The ALU will perform the operation and output aan - internal data bus Te ALU is of 8 bits so at a time operation on 8 bit data can only be performed, 4.5.2 Accumulator : The accumulator is a 8 bit general purpose register connected to intermal data bus ang to ALU. It is also called as A register. As it is connected as one of the inputs 10 ALU, it is usc, in most of the arithmetic and logic instructions. After performing an operation, the ALU places ig result on internal data bus, from there it is generally stored in accumulator. So accumutator ig integral part in performing different operations. Because of its general purpose nature it can also by used to store 8 bits of data temporarily 4.5.3 Temporary Register : ‘The other input to ALU is given by temporary register. This register is not available for user, It is only used internally by microprocessor. To perform arithmetic and logical operations microprocessor assumes one data is available in accumulator and takes another data from other register (depends on instruction) into temporary register and then performs operation on the two daty bytes. Example : ADD B instruction, adds A reg and B reg contents, the result is stored in A reg In this case one data is available in A reg. The other data is available in B register, this other dia from B register is transferred to temporary register and then add operation is performed on that This temporary register is also used for other operations such a8 register to register data transfer, ct. 4.5.4 Flag Register (PSW) : The flag register is nothing but a group of flip-flops used to give status of different operations result, The flag register is connected to ALU. When an operation is performed by ALU, the result is transferred on internal data bus and status of result will be stored in flip flops. It is clear that for al other operations, except related to ALU, the flags doesn’t get affected. It will only give status if an operation is performed in ALUor Techniques process 49 8085 Microprocessor note : Output of flag register is not ay register and manipulate | Kectly accessible to the study, instnicton cot? INDIRECTLY, wth sone iechitues Batwa i ie " Te ferent Mags and Weir postions in fag gine mah AS shown in Fig, 4.6, . D 2, o _ nin Fig. 4,6, D, eetleee x [ac Tx > =! Po cy L—+ Cary flag ooo Rarity flag ‘Auxillary carry flag “vb Pa eo tag X indicates unspeciied bis Sn flag Fig. 4.6 : 8085 flag register ) CY Carry flag + If an operation performed in ALU flag is SET. It works as 9% pj it Ce i Addition and as borrow flag for subtraction, If there a it, Le. D>, of the result, CY flag is RESET. ) AC Ausiliary carry flag : If an operation performed in ALU generates a carry from lower nibble (i.e. Dg to Ds) to upper nibble (ie, Dy t0 D,) th is i 1s 10 Dz) the AC Mag is set ie, a cary given by D, bit to D, is a AC flag This is not a general pumpose flag, it is onh i ot a flag, ly used internally by microprocessor to perform binary to BCD conversion. I is not available for progranuner for any decision making. - Z — Zero flag : If an operation in ALU results in zero, th flag is SET. is not zero, the zero flag is RESET. ni SA SET I he Pa S Sign flag : In sign magnitude format, the sign of a number is indicated by MSB bit. If MSB bit = 0, the mumber is positive and if MSB bit = 1, the mumber is negative, In 8085 MSB bit is D, bit. The sign flag is exact replica of D, bit of the result, If D, = 1, the flag is set and if D, = 0, the flag is reset, This flag can be used to perform operation on signed numbers, Parity flag : This bit is used to indicate the parity of the result, If the result contain even number of 1’s this flag is set. If the result contains odd number of 1's this flag is reset, ie. by insertion of flag bit microprocessor maintains odd parity for result generates a cary from Dy bit, the CY Note : In 8085 overflow flag is not present. Basically, the overflow flag and carry flag are not same. The overflow flag is used by other processor Ex. 8086. It is used to indicate overflow condition. It is set if the result of a signed operation is too large to fit in the number of bits available, When we want to represent signed numbers (ie. positive and negative numbers) we use 2's complement sign magnitude form. In this form the MSB is used as a sign bit and remaining 7 bits are used as magnitude, So for an & bit number the allowed range of numbers is + 127 to ~128. When result of any arithmetic operation exceeds this limit, this indicates an overflow] condition. In 8085 overflow condition can be checked by checking O7 bit of operands and result.= Microprocessor Techniques 4H0 ee £085 Mictoprocas, 46 Register Group : Se TRS group consists of 3 types of registers : : . (0 Temporary registers (ii) General purpose registers (tii) Special purpose registers, 4.6.1 Temporary Registers (W and Z) : The W and Z registers vailable for user. They are used by micro a sisters are not availat ntemal operations such as to store operand, immediate operand oF address of memory PESO fo 4.6.2. General Purpose Registers : The SO8S contains 6 general purpose registers of 8 bits each, named as B, C, D, E, H These can be used to store § bits of data or can be used to form a register pair to store 16 py data. The register pairs available are BC, DE and HL, These registers are programmable by a User can store any data in these registers and use it to perform different operations, 7 46.3 Special Purpose Registers : The S085 contains 3 special purpose registers such as program counter, stack pointer ang incrementer / decrementer latch. (2) Program counter : This is a 16 bit register used for execution of program. This regicer always points to address of memory from where the next instruction is to be fetched and executed When microprocessor performs one operation of taking instruction i.e. fetching, the PC contents are automatically incremented by one to point to next location. In this way, PC keeps the track for execution of program. Upon reset PC contents are set to 0000 H, so after reset operation microprocessor will start execution of program from 0000 H onwards. The program counter is of 16 bits. The main reason behind this is that the 8085 contains 16 lines. By using 16 address lines one can select any memory location in the memory map of $085 (b) Stack pointer : This is a 16 bit register used to define the stack starting address. Stack ig a reserved portion of memory where register pair information cen be stored or taken back under software control, The stack pointer is used to keep track of data stored on stack. [Refer section 387 in chapter 3 for operation in stack], (c)_ Incrementer/decrementer latch : This 16 bit register is used, to increment or decrement the contents of PC and SP registers. In coordination with these registers, two buffers are used. (A) Address buffer This is an 8 bit unidirectional buffer used for Ag to Ays address ling. These are used to output higher order address. on Ag to Ays. When they are not in use or under certain conditions such as reset, hold, halt, this buffer is used to tristate Ag to Ays address lines (B) Address/data buffer : This is an 8 bit bidirectional buffer used for address/data, ‘The address/data signals are multiplexed on AD, to AD, lines, In earlier part it is used to output lower order address Ay to A, and in later part it is used to input or output data Dg to D>. The address is taken from address lines and data is taken or transferred on intemal data bus. Under certain condition such as reset, hold, halt this buffer is used to tristate AD, to AD, address/data lines. The! various sources of addresses for the address register includes program counter, stack pointe, temporary registers, BC pair, DE pair and HL pair. These are as shown in Fig. 4.7.LO AAE Fit, 4.7 + Varlous sources off addreaves Hote : As mentioned to you, PC punks to program mamary end OP ports wo data memory In Shon, any register that is used as 4 pointer, to point mremery, have to generate “Address” OHILY, Gomes way, a5 BC, DE and HL paits can be used a8 ‘Data pointer (Pointing to data memory”, pit output address. 7 Interrupt Control ; This block accepts different interrupt request inputs such as TRAP, RST 75, RST 65, 55 and INTR, When a valid interrupt request is present, it informs control logic to take action response 19 ct signa Note : Presently this is enough, At this stage too much involvement in interrupt part vill riot be much comfortable, Serial I/O Control Group : The data transferred on Dy to Dy lines is a parallel data, but under certain condition it is yantagcous to usc serial data transfer, 8085 implements this by using SID and SOD signals. The on these lines is accepted or transferred under software control by setial YO control block. In to perform serial data transfer there are two special instructions RIM and SIM. 9 Instruction Register, Decoder and Control Group : 11 Instruction Register : When an instruction is fetched from memory it is loaded in instruction register. These ‘ae then provided to decoder for decoding. This register is only activated when an tion code or OPCODE. is available on internal data bus. It is non programmable register 101 available for programmers use. Remember it accepts only OPCODE of instruction, operands Nol accepted by this register.5.1__ Introduction : ‘This chapter steps towards developing “stem” using Be ia) devciorme. Sm microprocessor based system, we have to follow, the steps given aS follows : Step 1: Design Reset circuit. Step 2: Design CLK circuit Step 3: Generate address and data bus, SEPARATELY. Step 4: Generate control signals. [ Note: Above stops are used to genetate the ciscuit which is “STANDARD” and should be used in your design, as it is. Also referred as “Basic skeleton” for microprocessor system. ] Step 5 Once you are ready with address, data and control signals interface memory devices. Step 6 : Interface V/O devices, as per your application. Table - 1 In this chapter, we will concentrate on Step - 1 to Step - 5. Step - 6 will come into picture, when we complete study of 1/0 devices. ‘Note : For generating control signals, and for interfacing memory or VO we require 74244, 74245, 74373 and 74138. So refer chapter - 2; just for refreshing the pin diagram and truth table. 5.2 Oscillator Circuit : 8085 provides ON CHIP OSCILLATOR. Refer Fig. 5.1 for the same.esor Techniques 1,c tak circuit iq i c 2 @ * 5 ek generator, extemal clock g a7[}otk out @ of this. pile Fig. 5.1: On chip osci _ su crystal Interface : On chip oscillator circuit gig, 5.2 shows crystal interfaced to i used, When We Want stable frequen’ int? cpa stl iS grounded; this avoids external wise interference Cat Cy/ Cy in the range of 10-20 pp: ig suseena by yqctuor for start UP Purpose. In industry, people use a EATONLY for clock generation. Crystal detennine, ee Seidion The oscillvor output is then fed to flip-top, ‘which gods to clock signals, #y and 65, These signals drives iment gos crits. 6, signal is given t0 pin no. 37 ie. clock outs to SEC, =o give external peripherals Py Fig. 5.2 : Crystal interfacing As flipflop divides by 2, the clock frequency is half of the sas; for example 6 MHz crystal will produce 3 MHZ clock, In acwork connected (0 Xy—X, inputs must be twice the desired cloc ald riving frequency of the timing eneral, the frequency of driving k frequency. $22 LC Drive : One can also use LC+- resonated tank circuit instead aps The circuit should be used when frequency Uenace of 10% is allowed. Resonating frequency is given L b, 1 f= aL (C+C,) Fig. 53 : LC tank Tre manufacturer recommends C > 30 pF to minimize frequency variation caused by Ciq Gt With temperature).aware (Memory Interfacing) Microprocessor Techniques 53 9085 Her 5.2.3 RC Tuned Circuit : rature and voltage range _ RC network is cheap; but has wide variations over the tempe! Specified by the manufacturer. Refer Fig. 5.4, for RC circuit. 5.2.4 External Osci cillator : different frequencies. The output is wou can design your own oscillator Now-a-days in the market, you get ready oscillator of Perfectly ‘TTL compatible. Even if you don't want ready stuff, Cirenit. Fig. 5.5 depicts the connections. external oscillator input (TTL) NC 5 Fig. 5.5 Fig. 5.4: RC tuned circuit 5.3 Reset Circuit i ‘Manual reset. 8085 requires In microprocessor we provide : (i) Power ON reset and di) “active low input”. The circuit we use, should remain “LOW”, for few msec, and then should reach to “HIGH” logic. This requirement ask for simple “Integrator circuit”. Refer Fig. 5.6. “Amplitude Voc Voc t R Ve To RESETIN Vo=to = a a et period {c) t @ % ty (a) Reset circuit (b) Waveform of power (© Waveform across supply, when switched ON capacitor C Fig, 56 When power supply is switched ON at time to, capacitor will start charging exponentially. Vjyz is 2.4V. For a microprocessor, voltage level below 2.4V will be treated as “LOW” logic, Duc to R in series, capacitor will take sometime to reach to 2.4V icc. ty. (t)-tg) => Reset period, because after t,, Vo will be > 2.4V therefore treated as HIGH LOGIC, Typical value of R we select is 1kQ to 10kO; and C from | pf to 10 pf. Any combination will do,gun © ‘ore, pe as swriched OFF, we should provide tha \ eg pots for capactior. For that we wet ai rE $7 Shows TES network with diode ang 2 apenas Whe po" Spl is switched ORF coz 0S diode will foward biased and ate? po eves ph and capacitor will be mi fa all you Wem mamal aS Capacneé will be discharged qibeee 22 posp resisance. a8 It offers low impedance path, Switch} Foe wl bone down Vo 5 OV. Thus, sytem ig s t Fig. $.7 : Reset network with diode and manual reset Fo" proper RESET, signal should be low for atleast 2 ‘clock periods. Afr reset, PC = O000H. So execution will begin from that address ONLY. Also referred 2s reset location for 2085, ‘will disable intemal interrupt circuit of mict misroprovessor should be “MENTALLY” requirements) for accepting interrupt. Toprocessor. This is just because Prepared (fulfiling some initial Due 1 iaoduction of crystal and reset circuit, at this stage we have two contol signal ready ‘nit wie CLK OUT and RESET OUT; to be used for external peripheral 54 Generating Separate Address and Data Bus 5 Next step in microprocessor system design is to generate separate address and data bus. In Imei we have multiplexed address and data So firstly, we have to demultiplex it 541 Demultiplexing Address and Data Bus : Operation = (Address will appear on AD, ~ AD; lines. ©) ALE will go high, forcing Enable (G) = 1. This will make 74LS373 latch “transparent” ic whutever will be input, that will be output. Presently input is address (A,— Aq ). Therefore ouput is A,— Ap. B) Before addre: pears, ALE = Enable(G) = 0. Due to this contents in FF will get latched : Ereatiough aera: output will not change, Thus till next cycle ie. unless next ALE appears, A, ~ Ay status is LATCHED and will not change. ') AD,~AD,, will be continued as data bus, ~. labelled as Dy to D,, only. : plex . Th tof From Ajg~ Ag. we have PURE (not muliplexed) _ order — a us, ae x 53(4,— A.) and upper onder address, in total will provide us 16 bit address ( Ay5~ Ag). Thus5 Hardwe Microprocessor Techniques _ 55 al ato (Memory Intertacing fat this stage we are ready with Ayy~ Ap address bus and Dy = Do data bus IC 74LS373 ‘ADy AD, Ape el ADs Separate AD, address bus ADs ADs AD; ALE Soparate AD! na mete ADH Gath APH ' ALL PLL int ' iat (a) Demultiplexing address/data (b) Waveforms Fig. 5.8 5.5 Generation of Control Signals : In 8085 microprocessor, control signals are not directly available for reading and writing data from memory or I/O device. But it contains 10/M to differentiate between memory and 1/0 device, RD to read data and WR to write data. By using these lines we can generate four separate signals read/write for memory and read/write for I/O device. The truth table will be as follows: lo/M RD WR Control signal 0 0 1 | Memory read 0 1 0 | Memory write 1 0 1__| VO read- 1 1 0 {VO write, Table - 2oy Teche arene ys — 2085 Hardware of gnals required are also pot 02 active low and a! OR WO and We call them as MEMR (memos ¢ weite), read) and TOW (110 write, i R (memory read), ae th table one can directly draw é an 4 multifunction logic as shown in Fig 5.9, Fig. 5.9 : Generation of control signals cad of logic gates, we can prefer 74LS138 (3:8 line decoder). pot inst fo ma | RD | WR | Active output line Lo _| (B) (A) 0 0 0 0 —> Impossible condition 0 0 1 1 > MEMR: 0 1 0 2 + MEMW 0 1 1 3 ~ No operation: * 1 0 0 4 Impossible condition 1 0 1 5 > TOR 1 1 0 6 + I0W 1 1 1 1 > No operation Table - 3 = 1. It represents that it is a MEMR 4 When the combination on 10/4 = 0, RD = 0 and WR 1 output line of 3:8 control signal, For the above ¢ combination 1° output line is active so decoder can be used as MEMR signal. Sinialy, 9 of 0, RD = 0 and WR = 1, 2" output line is active. tis a MEMW signal. « OAM = 1, RD = 0 and WR = 1, 5” output line is active. Itis a JOR signal. ) ine is active. It is a TOW signal. 1O/M = 1, RD = 1 and WR = 0, 6” output li a ein BD and WR as C, B, A inqusio 38 The above 4 points specifies that, if we use 10/M, e Be a eeMicroprocessor Techniques _5T_ 2008 aro (MOTE en eecerrexpet es 1, 2, $ amid 6 can be Used As A COULOL sigUAHe “The deooder respectively, the ontpat lines 1, Las 7 pe problem of tiversion also as T4138 outputs are inverted, The 38 decoder an jt connections will be as shown in Fig. $.10, Voc 3:8 decoder 74138 Fig. 5.10 : Generation of control signals using decoder 5.6 Basic 8085 Microprocessor Unit : The data sheet of 8085 specifies that, its buses can source 400 1A and sink 2 mA of curren, ‘These values put a limit on, how many TTL loads can be interfaced to the bus. If your application asks for more number of peripheral devices (memory as well as /O), then PCB size will increase, In such situation we would like to increase driving capability of 8085 buses. To achieve this, we will use 74LS244 (unidirectional) and 74LS245 (bi-directional) buffers. Let’s refer Fig. 5.11 first, which implements buffer in the circuit. (1) Crystal of 6 MHz with 20 pF capacitors, is interfaced to X, and X, terminal of 8085 microprocessor. (2) Power ON reset circuit, with fast discharge and “Manual reset” is interfaced to RESETIN pin. 10k with 1 pF, will provide approximately 10 msec timing for reset. @) As Ays~Ag address lines re unidirectional, buffer 74L$244 is used to increase driving capacity. (4) For lower order-address bus, in demultiplexing, we have already used 74L$373 latch, which has buffered output, so no need of extra buffer. Thus control we have Ays— Ap, buffered address bus. (5) As data bus is bi-directional, buffer.74LS245 is used, Enable terminal (G) is grounded. Data flow direction is controlled by DIR pin. This pin is interfaced to RD pin When RD = 0 (Read operation), data flow is from memory Or VO to microprocessor. RD = 1 (Read operation), data flow is from microprocessor to memory or /O. (6) DMA action is not used. Therefore HOLD = 0 and HLDA'= NC. (Not connected)inners ieee, Mysto Address Bus Lover sae | Po 4, ouatntomenany719 Foy a 1:2_, 3p me > x rm mame 10 processor 8085, Fig, $1 : Basic 8085 microprocessor unit or basic skeleton of micro]